The e6500 core manual defines PWRMGTCR0 as SPR 1019 (0x3fb). QorIQ U-Boot and kernel access its fields during processor power setup.
Define and register PWRMGTCR0 using the existing 32-bit SPR storage to retain the programmed control fields. Reference: E6500RM (Rev.0), section 2.7.7 https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9d3d27be91..b716ccf540 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2346,6 +2346,7 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_Exxx_L2CSR1 (0x3FA) #define SPR_ICTC (0x3FB) #define SPR_40x_ICCR (0x3FB) +#define SPR_Exxx_PWRMGTCR0 (0x3FB) #define SPR_THRM1 (0x3FC) #define SPR_403_PBL1 (0x3FC) #define SPR_SP (0x3FD) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 032b8b606e..4d12152659 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -3026,6 +3026,9 @@ static void init_proc_e500(CPUPPCState *env, int version) } if (version == fsl_e6500) { + spr_register(env, SPR_Exxx_PWRMGTCR0, "PWRMGTCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, 0); /* Thread identification */ spr_register(env, SPR_TIR, "TIR", SPR_NOACCESS, SPR_NOACCESS, -- 2.53.0
