The L1 configuration registers encode a 64-byte cache block with CBSIZE=1. The models instead set CBSIZE=2, advertising 128 bytes despite using 64 bytes for cache operations.
Use the correct field value for both caches. Reference: - E500MCRM (Rev.3), sections 2.14.4 and 2.14.5 https://www.nxp.com/docs/en/reference-manual/E500MCRM.pdf - E5500RM (Rev.4), sections 2.14.4 and 2.14.5 https://www.nxp.com/webapp/Download?colCode=E5500RM Fixes: a496e8eeba51 ("PPC: E500: Populate L1CFG0 SPR") Fixes: d2ea2bf740c5 ("PPC: Add L1CFG1 SPR emulation") Cc: [email protected] Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 96bae6a6d1..db807f64c2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2886,8 +2886,8 @@ static void init_proc_e500(CPUPPCState *env, int version) case fsl_e5500: env->dcache_line_size = 64; env->icache_line_size = 64; - l1cfg0 |= 0x1000000; /* 64 byte cache block size */ - l1cfg1 |= 0x1000000; /* 64 byte cache block size */ + l1cfg0 |= 0x00800000; /* 64 byte cache block size */ + l1cfg1 |= 0x00800000; /* 64 byte cache block size */ break; case fsl_e6500: env->dcache_line_size = 32; -- 2.53.0
