On 13/10/26 10:38, Peter Maydell wrote:
We put the definitions of GICv5 IRS registers and guest-memory data
structures directly into arm_gicv5.c. It turns out that there are a
few cases where we would like them outside that file (for instance
register reset is handled in arm_gicv5_common.c).
Move the definitions to their own header file.
There are pre-existing typo worth fixing before moving IMO.
Signed-off-by: Peter Maydell <[email protected]>
---
hw/intc/arm_gicv5.c | 270 +----------------------------
include/hw/intc/arm_gicv5_regs.h | 286 +++++++++++++++++++++++++++++++
2 files changed, 287 insertions(+), 269 deletions(-)
create mode 100644 include/hw/intc/arm_gicv5_regs.h
-REG64(IRS_VPE_SELR, 0x240)
- FIELD(IRS_VPE_SELR, VM_ID, 0, 16)
- FIELD(IRS_VPE_SELR, VPE_ID, 32, 16)
- FIELD(IRS_VPE_SELR, S, 63, 1)
-
-REG64(IRS_VPE_DBR, 0x248)
- FIELD(IRS_VPE_DBR, INTID, 0, 24)
- FIELD(IRS_VPE_DBR, DBPM, 32, 5)
- FIELD(IRS_VPE_DBR, REQ_DB, 62, 1)
- FIELD(IRS_VPE_DBR, DBV, 63, 1)
-
-REG32(IRS_VPE_HPPIR, 0x250)
Pre-existing (or maybe that changed since previous releases)
this register is 64-bit.
- FIELD(IRS_VPE_HPPIR, ID, 0, 24)
- FIELD(IRS_VPE_HPPIR, TYPE, 29, 3)
- FIELD(IRS_VPE_HPPIR, HPPIV, 32, 1)
(thus the expanded HPPIV definitions might be wrong).
-REG32(IRS_VPE_CR0, 0x258)
- FIELD(IRS_VPE_CR0, DPS, 0, 1)
-
-REG32(IRS_VPE_STATUSR, 0x25c)
- FIELD(IRS_VPE_STATUSR, IDLE, 0, 1)
- FIELD(IRS_VPE_STATUSR, V, 1, 1)
[...]
-REG32(IRS_MEC_IDR, 0x340)
- FIELD(IRS_MEC_IDR, MECIDSIZE, 0, 4)
-
-REG32(IRS_MEC_MECID_R, 0x344)
- FIELD(IRS_MEC_MICID_R, MECID, 0, 16)
Pre-existing s/IRS_MEC_MECID_R/IRS_MEC_MICID_R/ typo?
-
-REG32(IRS_MPAM_IDR, 0x380)
- FIELD(IRS_MPAM_IDR, PARTID_MAX, 0, 16)
- FIELD(IRS_MPAM_IDR, PMG_MAX, 16, 8)
- FIELD(IRS_MPAM_IDR, HAS_MPAM_SP, 24, 1)
-
-REG32(IRS_MPAM_PARTID_R, 0x384)
- FIELD(IRS_MPAM_IDR, PARTID, 0, 16)
- FIELD(IRS_MPAM_IDR, PMG, 16, 8)
- FIELD(IRS_MPAM_IDR, MPAM_SP, 24, 2)
- FIELD(IRS_MPAM_IDR, IDLE, 31, 1)
s/IRS_MPAM_IDR/IRS_MPAM_PARTID_R/ typo!
-
-REG64(IRS_SWERR_STATUSR, 0x3c0)
- FIELD(IRS_SWERR_STATUSR, V, 0, 1)
- FIELD(IRS_SWERR_STATUSR, S0V, 1, 1)
- FIELD(IRS_SWERR_STATUSR, S1V, 2, 1)
- FIELD(IRS_SWERR_STATUSR, OF, 3, 1)
- FIELD(IRS_SWERR_STATUSR, EC, 16, 8)
- FIELD(IRS_SWERR_STATUSR, IMP_EC, 24, 8)
-
-REG64(IRS_SWERR_SYNDROMER0, 0x3c8)
- FIELD(IRS_SWERR_SYNDROMER0, VM_ID, 0, 16)
- FIELD(IRS_SWERR_SYNDROMER0, ID, 32, 24)
- FIELD(IRS_SWERR_SYNDROMER0, TYPE, 60, 3)
- FIELD(IRS_SWERR_SYNDROMER0, VIRTUAL, 63, 1)
-
-REG64(IRS_SWERR_SYNDROMER1, 0x3d0)
- FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53)
s/IRS_SWERR_SYNDROMER1/IRS_SWERR_SYNDROMER2/ typo?
-
-REG32(IRS_IDREGS, 0xffd0)
-REG32(IRS_DEVARCH, 0xffbc)
-
-FIELD(L1_ISTE, VALID, 0, 1)
-FIELD(L1_ISTE, L2_ADDR, 12, 44)
-
-FIELD(L2_ISTE, PENDING, 0, 1)
-FIELD(L2_ISTE, ACTIVE, 1, 1)
-FIELD(L2_ISTE, HM, 2, 1)
-FIELD(L2_ISTE, ENABLE, 3, 1)
-FIELD(L2_ISTE, IRM, 4, 1)
-FIELD(L2_ISTE, HWU, 9, 2)
-FIELD(L2_ISTE, PRIORITY, 11, 5)
-FIELD(L2_ISTE, IAFFID, 16, 16)
