IRS_VPE_CR0 is a 32-bit VPE configuration register which has semantics similar to IRS_VPE_DBR. However, the only configuration field it has is for configuring 1-of-N VPE selection. Since QEMU does not implement the optional 1-of-N handling, for us the entire register is RES0.
We don't need to implement the "writes to the register trigger a re-check of the validity of the VPE in IRS_VPE_SELR and update IRS_VPE_STATUSR.V" when the whole register is RES0, so our handling of the register can be simple. Signed-off-by: Peter Maydell <[email protected]> --- hw/intc/arm_gicv5.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index f7d2d4a7143..18ca7034011 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -2334,6 +2334,10 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, *data = 0; } return true; + case A_IRS_VPE_CR0: + /* RES0 when VIRT_ONE_N is not implemented */ + *data = 0; + return true; case A_IRS_VPE_STATUSR: if (gicv5_domain_has_virt(cs, domain)) { *data = cs->irs_vpe_statusr[domain]; @@ -2524,6 +2528,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset, irs_vpe_dbr_write(s, domain, deposit64(cs->irs_vpe_dbr[domain], 32, 32, data)); return true; + case A_IRS_VPE_CR0: + /* RES0 when VIRT_ONE_N is not implemented */ + return true; case A_IRS_SPI_SELR: cs->irs_spi_selr[domain] = data; return true; -- 2.43.0
