On Tue, 13 Oct 2026 at 09:40, Peter Maydell <[email protected]> wrote: > > In this commit we update the logic for writes to the virtual PPI > pending state by the guest using the PPI_CPEND or PPI_SPEND registers > to honour the DVI registers, so that the pending state of the > underlying physical PPI is updated. > > Signed-off-by: Peter Maydell <[email protected]> > --- > target/arm/tcg/gicv5-cpuif.c | 69 ++++++++++++++++++++++++++++++++---- > 1 file changed, 63 insertions(+), 6 deletions(-) > > diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c > index cdde759bf41..5a2927faf75 100644 > --- a/target/arm/tcg/gicv5-cpuif.c > +++ b/target/arm/tcg/gicv5-cpuif.c > @@ -816,16 +816,61 @@ static uint64_t gic_ppi_pend_read(CPUARMState *env, > const ARMCPRegInfo *ri) > } > } > > +static uint64_t gic_ppi_vpend_to_ppend(CPUARMState *env, > + uint64_t value, int reg) > +{ > + /* > + * Given a mask of bits which are virtual PPI pending bits being > + * changed, output the mask of bits which are to be changed in the > + * physical PPI pending state, by adjusting them for the the timer > + * PPI redirection. We require that the input value has already > + * had the bits masked out for vPPIs that are not direct-injected. > + */ > + if (reg == 0 && (arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == HCR_NV) { > + if (arm_is_secure_below_el3(env)) { > + /* vPPI 20 is pPPI 30; vPPI 19 is pPPI 27 */ > + if (value & (1 << 20)) { > + value |= 1 << 30; > + } > + if (value & (1 << 19)) { > + value |= 1 << 27; > + } > + } else { > + /* vPPI 26 is pPPI 30; vPPI 28 is pPPI 27 */ > + if (value & (1 << 26)) { > + value |= 1 << 30; > + } > + if (value & (1 << 28)) { > + value |= 1 << 27; > + } > + } > + value &= ~((1 << 26) | (1 << 28));
This "clear bits 26 and 28" line should be inside the "else" block, and the "if" block should have an equivalent line for "clear bits 19 and 20". > + } > + return value; > +} -- PMM
