Implement the ICH_PPI_PRIORITYR<n>_EL2 registers, which are the hypervisor's interface to its guest's PPI priority register state. As with ICC_PPI_PRIORITY<n>_EL1, we define these programmatically to avoid listing out 16 near-identical cpreg definitions.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 62262c594d7..287cfa87140 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -599,6 +599,7 @@ typedef struct CPUArchState { uint64_t ich_ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_enable[GICV5_NUM_PPIS / 64]; + uint64_t ich_ppi_priority[GICV5_NUM_PPIS / 8]; } gicv5_cpuif; struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 6dec0ec1ea6..b901e64ef0d 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -481,6 +481,12 @@ static void gic_ich_ppi_active_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void gic_ich_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + /* * ICC_APR_EL1 is banked and reads/writes as the version for the * current logical interrupt domain. @@ -1024,5 +1030,20 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &ppi_prio); } + /* Similarly for ICH_PPI_PRIORITYR<n>_EL2 */ + for (int i = 0; i < 16; i++) { + g_autofree char *name = g_strdup_printf("ICH_PPI_PRIORITYR%d_EL2", i); + ARMCPRegInfo ppi_prio = { + .name = name, .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, + .crm = 14 + (i >> 3), .opc2 = i & 7, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb80 + (8 * i), + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_priority[i]), + .writefn = gic_ich_ppi_priority_write, + }; + define_one_arm_cp_reg(cpu, &ppi_prio); + } } } -- 2.43.0
