Implement the ICH_PPI_ENABLERn_EL2, ICH_PPI_PENDRn_EL2 and ICH_PPI_ACTIVERn_EL2 registers. These are the hypervisor interface to the underlying state of its guest's PPI interrupts. Unlike the ICC PPI registers, these don't have set and clear register pairs.
We mark these as ARM_CP_IO and give them a writefn, even though right now the only thing the writefn does is a raw_write to the underlying CPU struct field, because eventually hypervisor writes to these registers will need to trigger recalculation of the highest priority pending PPI and possible signalling of VIRQ. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 3 ++ target/arm/tcg/gicv5-cpuif.c | 64 ++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a93fd362417..62262c594d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -596,6 +596,9 @@ typedef struct CPUArchState { GICv5PendingIrq ppi_hppi[NUM_GICV5_DOMAINS]; uint64_t ich_apr_el2; + uint64_t ich_ppi_active[GICV5_NUM_PPIS / 64]; + uint64_t ich_ppi_pend[GICV5_NUM_PPIS / 64]; + uint64_t ich_ppi_enable[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 83c9be2b0e6..6dec0ec1ea6 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -463,6 +463,24 @@ static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri, gic_recalc_ppi_hppi(env); } +static void gic_ich_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + +static void gic_ich_ppi_pend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + +static void gic_ich_ppi_active_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + /* * ICC_APR_EL1 is banked and reads/writes as the version for the * current logical interrupt domain. @@ -937,6 +955,52 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .accessfn = access_gicv5_ich_reg, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_apr_el2), }, + { .name = "ICH_PPI_ENABLER0_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 2, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb50, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_enable[0]), + .writefn = gic_ich_ppi_enable_write, + }, + { .name = "ICH_PPI_ENABLER1_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 3, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb58, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_enable[1]), + .writefn = gic_ich_ppi_enable_write, + }, + { .name = "ICH_PPI_PENDR0_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 4, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_pend[0]), + .writefn = gic_ich_ppi_pend_write, + }, + { .name = "ICH_PPI_PENDR1_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 5, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_pend[1]), + .writefn = gic_ich_ppi_pend_write, + }, + { .name = "ICH_PPI_ACTIVER0_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 6, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb30, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_active[0]), + .writefn = gic_ich_ppi_active_write, + }, + { .name = "ICH_PPI_ACTIVER1_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 10, .opc2 = 7, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xb38, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_active[1]), + .writefn = gic_ich_ppi_active_write, + }, }; void define_gicv5_cpuif_regs(ARMCPU *cpu) -- 2.43.0
