Annotate the GICv5 cpuif register cpreg structs with the fine-grained trap information. This covers all the bits in ICH_HFGRTR_EL2 and ICH_HFGWTR_EL2.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 55dc2e3b3b2..a829b90f334 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -855,17 +855,20 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { { .name = "ICC_IDR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, + .fgt = FGT_ICC_IDRN_EL1, .resetvalue = QEMU_ICC_IDR0, }, { .name = "ICC_ICSR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 4, .access = PL1_RW, .type = ARM_CP_NO_RAW, + .fgt = FGT_ICC_ICSR_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.icc_icsr_el1), .resetvalue = 0, }, { .name = "ICC_IAFFIDR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 5, .access = PL1_R, .type = ARM_CP_NO_RAW, + .fgt = FGT_ICC_IAFFIDR_EL1, /* ICC_IAFFIDR_EL1 holds the IAFFID only, in its low bits */ .fieldoffset = offsetof(CPUARMState, gicv5.iaffid), /* @@ -877,83 +880,97 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { { .name = "ICC_PPI_CACTIVER0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), .writefn = gic_ppi_cactive_write, }, { .name = "ICC_PPI_CACTIVER1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), .writefn = gic_ppi_cactive_write, }, { .name = "ICC_PPI_SACTIVER0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 2, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), .writefn = gic_ppi_sactive_write, }, { .name = "ICC_PPI_SACTIVER1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 3, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_ACTIVERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), .writefn = gic_ppi_sactive_write, }, { .name = "ICC_PPI_HMR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 0, .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_HMRN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[0]), .resetvalue = PPI_HMR0_RESET, }, { .name = "ICC_PPI_HMR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 1, .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_HMRN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue = PPI_HMR1_RESET, }, { .name = "ICC_HPPIR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 3, .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_HPPIR_EL1, .readfn = gic_icc_hppir_el1_read, }, { .name = "ICC_PPI_ENABLER0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 6, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_ENABLERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_enable[0]), .writefn = gic_ppi_enable_write, }, { .name = "ICC_PPI_ENABLER1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 7, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_ENABLERN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_enable[1]), .writefn = gic_ppi_enable_write, }, { .name = "ICC_PPI_CPENDR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 4, .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_PENDRN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), .writefn = gic_ppi_cpend_write, }, { .name = "ICC_PPI_CPENDR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 5, .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_PENDRN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), .writefn = gic_ppi_cpend_write, }, { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 6, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_PENDRN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), .writefn = gic_ppi_spend_write, }, { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 7, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_PENDRN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), .writefn = gic_ppi_spend_write, }, { .name = "ICC_APR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_APR_EL1, .readfn = gic_icc_apr_el1_read, .writefn = gic_icc_apr_el1_write, .resetfn = gic_icc_apr_el1_reset, @@ -961,6 +978,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { { .name = "ICC_CR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_CR0_EL1, .readfn = gic_icc_cr0_el1_read, .writefn = gic_icc_cr0_el1_write, .resetfn = gic_icc_cr0_el1_reset, @@ -968,6 +986,7 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { { .name = "ICC_PCR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 2, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PCR_EL1, .readfn = gic_icc_pcr_el1_read, .writefn = gic_icc_pcr_el1_write, .resetfn = gic_icc_pcr_el1_reset, @@ -1102,6 +1121,7 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 14 + (i >> 3), .opc2 = i & 7, .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_ICC_PPI_PRIORITYRN_EL1, .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_priority[i]), .writefn = gic_ppi_priority_write, .raw_writefn = raw_write, }; -- 2.43.0
