Re: [PATCH v4 02/18] hw/riscv: Trace RAM Sink initial impl

[Jay Chang]

> +static uint64_t tr_ramsink_msgread(void *opaque, hwaddr addr, unsigned
> size)
> +{
> +    TraceRamSink *tram = TRACE_RAM_SINK(opaque);
> +
> +    switch (size) {
> +    case 1:
> +        return tram->msgs[addr];
> +    case 2:
> +        return (uint16_t)tram->msgs[addr];
> +    case 4:
> +        return (uint32_t)tram->msgs[addr];
> +    default:
> +        g_assert_not_reached();
> +    }
>


Could we use little-endian load helpers for the multi-byte accesses? As
written, both cases only read tram->msgs[addr]; the casts do not load the
following bytes. For example:

case 2:
    return lduw_le_p(&tram->msgs[addr]);
case 4:
    return ldl_le_p(&tram->msgs[addr]);

Thanks
Jay Chang