No need to use the low-level QOM API when an object
inherits from QDev. Directly use the QDev API to set
its properties.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
hw/riscv/microchip_pfsoc.c | 8 ++++----
hw/riscv/opentitan.c | 9 +++------
hw/riscv/shakti_c.c | 7 +++----
hw/riscv/sifive_e.c | 8 +++-----
hw/riscv/sifive_u.c | 9 +++------
hw/riscv/spike.c | 10 ++++------
hw/riscv/virt.c | 9 +++------
7 files changed, 23 insertions(+), 37 deletions(-)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 82ae5e7023..ff6c4b0471 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -423,16 +423,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
qdev_set_nic_properties(DEVICE(&s->gem1), nd);
}
- object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
- object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
+ qdev_prop_set_uint32(DEVICE(&s->gem0), "revision", GEM_REVISION);
+ qdev_prop_set_uint8(DEVICE(&s->gem0), "phy-addr", 8);
sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
memmap[MICROCHIP_PFSOC_GEM0].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
- object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
- object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
+ qdev_prop_set_uint32(DEVICE(&s->gem1), "revision", GEM_REVISION);
+ qdev_prop_set_uint8(DEVICE(&s->gem1), "phy-addr", 9);
sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
memmap[MICROCHIP_PFSOC_GEM1].base);
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 64d5d435b9..f69db8c31e 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -145,12 +145,9 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
MemoryRegion *sys_mem = get_system_memory();
int i;
- object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
- &error_abort);
- object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
- &error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
- &error_abort);
+ qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type", ms->cpu_type);
+ qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", ms->smp.cpus);
+ qdev_prop_set_uint64(DEVICE(&s->cpus), "resetvec", s->resetvec);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
/* Boot ROM */
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index e43cc9445c..32d3d7cbab 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -168,10 +168,9 @@ static void shakti_c_soc_instance_init(Object *obj)
* So let it be in instance_init. When supported should use ms->cpu_type
* instead of TYPE_RISCV_CPU_SHAKTI_C
*/
- object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
- TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
- object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
- &error_abort);
+ qdev_prop_set_string(DEVICE(&sss->cpus), "cpu-type",
+ TYPE_RISCV_CPU_SHAKTI_C);
+ qdev_prop_set_uint32(DEVICE(&sss->cpus), "num-harts", 1);
}
static const TypeInfo shakti_c_type_info = {
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 3e3f4b0088..0f5dfc5f3d 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -178,9 +178,8 @@ static void sifive_e_soc_init(Object *obj)
SiFiveESoCState *s = RISCV_E_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
- object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
- &error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004,
&error_abort);
+ qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", ms->smp.cpus);
+ qdev_prop_set_uint64(DEVICE(&s->cpus), "resetvec", 0x1004);
object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
TYPE_SIFIVE_GPIO);
}
@@ -192,8 +191,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error
**errp)
SiFiveESoCState *s = RISCV_E_SOC(dev);
MemoryRegion *sys_mem = get_system_memory();
- object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
- &error_abort);
+ qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type", ms->cpu_type);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
/* Mask ROM */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2fb6ee231f..97f504d011 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -540,10 +540,8 @@ static void sifive_u_machine_init(MachineState *machine)
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
- object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
- &error_abort);
- object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
- &error_abort);
+ qdev_prop_set_uint32(DEVICE(&s->soc), "serial", s->serial);
+ qdev_prop_set_string(DEVICE(&s->soc), "cpu-type", machine->cpu_type);
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* register RAM */
@@ -905,8 +903,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
**errp)
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem), nd);
}
- object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
- &error_abort);
+ qdev_prop_set_uint32(DEVICE(&s->gem), "revision", GEM_REVISION);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
return;
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index badc11ec43..328278d820 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "hw/qdev-properties.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
@@ -238,12 +239,9 @@ static void spike_board_init(MachineState *machine)
object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
TYPE_RISCV_HART_ARRAY);
g_free(soc_name);
- object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
- machine->cpu_type, &error_abort);
- object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
- base_hartid, &error_abort);
- object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
- hart_count, &error_abort);
+ qdev_prop_set_string(DEVICE(&s->soc[i]), "cpu-type",
machine->cpu_type);
+ qdev_prop_set_uint32(DEVICE(&s->soc[i]), "hartid-base", base_hartid);
+ qdev_prop_set_uint32(DEVICE(&s->soc[i]), "num-harts", hart_count);
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
/* Core Local Interruptor (timer and IPI) for each socket */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a11b4b010..0e091cb65f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1360,12 +1360,9 @@ static void virt_machine_init(MachineState *machine)
object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
TYPE_RISCV_HART_ARRAY);
g_free(soc_name);
- object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
- machine->cpu_type, &error_abort);
- object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
- base_hartid, &error_abort);
- object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
- hart_count, &error_abort);
+ qdev_prop_set_string(DEVICE(&s->soc[i]), "cpu-type",
machine->cpu_type);
+ qdev_prop_set_uint32(DEVICE(&s->soc[i]), "hartid-base", base_hartid);
+ qdev_prop_set_uint32(DEVICE(&s->soc[i]), "num-harts", hart_count);
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
if (!kvm_enabled()) {
--
2.38.1
