No need to use the low-level QOM API when an object inherits from QDev. Directly use the QDev API to set its properties.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org> --- hw/mips/boston.c | 6 ++---- hw/mips/cps.c | 42 ++++++++++++++---------------------------- hw/mips/jazz.c | 3 +-- hw/mips/malta.c | 6 ++---- 4 files changed, 19 insertions(+), 38 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 21ad844519..f3c2179f66 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -700,10 +700,8 @@ static void boston_mach_init(MachineState *machine) } object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); - object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, - &error_fatal); - object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, - &error_fatal); + qdev_prop_set_string(DEVICE(&s->cps), "cpu-type", machine->cpu_type); + qdev_prop_set_uint32(DEVICE(&s->cps), "num-vp", machine->smp.cpus); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", qdev_get_clock_out(dev, "cpu-refclk")); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 2b5269ebf1..3109644c5e 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -79,10 +79,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) CPUMIPSState *env = &cpu->env; /* All VPs are halted on reset. Leave powering up to CPC. */ - if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true, - errp)) { - return; - } + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", true); + /* All cores use the same clock tree */ qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); @@ -106,12 +104,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); - object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); - object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, - &error_abort); - object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, - &error_abort); + qdev_prop_set_link(DEVICE(&s->itu), "cpu[0]", OBJECT(first_cpu)); + qdev_prop_set_uint32(DEVICE(&s->itu), "num-fifo", 16); + qdev_prop_set_uint32(DEVICE(&s->itu), "num-semaphores", 16); if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { return; } @@ -122,10 +117,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Cluster Power Controller */ object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); - object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, - &error_abort); - object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, - &error_abort); + qdev_prop_set_uint32(DEVICE(&s->cpc), "num-vp", s->num_vp); + qdev_prop_set_uint64(DEVICE(&s->cpc), "vp-start-running", 0x1); if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) { return; } @@ -135,10 +128,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Global Interrupt Controller */ object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); - object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp, - &error_abort); - object_property_set_uint(OBJECT(&s->gic), "num-irq", 128, - &error_abort); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-vp", s->num_vp); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", 128); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { return; } @@ -150,16 +141,11 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); - object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, - &error_abort); - object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, - &error_abort); - object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, - &error_abort); - object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), - &error_abort); - object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), - &error_abort); + qdev_prop_set_uint32(DEVICE(&s->gcr), "num-vp", s->num_vp); + qdev_prop_set_int32(DEVICE(&s->gcr), "gcr-rev", 0x800); + qdev_prop_set_uint64(DEVICE(&s->gcr), "gcr-base", gcr_base); + qdev_prop_set_link(DEVICE(&s->gcr), "gic", OBJECT(&s->gic.mr)); + qdev_prop_set_link(DEVICE(&s->gcr), "cpc", OBJECT(&s->cpc.mr)); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { return; } diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 6aefe9a61b..d18aeb439b 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -302,8 +302,7 @@ static void mips_jazz_init(MachineState *machine, qdev_set_nic_properties(dev, nd); qdev_prop_set_uint8(dev, "it_shift", 2); qdev_prop_set_bit(dev, "big_endian", big_endian > 0); - object_property_set_link(OBJECT(dev), "dma_mr", - OBJECT(rc4030_dma_mr), &error_abort); + qdev_prop_set_link(dev, "dma_mr", OBJECT(rc4030_dma_mr)); sysbus = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sysbus, &error_fatal); sysbus_mmio_map(sysbus, 0, 0x80001000); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index af9021316d..3b88668bae 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1064,10 +1064,8 @@ static void create_cps(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); - object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, - &error_fatal); - object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, - &error_fatal); + qdev_prop_set_string(DEVICE(&s->cps), "cpu-type", ms->cpu_type); + qdev_prop_set_uint32(DEVICE(&s->cps), "num-vp", ms->smp.cpus); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); -- 2.38.1