> I've already started putting together a clone using an Xilinx > XC9572XL, which I have lying around. The Verilog file compiled from > the get-go, I just had to remove the additional SS lines because of > Pin restrictions in the small chip on my eval board. The long lines to > the board might not exactly help, though... might take a while, but I > will try to make a GoldCard compatible QL-SD one way or another, now > that I have your release to base it on :-) > Doesnt gold card have a parralell port?
That should be enough IO pins to connect an SD card which just needs SPI. Graeme _______________________________________________ QL-Users Mailing List
