Herman Bruyninckx wrote:
> I have a dual Pentium III 700Mhz, and I wanted to investigate how it
> compares to DSP performance, when everything can be kept in cache.
Keeping things in cache is only half of the way ... the bigger
problem is to bother around with latencies caused by
the pci-architecture ... with modern chip-sets, itīs hard to
tell what exactly is going on ... several things have to
be taken into account:
1. CPU to Host-Bridge latency: you will have to disable caching and
write combinig in case your I/O card is memory mapped.
Even then, you have latencies when sharing the CPU-bus
with another processor.
2. Host-Bridge to PCI-Bus latency: you might disable the
read/write fifo (usual depth: 64) of the Host-Bridge.
3. you realy should disable PCI-Burst operations, which
can by up to 64 cycles. Otherwise having, for example,
five PCI-device, the arbitration could go up to 10 ĩs in
this stage.
4. Latencys caused be the I/O-Card itself
If a worst case latency of about 20 ĩs are just fine for
your application, then stay with RTL and standard settings.
Otherwise itīs going deep into details:
One solution could be the mentioned idea with the second
OS on the second CPU.
Another method would be to disallow any kind of linux-kernel
activities on the second processor. Some times ago,
i took a look into the code of the kernel scheduler ...
it should be feasabel to keep away user-space processes
and kernel threads from the second processor by modifiying
the code a little bit.
Linux-Interrupts can be directed the the first CPU
by simply reprograming the I/O-APIC, as far as i got it.
So the second CPU should completly belongs to your
RTL-application, that even could fit into the L1-Cache
of the CPU.
If this didnīt scared you then go reading on:
Getting rid of the PCI-latencies is a little bit more
difficult: You could use the three-wire APIC protocoll to
attach a special I/O-Card directly onto the CPU.
The maximum latency/jitter is less then one microsecond in
this case, but then you have to bother around with
a 100 MHz serial line, simulation a local APIC ...
Just a dream ...
Bernhard
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