[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexR52 implements setResetAddr interface

[Yu-hsin Wang (Gerrit) via gem5-dev]

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53328 )


Change subject: fastmodel: CortexR52 implements setResetAddr interface
..

fastmodel: CortexR52 implements setResetAddr interface

Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53328
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Earl Ou 
---
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
8 files changed, 45 insertions(+), 2 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

index f5817f9..85a4c2a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -79,6 +79,12 @@
 set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
 }

+void
+CortexR52::setResetAddr(Addr addr, bool secure)
+{
+evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
 Port &
 CortexR52::getPort(const std::string _name, PortID idx)
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh  
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh

index c43052b..76c7d33 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
@@ -72,6 +72,8 @@

 void setCluster(CortexR52Cluster *_cluster, int _num);

+void setResetAddr(Addr addr, bool secure = false) override;
+
 Port (const std::string _name,
 PortID idx=InvalidPortID) override;
 };
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 5dcda4e..720f1cc 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -66,7 +66,7 @@
 void
 ScxEvsCortexR52::setResetAddr(int core, Addr addr, bool secure)
 {
-panic("Not implemented for R52.");
+this->corePins[core]->cfgvectable.set_state(0, addr);
 }

 template 
@@ -78,7 +78,8 @@
 amba(evs->amba[cpu], name + ".amba", -1),
 core_reset(name + ".core_reset", 0),
 poweron_reset(name + ".poweron_reset", 0),
-halt(name + ".halt", 0)
+halt(name + ".halt", 0),
+cfgvectable((name + "cfgvectable").c_str())
 {
 for (int i = 0; i < Evs::PpiCount; i++) {
 ppis.emplace_back(
@@ -87,6 +88,7 @@
 core_reset.signal_out.bind(evs->core_reset[cpu]);
 poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
 halt.signal_out.bind(evs->halt[cpu]);
+cfgvectable.bind(evs->cfgvectable[cpu]);
 }


diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index a616a4d..fa9d7fe 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -79,6 +79,8 @@
 struct CorePins
 {
 using CoreInt = IntSinkPin;
+template 
+using SignalInitiator = amba_pv::signal_master_port;

 std::string name;
 Evs *evs;
@@ -107,6 +109,8 @@
 SignalSender core_reset;
 SignalSender poweron_reset;
 SignalSender halt;
+
+SignalInitiator cfgvectable;
 };

 std::vector> corePins;
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

index a15fe74..36f3279 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -59,6 +59,9 @@
 self.ppi_0 => core.extppi_in_0;

 self.spi => core.spi_in;
+
+// Core reset addrs.
+self.cfgvectable => core.cfgvectable;
 }

 properties
@@ -74,6 +77,7 @@
 slave port poweron_reset[1];
 slave port halt[1];
 slave port top_reset;
+slave port cfgvectable[1];

 slave port clock_rate_s
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa

index 9b992a4..492d289 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -60,6 +60,9 @@
 self.ppi_1 => core.extppi_in_1;

 self.spi => core.spi_in;
+
+// Core reset addrs.
+self.cfgvectable => core.cfgvectable;
 }

 properties
@@ -75,6 +78,7 @@
 slave port poweron_reset[2];
 slave port halt[2];
 slave port top_reset;
+slave port cfgvectable[2];

 slave port clock_rate_s
 {
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa  
b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa

index 

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 implements setResetAddr interface

[Yu-hsin Wang (Gerrit) via gem5-dev]

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53327 )


Change subject: fastmodel: CortexA76 implements setResetAddr interface
..

fastmodel: CortexA76 implements setResetAddr interface

Change-Id: I3612a62e2145d3442f01a69b21954fc00dd5ade9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53327
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Earl Ou 
---
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
8 files changed, 47 insertions(+), 3 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index e9b468d..e77e734 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -95,6 +95,12 @@
 set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
 }

+void
+CortexA76::setResetAddr(Addr addr, bool secure)
+{
+evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
 Port &
 CortexA76::getPort(const std::string _name, PortID idx)
 {
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

index 79d9eee..39f916e 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -74,6 +74,8 @@

 void setCluster(CortexA76Cluster *_cluster, int _num);

+void setResetAddr(Addr addr, bool secure = false) override;
+
 Port (const std::string _name,
 PortID idx=InvalidPortID) override;
 };
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 4b25014..935d139 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -67,7 +67,7 @@
 void
 ScxEvsCortexA76::setResetAddr(int core, Addr addr, bool secure)
 {
-panic("Not implemented for A76.");
+this->rvbaraddr[core]->set_state(0, addr);
 }

 template 
@@ -91,6 +91,8 @@
 new SignalReceiver(csprintf("vcpumntirq[%d]", i)));
 cntpnsirq.emplace_back(
 new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
+rvbaraddr.emplace_back(new SignalInitiator(
+csprintf("rvbaraddr[%d]", i).c_str()));

 Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
 Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
@@ -101,6 +103,7 @@
 Base::pmuirq[i].bind(pmuirq[i]->signal_in);
 Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
 Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);
+rvbaraddr[i]->bind(Base::rvbaraddr[i]);
 }

 clockRateControl.bind(this->clock_rate_s);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index 37f8363..7c834d0 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -69,10 +69,13 @@
 ClockRateControlInitiatorSocket clockRateControl;
 ClockRateControlInitiatorSocket periphClockRateControl;

-typedef sc_gem5::TlmTargetBaseWrapper<
+using TlmGicTarget = sc_gem5::TlmTargetBaseWrapper<
 64, svp_gicv3_comms::gicv3_comms_fw_if,
 svp_gicv3_comms::gicv3_comms_bw_if, 1,
-sc_core::SC_ONE_OR_MORE_BOUND> TlmGicTarget;
+sc_core::SC_ONE_OR_MORE_BOUND>;
+
+template 
+using SignalInitiator = amba_pv::signal_master_port;

 AmbaInitiator amba;
 std::vector> redist;
@@ -86,6 +89,7 @@
 std::vector> pmuirq;
 std::vector> vcpumntirq;
 std::vector> cntpnsirq;
+std::vector>> rvbaraddr;

 CortexA76Cluster *gem5CpuCluster;

diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa

index 04dae41..b83efc6 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -57,6 +57,9 @@
 core.pmuirq => self.pmuirq;
 core.vcpumntirq => self.vcpumntirq;

+// Core reset addrs.
+self.rvbaraddr => core.rvbaraddr;
+
 // Clocks.
 clock1Hz.clk_out => clockDiv.clk_in;
 clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -96,4 +99,5 @@
 master port pmuirq[1];
 master port vcpumntirq[1];
 master port cntpnsirq[1];
+slave port rvbaraddr[1];
 }
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa

index 0279140..4ab0b07 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ 

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add setResetAddr interface

[Yu-hsin Wang (Gerrit) via gem5-dev]

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53326 )


Change subject: fastmodel: add setResetAddr interface
..

fastmodel: add setResetAddr interface

setResetAddr interface allows us to change the reset addr of fastmodel
cores. This will enable us to simulate hard reset or even complicated
boot sequence.

Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53326
Reviewed-by: Earl Ou 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/iris/cpu.hh
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
5 files changed, 43 insertions(+), 0 deletions(-)

Approvals:
  Earl Ou: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 4e0add6..4b25014 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -64,6 +64,13 @@
 }

 template 
+void
+ScxEvsCortexA76::setResetAddr(int core, Addr addr, bool secure)
+{
+panic("Not implemented for A76.");
+}
+
+template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index f0e2ef5..37f8363 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -113,6 +113,8 @@
 void setSysCounterFrq(uint64_t sys_counter_frq) override;

 void setCluster(SimObject *cluster) override;
+
+void setResetAddr(int core, Addr addr, bool secure) override;
 };

 struct ScxEvsCortexA76x1Types
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 7f992f2..5dcda4e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -63,6 +63,13 @@
 }

 template 
+void
+ScxEvsCortexR52::setResetAddr(int core, Addr addr, bool secure)
+{
+panic("Not implemented for R52.");
+}
+
+template 
 ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) :
 name(csprintf("%s.cpu%s", _evs->name(), _cpu)),
 evs(_evs), cpu(_cpu),
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh  
b/src/arch/arm/fastmodel/CortexR52/evs.hh

index 20870df..a616a4d 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -156,6 +156,8 @@
 void setSysCounterFrq(uint64_t sys_counter_frq) override;

 void setCluster(SimObject *cluster) override;
+
+void setResetAddr(int core, Addr addr, bool secure) override;
 };

 struct ScxEvsCortexR52x1Types
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh  
b/src/arch/arm/fastmodel/iris/cpu.hh

index 5cb8820..b43eb8e 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -51,6 +51,7 @@
 virtual void setClkPeriod(Tick clk_period) = 0;
 virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
 virtual void setCluster(SimObject *cluster) = 0;
+virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
 };

 // This CPU class adds some mechanisms which help attach the gem5 and fast
@@ -86,6 +87,12 @@
 Counter totalInsts() const override;
 Counter totalOps() const override { return totalInsts(); }

+virtual void
+setResetAddr(Addr addr, bool secure = false)
+{
+panic("%s not implemented.", __FUNCTION__);
+}
+
   protected:
 sc_core::sc_module *evs;
 // Hold casted pointer to *evs.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53326
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Gerrit-Change-Number: 53326
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Philip Metzler 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Delete extraneous registers header

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53743 )



Change subject: arch-gcn3: Delete extraneous registers header
..

arch-gcn3: Delete extraneous registers header

This file is a duplicate of arch/amdgpu/gcn3/gpu_registers.hh and is in
the wrong location. It should be removed to avoid mistakenly editing the
wrong file.

Change-Id: Ie96e22fe8f78fda954af788b472ec2df4782e4a5
---
D src/arch/gcn3/registers.hh
1 file changed, 13 insertions(+), 235 deletions(-)



diff --git a/src/arch/gcn3/registers.hh b/src/arch/gcn3/registers.hh
deleted file mode 100644
index 130f052..000
--- a/src/arch/gcn3/registers.hh
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * For use for simulation and test purposes only
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are  
met:

- *
- * 1. Redistributions of source code must retain the above copyright  
notice,

- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright  
notice,
- * this list of conditions and the following disclaimer in the  
documentation

- * and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from  
this

- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS  
IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,  
THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  
PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS  
BE

- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_GCN3_REGISTERS_HH__
-#define __ARCH_GCN3_REGISTERS_HH__
-
-#include 
-#include 
-#include 
-
-#include "arch/generic/vec_reg.hh"
-#include "base/intmath.hh"
-#include "base/logging.hh"
-
-namespace gem5
-{
-
-namespace Gcn3ISA
-{
-enum OpSelector : int
-{
-REG_SGPR_MIN = 0,
-REG_SGPR_MAX = 101,
-REG_FLAT_SCRATCH_LO = 102,
-REG_FLAT_SCRATCH_HI = 103,
-REG_XNACK_MASK_LO = 104,
-REG_XNACK_MASK_HI = 105,
-REG_VCC_LO = 106,
-REG_VCC_HI = 107,
-REG_TBA_LO = 108,
-REG_TBA_HI = 109,
-REG_TMA_LO = 110,
-REG_TMA_HI = 111,
-REG_TTMP_0 = 112,
-REG_TTMP_1 = 113,
-REG_TTMP_2 = 114,
-REG_TTMP_3 = 115,
-REG_TTMP_4 = 116,
-REG_TTMP_5 = 117,
-REG_TTMP_6 = 118,
-REG_TTMP_7 = 119,
-REG_TTMP_8 = 120,
-REG_TTMP_9 = 121,
-REG_TTMP_10 = 122,
-REG_TTMP_11 = 123,
-REG_M0 = 124,
-REG_RESERVED_1 = 125,
-REG_EXEC_LO = 126,
-REG_EXEC_HI = 127,
-REG_ZERO = 128,
-REG_INT_CONST_POS_MIN = 129,
-REG_INT_CONST_POS_MAX = 192,
-REG_INT_CONST_NEG_MIN = 193,
-REG_INT_CONST_NEG_MAX = 208,
-REG_RESERVED_2 = 209,
-REG_RESERVED_3 = 210,
-REG_RESERVED_4 = 211,
-REG_RESERVED_5 = 212,
-REG_RESERVED_6 = 213,
-REG_RESERVED_7 = 214,
-REG_RESERVED_8 = 215,
-REG_RESERVED_9 = 216,
-REG_RESERVED_10 = 217,
-REG_RESERVED_11 = 218,
-REG_RESERVED_12 = 219,
-REG_RESERVED_13 = 220,
-REG_RESERVED_14 = 221,
-REG_RESERVED_15 = 222,
-REG_RESERVED_16 = 223,
-REG_RESERVED_17 = 224,
-REG_RESERVED_18 = 225,
-REG_RESERVED_19 = 226,
-REG_RESERVED_20 = 227,
-REG_RESERVED_21 = 228,
-REG_RESERVED_22 = 229,
-REG_RESERVED_23 = 230,
-REG_RESERVED_24 = 231,
-REG_RESERVED_25 = 232,
-REG_RESERVED_26 = 233,
-REG_RESERVED_27 = 234,
-REG_RESERVED_28 = 235,
-REG_RESERVED_29 = 236,
-REG_RESERVED_30 = 237,
-REG_RESERVED_31 = 238,
-REG_RESERVED_32 = 239,
-REG_POS_HALF = 240,
-REG_NEG_HALF = 241,
-REG_POS_ONE = 242,
-REG_NEG_ONE = 243,
-REG_POS_TWO = 244,
-REG_NEG_TWO = 245,
-REG_POS_FOUR = 246,
-REG_NEG_FOUR = 247,
-REG_PI = 248,
-/* NOTE: SDWA and 

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Hook up the newfstatat system call for 64 bit Linux.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53206 )


Change subject: arch-x86: Hook up the newfstatat system call for 64 bit  
Linux.

..

arch-x86: Hook up the newfstatat system call for 64 bit Linux.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1117

Change-Id: I711fc7d7009621bb317981293725416ae74d1d3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53206
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/arch/x86/linux/syscall_tbl64.cc
1 file changed, 16 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/linux/syscall_tbl64.cc  
b/src/arch/x86/linux/syscall_tbl64.cc

index aef7c2f..27ee8ec 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -309,7 +309,7 @@
 { 259, "mknodat", mknodatFunc },
 { 260, "fchownat", fchownatFunc },
 { 261, "futimesat", futimesatFunc },
-{ 262, "newfstatat" },
+{ 262, "newfstatat", newfstatatFunc },
 { 263, "unlinkat", unlinkatFunc },
 { 264, "renameat", renameatFunc },
 { 265, "linkat" },

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I711fc7d7009621bb317981293725416ae74d1d3d
Gerrit-Change-Number: 53206
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Hook up system calls for 64 bit processes.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53203 )


Change subject: arch-x86: Hook up system calls for 64 bit processes.
..

arch-x86: Hook up system calls for 64 bit processes.

These system calls already exist, they just weren't hooked up yet.

Change-Id: I5c2c66d34d0286aafe686e6511948ed4a6719672
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53203
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/arch/x86/linux/syscall_tbl64.cc
1 file changed, 29 insertions(+), 14 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/linux/syscall_tbl64.cc  
b/src/arch/x86/linux/syscall_tbl64.cc

index f22ff20..aef7c2f 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -60,7 +60,7 @@
 {  18, "pwrite64", pwrite64Func },
 {  19, "readv", readvFunc },
 {  20, "writev", writevFunc },
-{  21, "access", ignoreFunc },
+{  21, "access", accessFunc },
 {  22, "pipe", pipeFunc },
 {  23, "select", selectFunc },
 {  24, "sched_yield", ignoreWarnOnceFunc },
@@ -133,10 +133,10 @@
 {  87, "unlink", unlinkFunc },
 {  88, "symlink", symlinkFunc },
 {  89, "readlink", readlinkFunc },
-{  90, "chmod", ignoreFunc },
-{  91, "fchmod" },
-{  92, "chown" },
-{  93, "fchown" },
+{  90, "chmod", chmodFunc },
+{  91, "fchmod", fchmodFunc },
+{  92, "chown", chownFunc },
+{  93, "fchown", fchownFunc },
 {  94, "lchown" },
 {  95, "umask", umaskFunc },
 {  96, "gettimeofday", gettimeofdayFunc },
@@ -282,7 +282,7 @@
 { 232, "epoll_wait" },
 { 233, "epoll_ctl" },
 { 234, "tgkill", tgkillFunc },
-{ 235, "utimes" },
+{ 235, "utimes", utimesFunc },
 { 236, "vserver" },
 { 237, "mbind", ignoreFunc },
 { 238, "set_mempolicy" },
@@ -305,18 +305,18 @@
 { 255, "inotify_rm_watch" },
 { 256, "migrate_pages" },
 { 257, "openat", openatFunc },
-{ 258, "mkdirat" },
-{ 259, "mknodat" },
-{ 260, "fchownat" },
-{ 261, "futimesat" },
+{ 258, "mkdirat", mkdiratFunc },
+{ 259, "mknodat", mknodatFunc },
+{ 260, "fchownat", fchownatFunc },
+{ 261, "futimesat", futimesatFunc },
 { 262, "newfstatat" },
-{ 263, "unlinkat" },
-{ 264, "renameat" },
+{ 263, "unlinkat", unlinkatFunc },
+{ 264, "renameat", renameatFunc },
 { 265, "linkat" },
 { 266, "symlinkat" },
 { 267, "readlinkat", readlinkFunc },
-{ 268, "fchmodat" },
-{ 269, "faccessat" },
+{ 268, "fchmodat", fchmodatFunc },
+{ 269, "faccessat", faccessatFunc },
 { 270, "pselect6" },
 { 271, "ppoll" },
 { 272, "unshare" },

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5c2c66d34d0286aafe686e6511948ed4a6719672
Gerrit-Change-Number: 53203
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Handle empty paths when resolving an "at" path.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53683 )


Change subject: sim-se: Handle empty paths when resolving an "at" path.
..

sim-se: Handle empty paths when resolving an "at" path.

When the "path" argument is empty, use the file name of the node
referred to by the fd file descriptor. This matches the behavior of
"at" system calls when the TGT_AT_EMPTY_PATH flag is set. The system
calls themselves are responsible for checking for that flag, and
returning an error if an empty "path" is not allowed.

Change-Id: Ib48d91ff983b3edb6f65e83686b90d79d74f3471
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53683
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/sim/syscall_emul.hh
1 file changed, 23 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index c53175b..2f49f5e 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -367,7 +367,10 @@
 if (!ffdp)
 return -EBADF;

-path = ffdp->getFileName() + "/" + path;
+if (path.empty())
+path = ffdp->getFileName();
+else
+path = ffdp->getFileName() + "/" + path;
 }

 return 0;

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib48d91ff983b3edb6f65e83686b90d79d74f3471
Gerrit-Change-Number: 53683
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Implement the newfstatat system call.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53205 )


Change subject: sim-se: Implement the newfstatat system call.
..

sim-se: Implement the newfstatat system call.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1117

Change-Id: Id611bc7d6369b7d94ce27f33aff74a61879ce900
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53205
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/sim/syscall_emul.hh
1 file changed, 54 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 2f49f5e..a74aabf 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1371,6 +1371,45 @@
 return 0;
 }

+/// Target newfstatat() handler.
+template 
+SyscallReturn
+newfstatatFunc(SyscallDesc *desc, ThreadContext *tc, int dirfd,
+   VPtr<> pathname, VPtr tgt_stat,
+   int flags)
+{
+std::string path;
+
+if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
+return -EFAULT;
+
+if (path.empty() && !(flags & OS::TGT_AT_EMPTY_PATH))
+return -ENOENT;
+flags = flags & ~OS::TGT_AT_EMPTY_PATH;
+
+warn_if(flags != 0, "newfstatat: Flag bits %#x not supported.", flags);
+
+// Modifying path from the directory descriptor
+if (auto res = atSyscallPath(tc, dirfd, path); !res.successful()) {
+return res;
+}
+
+auto p = tc->getProcessPtr();
+
+// Adjust path for cwd and redirection
+path = p->checkPathRedirect(path);
+
+struct stat host_buf;
+int result = stat(path.c_str(), _buf);
+
+if (result < 0)
+return -errno;
+
+copyOutStatBuf(tgt_stat, _buf);
+
+return 0;
+}
+
 /// Target fstatat64() handler.
 template 
 SyscallReturn

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id611bc7d6369b7d94ce27f33aff74a61879ce900
Gerrit-Change-Number: 53205
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Added LupV script to configs

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53046 )


Change subject: configs: Added LupV script to configs
..

configs: Added LupV script to configs

This commit adds run_lupv.py, the script to run the LupVBoard, as well
as a README that details how to set up your system in order to run
the LupIO devices.

Change-Id: Ibea098f0409819b4c79063ab0be01518c7c6a61f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53046
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A configs/example/lupv/run_lupv.py
A configs/example/lupv/README.md
2 files changed, 173 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/lupv/README.md b/configs/example/lupv/README.md
new file mode 100644
index 000..d5895db
--- /dev/null
+++ b/configs/example/lupv/README.md
@@ -0,0 +1,44 @@
+# README
+
+This README details how to build a RISCV full system that utilizes the
+lupIO devices. The LupIO devices were created by Professor Joël  
Porquet-Lupine,

+and more information about the device can be found [here](
+https://luplab.cs.ucdavis.edu/assets/lupio/wcae21-porquet-lupio-paper.pdf).  
The

+specs for each individual device can be found [here](
+https://gitlab.com/luplab/lupio/lupio-specs), and the Linux drivers for  
each of

+these devices can be found [here](https://gitlab.com/luplab/lupio/linux).
+
+To build the RISCV gem5 binary execute:
+
+```sh
+scons build/RISCV/gem5.opt
+```
+
+Then, to run the LupIO example execute:
+
+
+``` bash
+.build/RISCV/gem5.opt configs/example/lupv/run_lupv.py  [cpu type] [num  
cpus]

+```
+
+Note: valid cpu types are `atomic` and `timing` for now.
+
+For example:
+
+```bash
+gem5/build/RISCV/gem5.opt configs/example/lupv/run_lupv.py atomic 1
+```
+
+You can observe the stdout of the simulated system in  
`m5out/system.terminal`.

+Then, you can open up a separate terminal and use m5term to connect to the
+simulated console. The port number will be specified in the gem5 simulation
+as `0: system.remote_gdb: listening for remote gdb on port `
+
+example:
+
+```bash
+m5term localhost 3456
+```
+
+This should allow you to run busybox, in which you can see the LupIO  
device at

+work!
\ No newline at end of file
diff --git a/configs/example/lupv/run_lupv.py  
b/configs/example/lupv/run_lupv.py

new file mode 100644
index 000..721adcd
--- /dev/null
+++ b/configs/example/lupv/run_lupv.py
@@ -0,0 +1,112 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This example runs a simple linux boot.
+Characteristics
+---
+* Runs exclusively on the RISC-V ISA with the classic caches
+* Assumes that the kernel is compiled into the bootloader
+* Automatically generates the DTB file
+"""
+
+import m5
+from m5.objects import Root
+
+from gem5.runtime import get_runtime_isa
+from gem5.components.boards.experimental.lupv_board import LupvBoard
+from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.isas import ISA
+from gem5.utils.requires import requires
+from gem5.resources.resource import Resource, CustomResource
+
+import argparse
+
+# 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Update the LupvBoard to use KernelDiskWorkload

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53085 )


Change subject: stdlib: Update the LupvBoard to use KernelDiskWorkload
..

stdlib: Update the LupvBoard to use KernelDiskWorkload

Change-Id: I5857f70e6ca61b8916792e634d20cdf827b21bd0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53085
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/experimental/lupv_board.py
1 file changed, 53 insertions(+), 52 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

index d14326c..d6b1dc5 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -25,13 +25,15 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 import os
-from typing import Optional, List
+from typing import List

 from utils.override import overrides
 from ..abstract_board import AbstractBoard
 from ...processors.abstract_processor import AbstractProcessor
 from ...memory.abstract_memory_system import AbstractMemorySystem
 from ...cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

+from ..kernel_disk_workload import KernelDiskWorkload
+from resources.resource import AbstractResource
 from isas import ISA
 from utils.requires import requires

@@ -71,7 +73,7 @@
 FdtState,
 )

-class LupvBoard(AbstractBoard):
+class LupvBoard(AbstractBoard, KernelDiskWorkload):
 """
 A board capable of full system simulation for RISC-V.
 This board uses a set of LupIO education-friendly devices.
@@ -272,56 +274,7 @@
 self.mem_ranges = [AddrRange(start=0x8000, size=mem_size)]
 memory.set_memory_range(self.mem_ranges)

-def set_workload(
-self, bootloader: str, disk_image: str, command: Optional[str] =  
None

-):
-"""Setup the full system files
-See https://github.com/darchr/lupio-gem5/blob/lupio/README.md
-for running the full system, and downloading the right files to do  
so.

-The command passes in a boot loader and disk image, as well as the
-script to start the simulaiton.
-After the workload is set up, this function will generate the  
device

-tree file and output it to the output directory.
-
-**Limitations**
-* Only supports a Linux kernel
-* Must use the provided bootloader and disk image as denoted in the
-README above.
-"""
-self.workload.object_file = bootloader
-# Set the disk image for the block device to use
-image = CowDiskImage(
-child=RawDiskImage(read_only=True),
-read_only=False
-)
-image.child.image_file = disk_image
-self.lupio_blk.image = image
-
-# Linux boot command flags
-kernel_cmd = [
-"earlycon console=ttyLIO0",
-"root=/dev/lda1",
-"ro"
-]
-self.workload.command_line = " ".join(kernel_cmd)
-
-# Note: This must be called after set_workload because it looks  
for an

-# attribute named "disk" and connects
-self._setup_io_devices()
-self._setup_pma()
-
-# Default DTB address if bbl is built with --with-dts option
-self.workload.dtb_addr = 0x87E0
-
-# We need to wait to generate the device tree until after the disk  
is
-# set up. Now that the disk and workload are set, we can generate  
the

-# device tree file.
-self.generate_device_tree(m5.options.outdir)
-self.workload.dtb_filename = os.path.join(
-m5.options.outdir, "device.dtb"
-)
-
-def generate_device_tree(self, outdir: str) -> None:
+def _generate_device_tree(self, outdir: str) -> None:
 """Creates the dtb and dts files.
 Creates two files in the outdir: 'device.dtb' and 'device.dts'
 :param outdir: Directory to output the files
@@ -564,3 +517,38 @@
 fdt.add_rootnode(root)
 fdt.writeDtsFile(os.path.join(outdir, "device.dts"))
 fdt.writeDtbFile(os.path.join(outdir, "device.dtb"))
+
+@overrides(KernelDiskWorkload)
+def get_default_kernel_args(self) -> List[str]:
+return ["earlycon console=ttyLIO0", "root={root_value}", "ro"]
+
+@overrides(KernelDiskWorkload)
+def get_disk_device(self) -> str:
+return "/dev/lda"
+
+@overrides(KernelDiskWorkload)
+def _add_disk_to_board(self, disk_image: AbstractResource) -> None:
+# Note: This must be called after set_workload because it looks  
for an

+# attribute named 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Update the LupvBoard to use 'requires'

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53084 )


Change subject: stdlib: Update the LupvBoard to use 'requires'
..

stdlib: Update the LupvBoard to use 'requires'

Usage of this function was previously avoided due to a bug which has
since been fixed:
https://gem5-review.googlesource.com/c/public/gem5/+/53003

Change-Id: Idc76ca26d02dcfbb290cebcca297e50e905d8e6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53084
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/experimental/lupv_board.py
1 file changed, 21 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

index e2787d5..d14326c 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -33,7 +33,7 @@
 from ...memory.abstract_memory_system import AbstractMemorySystem
 from ...cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

 from isas import ISA
-from runtime import get_runtime_isa
+from utils.requires import requires

 import m5
 from m5.objects import (
@@ -89,15 +89,12 @@
 cache_hierarchy: AbstractCacheHierarchy,
 ) -> None:

-super().__init__(clk_freq, processor, memory, cache_hierarchy)
-if get_runtime_isa() != ISA.RISCV:
-raise EnvironmentError(
-"RiscvBoard will only work with the RISC-V ISA. Please"
-" recompile gem5 with ISA=RISCV."
-)
+requires(isa_required=ISA.RISCV)
 if cache_hierarchy.is_ruby():
 raise EnvironmentError("RiscvBoard is not compatible with  
Ruby")


+super().__init__(clk_freq, processor, memory, cache_hierarchy)
+
 @overrides(AbstractBoard)
 def _setup_board(self) -> None:


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53084
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idc76ca26d02dcfbb290cebcca297e50e905d8e6d
Gerrit-Change-Number: 53084
Gerrit-PatchSet: 11
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Added new Lupio-IPI device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53041 )


Change subject: dev: Added new Lupio-IPI device
..

dev: Added new Lupio-IPI device

Added the LupIO inter-processor interrupt controller
device which will allow for us to use an SMP system
with the LupIO devices.

Change-Id: Iceab7446b36fb4d9b7605f3ba28665fca509d55d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53041
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/LupioIPI.py
A src/dev/lupio/lupio_ipi.cc
A src/dev/lupio/lupio_ipi.hh
M src/dev/lupio/SConscript
4 files changed, 261 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioIPI.py b/src/dev/lupio/LupioIPI.py
new file mode 100644
index 000..f74c5c6
--- /dev/null
+++ b/src/dev/lupio/LupioIPI.py
@@ -0,0 +1,36 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import Param
+
+class LupioIPI(BasicPioDevice):
+type = 'LupioIPI'
+cxx_class='gem5::LupioIPI'
+cxx_header = 'dev/lupio/lupio_ipi.hh'
+pio_size = Param.Addr(0x1000, "PIO Size")
+int_type = Param.Int("Type of interrupt")
+num_threads = Param.Int("Number of threads")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
index 93600236..47087f0 100644
--- a/src/dev/lupio/SConscript
+++ b/src/dev/lupio/SConscript
@@ -27,6 +27,7 @@
 Import('*')

 SimObject('LupioBLK.py', tags='riscv isa')
+SimObject('LupioIPI.py', tags='riscv isa')
 SimObject('LupioPIC.py', tags='riscv isa')
 SimObject('LupioRNG.py', tags='riscv isa')
 SimObject('LupioRTC.py', tags='riscv isa')
@@ -34,6 +35,7 @@
 SimObject('LupioTTY.py', tags='riscv isa')

 DebugFlag('LupioBLK')
+DebugFlag('LupioIPI')
 DebugFlag('LupioPIC')
 DebugFlag('LupioRNG')
 DebugFlag('LupioRTC')
@@ -41,6 +43,7 @@
 DebugFlag('LupioTTY')

 Source('lupio_blk.cc', tags='riscv isa')
+Source('lupio_ipi.cc', tags='riscv isa')
 Source('lupio_pic.cc', tags='riscv isa')
 Source('lupio_rng.cc', tags='riscv isa')
 Source('lupio_rtc.cc', tags='riscv isa')
diff --git a/src/dev/lupio/lupio_ipi.cc b/src/dev/lupio/lupio_ipi.cc
new file mode 100644
index 000..1504275
--- /dev/null
+++ b/src/dev/lupio/lupio_ipi.cc
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Modified LupV Platform + Board to use LupioPIC + TMR

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53037 )


Change subject: stdlib: Modified LupV Platform + Board to use LupioPIC + TMR
..

stdlib: Modified LupV Platform + Board to use LupioPIC + TMR

This added both the LupioPIC and LupioTMR to the LupVBoard.  While
both the PLIC and CLINT are left in the board for the bootloader
to recognize, they aren't used within the system.  In addition, the
LupV Platform was changed in order to use the LupioPIC to handle
interrupts instead of the PLIC.

Change-Id: I57005903a7ec1136b42433ef5022ccb995abb9d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53037
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/dev/riscv/lupv.cc
M src/dev/riscv/lupv.hh
M src/dev/riscv/LupV.py
M src/python/gem5/components/boards/lupv_board.py
4 files changed, 104 insertions(+), 13 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/riscv/LupV.py b/src/dev/riscv/LupV.py
index d14595e..12273a6 100644
--- a/src/dev/riscv/LupV.py
+++ b/src/dev/riscv/LupV.py
@@ -31,5 +31,5 @@
 type = 'LupV'
 cxx_header = "dev/riscv/lupv.hh"
 cxx_class = 'gem5::LupV'
-pic = Param.Plic("PIC")
+pic = Param.LupioPIC("PIC")
 uart_int_id = Param.Int("Interrupt ID to be used if the PLIC is used  
here")

diff --git a/src/dev/riscv/lupv.cc b/src/dev/riscv/lupv.cc
index 7658b2a..35b8f79 100644
--- a/src/dev/riscv/lupv.cc
+++ b/src/dev/riscv/lupv.cc
@@ -28,7 +28,7 @@

 #include "dev/riscv/lupv.hh"

-#include "dev/riscv/plic.hh"
+#include "dev/lupio/lupio_pic.hh"
 #include "params/LupV.hh"

 namespace gem5
diff --git a/src/dev/riscv/lupv.hh b/src/dev/riscv/lupv.hh
index 0f5fc96..129e9d5 100644
--- a/src/dev/riscv/lupv.hh
+++ b/src/dev/riscv/lupv.hh
@@ -29,8 +29,8 @@
 #ifndef __DEV_RISCV_LUPV_HH__
 #define __DEV_RISCV_LUPV_HH__

+#include "dev/lupio/lupio_pic.hh"
 #include "dev/platform.hh"
-#include "dev/riscv/plic.hh"
 #include "params/LupV.hh"

 namespace gem5
@@ -49,7 +49,7 @@
 class LupV : public Platform
 {
   public:
-Plic *pic;
+LupioPIC *pic;
 int uartIntID;

   public:
diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/lupv_board.py

index 5fb2b13..00ca934 100644
--- a/src/python/gem5/components/boards/lupv_board.py
+++ b/src/python/gem5/components/boards/lupv_board.py
@@ -48,16 +48,16 @@
 Plic,
 Terminal,
 LupioBLK,
+LupioPIC,
 LupioRNG,
 LupioRTC,
+LupioTMR,
 LupioTTY,
 LupV,
 AddrRange,
 CowDiskImage,
 RawDiskImage,
 Frequency,
-RiscvMmioVirtIO,
-VirtIOBlock,
 Port,
 )

@@ -99,6 +99,9 @@

 # Initialize all the devices that we want to use on this board
 # Interrupt IDS for PIC Device
+self._excep_code = { 'INT_SOFT_SUPER': 1, 'INT_TIMER_SUPER': 5,
+ 'INT_TIMER_MACHINE': 7, 'INT_EXT_SUPER': 9,
+ 'INT_EXT_MACHINE': 10 }
 self._int_ids = { 'TTY': 1, 'BLK': 2, 'RNG': 3}

 # CLINT
@@ -107,9 +110,15 @@
 # PLIC
 self.pic = Plic(pio_addr=0xc00)

+# LUPIO PIC
+self.lupio_pic = LupioPIC(
+pio_addr=0x20002000,
+int_type = self._excep_code['INT_EXT_SUPER']
+)
+
 #LupV Platform
 self.lupv = LupV(
-pic = self.pic,
+pic = self.lupio_pic,
 uart_int_id = self._int_ids['TTY']
 )

@@ -130,6 +139,12 @@
 # LUPIO RTC
 self.lupio_rtc = LupioRTC(pio_addr=0x20004000)

+# LUPIO TMR
+self.lupio_tmr = LupioTMR(
+pio_addr=0x20006000,
+int_type = self._excep_code['INT_TIMER_SUPER']
+)
+
 # LUPIO TTY
 self.lupio_tty = LupioTTY(
 pio_addr=0x20007000,
@@ -143,9 +158,18 @@
 self._int_ids['BLK'],
 self._int_ids['RNG']
 ]
-self.pic.n_contexts = self.processor.get_num_cores() * 2
-self.pic.n_src = max(pic_srcs) + 1

+# Set the number of sources to the PIC as 0 because we've removed  
the
+# connections from all the external devices to the PIC, and moved  
them
+# to the LupioPIC.  The PIC and CLINT only remain on the board at  
this

+# point for our bbl to use upon startup, and will
+# remain unused during the simulation
+self.pic.n_src = 0
+self.pic.n_contexts = 0
+self.lupio_pic.n_src = max(pic_srcs) + 1
+self.lupio_pic.num_threads = self.processor.get_num_cores()
+
+self.lupio_tmr.num_threads = self.processor.get_num_cores()
 self.clint.num_threads = self.processor.get_num_cores()

 # Add the RTC
@@ -159,6 +183,8 @@
 self._on_chip_devices = [
 

[gem5-dev] Change in gem5/gem5[develop]: dev: Added new LupIO-PIC device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53036 )


Change subject: dev: Added new LupIO-PIC device
..

dev: Added new LupIO-PIC device

This device is a virtual programmable interrupt controller, and it
manages interrupt requests from up to 32 sources.  It is implemented
as a BasicPioDevice.

The following are the specifications regarding the LupIO-PIC:
https://gitlab.com/luplab/lupio/lupio-specs/-/blob/main/lupio-pic.md
Change-Id: I9ccdb607789f62cc89bdd7392d8e59c8e5c24797
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53036
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/lupio_pic.cc
A src/dev/lupio/lupio_pic.hh
A src/dev/lupio/LupioPIC.py
M src/dev/lupio/SConscript
4 files changed, 328 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioPIC.py b/src/dev/lupio/LupioPIC.py
new file mode 100644
index 000..992501b
--- /dev/null
+++ b/src/dev/lupio/LupioPIC.py
@@ -0,0 +1,38 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import Param
+
+class LupioPIC(BasicPioDevice):
+
+type = 'LupioPIC'
+cxx_class='gem5::LupioPIC'
+cxx_header = 'dev/lupio/lupio_pic.hh'
+pio_size = Param.Addr(0x1000, "PIO Size")
+n_src = Param.Int("Number of interrupt sources")
+num_threads = Param.Int("Number of threads")
+int_type = Param.Int("Type of interrupt")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
index 1eb0187..93600236 100644
--- a/src/dev/lupio/SConscript
+++ b/src/dev/lupio/SConscript
@@ -27,19 +27,22 @@
 Import('*')

 SimObject('LupioBLK.py', tags='riscv isa')
+SimObject('LupioPIC.py', tags='riscv isa')
 SimObject('LupioRNG.py', tags='riscv isa')
 SimObject('LupioRTC.py', tags='riscv isa')
 SimObject('LupioTMR.py', tags='riscv isa')
 SimObject('LupioTTY.py', tags='riscv isa')

 DebugFlag('LupioBLK')
+DebugFlag('LupioPIC')
 DebugFlag('LupioRNG')
 DebugFlag('LupioRTC')
 DebugFlag('LupioTMR')
 DebugFlag('LupioTTY')

 Source('lupio_blk.cc', tags='riscv isa')
+Source('lupio_pic.cc', tags='riscv isa')
 Source('lupio_rng.cc', tags='riscv isa')
 Source('lupio_rtc.cc', tags='riscv isa')
 Source('lupio_tmr.cc', tags='riscv isa')
-Source('lupio_tty.cc', tags='riscv isa')
\ No newline at end of file
+Source('lupio_tty.cc', tags='riscv isa')
diff --git a/src/dev/lupio/lupio_pic.cc b/src/dev/lupio/lupio_pic.cc
new file mode 100644
index 000..010a5d8
--- /dev/null
+++ b/src/dev/lupio/lupio_pic.cc
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used 

[gem5-dev] Change in gem5/gem5[develop]: dev: Modify LupIO-TMR for SMP support

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53039 )


Change subject: dev: Modify LupIO-TMR for SMP support
..

dev: Modify LupIO-TMR for SMP support

Added a new LupioTimer struct, as well as a timer event function for
SMP support.

Change-Id: Idbcc549dfa3c5f8d5342d7e2250337a7482a1ac0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53039
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/dev/lupio/lupio_tmr.cc
M src/dev/lupio/lupio_tmr.hh
M src/dev/lupio/lupio_pic.cc
M src/dev/lupio/lupio_pic.hh
4 files changed, 136 insertions(+), 72 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/lupio_pic.cc b/src/dev/lupio/lupio_pic.cc
index 010a5d8..d83ffcf 100644
--- a/src/dev/lupio/lupio_pic.cc
+++ b/src/dev/lupio/lupio_pic.cc
@@ -34,8 +34,6 @@
 #include "params/LupioPIC.hh"
 #include "sim/system.hh"

-#define LUPIO_PIC_NSRC  32
-
 namespace gem5
 {

@@ -44,23 +42,26 @@
 system(params.system),
 nSrc(params.n_src),
 nThread(params.num_threads),
-intType(params.int_type)
+intType(params.int_type),
+mask{0},
+enable{0}
 {
+// CPU0 receives all IRQ sources by default
+enable[0] = 0x;
 DPRINTF(LupioPIC, "LupioPIC initalized\n");
 }

 void
 LupioPIC::lupioPicUpdateIRQ()
 {
-if (nThread > 1 ) {
-panic("This device currently does not have SMP support\n");
-}
+for (int cpu = 0; cpu < nThread; cpu++) {
+auto tc = system->threads[cpu];

-auto tc = system->threads[0];
-if (pending & mask) {
-tc->getCpuPtr()->postInterrupt(tc->threadId(), intType, 0);
-} else {
-tc->getCpuPtr()->clearInterrupt(tc->threadId(), intType, 0);
+if (enable[cpu] & mask[cpu] & pending) {
+tc->getCpuPtr()->postInterrupt(tc->threadId(), intType, 0);
+} else {
+tc->getCpuPtr()->clearInterrupt(tc->threadId(), intType, 0);
+}
 }
 }

@@ -89,20 +90,26 @@
 {
 uint32_t r = 0;

-switch (addr >> 2) {
+int cpu = addr >> LUPIO_PIC_MAX;
+int reg = (addr >> 2) & (LUPIO_PIC_MAX - 1);
+
+switch (reg) {
 case LUPIO_PIC_PRIO:
 // Value will be 32 if there is no unmasked pending IRQ
-r = ctz32(pending & mask);
+r = ctz32(pending & mask[cpu] & enable[cpu]);
 DPRINTF(LupioPIC, "Read PIC_PRIO: %d\n", r);
 break;
 case LUPIO_PIC_MASK:
-r = mask;
+r = mask[cpu];
 DPRINTF(LupioPIC, "Read PIC_MASK: %d\n", r);
 break;
 case LUPIO_PIC_PEND:
-   r = pending;
+r = (enable[cpu] & pending);
 DPRINTF(LupioPIC, "Read PIC_PEND: %d\n", r);
 break;
+ case LUPIO_PIC_ENAB:
+r = enable[cpu];
+break;

 default:
 panic("Unexpected read to the LupioPIC device at  
address %#llx!",

@@ -117,10 +124,18 @@
 {
 uint32_t val = val64;

-switch (addr >> 2) {
+int cpu = addr >> LUPIO_PIC_MAX;
+int reg = (addr >> 2) & (LUPIO_PIC_MAX - 1);
+
+switch (reg) {
 case LUPIO_PIC_MASK:
-mask = val;
-DPRINTF(LupioPIC, "Write PIC_MASK: %d\n", mask);
+mask[cpu] = val;
+DPRINTF(LupioPIC, "Write PIC_MASK: %d\n", mask[cpu]);
+lupioPicUpdateIRQ();
+break;
+case LUPIO_PIC_ENAB:
+enable[cpu] = val;
+DPRINTF(LupioPIC, "Write PIC_ENAB: %d\n", enable[cpu]);
 lupioPicUpdateIRQ();
 break;

diff --git a/src/dev/lupio/lupio_pic.hh b/src/dev/lupio/lupio_pic.hh
index 2ed1d17..ce4815c 100644
--- a/src/dev/lupio/lupio_pic.hh
+++ b/src/dev/lupio/lupio_pic.hh
@@ -35,6 +35,8 @@
 #include "params/LupioPIC.hh"
 #include "sim/system.hh"

+#define LUPIO_PIC_NSRC 32
+
 namespace gem5
 {

@@ -62,13 +64,18 @@
 LUPIO_PIC_PRIO,
 LUPIO_PIC_MASK,
 LUPIO_PIC_PEND,
+LUPIO_PIC_ENAB,

 // Max offset
 LUPIO_PIC_MAX,
 };

 uint32_t pending = 0;
-uint32_t mask = 0;
+// Register for masking or unmasking up to 32 sources
+uint32_t mask[LUPIO_PIC_NSRC];
+// Regitser to determine which input IRQ is routed to the
+// corresponding processor
+uint32_t enable[LUPIO_PIC_NSRC];

   protected:
 /**
diff --git a/src/dev/lupio/lupio_tmr.cc b/src/dev/lupio/lupio_tmr.cc
index b440015..63c0021 100644
--- a/src/dev/lupio/lupio_tmr.cc
+++ b/src/dev/lupio/lupio_tmr.cc
@@ -34,11 +34,11 @@
 #include "params/LupioTMR.hh"

 // Specific fields for CTRL
-#define LUPIO_TMR_IE0x1
-#define LUPIO_TMR_PD0x2
+#define LUPIO_TMR_IRQE0x1
+#define LUPIO_TMR_PRDC0x2

 // Specific fields for STAT
-#define LUPIO_TMR_EX0x1
+#define 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Moved LupV Board to an experimental folder

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53045 )


Change subject: stdlib: Moved LupV Board to an experimental folder
..

stdlib: Moved LupV Board to an experimental folder

Change-Id: I9cd67177fe8f0cb34bebb4fd3f9d3af0a518c7b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53045
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/SConscript
R src/python/gem5/components/boards/experimental/lupv_board.py
A src/python/gem5/components/boards/experimental/__init__.py
3 files changed, 27 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index 90ac7cd..dd02dd3 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -37,7 +37,10 @@
  
PySource('gem5.components.boards', 'gem5/components/boards/abstract_board.py')

 PySource('gem5.components.boards', 'gem5/components/boards/mem_mode.py')
 PySource('gem5.components.boards', 'gem5/components/boards/riscv_board.py')
-PySource('gem5.components.boards', 'gem5/components/boards/lupv_board.py')
+PySource('gem5.components.boards.experimental',
+'gem5/components/boards/experimental/__init__.py')
+PySource('gem5.components.boards.experimental',
+'gem5/components/boards/experimental/lupv_board.py')
  
PySource('gem5.components.boards', 'gem5/components/boards/simple_board.py')

 PySource('gem5.components.boards', 'gem5/components/boards/test_board.py')
 PySource('gem5.components.boards', 'gem5/components/boards/x86_board.py')
diff --git a/src/python/gem5/components/boards/experimental/__init__.py  
b/src/python/gem5/components/boards/experimental/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/components/boards/experimental/__init__.py
diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

similarity index 97%
rename from src/python/gem5/components/boards/lupv_board.py
rename to src/python/gem5/components/boards/experimental/lupv_board.py
index c6073a8..28aa209 100644
--- a/src/python/gem5/components/boards/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -27,14 +27,14 @@
 import os
 from typing import Optional

-from ...utils.override import overrides
-from .simple_board import SimpleBoard
-from .abstract_board import AbstractBoard
-from ..processors.abstract_processor import AbstractProcessor
-from ..memory.abstract_memory_system import AbstractMemorySystem
-from ..cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

-from ...isas import ISA
-from ...runtime import get_runtime_isa
+from utils.override import overrides
+from ..simple_board import SimpleBoard
+from ..abstract_board import AbstractBoard
+from ...processors.abstract_processor import AbstractProcessor
+from ...memory.abstract_memory_system import AbstractMemorySystem
+from ...cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

+from isas import ISA
+from runtime import get_runtime_isa

 import m5
 from m5.objects import (
@@ -173,10 +173,10 @@
 self._int_ids['RNG']
 ]

-# Set the number of sources to the PIC as 0 because we've removed  
the
+# Set the number of sources to the PIC as 0 because we've removed  
the
 # connections from all the external devices to the PIC, and moved  
them
 # to the LupioPIC.  The PIC and CLINT only remain on the board at  
this

-# point for our bbl to use upon startup, and will
+# point for our bbl to use upon startup, and will
 # remain unused during the simulation
 self.pic.n_src = 0
 self.pic.n_contexts = 0

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9cd67177fe8f0cb34bebb4fd3f9d3af0a518c7b6
Gerrit-Change-Number: 53045
Gerrit-PatchSet: 11
Gerrit-Owner: melissa jost 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Added new Lupio-SYS device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53043 )


Change subject: dev: Added new Lupio-SYS device
..

dev: Added new Lupio-SYS device

This adds the LupIO system controller, in which we provide a
way to halt or reboot the system.  It is implemented as a
BasicPIODevice.

Change-Id: I0031ac65d2aaca3460dcd4c59543a75230b0b52a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53043
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/lupio_sys.cc
A src/dev/lupio/lupio_sys.hh
A src/dev/lupio/LupioSYS.py
M src/dev/lupio/SConscript
4 files changed, 234 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioSYS.py b/src/dev/lupio/LupioSYS.py
new file mode 100644
index 000..d300e91
--- /dev/null
+++ b/src/dev/lupio/LupioSYS.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import Param
+
+class LupioSYS(BasicPioDevice):
+type = 'LupioSYS'
+cxx_class='gem5::LupioSYS'
+cxx_header = 'dev/lupio/lupio_sys.hh'
+pio_size = Param.Addr(0x1000, "PIO Size")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
index 47087f0..82fb81e 100644
--- a/src/dev/lupio/SConscript
+++ b/src/dev/lupio/SConscript
@@ -33,6 +33,7 @@
 SimObject('LupioRTC.py', tags='riscv isa')
 SimObject('LupioTMR.py', tags='riscv isa')
 SimObject('LupioTTY.py', tags='riscv isa')
+SimObject('LupioSYS.py', tags='riscv isa')

 DebugFlag('LupioBLK')
 DebugFlag('LupioIPI')
@@ -41,6 +42,7 @@
 DebugFlag('LupioRTC')
 DebugFlag('LupioTMR')
 DebugFlag('LupioTTY')
+DebugFlag('LupioSYS')

 Source('lupio_blk.cc', tags='riscv isa')
 Source('lupio_ipi.cc', tags='riscv isa')
@@ -49,3 +51,4 @@
 Source('lupio_rtc.cc', tags='riscv isa')
 Source('lupio_tmr.cc', tags='riscv isa')
 Source('lupio_tty.cc', tags='riscv isa')
+Source('lupio_sys.cc', tags='riscv isa')
diff --git a/src/dev/lupio/lupio_sys.cc b/src/dev/lupio/lupio_sys.cc
new file mode 100644
index 000..0596b0e
--- /dev/null
+++ b/src/dev/lupio/lupio_sys.cc
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Update the LupvBoard to account for stdlib changes

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53083 )


Change subject: stdlib: Update the LupvBoard to account for stdlib changes
..

stdlib: Update the LupvBoard to account for stdlib changes

This patch updates the board to account for the following changes:

* https://gem5-review.googlesource.com/c/public/gem5/+/51790
* https://gem5-review.googlesource.com/c/public/gem5/+/52184
* https://gem5-review.googlesource.com/c/public/gem5/+/52183

These changes, broadly speaking, remove the SimpeBoard as a superclass
and instead have all the boards inherit directly from the AbstractBoard.
It also fixes the order of operations (the order in which components are
incorporated and the board it setup).

Change-Id: I829ed515da28163cafbd292a9c141be4d350636e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53083
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/experimental/lupv_board.py
1 file changed, 43 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py  
b/src/python/gem5/components/boards/experimental/lupv_board.py

index 28aa209..e2787d5 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -25,10 +25,9 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 import os
-from typing import Optional
+from typing import Optional, List

 from utils.override import overrides
-from ..simple_board import SimpleBoard
 from ..abstract_board import AbstractBoard
 from ...processors.abstract_processor import AbstractProcessor
 from ...memory.abstract_memory_system import AbstractMemorySystem
@@ -72,7 +71,7 @@
 FdtState,
 )

-class LupvBoard(SimpleBoard):
+class LupvBoard(AbstractBoard):
 """
 A board capable of full system simulation for RISC-V.
 This board uses a set of LupIO education-friendly devices.
@@ -89,6 +88,7 @@
 memory: AbstractMemorySystem,
 cache_hierarchy: AbstractCacheHierarchy,
 ) -> None:
+
 super().__init__(clk_freq, processor, memory, cache_hierarchy)
 if get_runtime_isa() != ISA.RISCV:
 raise EnvironmentError(
@@ -97,6 +97,10 @@
 )
 if cache_hierarchy.is_ruby():
 raise EnvironmentError("RiscvBoard is not compatible with  
Ruby")

+
+@overrides(AbstractBoard)
+def _setup_board(self) -> None:
+
 self.workload = RiscvLinux()

 # Initialize all the devices that we want to use on this board
@@ -240,6 +244,17 @@
 )

 @overrides(AbstractBoard)
+def has_dma_ports(self) -> bool:
+return False
+
+@overrides(AbstractBoard)
+def get_dma_ports(self) -> List[Port]:
+raise NotImplementedError(
+"The LupvBoard does not have DMA Ports. "
+"Use `has_dma_ports()` to check this."
+)
+
+@overrides(AbstractBoard)
 def has_io_bus(self) -> bool:
 return True

@@ -254,7 +269,7 @@
 return self.iobus.mem_side_ports

 @overrides(AbstractBoard)
-def setup_memory_ranges(self):
+def _setup_memory_ranges(self):
 memory = self.get_memory()
 mem_size = memory.get_size()
 self.mem_ranges = [AddrRange(start=0x8000, size=mem_size)]

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I829ed515da28163cafbd292a9c141be4d350636e
Gerrit-Change-Number: 53083
Gerrit-PatchSet: 11
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Added LupIO-IPI to the LupV Board

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53042 )


Change subject: stdlib: Added LupIO-IPI to the LupV Board
..

stdlib: Added LupIO-IPI to the LupV Board

This adds the LupioIPI device to our LupV Board, which
finalizes the changes needed for the LupIO devices to run
with SMP support.

Change-Id: I3e51dae6d8d589d3b38c57c33322e740c832a03d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53042
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/lupv_board.py
1 file changed, 46 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/lupv_board.py

index 00ca934..11a9ebc 100644
--- a/src/python/gem5/components/boards/lupv_board.py
+++ b/src/python/gem5/components/boards/lupv_board.py
@@ -48,6 +48,7 @@
 Plic,
 Terminal,
 LupioBLK,
+LupioIPI,
 LupioPIC,
 LupioRNG,
 LupioRTC,
@@ -110,10 +111,18 @@
 # PLIC
 self.pic = Plic(pio_addr=0xc00)

+# LUPIO IPI
+self.lupio_ipi = LupioIPI(
+pio_addr=0x20001000,
+int_type=self._excep_code['INT_SOFT_SUPER'],
+num_threads = self.processor.get_num_cores()
+)
+
 # LUPIO PIC
 self.lupio_pic = LupioPIC(
 pio_addr=0x20002000,
-int_type = self._excep_code['INT_EXT_SUPER']
+int_type = self._excep_code['INT_EXT_SUPER'],
+num_threads = self.processor.get_num_cores()
 )

 #LupV Platform
@@ -142,7 +151,8 @@
 # LUPIO TMR
 self.lupio_tmr = LupioTMR(
 pio_addr=0x20006000,
-int_type = self._excep_code['INT_TIMER_SUPER']
+int_type = self._excep_code['INT_TIMER_SUPER'],
+num_threads = self.processor.get_num_cores()
 )

 # LUPIO TTY
@@ -183,6 +193,7 @@
 self._on_chip_devices = [
 self.clint,
 self.pic,
+self.lupio_ipi,
 self.lupio_pic,
 self.lupio_tmr
 ]
@@ -423,6 +434,22 @@

 soc_node.append(plic_node)

+# LupioIPI Device
+lupio_ipi = self.lupio_ipi
+lupio_ipi_node = lupio_ipi.generateBasicPioDeviceNode(soc_state,
+"lupio-ipi", lupio_ipi.pio_addr,
+lupio_ipi.pio_size)
+int_extended = list()
+for i, core in enumerate(self.get_processor().get_cores()):
+phandle = state.phandle(f"cpu@{i}.int_state")
+int_extended.append(phandle)
+int_extended.append(self._excep_code['INT_SOFT_SUPER'])
+lupio_ipi_node.append(
+FdtPropertyWords("interrupts-extended", int_extended))
+lupio_ipi_node.append(FdtProperty("interrupt-controller"))
+lupio_ipi_node.appendCompatible(["lupio,ipi"])
+soc_node.append(lupio_ipi_node)
+
 # LupioPIC Device
 lupio_pic = self.lupio_pic
 lupio_pic_node = lupio_pic.generateBasicPioDeviceNode(soc_state,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e51dae6d8d589d3b38c57c33322e740c832a03d
Gerrit-Change-Number: 53042
Gerrit-PatchSet: 11
Gerrit-Owner: melissa jost 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Added Lupio-SYS device to LupV Board

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53044 )


Change subject: stdlib: Added Lupio-SYS device to LupV Board
..

stdlib: Added Lupio-SYS device to LupV Board

This adds the Lupio-SYS device to the LupV Board, which finalizes
all of the devices needed to complete the LupIO device
collection within gem5.

Change-Id: I5af34d8c2735d74f4240d3077ed162dd25f2bcb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53044
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/lupv_board.py
1 file changed, 46 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/lupv_board.py

index 11a9ebc..c6073a8 100644
--- a/src/python/gem5/components/boards/lupv_board.py
+++ b/src/python/gem5/components/boards/lupv_board.py
@@ -54,6 +54,7 @@
 LupioRTC,
 LupioTMR,
 LupioTTY,
+LupioSYS,
 LupV,
 AddrRange,
 CowDiskImage,
@@ -148,6 +149,9 @@
 # LUPIO RTC
 self.lupio_rtc = LupioRTC(pio_addr=0x20004000)

+#LUPIO SYS
+self.lupio_sys = LupioSYS(pio_addr= 0x20003000)
+
 # LUPIO TMR
 self.lupio_tmr = LupioTMR(
 pio_addr=0x20006000,
@@ -200,6 +204,7 @@
 self._off_chip_devices = [
 self.lupio_blk,
 self.lupio_tty,
+self.lupio_sys,
 self.lupio_rng,
 self.lupio_rtc
 ]
@@ -265,6 +270,7 @@
 script to start the simulaiton.
 After the workload is set up, this function will generate the  
device

 tree file and output it to the output directory.
+
 **Limitations**
 * Only supports a Linux kernel
 * Must use the provided bootloader and disk image as denoted in the
@@ -497,6 +503,29 @@
 state.phandle(self.lupio_pic)))
 soc_node.append(lupio_rng_node)

+#LupioSYS Device
+lupio_sys = self.lupio_sys
+lupio_sys_node = lupio_sys.generateBasicPioDeviceNode(soc_state,
+"lupio-sys", lupio_sys.pio_addr,  
lupio_sys.pio_size)

+lupio_sys_node.appendCompatible(["syscon"])
+sys_phandle = state.phandle(self.lupio_sys)
+lupio_sys_node.append(FdtPropertyWords("phandle", [sys_phandle]))
+soc_node.append(lupio_sys_node)
+
+poweroff_node = FdtNode("poweroff")
+poweroff_node.appendCompatible(["syscon-poweroff"])
+poweroff_node.append(FdtPropertyWords("regmap", [sys_phandle]))
+poweroff_node.append(FdtPropertyWords("offset", [0x0]))
+poweroff_node.append(FdtPropertyWords("value", [1]))
+soc_node.append(poweroff_node)
+
+reboot_node = FdtNode("reboot")
+reboot_node.appendCompatible(["syscon-reboot"])
+reboot_node.append(FdtPropertyWords("regmap", [sys_phandle]))
+reboot_node.append(FdtPropertyWords("offset", [0x4]))
+reboot_node.append(FdtPropertyWords("value", [1]))
+soc_node.append(reboot_node)
+
 # LupioRTC Device
 lupio_rtc = self.lupio_rtc
 lupio_rtc_node = lupio_rtc.generateBasicPioDeviceNode(

--
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Gerrit-Change-Number: 53044
Gerrit-PatchSet: 11
Gerrit-Owner: melissa jost 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Modified LupioBLK and LupioTTY to use LupioPIC

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53038 )


Change subject: dev: Modified LupioBLK and LupioTTY to use LupioPIC
..

dev: Modified LupioBLK and LupioTTY to use LupioPIC

This replaced the PLIC device within the LupioBLK and
LupioTTY with the LupioPIC, so that interrupts now go
through the LupioPIC, and the PLIC isn't used anymore.

Change-Id: I0eb5d5c5df9cb43cfb5e8e3a5bf4176f48320696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53038
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/dev/lupio/lupio_tty.hh
M src/dev/lupio/lupio_blk.hh
2 files changed, 19 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/lupio_blk.hh b/src/dev/lupio/lupio_blk.hh
index c767ad1..4e56164 100644
--- a/src/dev/lupio/lupio_blk.hh
+++ b/src/dev/lupio/lupio_blk.hh
@@ -32,6 +32,7 @@
 #include "debug/LupioBLK.hh"
 #include "dev/dma_device.hh"
 #include "dev/io_device.hh"
+#include "dev/lupio/lupio_pic.hh"
 #include "dev/platform.hh"
 #include "dev/storage/disk_image.hh"
 #include "params/LupioBLK.hh"
diff --git a/src/dev/lupio/lupio_tty.hh b/src/dev/lupio/lupio_tty.hh
index 1124193..e971a9f 100644
--- a/src/dev/lupio/lupio_tty.hh
+++ b/src/dev/lupio/lupio_tty.hh
@@ -30,6 +30,7 @@
 #define __LUPIO_TTY_HH__

 #include "dev/io_device.hh"
+#include "dev/lupio/lupio_pic.hh"
 #include "dev/platform.hh"
 #include "dev/serial/serial.hh"
 #include "params/LupioTTY.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0eb5d5c5df9cb43cfb5e8e3a5bf4176f48320696
Gerrit-Change-Number: 53038
Gerrit-PatchSet: 11
Gerrit-Owner: melissa jost 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Added new Lupio-BLK Device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53033 )


Change subject: dev: Added new Lupio-BLK Device
..

dev: Added new Lupio-BLK Device

This is a virtual block device that provides a disk-like interface
for second level storage.  It is implemented as a DMADevice, and
allows for the transfer of blocks from the block device to main
memory, and vice versa.

The following are the specifications regarding the LupIO-BLK:
https://gitlab.com/luplab/lupio/lupio-specs/-/blob/main/lupio-blk.md

Change-Id: Ifabc9b715fadb218e84952694d666b803e46e1f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53033
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/LupioBLK.py
A src/dev/lupio/lupio_blk.cc
A src/dev/lupio/lupio_blk.hh
M src/dev/lupio/SConscript
4 files changed, 421 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioBLK.py b/src/dev/lupio/LupioBLK.py
new file mode 100644
index 000..fc3479f
--- /dev/null
+++ b/src/dev/lupio/LupioBLK.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import DmaDevice
+
+from m5.params import Param
+from m5.proxy import Parent
+
+class LupioBLK(DmaDevice):
+
+type = 'LupioBLK'
+cxx_class='gem5::LupioBLK'
+cxx_header = 'dev/lupio/lupio_blk.hh'
+pio_size = Param.Addr(0x1000, "PIO Size")
+image = Param.DiskImage("Disk image")
+pio_addr = Param.Addr("Device Address")
+latency = Param.Latency('0ns', "DMA Device Latency")
+platform = Param.Platform(Parent.any,
+  "Platform this device is part of.")
+int_id = Param.Int("Interrupt ID for the PIC to use")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
index c5d6b8f..1ea8a82 100644
--- a/src/dev/lupio/SConscript
+++ b/src/dev/lupio/SConscript
@@ -26,14 +26,17 @@

 Import('*')

+SimObject('LupioBLK.py', tags='riscv isa')
 SimObject('LupioRNG.py', tags='riscv isa')
 SimObject('LupioRTC.py', tags='riscv isa')
 SimObject('LupioTTY.py', tags='riscv isa')

+DebugFlag('LupioBLK')
 DebugFlag('LupioRNG')
 DebugFlag('LupioRTC')
 DebugFlag('LupioTTY')

+Source('lupio_blk.cc', tags='riscv isa')
 Source('lupio_rng.cc', tags='riscv isa')
 Source('lupio_rtc.cc', tags='riscv isa')
 Source('lupio_tty.cc', tags='riscv isa')
diff --git a/src/dev/lupio/lupio_blk.cc b/src/dev/lupio/lupio_blk.cc
new file mode 100644
index 000..796c71c
--- /dev/null
+++ b/src/dev/lupio/lupio_blk.cc
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Added LupioBLK Device to LupVBoard

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53034 )


Change subject: stdlib: Added LupioBLK Device to LupVBoard
..

stdlib: Added LupioBLK Device to LupVBoard

This adds the LupioBLK device to the growing LupVBoard,
as well as removes the VirtIOMMIO Device from the board.

Change-Id: Ibb45ecff07c7ce5d5d7be8cd8e20e9f62b591b02
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53034
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/lupv_board.py
1 file changed, 43 insertions(+), 24 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/lupv_board.py

index 932fcd7..5fb2b13 100644
--- a/src/python/gem5/components/boards/lupv_board.py
+++ b/src/python/gem5/components/boards/lupv_board.py
@@ -47,6 +47,7 @@
 Clint,
 Plic,
 Terminal,
+LupioBLK,
 LupioRNG,
 LupioRTC,
 LupioTTY,
@@ -98,7 +99,7 @@

 # Initialize all the devices that we want to use on this board
 # Interrupt IDS for PIC Device
-self._int_ids = { 'TTY': 1, 'DISK': 2, 'RNG': 3}
+self._int_ids = { 'TTY': 1, 'BLK': 2, 'RNG': 3}

 # CLINT
 self.clint = Clint(pio_addr=0x200)
@@ -112,6 +113,13 @@
 uart_int_id = self._int_ids['TTY']
 )

+# LUPIO BLK
+self.lupio_blk = LupioBLK(
+pio_addr=0x2000,
+platform = self.lupv,
+int_id = self._int_ids['BLK']
+)
+
 # LUPIO RNG
 self.lupio_rng = LupioRNG(
 pio_addr=0x20005000,
@@ -122,14 +130,6 @@
 # LUPIO RTC
 self.lupio_rtc = LupioRTC(pio_addr=0x20004000)

-# VirtIO Disk
-self.disk = RiscvMmioVirtIO(
-vio=VirtIOBlock(),
-interrupt_id=self._int_ids['DISK'],
-pio_size=4096,
-pio_addr=0x10008000,
-)
-
 # LUPIO TTY
 self.lupio_tty = LupioTTY(
 pio_addr=0x20007000,
@@ -140,7 +140,7 @@

 pic_srcs = [
 self._int_ids['TTY'],
-self._int_ids['DISK'],
+self._int_ids['BLK'],
 self._int_ids['RNG']
 ]
 self.pic.n_contexts = self.processor.get_num_cores() * 2
@@ -161,8 +161,8 @@
 self.pic,
 ]
 self._off_chip_devices = [
+self.lupio_blk,
 self.lupio_tty,
-self.disk,
 self.lupio_rng,
 self.lupio_rtc
 ]
@@ -171,6 +171,7 @@
 """Connect the I/O devices to the I/O bus"""
 for device in self._off_chip_devices:
 device.pio = self.iobus.mem_side_ports
+self.lupio_blk.dma = self.iobus.cpu_side_ports

 for device in self._on_chip_devices:
 device.pio = self.get_cache_hierarchy().get_mem_side_port()
@@ -239,12 +240,12 @@
 read_only=False
 )
 image.child.image_file = disk_image
-self.disk.vio.image = image
+self.lupio_blk.image = image

 # Linux boot command flags
 kernel_cmd = [
 "earlycon console=ttyLIO0",
-"root=/dev/vda1",
+"root=/dev/lda1",
 "ro"
 ]
 self.workload.command_line = " ".join(kernel_cmd)
@@ -370,17 +371,19 @@

 soc_node.append(plic_node)

-# VirtIO MMIO disk node
-disk = self.disk
-disk_node = disk.generateBasicPioDeviceNode(
-soc_state, "virtio_mmio", disk.pio_addr, disk.pio_size
-)
-disk_node.append(FdtPropertyWords("interrupts",  
[disk.interrupt_id]))

-disk_node.append(
-FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
-)
-disk_node.appendCompatible(["virtio,mmio"])
-soc_node.append(disk_node)
+# LupioBLK Device
+lupio_blk = self.lupio_blk
+lupio_blk_node = lupio_blk.generateBasicPioDeviceNode(soc_state,
+"lupio-blk", lupio_blk.pio_addr,
+lupio_blk.pio_size)
+lupio_blk_node.appendCompatible(["lupio,blk"])
+lupio_blk_node.append(
+FdtPropertyWords("interrupts",
+[self.lupio_blk.int_id]))
+lupio_blk_node.append(
+FdtPropertyWords("interrupt-parent",
+state.phandle(self.pic)))
+soc_node.append(lupio_blk_node)

 # LupioRNG Device
 lupio_rng = self.lupio_rng

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop

[gem5-dev] Change in gem5/gem5[develop]: dev: Added new LupIO-RTC device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53026 )


Change subject: dev: Added new LupIO-RTC device
..

dev: Added new LupIO-RTC device

This device supplies the computer system with the simulated time by
retrieving the current tick number and converting to seconds, then
returning that time in ISO 8601 format. It is implemented as a
BasicPioDevice and is read-only.

The following are the specifications regarding the LupIO-RTC:
https://gitlab.com/luplab/lupio/lupio-specs/-/blob/main/lupio-rtc.md

Change-Id: Ic99291e5c862e728dac90b15ca818d42f25cbbee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53026
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/lupio_rtc.cc
A src/dev/lupio/lupio_rtc.hh
A src/dev/lupio/SConscript
A src/dev/lupio/LupioRTC.py
4 files changed, 302 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioRTC.py b/src/dev/lupio/LupioRTC.py
new file mode 100644
index 000..8392e65
--- /dev/null
+++ b/src/dev/lupio/LupioRTC.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import Param
+
+class LupioRTC(BasicPioDevice):
+type = 'LupioRTC'
+cxx_class='gem5::LupioRTC'
+cxx_header = 'dev/lupio/lupio_rtc.hh'
+time = Param.Time('01/01/2020', "Initial system time to use")
+pio_size = Param.Addr(0x1000, "PIO Size")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
new file mode 100644
index 000..30fbbe0
--- /dev/null
+++ b/src/dev/lupio/SConscript
@@ -0,0 +1,33 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+SimObject('LupioRTC.py', tags='riscv 

[gem5-dev] Change in gem5/gem5[develop]: dev: Added new LupIO-RNG device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53029 )


Change subject: dev: Added new LupIO-RNG device
..

dev: Added new LupIO-RNG device

This device is a random number generator that uses the Mersenne
Twister in order to provide the system with a set of random
numbers.  It is implemented as a BasicPioDevice, and has both
read and write capabilities.

The following are the specifications regarding the LupIO-RNG:
https://gitlab.com/luplab/lupio/lupio-specs/-/blob/main/lupio-rng.md

Change-Id: Ia6aeb610ebe5589ed1f1548b823c5165236b03e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53029
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/LupioRNG.py
A src/dev/lupio/lupio_rng.cc
A src/dev/lupio/lupio_rng.hh
M src/dev/lupio/SConscript
4 files changed, 291 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioRNG.py b/src/dev/lupio/LupioRNG.py
new file mode 100644
index 000..c6d2c17
--- /dev/null
+++ b/src/dev/lupio/LupioRNG.py
@@ -0,0 +1,40 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import Param
+from m5.proxy import Parent
+
+class LupioRNG(BasicPioDevice):
+
+type = 'LupioRNG'
+cxx_class='gem5::LupioRNG'
+cxx_header = 'dev/lupio/lupio_rng.hh'
+pio_size = Param.Addr(0x1000, "PIO Size")
+seed = Param.Int(0, "Initial seed for the random number generator")
+platform = Param.Platform(Parent.any,
+  "Platform this device is part of.")
+int_id = Param.Int("Interrupt ID to be used by the PIC")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
index 30fbbe0..775412c 100644
--- a/src/dev/lupio/SConscript
+++ b/src/dev/lupio/SConscript
@@ -27,7 +27,10 @@
 Import('*')

 SimObject('LupioRTC.py', tags='riscv isa')
+SimObject('LupioRNG.py', tags='riscv isa')

+DebugFlag('LupioRNG')
 DebugFlag('LupioRTC')

 Source('lupio_rtc.cc', tags='riscv isa')
+Source('lupio_rng.cc', tags='riscv isa')
diff --git a/src/dev/lupio/lupio_rng.cc b/src/dev/lupio/lupio_rng.cc
new file mode 100644
index 000..f3036de
--- /dev/null
+++ b/src/dev/lupio/lupio_rng.cc
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ 

[gem5-dev] Change in gem5/gem5[develop]: dev: Added new LupIO-TTY device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53031 )


Change subject: dev: Added new LupIO-TTY device
..

dev: Added new LupIO-TTY device

This device is notfied when data is available from the terminal
(e.g. from keyboard input) in order to receive characters. It also
transmits characters to the terminal to be displayed.

The following are the specifications regarding the LupIO-TTY:
https://gitlab.com/luplab/lupio/lupio-specs/-/blob/main/lupio-tty.md

Change-Id: Icc8294984989cfa422d8ed227da39debfa49ab36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53031
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/lupio_tty.cc
A src/dev/lupio/lupio_tty.hh
A src/dev/lupio/LupioTTY.py
M src/dev/lupio/SConscript
4 files changed, 358 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioTTY.py b/src/dev/lupio/LupioTTY.py
new file mode 100644
index 000..972311f
--- /dev/null
+++ b/src/dev/lupio/LupioTTY.py
@@ -0,0 +1,40 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import Param
+from m5.proxy import Parent
+
+from m5.objects.Device import BasicPioDevice
+
+class LupioTTY(BasicPioDevice):
+type = 'LupioTTY'
+cxx_class = 'gem5::LupioTTY'
+cxx_header = "dev/lupio/lupio_tty.hh"
+terminal = Param.SerialDevice(Parent.any, "The terminal")
+pio_size = Param.Addr(0x1000, "PIO size")
+platform = Param.Platform(Parent.any,
+  "Platform this device is part of.")
+int_id = Param.Int("Interrupt ID for the PIC to use")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
index 775412c..c5d6b8f 100644
--- a/src/dev/lupio/SConscript
+++ b/src/dev/lupio/SConscript
@@ -26,11 +26,14 @@

 Import('*')

-SimObject('LupioRTC.py', tags='riscv isa')
 SimObject('LupioRNG.py', tags='riscv isa')
+SimObject('LupioRTC.py', tags='riscv isa')
+SimObject('LupioTTY.py', tags='riscv isa')

 DebugFlag('LupioRNG')
 DebugFlag('LupioRTC')
+DebugFlag('LupioTTY')

-Source('lupio_rtc.cc', tags='riscv isa')
 Source('lupio_rng.cc', tags='riscv isa')
+Source('lupio_rtc.cc', tags='riscv isa')
+Source('lupio_tty.cc', tags='riscv isa')
diff --git a/src/dev/lupio/lupio_tty.cc b/src/dev/lupio/lupio_tty.cc
new file mode 100644
index 000..0989947
--- /dev/null
+++ b/src/dev/lupio/lupio_tty.cc
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 

[gem5-dev] Change in gem5/gem5[develop]: dev: Added new LupIO-TMR device

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53035 )


Change subject: dev: Added new LupIO-TMR device
..

dev: Added new LupIO-TMR device

This device is a virtual timer that provides both a real-time
counter, as well as a configurable timer with periodic and
one-shot modes.  It uses Ticks to measure time, and is
implemented as a BasicPioDevice.

The following are the specifications regarding the LupIO-TMR:
https://gitlab.com/luplab/lupio/lupio-specs/-/blob/main/lupio-tmr.md

Change-Id: I6fd6f4926494a44d20e1e0289f502535e84d7a69
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53035
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/lupio/lupio_tmr.cc
A src/dev/lupio/lupio_tmr.hh
A src/dev/lupio/LupioTMR.py
M src/dev/lupio/SConscript
4 files changed, 384 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/lupio/LupioTMR.py b/src/dev/lupio/LupioTMR.py
new file mode 100644
index 000..93340da
--- /dev/null
+++ b/src/dev/lupio/LupioTMR.py
@@ -0,0 +1,36 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import Param
+
+class LupioTMR(BasicPioDevice):
+type = 'LupioTMR'
+cxx_class='gem5::LupioTMR'
+cxx_header = 'dev/lupio/lupio_tmr.hh'
+pio_size = Param.Addr(0x1000, "PIO Size")
+num_threads = Param.Int("Number of threads in the system.")
+int_type = Param.Int("Type of interrupt.")
diff --git a/src/dev/lupio/SConscript b/src/dev/lupio/SConscript
index 1ea8a82..1eb0187 100644
--- a/src/dev/lupio/SConscript
+++ b/src/dev/lupio/SConscript
@@ -29,14 +29,17 @@
 SimObject('LupioBLK.py', tags='riscv isa')
 SimObject('LupioRNG.py', tags='riscv isa')
 SimObject('LupioRTC.py', tags='riscv isa')
+SimObject('LupioTMR.py', tags='riscv isa')
 SimObject('LupioTTY.py', tags='riscv isa')

 DebugFlag('LupioBLK')
 DebugFlag('LupioRNG')
 DebugFlag('LupioRTC')
+DebugFlag('LupioTMR')
 DebugFlag('LupioTTY')

 Source('lupio_blk.cc', tags='riscv isa')
 Source('lupio_rng.cc', tags='riscv isa')
 Source('lupio_rtc.cc', tags='riscv isa')
-Source('lupio_tty.cc', tags='riscv isa')
+Source('lupio_tmr.cc', tags='riscv isa')
+Source('lupio_tty.cc', tags='riscv isa')
\ No newline at end of file
diff --git a/src/dev/lupio/lupio_tmr.cc b/src/dev/lupio/lupio_tmr.cc
new file mode 100644
index 000..b440015
--- /dev/null
+++ b/src/dev/lupio/lupio_tmr.cc
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Introduced new LupV Board

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53028 )


 (

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Introduced new LupV Board
..

stdlib: Introduced new LupV Board

This LupV Board was created in order to connect all of the LupIO
devices, and allow us to run a full RISC-V system with them.  As
the LupIO devices continue to be added, they will be integrated
into this board, and replace the current IO components.

The LupIO devices are a collection of processor
agnostic and easily implemented virtual devices. Details about the
specifications of all eight LupIO devices can be found here:
https://gitlab.com/luplab/lupio/lupio-specs

Information about how to build a RISCV full system with the LupIO-RTC
can be found here:
https://github.com/darchr/lupio-gem5/blob/lupio/README.md

Change-Id: I7d3186d3778d40b38027f245290432dbf4279dea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53028
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/SConscript
A src/python/gem5/components/boards/lupv_board.py
2 files changed, 426 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index 3d91ccb..90ac7cd 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -37,6 +37,7 @@
  
PySource('gem5.components.boards', 'gem5/components/boards/abstract_board.py')

 PySource('gem5.components.boards', 'gem5/components/boards/mem_mode.py')
 PySource('gem5.components.boards', 'gem5/components/boards/riscv_board.py')
+PySource('gem5.components.boards', 'gem5/components/boards/lupv_board.py')
  
PySource('gem5.components.boards', 'gem5/components/boards/simple_board.py')

 PySource('gem5.components.boards', 'gem5/components/boards/test_board.py')
 PySource('gem5.components.boards', 'gem5/components/boards/x86_board.py')
diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/lupv_board.py

new file mode 100644
index 000..18f0337
--- /dev/null
+++ b/src/python/gem5/components/boards/lupv_board.py
@@ -0,0 +1,398 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+from typing import Optional
+
+from ...utils.override import overrides
+from .simple_board import SimpleBoard
+from .abstract_board import AbstractBoard
+from ..processors.abstract_processor import AbstractProcessor
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

+from ...isas import ISA
+from ...runtime import get_runtime_isa
+
+import m5
+from m5.objects import (
+Bridge,
+PMAChecker,
+RiscvLinux,
+RiscvRTC,
+AddrRange,
+IOXBar,
+Clint,
+Plic,
+Uart8250,
+Terminal,
+LupioRTC,
+LupV,
+AddrRange,
+CowDiskImage,
+RawDiskImage,
+Frequency,
+RiscvMmioVirtIO,
+VirtIOBlock,
+Port,
+)
+
+from m5.util.fdthelper import (
+Fdt,
+FdtNode,
+FdtProperty,
+FdtPropertyStrings,
+FdtPropertyWords,
+FdtState,
+)
+
+class LupvBoard(SimpleBoard):
+"""
+A board capable of full system 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Added LupioTTY to LupVBoard

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53032 )


Change subject: stdlib: Added LupioTTY to LupVBoard
..

stdlib: Added LupioTTY to LupVBoard

This added the new LupioTTY device to the growing
LupVBoard, and replaced the Uart8250 device in this
system.

Change-Id: Ib9a09565e8522178fd9c9f900db9d3b87e8b48fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53032
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/lupv_board.py
1 file changed, 42 insertions(+), 23 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/lupv_board.py

index 0316def..932fcd7 100644
--- a/src/python/gem5/components/boards/lupv_board.py
+++ b/src/python/gem5/components/boards/lupv_board.py
@@ -46,10 +46,10 @@
 IOXBar,
 Clint,
 Plic,
-Uart8250,
 Terminal,
 LupioRNG,
 LupioRTC,
+LupioTTY,
 LupV,
 AddrRange,
 CowDiskImage,
@@ -98,7 +98,7 @@

 # Initialize all the devices that we want to use on this board
 # Interrupt IDS for PIC Device
-self._int_ids = { 'UART': 1, 'DISK': 2, 'RNG': 3}
+self._int_ids = { 'TTY': 1, 'DISK': 2, 'RNG': 3}

 # CLINT
 self.clint = Clint(pio_addr=0x200)
@@ -109,7 +109,7 @@
 #LupV Platform
 self.lupv = LupV(
 pic = self.pic,
-uart_int_id = self._int_ids['UART']
+uart_int_id = self._int_ids['TTY']
 )

 # LUPIO RNG
@@ -130,12 +130,16 @@
 pio_addr=0x10008000,
 )

-# UART
-self.uart = Uart8250(pio_addr=0x1000)
+# LUPIO TTY
+self.lupio_tty = LupioTTY(
+pio_addr=0x20007000,
+platform = self.lupv,
+int_id = self._int_ids['TTY']
+)
 self.terminal = Terminal()

 pic_srcs = [
-self._int_ids['UART'],
+self._int_ids['TTY'],
 self._int_ids['DISK'],
 self._int_ids['RNG']
 ]
@@ -157,7 +161,7 @@
 self.pic,
 ]
 self._off_chip_devices = [
-self.uart,
+self.lupio_tty,
 self.disk,
 self.lupio_rng,
 self.lupio_rtc
@@ -239,7 +243,7 @@

 # Linux boot command flags
 kernel_cmd = [
-"earlycon console=ttyS0",
+"earlycon console=ttyLIO0",
 "root=/dev/vda1",
 "ro"
 ]
@@ -366,21 +370,6 @@

 soc_node.append(plic_node)

-# UART node
-uart = self.uart
-uart_node = uart.generateBasicPioDeviceNode(
-soc_state, "uart", uart.pio_addr, uart.pio_size
-)
-uart_node.append(
-FdtPropertyWords("interrupts", [self._int_ids['UART']])
-)
-uart_node.append(FdtPropertyWords("clock-frequency", [0x384000]))
-uart_node.append(
-FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
-)
-uart_node.appendCompatible(["ns8250"])
-soc_node.append(uart_node)
-
 # VirtIO MMIO disk node
 disk = self.disk
 disk_node = disk.generateBasicPioDeviceNode(
@@ -414,6 +403,19 @@
 lupio_rtc_node.appendCompatible(["lupio,rtc"])
 soc_node.append(lupio_rtc_node)

+# LupioTTY Device
+lupio_tty = self.lupio_tty
+lupio_tty_node = lupio_tty.generateBasicPioDeviceNode(soc_state,
+"lupio-tty", lupio_tty.pio_addr,  
lupio_tty.pio_size)

+lupio_tty_node.appendCompatible(["lupio,tty"])
+lupio_tty_node.append(
+FdtPropertyWords("interrupts",
+[self.lupio_tty.int_id]))
+lupio_tty_node.append(
+FdtPropertyWords("interrupt-parent",
+state.phandle(self.pic)))
+soc_node.append(lupio_tty_node)
+
 root.append(soc_node)
 fdt = Fdt()
 fdt.add_rootnode(root)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53032
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib9a09565e8522178fd9c9f900db9d3b87e8b48fb
Gerrit-Change-Number: 53032
Gerrit-PatchSet: 9
Gerrit-Owner: melissa jost 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] Change in gem5/gem5[develop]: dev: Introduced new LupV Platform

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53027 )


Change subject: dev: Introduced new LupV Platform
..

dev: Introduced new LupV Platform

This is a platform with a RISC-V processor and the LupIO devices that
will allow users to decide which programmable interrupt controller to
use in their system. It currently uses the PLIC device.

Change-Id: Ife6cf5c14845be725e66178693e9ba0ee5fda511
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53027
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
A src/dev/riscv/lupv.cc
A src/dev/riscv/lupv.hh
A src/dev/riscv/LupV.py
M src/dev/riscv/SConscript
4 files changed, 217 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/riscv/LupV.py b/src/dev/riscv/LupV.py
new file mode 100644
index 000..d14595e
--- /dev/null
+++ b/src/dev/riscv/LupV.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Platform import Platform
+from m5.params import Param
+
+class LupV(Platform):
+type = 'LupV'
+cxx_header = "dev/riscv/lupv.hh"
+cxx_class = 'gem5::LupV'
+pic = Param.Plic("PIC")
+uart_int_id = Param.Int("Interrupt ID to be used if the PLIC is used  
here")

diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index 23f1074..5124b55 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -29,6 +29,7 @@
 Import('*')

 SimObject('HiFive.py', tags='riscv isa')
+SimObject('LupV.py', tags='riscv isa')
 SimObject('Clint.py', tags='riscv isa')
 SimObject('PlicDevice.py', tags='riscv isa')
 SimObject('Plic.py', tags='riscv isa')
@@ -40,6 +41,7 @@
 DebugFlag('VirtIOMMIO', tags='riscv isa')

 Source('hifive.cc', tags='riscv isa')
+Source('lupv.cc', tags='riscv isa')
 Source('clint.cc', tags='riscv isa')
 Source('plic_device.cc', tags='riscv isa')
 Source('plic.cc', tags='riscv isa')
diff --git a/src/dev/riscv/lupv.cc b/src/dev/riscv/lupv.cc
new file mode 100644
index 000..7658b2a
--- /dev/null
+++ b/src/dev/riscv/lupv.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Added LupioRNG to LupVBoard

[melissa jost (Gerrit) via gem5-dev]

melissa jost has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53030 )


Change subject: stdlib: Added LupioRNG to LupVBoard
..

stdlib: Added LupioRNG to LupVBoard

This adds the LupioRNG device to our LupVBoard, adding
random number generation capability to this RISC-V
based system.

Change-Id: I89c78c119a46cc7b056005d8abef16b1816ee4c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53030
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/lupv_board.py
1 file changed, 42 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/lupv_board.py  
b/src/python/gem5/components/boards/lupv_board.py

index 18f0337..0316def 100644
--- a/src/python/gem5/components/boards/lupv_board.py
+++ b/src/python/gem5/components/boards/lupv_board.py
@@ -48,6 +48,7 @@
 Plic,
 Uart8250,
 Terminal,
+LupioRNG,
 LupioRTC,
 LupV,
 AddrRange,
@@ -97,7 +98,7 @@

 # Initialize all the devices that we want to use on this board
 # Interrupt IDS for PIC Device
-self._int_ids = { 'UART': 1, 'DISK': 2}
+self._int_ids = { 'UART': 1, 'DISK': 2, 'RNG': 3}

 # CLINT
 self.clint = Clint(pio_addr=0x200)
@@ -111,6 +112,13 @@
 uart_int_id = self._int_ids['UART']
 )

+# LUPIO RNG
+self.lupio_rng = LupioRNG(
+pio_addr=0x20005000,
+platform = self.lupv,
+int_id = self._int_ids['RNG']
+)
+
 # LUPIO RTC
 self.lupio_rtc = LupioRTC(pio_addr=0x20004000)

@@ -128,7 +136,8 @@

 pic_srcs = [
 self._int_ids['UART'],
-self._int_ids['DISK']
+self._int_ids['DISK'],
+self._int_ids['RNG']
 ]
 self.pic.n_contexts = self.processor.get_num_cores() * 2
 self.pic.n_src = max(pic_srcs) + 1
@@ -150,6 +159,7 @@
 self._off_chip_devices = [
 self.uart,
 self.disk,
+self.lupio_rng,
 self.lupio_rtc
 ]

@@ -383,6 +393,19 @@
 disk_node.appendCompatible(["virtio,mmio"])
 soc_node.append(disk_node)

+# LupioRNG Device
+lupio_rng = self.lupio_rng
+lupio_rng_node = lupio_rng.generateBasicPioDeviceNode(soc_state,
+"lupio-rng",  
lupio_rng.pio_addr,lupio_rng.pio_size)

+lupio_rng_node.appendCompatible(["lupio,rng"])
+lupio_rng_node.append(
+FdtPropertyWords("interrupts",
+[self.lupio_rng.int_id]))
+lupio_rng_node.append(
+FdtPropertyWords("interrupt-parent",
+state.phandle(self.pic)))
+soc_node.append(lupio_rng_node)
+
 # LupioRTC Device
 lupio_rtc = self.lupio_rtc
 lupio_rtc_node = lupio_rtc.generateBasicPioDeviceNode(

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I89c78c119a46cc7b056005d8abef16b1816ee4c4
Gerrit-Change-Number: 53030
Gerrit-PatchSet: 8
Gerrit-Owner: melissa jost 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Fix segfalt in simulate_limit_event shortcut

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53723 )



Change subject: ext: Fix segfalt in simulate_limit_event shortcut
..

ext: Fix segfalt in simulate_limit_event shortcut

In the SST integration the top of the main queue is checked
for an event before starting the simulation.

If the first event is scheduled after the ending tick, we are
just returning the simulate_limit_event without entering
the simulation loop.

If the method is called with an empty queue, the following
line will segfault (getHead() == nullptr):

gem5::mainEventQueue[0]->getHead()->when()

With this patch we are covering the case where we have
an empty event queue

Change-Id: I04463b45b269361172a9dd2fe1ba6e9428ac64f5
Signed-off-by: Giacomo Travaglini 
---
M ext/sst/gem5.cc
1 file changed, 28 insertions(+), 1 deletion(-)



diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index 924ee49..c93c722 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -285,8 +285,10 @@

 // Here, if the next event in gem5's queue is not executed within the  
next

 // cycle, there's no need to enter the gem5's sim loop.
-if (next_end_tick < gem5::mainEventQueue[0]->getHead()->when())
+if (gem5::mainEventQueue[0]->empty() ||
+next_end_tick < gem5::mainEventQueue[0]->getHead()->when()) {
 return gem5::simulate_limit_event;
+}
 gem5::simulate_limit_event->reschedule(next_end_tick);
 gem5::Event *local_event = doSimLoop(gem5::mainEventQueue[0]);
 gem5::BaseGlobalEvent *global_event = local_event->globalEvent();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04463b45b269361172a9dd2fe1ba6e9428ac64f5
Gerrit-Change-Number: 53723
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons,misc: Fix broken X86_MI_example build_opts

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53684 )


Change subject: scons,misc: Fix broken X86_MI_example build_opts
..

scons,misc: Fix broken X86_MI_example build_opts

This bug was causing the compiler tests to fail:
https://jenkins.gem5.org/job/compiler-checks/65/

Change-Id: I472a50a4a415108d177255fa396e67385104b059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53684
Maintainer: Bobby Bruce 
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M build_opts/X86_MI_example
1 file changed, 17 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/build_opts/X86_MI_example b/build_opts/X86_MI_example
index 5fb47a3..60d1645 100644
--- a/build_opts/X86_MI_example
+++ b/build_opts/X86_MI_example
@@ -1,3 +1,3 @@
 TARGET_ISA = 'x86'
 CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
-PROTOCOL = 'MI_example
+PROTOCOL = 'MI_example'

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I472a50a4a415108d177255fa396e67385104b059
Gerrit-Change-Number: 53684
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: compiler-checks #68

[jenkins-no-reply--- via gem5-dev]

See 


Changes:

[Jason Lowe-Power] arch-arm,arch-sparc: Remove legacy stat for faults

[chenzou] base-stats: HDF5 calls with better compatibility


--
Started
Running as SYSTEM
Building in workspace 
The recommended git tool is: NONE
No credentials specified
 > git rev-parse --resolve-git-dir 
 >  # timeout=10
Fetching changes from the remote Git repository
 > git config remote.origin.url https://gem5.googlesource.com/public/gem5 # 
 > timeout=10
Fetching upstream changes from https://gem5.googlesource.com/public/gem5
 > git --version # timeout=10
 > git --version # 'git version 2.25.1'
 > git fetch --tags --force --progress -- 
 > https://gem5.googlesource.com/public/gem5 
 > +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
Checking out Revision a1c0436f405eb81ab29e647d6cb1b8b0a0f9ad32 
(refs/remotes/origin/develop)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f a1c0436f405eb81ab29e647d6cb1b8b0a0f9ad32 # timeout=10
Commit message: "base-stats: HDF5 calls with better compatibility"
 > git rev-list --no-walk d9b18b0f8dea4155c965bb6e0854664f1a156ef6 # timeout=10
[compiler-checks] $ /bin/sh -xe /tmp/jenkins17539539631771767010.sh
+ ./tests/compiler-tests.sh -j 40
Starting build tests with 'gcc-version-11'...
'gcc-version-11' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-11'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-11'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'X86_MI_example.fast' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'RISCV.opt' with 'gcc-version-11'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'Garnet_standalone.opt' with 'gcc-version-10'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'MIPS.opt' with 'gcc-version-9'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target 'X86_MI_example.opt' with 'gcc-version-8'...
  ! Failed with exit code 2.
  * Building target 'X86_MI_example.fast' with 'gcc-version-8'...
  ! Failed with exit code 2.
Starting build tests with 

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa,gpu-compute: Properly assign DmaVirtDevices in py

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53704 )


Change subject: dev-hsa,gpu-compute: Properly assign DmaVirtDevices in py
..

dev-hsa,gpu-compute: Properly assign DmaVirtDevices in py

These SimObjects are DmaVirtDevices in C++ but DmaDevices in the sim
object's python file. Make the sim object python files consistent.

Change-Id: I728ae737c5901e448628fc5ac877f261ca4c4393
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53704
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/GPU.py
M src/dev/hsa/HSADevice.py
2 files changed, 22 insertions(+), 4 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/hsa/HSADevice.py b/src/dev/hsa/HSADevice.py
index f67d9a8..8a6e61d 100644
--- a/src/dev/hsa/HSADevice.py
+++ b/src/dev/hsa/HSADevice.py
@@ -32,9 +32,9 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.Device import DmaDevice
+from m5.objects.Device import DmaVirtDevice

-class HSAPacketProcessor(DmaDevice):
+class HSAPacketProcessor(DmaVirtDevice):
 type = 'HSAPacketProcessor'
 cxx_header = 'dev/hsa/hsa_packet_processor.hh'
 cxx_class = 'gem5::HSAPacketProcessor'
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index b739e80..f714cc0 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -36,7 +36,7 @@

 from m5.objects.Bridge import Bridge
 from m5.objects.ClockedObject import ClockedObject
-from m5.objects.Device import DmaDevice
+from m5.objects.Device import DmaVirtDevice
 from m5.objects.LdsState import LdsState
 from m5.objects.Process import EmulatedDriver

@@ -267,7 +267,7 @@
 cxx_class = 'gem5::GPUDispatcher'
 cxx_header = 'gpu-compute/dispatcher.hh'

-class GPUCommandProcessor(DmaDevice):
+class GPUCommandProcessor(DmaVirtDevice):
 type = 'GPUCommandProcessor'
 cxx_class = 'gem5::GPUCommandProcessor'
 cxx_header = 'gpu-compute/gpu_command_processor.hh'

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I728ae737c5901e448628fc5ac877f261ca4c4393
Gerrit-Change-Number: 53704
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: Remove reference to old GPU ptls

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53703 )


Change subject: configs,mem-ruby: Remove reference to old GPU ptls
..

configs,mem-ruby: Remove reference to old GPU ptls

GPU_VIPER_Baseline, GPU_VIPER_Region, and GPU_RfO were removed some time
ago.

Change-Id: If873b0cfe8cc2b3096cbe97d4e13a8e02d2ec567
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53703
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M configs/ruby/AMD_Base_Constructor.py
M src/mem/ruby/protocol/SConsopts
2 files changed, 19 insertions(+), 6 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/ruby/AMD_Base_Constructor.py  
b/configs/ruby/AMD_Base_Constructor.py

index 1abc6d7..7f4fb43 100644
--- a/configs/ruby/AMD_Base_Constructor.py
+++ b/configs/ruby/AMD_Base_Constructor.py
@@ -102,9 +102,7 @@
 parser.add_argument("--cpu-to-dir-latency", type=int, default=15)

 def construct(options, system, ruby_system):
-if (buildEnv['PROTOCOL'] != 'GPU_VIPER' or
-buildEnv['PROTOCOL'] != 'GPU_VIPER_Region' or
-buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline'):
+if buildEnv['PROTOCOL'] != 'GPU_VIPER':
 panic("This script requires VIPER based protocols \
 to be built.")
 cpu_sequencers = []
diff --git a/src/mem/ruby/protocol/SConsopts  
b/src/mem/ruby/protocol/SConsopts

index ad3bd2f..03b87b4 100644
--- a/src/mem/ruby/protocol/SConsopts
+++ b/src/mem/ruby/protocol/SConsopts
@@ -32,9 +32,6 @@

 main.Append(ALL_PROTOCOLS=[
 'GPU_VIPER',
-'GPU_VIPER_Baseline',
-'GPU_VIPER_Region',
-'GPU_RfO',
 'MOESI_AMD_Base',
 'MESI_Two_Level',
 'MESI_Three_Level',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If873b0cfe8cc2b3096cbe97d4e13a8e02d2ec567
Gerrit-Change-Number: 53703
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Removing SingleChannelMemory

[Mahyar Samani (Gerrit) via gem5-dev]

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53304 )


Change subject: stdlib: Removing SingleChannelMemory
..

stdlib: Removing SingleChannelMemory

This change removes the code base for SingleChannelMemory and
replaces it with MultiChannelMemory. muli_channel defines all
the classes that were defined by single_channel. Basically any
SingleChannelMemory could be thought of as a MultiChannelMemory
with 1 channel.

Change-Id: If96079d5f77be5a3ba26d2c2ddb98f5c60375cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53304
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/riscv-fs.py
A src/python/gem5/components/memory/memory.py
M configs/example/gem5_library/arm-hello.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M src/python/gem5/components/memory/multi_channel.py
M src/python/SConscript
M src/python/gem5/components/memory/__init__.py
M configs/example/gem5_library/x86-ubuntu-run.py
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/configs/simple_binary_run.py
M src/python/gem5/components/memory/single_channel.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
M tests/gem5/configs/x86_boot_exit_run.py
15 files changed, 321 insertions(+), 345 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 540a96b..5a2f46c 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -47,11 +47,11 @@
 from gem5.isas import ISA
 from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes

 # This check ensures the gem5 binary is compiled to the ARM ISA target. If  
not,

 # an exception will be thrown.
diff --git a/configs/example/gem5_library/riscv-fs.py  
b/configs/example/gem5_library/riscv-fs.py

index f46a345..4d0a2c8 100644
--- a/configs/example/gem5_library/riscv-fs.py
+++ b/configs/example/gem5_library/riscv-fs.py
@@ -43,7 +43,7 @@
 from m5.objects import Root

 from gem5.components.boards.riscv_board import RiscvBoard
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.cachehierarchies.classic.\
 private_l1_private_l2_cache_hierarchy import (
diff --git a/configs/example/gem5_library/x86-ubuntu-run.py  
b/configs/example/gem5_library/x86-ubuntu-run.py

index 9979c14..622f4f3 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -47,8 +47,8 @@
 import m5
 from m5.objects import Root

-from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard
 from gem5.resources.resource import Resource
+from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard

 # Here we setup the board. The prebuilt X86DemoBoard allows for  
Full-System X86

 # simulation.
@@ -64,4 +64,4 @@

 root = Root(full_system=True, system=board)
 m5.instantiate()
-m5.simulate()
\ No newline at end of file
+m5.simulate()
diff --git a/src/python/SConscript b/src/python/SConscript
index 4487bdd..3d91ccb 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -133,8 +133,9 @@
 PySource('gem5.components.memory', 'gem5/components/memory/__init__.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py')

 PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
-PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')
 PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
+PySource('gem5.components.memory', 'gem5/components/memory/memory.py')
+PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/multi_channel.py')

 PySource('gem5.components.memory.dram_interfaces',
 'gem5/components/memory/dram_interfaces/__init__.py')
diff --git a/src/python/gem5/components/memory/__init__.py  
b/src/python/gem5/components/memory/__init__.py

index e69de29..5e16865 100644
--- a/src/python/gem5/components/memory/__init__.py
+++ 

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Add currEL function to the ISA class

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53624 )


Change subject: arch-arm, dev-arm: Add currEL function to the ISA class
..

arch-arm, dev-arm: Add currEL function to the ISA class

This utility is strictly ISA related. We are still keeping the
version accepting the TC as an argument; this is just
wrapping the ISA call.

In this way we are simplifying life for ISA devices, which have
a reference to the ISA object rather than a reference to the TC

Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53624
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/pmu.cc
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
7 files changed, 54 insertions(+), 35 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f9e2976..02af0bc 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -629,7 +629,7 @@
   miscRegName[misc_reg]);
 }
 #endif
-misc_reg = redirectRegVHE(tc, misc_reg);
+misc_reg = redirectRegVHE(misc_reg);

 switch (unflattenMiscReg(misc_reg)) {
   case MISCREG_HCR:
@@ -1006,7 +1006,7 @@
 miscRegName[misc_reg], val);
 }
 #endif
-misc_reg = redirectRegVHE(tc, misc_reg);
+misc_reg = redirectRegVHE(misc_reg);

 switch (unflattenMiscReg(misc_reg)) {
   case MISCREG_CPACR:
@@ -2555,6 +2555,14 @@
 }
 }

+ExceptionLevel
+ISA::currEL() const
+{
+CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
+
+return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
+}
+
 unsigned
 ISA::getCurSveVecLenInBits() const
 {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 696097c..2afcc51 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -859,10 +859,10 @@
  * HCR_EL2.E2H is enabled and executing at EL2
  */
 int
-redirectRegVHE(ThreadContext * tc, int misc_reg)
+redirectRegVHE(int misc_reg)
 {
 const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
-if (hcr.e2h == 0x0 || currEL(tc) != EL2)
+if (hcr.e2h == 0x0 || currEL() != EL2)
 return misc_reg;
 SCR scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
 bool sec_el2 = scr.eel2 &&  
release->has(ArmExtension::FEAT_SEL2);

@@ -961,6 +961,11 @@
 /** Return true if the PE is in Secure state */
 bool inSecureState() const;

+/**
+ * Returns the current Exception Level (EL) of the ISA object
+ */
+ExceptionLevel currEL() const;
+
 unsigned getCurSveVecLenInBits() const;

 unsigned getCurSveVecLenInBitsAtReset() const { return sveVL *  
128; }

diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 6956eb0..f0ab978 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -491,8 +491,7 @@
 assert(pmu.isa);

 const PMEVTYPER_t filter(this->filter);
-const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
-const ExceptionLevel el(currEL(cpsr));
+const ExceptionLevel el(pmu.isa->currEL());
 const bool secure(pmu.isa->inSecureState());

 switch (el) {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index d24f470..2a98eea 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -124,6 +124,13 @@
 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
 }

+ExceptionLevel
+currEL(const ThreadContext *tc)
+{
+return static_cast(
+const_cast(tc)->getIsaPtr())->currEL();
+}
+
 bool
 longDescFormatInUse(ThreadContext *tc)
 {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 9514eb0..0e5f3bb 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -108,13 +108,11 @@

 bool inAArch64(ThreadContext *tc);

-static inline ExceptionLevel
-currEL(const ThreadContext *tc)
-{
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
-}
+/**
+ * Returns the current Exception Level (EL) of the
+ * provided ThreadContext
+ */
+ExceptionLevel currEL(const ThreadContext *tc);

 inline ExceptionLevel
 currEL(CPSR cpsr)
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index a56cb66..6093e86 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -2336,29 +2336,10 @@
 return isa->inSecureState();
 }

-int
+ExceptionLevel
 Gicv3CPUInterface::currEL() const
 {
-CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
-

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Move inSecureState helper to ISA class

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53268 )


Change subject: arch-arm, dev-arm: Move inSecureState helper to ISA class
..

arch-arm, dev-arm: Move inSecureState helper to ISA class

The helper function should be really part of the Arm ISA class

Change-Id: Ida0393a12426c8973a9b8171ec2922c2dcec9f5a
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53268
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/pmu.cc
M src/arch/arm/utility.hh
M src/dev/arm/gic_v3_cpu_interface.cc
5 files changed, 49 insertions(+), 35 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f646109..f9e2976 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2531,6 +2531,30 @@
 return *gicv3CpuInterface.get();
 }

+bool
+ISA::inSecureState() const
+{
+if (!release->has(ArmExtension::SECURITY)) {
+return false;
+}
+
+SCR scr = miscRegs[MISCREG_SCR];
+CPSR cpsr = miscRegs[MISCREG_CPSR];
+
+switch ((OperatingMode) (uint8_t) cpsr.mode) {
+  case MODE_MON:
+  case MODE_EL3T:
+  case MODE_EL3H:
+return true;
+  case MODE_HYP:
+  case MODE_EL2T:
+  case MODE_EL2H:
+return false;
+  default:
+return !scr.ns;
+}
+}
+
 unsigned
 ISA::getCurSveVecLenInBits() const
 {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 645a765..696097c 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -844,15 +844,11 @@
 }
 } else {
 if (miscRegInfo[reg][MISCREG_BANKED]) {
-bool secure_reg = release->has(ArmExtension::SECURITY)  
&&

-  !highestELIs64 &&
-  inSecureState(miscRegs[MISCREG_SCR],
- 
miscRegs[MISCREG_CPSR]);

+bool secure_reg = !highestELIs64 && inSecureState();
 flat_idx += secure_reg ? 2 : 1;
 } else {
 flat_idx = snsBankedIndex64((MiscRegIndex)reg,
-!inSecureState(miscRegs[MISCREG_SCR],
-   miscRegs[MISCREG_CPSR]));
+!inSecureState());
 }
 }
 return flat_idx;
@@ -952,9 +948,8 @@
 }

 // do additional S/NS flattenings if mapped to NS while in S
-bool S = release->has(ArmExtension::SECURITY)  
&& !highestELIs64 &&

- inSecureState(miscRegs[MISCREG_SCR],
-   miscRegs[MISCREG_CPSR]);
+bool S = !highestELIs64 && inSecureState();
+
 int lower = lookUpMiscReg[flat_idx].lower;
 int upper = lookUpMiscReg[flat_idx].upper;
 // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD  
(no-op)

@@ -963,6 +958,9 @@
 return std::make_pair(lower, upper);
 }

+/** Return true if the PE is in Secure state */
+bool inSecureState() const;
+
 unsigned getCurSveVecLenInBits() const;

 unsigned getCurSveVecLenInBitsAtReset() const { return sveVL *  
128; }

diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 57df5f6..6956eb0 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -491,10 +491,9 @@
 assert(pmu.isa);

 const PMEVTYPER_t filter(this->filter);
-const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR));
 const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
 const ExceptionLevel el(currEL(cpsr));
-const bool secure(inSecureState(scr, cpsr));
+const bool secure(pmu.isa->inSecureState());

 switch (el) {
   case EL0:
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 46dda3a..2155e8c 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -217,23 +217,6 @@
 int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
TCR tcr, ExceptionLevel el);

-static inline bool
-inSecureState(SCR scr, CPSR cpsr)
-{
-switch ((OperatingMode) (uint8_t) cpsr.mode) {
-  case MODE_MON:
-  case MODE_EL3T:
-  case MODE_EL3H:
-return true;
-  case MODE_HYP:
-  case MODE_EL2T:
-  case MODE_EL2H:
-return false;
-  default:
-return !scr.ns;
-}
-}
-
 bool isSecureBelowEL3(ThreadContext *tc);

 bool longDescFormatInUse(ThreadContext *tc);
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index 4ae6b9b..a56cb66 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ 

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove currOpMode utility function

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53623 )


Change subject: arch-arm: Remove currOpMode utility function
..

arch-arm: Remove currOpMode utility function

This was used by the currEL function only. We are progressively
removing any interface referring to Armv7 concepts

Change-Id: I1d97b392d063e85562b9234c094b1f2166e75ac9
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53623
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/utility.hh
1 file changed, 20 insertions(+), 8 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 2155e8c..9514eb0 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -108,17 +108,12 @@

 bool inAArch64(ThreadContext *tc);

-static inline OperatingMode
-currOpMode(const ThreadContext *tc)
-{
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-return (OperatingMode) (uint8_t) cpsr.mode;
-}
-
 static inline ExceptionLevel
 currEL(const ThreadContext *tc)
 {
-return opModeToEL(currOpMode(tc));
+CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+
+return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
 }

 inline ExceptionLevel

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53623
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1d97b392d063e85562b9234c094b1f2166e75ac9
Gerrit-Change-Number: 53623
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu: Hotfix variable initialization

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53063 )


Change subject: dev-amdgpu: Hotfix variable initialization
..

dev-amdgpu: Hotfix variable initialization

These non-initialized variables were causing the trace reader not to
record all lines.

Change-Id: I88764493d8124c072bc90ff9c08aa26421467f7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53063
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/amdgpu/mmio_reader.hh
1 file changed, 19 insertions(+), 3 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/amdgpu/mmio_reader.hh b/src/dev/amdgpu/mmio_reader.hh
index 6c88f0b..a057183 100644
--- a/src/dev/amdgpu/mmio_reader.hh
+++ b/src/dev/amdgpu/mmio_reader.hh
@@ -99,9 +99,9 @@
 trace_BAR_t trace_BARs[6];

 /* Indexes used to print driver loading progress. */
-uint64_t trace_index;
-uint64_t trace_final_index;
-uint64_t trace_cur_index;
+uint64_t trace_index = 0;
+uint64_t trace_final_index = 0;
+uint64_t trace_cur_index = 0;

 /* An entry in the MMIO trace. */
 struct MmioTrace

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53063
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I88764493d8124c072bc90ff9c08aa26421467f7b
Gerrit-Change-Number: 53063
Gerrit-PatchSet: 2
Gerrit-Owner: Alexandru Duțu 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: compiler-checks #67

[jenkins-no-reply--- via gem5-dev]

See 


Changes:

[giacomo.travaglini] ext: Make gem5-SST Memory Size configurable from script


--
Started
Running as SYSTEM
Building in workspace 
The recommended git tool is: NONE
No credentials specified
 > git rev-parse --resolve-git-dir 
 >  # timeout=10
Fetching changes from the remote Git repository
 > git config remote.origin.url https://gem5.googlesource.com/public/gem5 # 
 > timeout=10
Fetching upstream changes from https://gem5.googlesource.com/public/gem5
 > git --version # timeout=10
 > git --version # 'git version 2.25.1'
 > git fetch --tags --force --progress -- 
 > https://gem5.googlesource.com/public/gem5 
 > +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
Checking out Revision d9b18b0f8dea4155c965bb6e0854664f1a156ef6 
(refs/remotes/origin/develop)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f d9b18b0f8dea4155c965bb6e0854664f1a156ef6 # timeout=10
Commit message: "ext: Make gem5-SST Memory Size configurable from script"
 > git rev-list --no-walk 404bf901d074b186ea70831f476d50374a78c0dd # timeout=10
[compiler-checks] $ /bin/sh -xe /tmp/jenkins6457729067644979194.sh
+ ./tests/compiler-tests.sh -j 70
Starting build tests with 'gcc-version-11'...
'gcc-version-11' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'POWER.opt' with 'gcc-version-11'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'X86_MI_example.fast' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-11'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-11'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'SPARC.opt' with 'gcc-version-10'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-9'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target 'NULL.opt' with 'gcc-version-8'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-8'...
Done.
Starting build tests with 'gcc-version-7'...
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-7'...

[gem5-dev] Change in gem5/gem5[develop]: base-stats: HDF5 calls with better compatibility

[Chen Zou (Gerrit) via gem5-dev]

Chen Zou has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53283 )


Change subject: base-stats: HDF5 calls with better compatibility
..

base-stats: HDF5 calls with better compatibility

H5Object.getObjName() is added at HDF5 V1.8.13.
As an example, compilation error would be thrown on CentOS 7.
obj.getObjnameByIdx(obj.getId()) would work with older versions.

Change-Id: I104eaac050db7501ab3a1aa3ad6dc1ee8b8d7e22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53283
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/stats/hdf5.cc
1 file changed, 18 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/base/stats/hdf5.cc b/src/base/stats/hdf5.cc
index d5b7f1e..03574b2 100644
--- a/src/base/stats/hdf5.cc
+++ b/src/base/stats/hdf5.cc
@@ -257,7 +257,7 @@
 fspace = H5::DataSpace(rank, dims, max_dims.data());
 try {
 DPRINTF(Stats, "Creating dataset %s in group %s\n",
-info.name, group.getObjName());
+info.name, group.getObjnameByIdx(group.getId()));
 data_set = group.createDataSet(info.name,
 H5::PredType::NATIVE_DOUBLE, fspace, props);
 } catch (const H5::Exception ) {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I104eaac050db7501ab3a1aa3ad6dc1ee8b8d7e22
Gerrit-Change-Number: 53283
Gerrit-PatchSet: 3
Gerrit-Owner: Chen Zou 
Gerrit-Reviewer: Chen Zou 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby Bruce 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: Remove reference to old GPU ptls

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53703 )



Change subject: configs,mem-ruby: Remove reference to old GPU ptls
..

configs,mem-ruby: Remove reference to old GPU ptls

GPU_VIPER_Baseline, GPU_VIPER_Region, and GPU_RfO were removed some time
ago.

Change-Id: If873b0cfe8cc2b3096cbe97d4e13a8e02d2ec567
---
M configs/ruby/AMD_Base_Constructor.py
M src/mem/ruby/protocol/SConsopts
2 files changed, 13 insertions(+), 6 deletions(-)



diff --git a/configs/ruby/AMD_Base_Constructor.py  
b/configs/ruby/AMD_Base_Constructor.py

index 1abc6d7..7f4fb43 100644
--- a/configs/ruby/AMD_Base_Constructor.py
+++ b/configs/ruby/AMD_Base_Constructor.py
@@ -102,9 +102,7 @@
 parser.add_argument("--cpu-to-dir-latency", type=int, default=15)

 def construct(options, system, ruby_system):
-if (buildEnv['PROTOCOL'] != 'GPU_VIPER' or
-buildEnv['PROTOCOL'] != 'GPU_VIPER_Region' or
-buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline'):
+if buildEnv['PROTOCOL'] != 'GPU_VIPER':
 panic("This script requires VIPER based protocols \
 to be built.")
 cpu_sequencers = []
diff --git a/src/mem/ruby/protocol/SConsopts  
b/src/mem/ruby/protocol/SConsopts

index ad3bd2f..03b87b4 100644
--- a/src/mem/ruby/protocol/SConsopts
+++ b/src/mem/ruby/protocol/SConsopts
@@ -32,9 +32,6 @@

 main.Append(ALL_PROTOCOLS=[
 'GPU_VIPER',
-'GPU_VIPER_Baseline',
-'GPU_VIPER_Region',
-'GPU_RfO',
 'MOESI_AMD_Base',
 'MESI_Two_Level',
 'MESI_Three_Level',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If873b0cfe8cc2b3096cbe97d4e13a8e02d2ec567
Gerrit-Change-Number: 53703
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-hsa,gpu-compute: Properly assign DmaVirtDevices in py

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53704 )



Change subject: dev-hsa,gpu-compute: Properly assign DmaVirtDevices in py
..

dev-hsa,gpu-compute: Properly assign DmaVirtDevices in py

These SimObjects are DmaVirtDevices in C++ but DmaDevices in the sim
object's python file. Make the sim object python files consistent.

Change-Id: I728ae737c5901e448628fc5ac877f261ca4c4393
---
M src/gpu-compute/GPU.py
M src/dev/hsa/HSADevice.py
2 files changed, 16 insertions(+), 4 deletions(-)



diff --git a/src/dev/hsa/HSADevice.py b/src/dev/hsa/HSADevice.py
index f67d9a8..8a6e61d 100644
--- a/src/dev/hsa/HSADevice.py
+++ b/src/dev/hsa/HSADevice.py
@@ -32,9 +32,9 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.Device import DmaDevice
+from m5.objects.Device import DmaVirtDevice

-class HSAPacketProcessor(DmaDevice):
+class HSAPacketProcessor(DmaVirtDevice):
 type = 'HSAPacketProcessor'
 cxx_header = 'dev/hsa/hsa_packet_processor.hh'
 cxx_class = 'gem5::HSAPacketProcessor'
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index b739e80..f714cc0 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -36,7 +36,7 @@

 from m5.objects.Bridge import Bridge
 from m5.objects.ClockedObject import ClockedObject
-from m5.objects.Device import DmaDevice
+from m5.objects.Device import DmaVirtDevice
 from m5.objects.LdsState import LdsState
 from m5.objects.Process import EmulatedDriver

@@ -267,7 +267,7 @@
 cxx_class = 'gem5::GPUDispatcher'
 cxx_header = 'gpu-compute/dispatcher.hh'

-class GPUCommandProcessor(DmaDevice):
+class GPUCommandProcessor(DmaVirtDevice):
 type = 'GPUCommandProcessor'
 cxx_class = 'gem5::GPUCommandProcessor'
 cxx_header = 'gpu-compute/gpu_command_processor.hh'

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I728ae737c5901e448628fc5ac877f261ca4c4393
Gerrit-Change-Number: 53704
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm,arch-sparc: Remove legacy stat for faults

[Jason Lowe-Power (Gerrit) via gem5-dev]

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52504 )


Change subject: arch-arm,arch-sparc: Remove legacy stat for faults
..

arch-arm,arch-sparc: Remove legacy stat for faults

This is a legacy stat that was not easy to tie to a Stats::Group.

In ARM, this stat wasn't actually counting all faults, it was only
counting the faults that occured in 32-bit mode, so it's probably safe
to remove the stat (it was wrong anyway). For SPARC, it's also unlikely
anyone is depending on this stat for their research.

Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52504
Reviewed-by: Gabe Black 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
4 files changed, 22 insertions(+), 8 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 64a07cb..e340d07 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -524,7 +524,6 @@
 FaultBase::invoke(tc);
 if (!FullSystem)
 return;
-countStat()++;

 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
 SCR scr = tc->readMiscReg(MISCREG_SCR);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 139d477..688faad 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -193,7 +193,6 @@
 // (exceptions taken in HYP mode or in AArch64 state)
 const ExceptionClass ec;

-FaultStat count;
 FaultVals(const FaultName& name_, const FaultOffset& offset_,
 const uint16_t& currELTOffset_, const uint16_t&  
currELHOffset_,

 const uint16_t& lowerEL64Offset_,
@@ -237,7 +236,6 @@

 ArmStaticInst *instrAnnotate(const StaticInstPtr );
 virtual void annotate(AnnotationIDs id, uint64_t val) {}
-virtual FaultStat& countStat() = 0;
 virtual FaultOffset offset(ThreadContext *tc) = 0;
 virtual FaultOffset offset64(ThreadContext *tc) = 0;
 virtual OperatingMode nextMode() = 0;
@@ -269,7 +267,6 @@
 ArmFaultVals(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 ArmFault(_machInst, _iss) {}
 FaultName name() const override { return vals.name; }
-FaultStat & countStat() override { return vals.count; }
 FaultOffset offset(ThreadContext *tc) override;

 FaultOffset offset64(ThreadContext *tc) override;
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index ec7386f..421befa 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -503,7 +503,6 @@
 if (!FullSystem)
 return;

-countStat()++;

 // We can refer to this to see what the trap level -was-, but something
 // in the middle could change it in the regfile out from under us.
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index df09dc4..a5fb503 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -65,7 +65,6 @@
 const TrapType trapType;
 const FaultPriority priority;
 const PrivilegeLevelSpec nextPrivilegeLevel;
-FaultStat count;
 FaultVals(const FaultName& name_, const TrapType& trapType_,
 const FaultPriority& priority_, const PrivilegeLevelSpec&  
il)

 : name(name_), trapType(trapType_), priority(priority_),
@@ -76,7 +75,6 @@
 nullStaticInstPtr);
 virtual TrapType trapType() = 0;
 virtual FaultPriority priority() = 0;
-virtual FaultStat & countStat() = 0;
 virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
 };

@@ -89,7 +87,6 @@
 FaultName name() const { return vals.name; }
 TrapType trapType() { return vals.trapType; }
 FaultPriority priority() { return vals.priority; }
-FaultStat & countStat() { return vals.count; }

 PrivilegeLevel
 getNextLevel(PrivilegeLevel current)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Gerrit-Change-Number: 52504
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: compiler-checks #65

[Bobby Bruce via gem5-dev]

Fix here: https://gem5-review.googlesource.com/c/public/gem5/+/53684

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Tue, Dec 7, 2021 at 12:31 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/compiler-checks/65/display/redirect?page=changes
> >
>
> Changes:
>
> [Bobby R. Bruce] scons,misc: Update default X86 protocol to MESI_Two_Level
>
> [Bobby R. Bruce] stdlib: Add X86DemoBoard
>
> [Bobby R. Bruce] tests: Add a nightly test for SST integration.
>
>
> --
> Started by timer
> Running as SYSTEM
> Building in workspace 
> The recommended git tool is: NONE
> No credentials specified
>  > git rev-parse --resolve-git-dir <
> https://jenkins.gem5.org/job/compiler-checks/ws/.git> # timeout=10
> Fetching changes from the remote Git repository
>  > git config remote.origin.url https://gem5.googlesource.com/public/gem5
> # timeout=10
> Fetching upstream changes from https://gem5.googlesource.com/public/gem5
>  > git --version # timeout=10
>  > git --version # 'git version 2.25.1'
>  > git fetch --tags --force --progress --
> https://gem5.googlesource.com/public/gem5
> +refs/heads/*:refs/remotes/origin/* # timeout=10
>  > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
> Checking out Revision cf7ce21848ea4aeee28737823e6e768f9a14ceaf
> (refs/remotes/origin/develop)
>  > git config core.sparsecheckout # timeout=10
>  > git checkout -f cf7ce21848ea4aeee28737823e6e768f9a14ceaf # timeout=10
> Commit message: "tests: Add a nightly test for SST integration."
>  > git rev-list --no-walk 35362d15f5e0ff914ff3ed76d1a385e76d282610 #
> timeout=10
> [compiler-checks] $ /bin/sh -xe /tmp/jenkins11657432297015308831.sh
> + ./tests/compiler-tests.sh -j 70
> Starting build tests with 'gcc-version-11'...
> 'gcc-version-11' was found in the comprehensive tests. All ISAs will be
> built.
>   * Building target 'POWER.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'POWER.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'Garnet_standalone.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'Garnet_standalone.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'MIPS.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'MIPS.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'X86_MI_example.opt' with 'gcc-version-11'...
>   ! Failed with exit code 2.
>   * Building target 'X86_MI_example.fast' with 'gcc-version-11'...
>   ! Failed with exit code 2.
>   * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MESI_Three_Level_HTM.fast' with
> 'gcc-version-11'...
> Done.
>   * Building target 'NULL.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'SPARC.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'SPARC.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'RISCV.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'RISCV.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_directory.fast' with
> 'gcc-version-11'...
> Done.
>   * Building target 'ARM.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'X86.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'X86.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'GCN3_X86.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'GCN3_X86.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
> Done.
>   * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
> Done.
> Starting build tests with 'gcc-version-10'...
>   * Building target 'ARM_MOESI_hammer.opt' with 

[gem5-dev] Change in gem5/gem5[develop]: scons,misc: Fix broken X86_MI_example build_opts

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53684 )



Change subject: scons,misc: Fix broken X86_MI_example build_opts
..

scons,misc: Fix broken X86_MI_example build_opts

This bug was causing the compiler tests to fail:
https://jenkins.gem5.org/job/compiler-checks/65/

Change-Id: I472a50a4a415108d177255fa396e67385104b059
---
M build_opts/X86_MI_example
1 file changed, 13 insertions(+), 1 deletion(-)



diff --git a/build_opts/X86_MI_example b/build_opts/X86_MI_example
index 5fb47a3..60d1645 100644
--- a/build_opts/X86_MI_example
+++ b/build_opts/X86_MI_example
@@ -1,3 +1,3 @@
 TARGET_ISA = 'x86'
 CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
-PROTOCOL = 'MI_example
+PROTOCOL = 'MI_example'

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I472a50a4a415108d177255fa396e67385104b059
Gerrit-Change-Number: 53684
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Build failed in Jenkins: compiler-checks #66

[jenkins-no-reply--- via gem5-dev]

See 


Changes:

[msamani] stdlib: Updated MuliChannelMemory constructor

[msamani] tests: Adding new test for traffic_gen

[msamani] stdlib: Adding clock_domain to GUPSGenerators

[msamani] test: Updating simple_traffic_run and adding tests

[msamani] tests: Adding MultiChannelMemory to x86-boot-tests

[msamani] tests: Adding MultiChannelMemory to riscv-boot


--
Started
Running as SYSTEM
Building in workspace 
The recommended git tool is: NONE
No credentials specified
 > git rev-parse --resolve-git-dir 
 >  # timeout=10
Fetching changes from the remote Git repository
 > git config remote.origin.url https://gem5.googlesource.com/public/gem5 # 
 > timeout=10
Fetching upstream changes from https://gem5.googlesource.com/public/gem5
 > git --version # timeout=10
 > git --version # 'git version 2.25.1'
 > git fetch --tags --force --progress -- 
 > https://gem5.googlesource.com/public/gem5 
 > +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
Checking out Revision 404bf901d074b186ea70831f476d50374a78c0dd 
(refs/remotes/origin/develop)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f 404bf901d074b186ea70831f476d50374a78c0dd # timeout=10
Commit message: "tests: Adding MultiChannelMemory to riscv-boot"
 > git rev-list --no-walk cf7ce21848ea4aeee28737823e6e768f9a14ceaf # timeout=10
[compiler-checks] $ /bin/sh -xe /tmp/jenkins15622977862381920238.sh
+ ./tests/compiler-tests.sh -j 70
Starting build tests with 'gcc-version-11'...
'gcc-version-11' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'NULL.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'X86_MI_example.fast' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-11'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-11'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-11'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-10'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-9'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-9'...
Done.
Starting build 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Use flattened register IDs in stored results in the checker CPU.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53663 )



Change subject: cpu: Use flattened register IDs in stored results in the  
checker CPU.

..

cpu: Use flattened register IDs in stored results in the checker CPU.

This makes the IDs comparable to ones recorded by the O3 CPU which works
in renamed (and hence flattened) IDs.

Change-Id: If5b028798b1065d8dbaf3a10ec2e22bb8c260ddd
---
M src/cpu/checker/cpu.hh
1 file changed, 18 insertions(+), 4 deletions(-)



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 37745c6..09a4878 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -197,8 +197,9 @@
 const RegId& id = si->destRegIdx(idx);
 if (id.is(InvalidRegClass))
 return;
-thread->setReg(id, val);
-result.emplace(id.regClass(), val);
+const RegId flat = id.flatten(*thread->getIsaPtr());
+thread->setRegFlat(flat, val);
+result.emplace(flat.regClass(), val);
 }

 void
@@ -207,8 +208,9 @@
 const RegId& id = si->destRegIdx(idx);
 if (id.is(InvalidRegClass))
 return;
-thread->setReg(id, val);
-result.emplace(id.regClass(), val);
+const RegId flat = id.flatten(*thread->getIsaPtr());
+thread->setRegFlat(flat, val);
+result.emplace(flat.regClass(), val);
 }

 bool readPredicate() const override { return thread->readPredicate(); }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If5b028798b1065d8dbaf3a10ec2e22bb8c260ddd
Gerrit-Change-Number: 53663
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Handle empty paths when resolving an "at" path.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53683 )



Change subject: sim-se: Handle empty paths when resolving an "at" path.
..

sim-se: Handle empty paths when resolving an "at" path.

When the "path" argument is empty, use the file name of the node
referred to by the fd file descriptor. This matches the behavior of
"at" system calls when the TGT_AT_EMPTY_PATH flag is set. The system
calls themselves are responsible for checking for that flag, and
returning an error if an empty "path" is not allowed.

Change-Id: Ib48d91ff983b3edb6f65e83686b90d79d74f3471
---
M src/sim/syscall_emul.hh
1 file changed, 19 insertions(+), 1 deletion(-)



diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index c53175b..2f49f5e 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -367,7 +367,10 @@
 if (!ffdp)
 return -EBADF;

-path = ffdp->getFileName() + "/" + path;
+if (path.empty())
+path = ffdp->getFileName();
+else
+path = ffdp->getFileName() + "/" + path;
 }

 return 0;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib48d91ff983b3edb6f65e83686b90d79d74f3471
Gerrit-Change-Number: 53683
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: ext: Make gem5-SST Memory Size configurable from script

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53625 )


Change subject: ext: Make gem5-SST Memory Size configurable from script
..

ext: Make gem5-SST Memory Size configurable from script

The memory interface param was hardcoded to 8GiB therefore
not matching any python changes in the memory size

Change-Id: I180f57f662886010a38a9b7ebbdbb73e0ae48276
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53625
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Hoa Nguyen 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M ext/sst/sst_responder_subcomponent.cc
M ext/sst/sst_responder_subcomponent.hh
2 files changed, 21 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Hoa Nguyen: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/ext/sst/sst_responder_subcomponent.cc  
b/ext/sst/sst_responder_subcomponent.cc

index 4c895ac..366f99a 100644
--- a/ext/sst/sst_responder_subcomponent.cc
+++ b/ext/sst/sst_responder_subcomponent.cc
@@ -40,6 +40,7 @@
 {
 sstResponder = new SSTResponder(this);
 gem5SimObjectName =  
params.find("response_receiver_name", "");

+memSize = params.find("mem_size", "8GiB");
 if (gem5SimObjectName == "")
 assert(false && "The response_receiver_name must be specified");
 }
@@ -58,7 +59,7 @@
 SST::Params interface_params;
 // This is how you tell the interface the name of the port it should  
use

 interface_params.insert("port", "port");
-interface_params.insert("mem_size", "8GiB");
+interface_params.insert("mem_size", memSize.c_str());
 // Loads a “memHierarchy.memInterface” into index 0 of the “memory”  
slot
 // SHARE_PORTS means the interface can use our port as if it were its  
own

 // INSERT_STATS means the interface will inherit our statistic
diff --git a/ext/sst/sst_responder_subcomponent.hh  
b/ext/sst/sst_responder_subcomponent.hh

index a897deb..51bc4f9 100644
--- a/ext/sst/sst_responder_subcomponent.hh
+++ b/ext/sst/sst_responder_subcomponent.hh
@@ -67,6 +67,7 @@
 std::vector initRequests;

 std::string gem5SimObjectName;
+std::string memSize;

   public:
 SSTResponderSubComponent(SST::ComponentId_t id, SST::Params& params);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I180f57f662886010a38a9b7ebbdbb73e0ae48276
Gerrit-Change-Number: 53625
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: compiler-checks #65

[jenkins-no-reply--- via gem5-dev]

See 


Changes:

[Bobby R. Bruce] scons,misc: Update default X86 protocol to MESI_Two_Level

[Bobby R. Bruce] stdlib: Add X86DemoBoard

[Bobby R. Bruce] tests: Add a nightly test for SST integration.


--
Started by timer
Running as SYSTEM
Building in workspace 
The recommended git tool is: NONE
No credentials specified
 > git rev-parse --resolve-git-dir 
 >  # timeout=10
Fetching changes from the remote Git repository
 > git config remote.origin.url https://gem5.googlesource.com/public/gem5 # 
 > timeout=10
Fetching upstream changes from https://gem5.googlesource.com/public/gem5
 > git --version # timeout=10
 > git --version # 'git version 2.25.1'
 > git fetch --tags --force --progress -- 
 > https://gem5.googlesource.com/public/gem5 
 > +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
Checking out Revision cf7ce21848ea4aeee28737823e6e768f9a14ceaf 
(refs/remotes/origin/develop)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f cf7ce21848ea4aeee28737823e6e768f9a14ceaf # timeout=10
Commit message: "tests: Add a nightly test for SST integration."
 > git rev-list --no-walk 35362d15f5e0ff914ff3ed76d1a385e76d282610 # timeout=10
[compiler-checks] $ /bin/sh -xe /tmp/jenkins11657432297015308831.sh
+ ./tests/compiler-tests.sh -j 70
Starting build tests with 'gcc-version-11'...
'gcc-version-11' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'POWER.opt' with 'gcc-version-11'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-11'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-11'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'X86_MI_example.fast' with 'gcc-version-11'...
  ! Failed with exit code 2.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-11'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-11'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-11'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-11'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-10'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'GCN3_X86.opt' with 'gcc-version-9'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-8'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-8'...
  

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding MultiChannelMemory to riscv-boot

[Mahyar Samani (Gerrit) via gem5-dev]

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53303 )


 (

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Adding MultiChannelMemory to riscv-boot
..

tests: Adding MultiChannelMemory to riscv-boot

This change adds MultiChannelMemory to the tests for full system
risc-v.

Change-Id: I3e9b6f7ac539c24ca9694c1c49afa09d0cecca2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53303
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
---
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M tests/gem5/configs/riscv_boot_exit_run.py
2 files changed, 79 insertions(+), 37 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index 8add619..45ce62c 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -36,15 +36,15 @@
 import m5
 from m5.objects import Root

-from gem5.components.boards.riscv_board import RiscvBoard
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.boards.riscv_board import RiscvBoard
+from gem5.components.processors.simple_processor import SimpleProcessor

 import argparse
+import importlib

 parser = argparse.ArgumentParser(
 description="A script to run the RISCV boot exit tests."
@@ -77,6 +77,14 @@
 )

 parser.add_argument(
+"-d",
+"--dram-class",
+type=str,
+required=True,
+help="The python class for the memory interface to use"
+)
+
+parser.add_argument(
 "-t",
 "--tick-exit",
 type=int,
@@ -117,7 +125,11 @@
 )

 # Setup the system memory.
-memory = SingleChannelDDR3_1600()
+python_module = "gem5.components.memory.multi_channel"
+memory_class = getattr(
+importlib.import_module(python_module), args.dram_class
+)
+memory = memory_class(size="4GiB")

 # Setup a processor.
 if args.cpu == "kvm":
diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py  
b/tests/gem5/riscv-boot-tests/test_linux_boot.py

index 9eb9ae3..6d4e9f1 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -40,12 +40,13 @@
 cpu: str,
 num_cpus: int,
 cache_type: str,
+memory_class: str,
 length: str,
 to_tick: Optional[int] = None,
 ):

-name = "{}-cpu_{}-{}-cores_riscv-boot-test".format(
-cpu, str(num_cpus), cache_type)
+name = "{}-cpu_{}-cores_{}_{}_riscv-boot-test".format(
+cpu, str(num_cpus), cache_type, memory_class)

 verifiers = []
 exit_regex = re.compile(
@@ -62,6 +63,8 @@
 str(num_cpus),
 "--mem-system",
 cache_type,
+"--dram-class",
+memory_class,
 "--resource-directory",
 resource_path,
 ]
@@ -94,6 +97,7 @@
 cpu="atomic",
 num_cpus=1,
 cache_type="classic",
+memory_class="SingleChannelDDR3_1600",
 length=constants.quick_tag,
 to_tick=100,  # Simulates 1/100th of a second.
 )
@@ -102,6 +106,7 @@
 cpu="timing",
 num_cpus=1,
 cache_type="classic",
+memory_class="SingleChannelDDR3_2133",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -110,6 +115,7 @@
 cpu="timing",
 num_cpus=1,
 cache_type="mi_example",
+memory_class="SingleChannelDDR4_2400",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -118,6 +124,7 @@
 cpu="o3",
 num_cpus=1,
 cache_type="classic",
+memory_class="DualChannelDDR3_1600",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -126,6 +133,7 @@
 cpu="timing",
 num_cpus=4,
 cache_type="classic",
+memory_class="DualChannelDDR3_2133",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -134,6 +142,7 @@
 cpu="timing",
 num_cpus=4,
 cache_type="mi_example",
+memory_class="DualChannelDDR4_2400",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -144,37 +153,42 @@
 # https://gem5.atlassian.net/browse/GEM5-1120, these tests have been  
disabled
 # until the exact error causing the Nightly tests to timeout is  
established.


-#test_boot(
-#cpu="atomic",
-#num_cpus=1,
-#cache_type="classic",
-#length=constants.long_tag,
-#)
+# test_boot(
+# cpu="atomic",
+# num_cpus=1,
+# cache_type="classic",
+# memory_class="HBM2Stack",
+# length=constants.long_tag,
+# )

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding MultiChannelMemory to x86-boot-tests

[Mahyar Samani (Gerrit) via gem5-dev]

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53243 )


 (

6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Adding MultiChannelMemory to x86-boot-tests
..

tests: Adding MultiChannelMemory to x86-boot-tests

This change adds modules from multi_channel.py to full system
tests for x86.

Change-Id: I585a381fa23c6595051ea917c080228e25e0a1a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53243
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
M tests/gem5/configs/x86_boot_exit_run.py
2 files changed, 60 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/x86_boot_exit_run.py  
b/tests/gem5/configs/x86_boot_exit_run.py

index 238136b..58e7713 100644
--- a/tests/gem5/configs/x86_boot_exit_run.py
+++ b/tests/gem5/configs/x86_boot_exit_run.py
@@ -35,16 +35,16 @@
 get_runtime_coherence_protocol,
 get_runtime_isa,
 )
-from gem5.utils.requires import requires
-from gem5.components.boards.x86_board import X86Board
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
+from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.components.boards.x86_board import X86Board
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor

 import argparse
+import importlib

 parser = argparse.ArgumentParser(
 description="A script to run the gem5 boot test. This test boots the "
@@ -75,6 +75,13 @@
 help="The CPU type.",
 )
 parser.add_argument(
+"-d",
+"--dram-class",
+type=str,
+required=True,
+help="The python class for the memory interface to use"
+)
+parser.add_argument(
 "-b",
 "--boot-type",
 type=str,
@@ -154,7 +161,11 @@
 # Setup the system memory.
 # Warning: This must be kept at 3GB for now. X86Motherboard does not  
support

 # anything else right now!
-memory = SingleChannelDDR3_1600(size="3GB")
+python_module = "gem5.components.memory.multi_channel"
+memory_class = getattr(
+importlib.import_module(python_module), args.dram_class
+)
+memory = memory_class(size="3GiB")

 # Setup a Processor.

diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py  
b/tests/gem5/x86-boot-tests/test_linux_boot.py

index d90f53b..77d1c0d 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -39,13 +39,14 @@
 cpu: str,
 num_cpus: int,
 mem_system: str,
+memory_class: str,
 length: str,
 boot_type: str = "init",
 to_tick: Optional[int] = None,
 ):

-name = "{}-cpu_{}-cores_{}_{}_x86-boot-test".format(
-cpu, str(num_cpus), mem_system, boot_type
+name = "{}-cpu_{}-cores_{}_{}_{}_x86-boot-test".format(
+cpu, str(num_cpus), mem_system, memory_class, boot_type
 )
 verifiers = []
 additional_config_args = []
@@ -89,6 +90,8 @@
 str(num_cpus),
 "--mem-system",
 mem_system,
+"--dram-class",
+memory_class,
 "--boot-type",
 boot_type,
 "--resource-directory",
@@ -108,6 +111,7 @@
 cpu="atomic",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelDDR3_1600",
 to_tick=100, #Simulates 1/100th of a second.
 length=constants.quick_tag,
 )
@@ -116,6 +120,7 @@
 cpu="timing",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelDDR3_2133",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -124,6 +129,7 @@
 cpu="atomic",
 num_cpus=4,
 mem_system="classic",
+memory_class="SingleChannelDDR4_2400",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -132,6 +138,7 @@
 cpu="o3",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelLPDDR3_1600",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -142,6 +149,7 @@
 cpu="atomic",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelHBM",
 boot_type="init",
 length=constants.long_tag,
 )
@@ -150,6 +158,7 @@
 cpu="timing",
 num_cpus=1,
 mem_system="mesi_two_level",
+memory_class="DualChannelDDR3_1600",
 boot_type="init",
  

[gem5-dev] Change in gem5/gem5[develop]: test: Updating simple_traffic_run and adding tests

[Mahyar Samani (Gerrit) via gem5-dev]

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53164 )


 (

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: test: Updating simple_traffic_run and adding tests
..

test: Updating simple_traffic_run and adding tests

This change updates simple_traffic_run.py with adding clock_domain
for GUPSGen based generators. Also the tests that resulted in
error before are now fixed and added.

Change-Id: I992898a3aef509afd9dec1f9b5d14c5fd67cff37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53164
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M tests/gem5/traffic_gen/simple_traffic_run.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
2 files changed, 24 insertions(+), 7 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/traffic_gen/simple_traffic_run.py  
b/tests/gem5/traffic_gen/simple_traffic_run.py

index 5230045..ede4993 100644
--- a/tests/gem5/traffic_gen/simple_traffic_run.py
+++ b/tests/gem5/traffic_gen/simple_traffic_run.py
@@ -35,7 +35,6 @@
 import argparse
 import importlib

-from os.path import join
 from m5.objects import Root, MemorySize
 from gem5.components.boards.test_board import TestBoard

@@ -71,15 +70,18 @@
 from gem5.components.processors.gups_generator import GUPSGenerator

 table_size = f"{int(mem_size / 2)}B"
-return GUPSGenerator(0, table_size, update_limit=1000)
+return GUPSGenerator(
+0, table_size, update_limit=1000, clk_freq="2GHz"
+)
 elif generator_class == "GUPSGeneratorEP":
 from gem5.components.processors.gups_generator_ep import (
 GUPSGeneratorEP,
 )

 table_size = f"{int(mem_size / 2)}B"
+
 return GUPSGeneratorEP(
-generator_cores, 0, table_size, update_limit=1000
+generator_cores, 0, table_size, update_limit=1000,  
clk_freq="2GHz"

 )
 elif generator_class == "GUPSGeneratorPAR":
 from gem5.components.processors.gups_generator_par import (
@@ -88,7 +90,7 @@

 table_size = f"{int(mem_size / 2)}B"
 return GUPSGeneratorPAR(
-generator_cores, 0, table_size, update_limit=1000
+generator_cores, 0, table_size, update_limit=1000,  
clk_freq="2GHz"

 )
 else:
 raise ValueError(f"Unknown generator class {generator_class}")
diff --git a/tests/gem5/traffic_gen/test_memory_traffic_gen.py  
b/tests/gem5/traffic_gen/test_memory_traffic_gen.py

index e5126ba..13b4638 100644
--- a/tests/gem5/traffic_gen/test_memory_traffic_gen.py
+++ b/tests/gem5/traffic_gen/test_memory_traffic_gen.py
@@ -106,9 +106,7 @@


 def create_single_core_tests(module, memory_classes):
-# TODO: Add GUPSGenerator to these tests after adding ClockDomain as
-# an input parameter.
-generator_classes = ["LinearGenerator", "RandomGenerator"]
+generator_classes =  
["LinearGenerator", "RandomGenerator", "GUPSGenerator"]

 for generator_class in generator_classes:
 for cache_class in cache_classes:
 for memory_class in memory_classes:

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53164
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I992898a3aef509afd9dec1f9b5d14c5fd67cff37
Gerrit-Change-Number: 53164
Gerrit-PatchSet: 10
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Adding clock_domain to GUPSGenerators

[Mahyar Samani (Gerrit) via gem5-dev]

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53163 )


 (

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Adding clock_domain to GUPSGenerators
..

stdlib: Adding clock_domain to GUPSGenerators

This change adds clock domain as a parameter to the GUPSGen
classes. This way the generator and other components can
work on different clock frequencies.

Change-Id: If916877a57b3c3a61073dad075e35f3f93af8459
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53163
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/python/gem5/components/processors/gups_generator_core.py
M src/python/gem5/components/processors/gups_generator_par.py
M src/python/gem5/components/processors/gups_generator.py
M src/python/gem5/components/processors/gups_generator_ep.py
4 files changed, 53 insertions(+), 21 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/processors/gups_generator.py  
b/src/python/gem5/components/processors/gups_generator.py

index 191be6b..41d1812 100644
--- a/src/python/gem5/components/processors/gups_generator.py
+++ b/src/python/gem5/components/processors/gups_generator.py
@@ -25,15 +25,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


-from ...utils.override import overrides
+from typing import Optional
 from m5.objects import Addr
+from ...utils.override import overrides

 from ..boards.mem_mode import MemMode
-
-from .gups_generator_core import GUPSGeneratorCore
-
 from .abstract_processor import AbstractProcessor
 from ..boards.abstract_board import AbstractBoard
+from .gups_generator_core import GUPSGeneratorCore


 class GUPSGenerator(AbstractProcessor):
@@ -42,6 +41,7 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int = 0,
+clk_freq: Optional[str] = None,
 ):
 """The GUPSGenerator class
 This class defines the interface for a single core GUPSGenerator,  
this

@@ -63,6 +63,7 @@
 start_addr=start_addr,
 mem_size=mem_size,
 update_limit=update_limit,
+clk_freq=clk_freq,
 )
 ]
 )
diff --git a/src/python/gem5/components/processors/gups_generator_core.py  
b/src/python/gem5/components/processors/gups_generator_core.py

index 8ce921e..f315b8b 100644
--- a/src/python/gem5/components/processors/gups_generator_core.py
+++ b/src/python/gem5/components/processors/gups_generator_core.py
@@ -24,10 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from m5.objects import Port, GUPSGen, Addr

+from typing import Optional
 from ...utils.override import overrides
 from .abstract_generator_core import AbstractGeneratorCore
+from m5.objects import Port, GUPSGen, Addr, SrcClockDomain, VoltageDomain


 class GUPSGeneratorCore(AbstractGeneratorCore):
@@ -36,14 +37,24 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int,
+clk_freq: Optional[str],
 ):
 """
 Create a GUPSGeneratorCore as the main generator.
 """
 super().__init__()
 self.generator = GUPSGen(
-start_addr=start_addr, mem_size=mem_size,  
update_limit=update_limit

-)
+start_addr=start_addr,
+mem_size=mem_size,
+update_limit=update_limit,
+)
+if clk_freq:
+clock_domain = SrcClockDomain(
+clock=clk_freq, voltage_domain=VoltageDomain()
+)
+self.generator.clk_domain = clock_domain
+
+

 @overrides(AbstractGeneratorCore)
 def connect_dcache(self, port: Port) -> None:
diff --git a/src/python/gem5/components/processors/gups_generator_ep.py  
b/src/python/gem5/components/processors/gups_generator_ep.py

index 203a88c..da27494 100644
--- a/src/python/gem5/components/processors/gups_generator_ep.py
+++ b/src/python/gem5/components/processors/gups_generator_ep.py
@@ -25,17 +25,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


-from ...utils.override import overrides
+from typing import Optional
 from m5.objects import Addr
-from m5.util.convert import toMemorySize
-
 from ..boards.mem_mode import MemMode
-
-from .gups_generator_core import GUPSGeneratorCore
-
+from ...utils.override import overrides
+from m5.util.convert import toMemorySize
 from .abstract_processor import AbstractProcessor
 from ..boards.abstract_board import AbstractBoard

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding new test for traffic_gen

[Mahyar Samani (Gerrit) via gem5-dev]

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52905 )


 (

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Adding new test for traffic_gen
..

tests: Adding new test for traffic_gen

This change adds new tests for MultiChannelMemory,
PrivateL1CacheHierarchy, PrivateL1PrivateL2CacheHierachy,
GUPSGenerator, GUPSGeneratorEP, GUPSGeneratorPAR.

Change-Id: I1db1281cdd4ade65d9abf2d979ef45342b63496a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52905
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
A tests/gem5/traffic_gen/simple_traffic_run.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
D tests/gem5/configs/simple_traffic_run.py
3 files changed, 309 insertions(+), 288 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/simple_traffic_run.py  
b/tests/gem5/configs/simple_traffic_run.py

deleted file mode 100644
index 33e4419..000
--- a/tests/gem5/configs/simple_traffic_run.py
+++ /dev/null
@@ -1,148 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-"""
-This scripts is used for checking the correctness of statistics reported
-by the gem5 simulator. It can excercise certain components in the memory
-subsystem. The reported values could be used to compare against a validated
-set of statistics.
-"""
-
-import m5
-import argparse
-import importlib
-
-from os.path import join
-from m5.objects import Root
-from m5.stats import gem5stats
-from gem5.components.boards.test_board import TestBoard
-from gem5.components.processors.linear_generator import LinearGenerator
-from gem5.components.processors.random_generator import RandomGenerator
-
-
-generator_class_map = {
-"LinearGenerator": LinearGenerator,
-"RandomGenerator": RandomGenerator,
-}
-
-generator_initializers = dict(rate="20GB/s")
-
-
-def cache_factory(cache_class):
-if cache_class == "NoCache":
-from gem5.components.cachehierarchies.classic.no_cache import  
NoCache

-
-return NoCache()
-elif cache_class == "MESITwoLevel":
-from gem5.components.cachehierarchies.ruby\
-.mesi_two_level_cache_hierarchy import (
-MESITwoLevelCacheHierarchy,
-)
-
-return MESITwoLevelCacheHierarchy(
-l1i_size="32KiB",
-l1i_assoc="8",
-l1d_size="32KiB",
-l1d_assoc="8",
-l2_size="256KiB",
-l2_assoc="4",
-num_l2_banks=1,
-)
-else:
-raise ValueError(f"The cache class {cache_class} is not  
supported.")

-
-
-parser = argparse.ArgumentParser(
-description="A traffic generator that can be used to test a gem5 "
-"memory component."
-)
-
-parser.add_argument(
-"generator_class",
-type=str,
-help="The class of generator to use.",
-choices=["LinearGenerator", "RandomGenerator"],
-)
-
-parser.add_argument(
-"cache_class",
-type=str,
-help="The cache class to import and instantiate.",
-choices=["NoCache", "MESITwoLevel"],
-)
-
-parser.add_argument(
-"mem_module",
-type=str,
-help="The python module to import for memory.",
-)
-
-parser.add_argument(
-"mem_class", type=str, 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Updated MuliChannelMemory constructor

[Mahyar Samani (Gerrit) via gem5-dev]

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52904 )


Change subject: stdlib: Updated MuliChannelMemory constructor
..

stdlib: Updated MuliChannelMemory constructor

This change updates the constructor for MultiChannelMemory. The
constructor now assumes every input parameter is of type string
and casts them to proper types inside the function. This way
the MultiChannelMemory could be tested easier. Considering that
tests might not want to pass in all the arguments and might use
argparser to read the inputs.

Change-Id: I80786066ccbb9cb1b7111831d9bc9d95e5204f40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52904
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M src/python/gem5/components/memory/multi_channel.py
1 file changed, 176 insertions(+), 15 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/memory/multi_channel.py  
b/src/python/gem5/components/memory/multi_channel.py

index 7d4baf1..8736f02 100644
--- a/src/python/gem5/components/memory/multi_channel.py
+++ b/src/python/gem5/components/memory/multi_channel.py
@@ -27,16 +27,21 @@
 """Multi channel "generic" DDR memory controllers
 """

-import enum
 from math import log
 from ...utils.override import overrides
 from m5.util.convert import toMemorySize
 from ..boards.abstract_board import AbstractBoard
 from .abstract_memory_system import AbstractMemorySystem
-from typing import Type, Sequence, Tuple, List, Optional
 from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port
+from typing import Type, Sequence, Tuple, List, Optional, Union


+def _try_convert(val, cls):
+try:
+return cls(val)
+except:
+raise Exception(f"Could not convert {val} to {cls}")
+
 def _isPow2(num):
 log_num = int(log(num, 2))
 if 2 ** log_num != num:
@@ -53,8 +58,8 @@
 def __init__(
 self,
 dram_interface_class: Type[DRAMInterface],
-num_channels: int,
-interleaving_size: int,
+num_channels: Union[int, str],
+interleaving_size: Union[int, str],
 size: Optional[str] = None,
 addr_mapping: Optional[str] = None,
 ) -> None:
@@ -66,12 +71,21 @@
 :param size: Optionally specify the size of the DRAM controller's
 address space. By default, it starts at 0 and ends at the size  
of

 the DRAM device specified
-:param add_mapping: Defines the address mapping scheme to be used.
-By default, it is RoRaBaChCo
+:param addr_mapping: Defines the address mapping scheme to be used.
+If None, it is defaulted to addr_mapping from  
dram_interface_class.
 :param interleaving_size: Defines the interleaving size of the  
multi-

 channel memory system. By default, it is equivalent to the atom
 size, i.e., 64.
 """
+num_channels = _try_convert(num_channels, int)
+interleaving_size = _try_convert(interleaving_size, int)
+
+if size:
+size = _try_convert(size, str)
+
+if addr_mapping:
+addr_mapping = _try_convert(addr_mapping, str)
+
 super().__init__()
 self._dram_class = dram_interface_class
 self._num_channels = num_channels
@@ -98,7 +112,6 @@
 MemCtrl(dram=self._dram[i]) for i in range(num_channels)
 ]

-
 def _get_dram_size(self, num_channels: int, dram: DRAMInterface) ->  
int:

 return num_channels * (
 dram.device_size.value
@@ -107,8 +120,6 @@
 )

 def _interleave_addresses(self):
-print(f"Memory is interleaving the address range {self._mem_range}"
-f" using {self._intlv_size} as interleaving size.")
 if self._addr_mapping == "RoRaBaChCo":
 rowbuffer_size = (
 self._dram_class.device_rowbuffer_size.value
@@ -127,8 +138,8 @@
 for i, ctrl in enumerate(self.mem_ctrl):
 ctrl.dram.range = AddrRange(
 start=self._mem_range.start,
-end=self._mem_range.size(),
-intlvHighBit = intlv_low_bit + intlv_bits - 1,
+size=self._mem_range.size(),
+intlvHighBit=intlv_low_bit + intlv_bits - 1,
 xorHighBit=0,
 intlvBits=intlv_bits,
 intlvMatch=i,
@@ -137,10 +148,12 @@
 @overrides(AbstractMemorySystem)
 def incorporate_memory(self, board: AbstractBoard) -> None:
 if self._intlv_size < int(board.get_cache_line_size()):
-raise ValueError("Memory interleaving size can not be smaller  
than"

-" board's cache line size.\nBoard's cache line size: "
-f"{board.get_cache_line_size()}\n, This memory's interleaving "
-f"size: