Re: [PATCH 1/5] mips: start.S: Add Octeon boot header compatibility
On 26.10.20 14:42, Daniel Schwierzeck wrote: Am Freitag, den 16.10.2020, 15:08 +0200 schrieb Stefan Roese: Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck --- arch/mips/cpu/start.S | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index d0c412236d..6de2470cc2 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -75,8 +75,13 @@ ENTRY(_start) /* U-Boot entry point */ + /* +* Octeon needs special handling here, as the binary might be +* patched to add a boot header for SPI, NAND or MMC booting. Only +* one branch plus nop is allowed here. +*/ I'd prefer a shorter and more imperative comment within one multi-line comment block, e.g. /* * U-Boot entry point. * Do not add instructions to the branch delay slot! Some SoC's * like Octeon might patch the final U-Boot binary at this location * with additional boot headers. */ Even better. Will change in v2. b reset -mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing +nop #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) /* @@ -123,6 +128,7 @@ ENTRY(_start) #endif reset: +mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing the extra indentation of one space is only required for instructions in delay slots and needs to be removed. Yes, thanks for catching. Thanks, Stefan
[PATCH 1/2] pinctrl: stm32: display bias information for all pins
Display the bias information for input gpios or AF configuration,
and not only for output pin, as described in Reference manual
(Table 81. Port bit configuration table).
Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration")
Signed-off-by: Patrick Delaunay
---
drivers/pinctrl/pinctrl_stm32.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index dbea99532c..262b2c3d7e 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -48,15 +48,15 @@ static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
"alt function",
};
-static const char * const pinmux_output[] = {
- [STM32_GPIO_PUPD_NO] = "bias-disable",
- [STM32_GPIO_PUPD_UP] = "bias-pull-up",
- [STM32_GPIO_PUPD_DOWN] = "bias-pull-down",
+static const char * const pinmux_bias[] = {
+ [STM32_GPIO_PUPD_NO] = "",
+ [STM32_GPIO_PUPD_UP] = "pull-up",
+ [STM32_GPIO_PUPD_DOWN] = "pull-down",
};
static const char * const pinmux_input[] = {
- [STM32_GPIO_OTYPE_PP] = "drive-push-pull",
- [STM32_GPIO_OTYPE_OD] = "drive-open-drain",
+ [STM32_GPIO_OTYPE_PP] = "push-pull",
+ [STM32_GPIO_OTYPE_OD] = "open-drain",
};
static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
@@ -213,6 +213,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
selector, gpio_idx, mode);
priv = dev_get_priv(gpio_dev);
+ pupd = (readl(>regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
switch (mode) {
@@ -224,20 +225,19 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice
*dev,
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
- snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
+ snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
+pinmux_bias[pupd]);
break;
case GPIOF_OUTPUT:
- pupd = (readl(>regs->pupdr) >> (gpio_idx * 2)) &
- PUPD_MASK;
snprintf(buf, size, "%s %s %s",
-pinmux_mode[mode], pinmux_output[pupd],
+pinmux_mode[mode], pinmux_bias[pupd],
label ? label : "");
break;
case GPIOF_INPUT:
otype = (readl(>regs->otyper) >> gpio_idx) & OTYPE_MSK;
- snprintf(buf, size, "%s %s %s",
+ snprintf(buf, size, "%s %s %s %s",
pinmux_mode[mode], pinmux_input[otype],
-label ? label : "");
+pinmux_bias[pupd], label ? label : "");
break;
}
--
2.17.1
[PATCH 2/2] gpio: stm32: correct the bias management
Use the bias configuration for all the GPIO configurations and not
only for input GPIO, as indicated in Reference manual
(Table 81. Port bit configuration table).
Fixes: 43efbb6a3ebf0223f9eab8d45916f602d876319f ("gpio: stm32: add ops
get_dir_flags")
Fixes: f13ff88b61c32ac8f0e9068c41328b265ef619eb ("gpio: stm32: add ops
set_dir_flags")
Signed-off-by: Patrick Delaunay
---
drivers/gpio/stm32_gpio.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index b885cfb57e..51e1efd701 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -212,11 +212,11 @@ static int stm32_gpio_set_dir_flags(struct udevice *dev,
unsigned int offset,
} else if (flags & GPIOD_IS_IN) {
stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
- if (flags & GPIOD_PULL_UP)
- stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
- else if (flags & GPIOD_PULL_DOWN)
- stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
}
+ if (flags & GPIOD_PULL_UP)
+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
+ else if (flags & GPIOD_PULL_DOWN)
+ stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
return 0;
}
@@ -243,16 +243,16 @@ static int stm32_gpio_get_dir_flags(struct udevice *dev,
unsigned int offset,
break;
case STM32_GPIO_MODE_IN:
dir_flags |= GPIOD_IS_IN;
- switch (stm32_gpio_get_pupd(regs, idx)) {
- case STM32_GPIO_PUPD_UP:
- dir_flags |= GPIOD_PULL_UP;
- break;
- case STM32_GPIO_PUPD_DOWN:
- dir_flags |= GPIOD_PULL_DOWN;
- break;
- default:
- break;
- }
+ break;
+ default:
+ break;
+ }
+ switch (stm32_gpio_get_pupd(regs, idx)) {
+ case STM32_GPIO_PUPD_UP:
+ dir_flags |= GPIOD_PULL_UP;
+ break;
+ case STM32_GPIO_PUPD_DOWN:
+ dir_flags |= GPIOD_PULL_DOWN;
break;
default:
break;
--
2.17.1
[PATCH v1 2/9] pca9450a: fix i2c address
From: Max Krummenacher
The I2C address is 0x25, not 0x35. This according to the datasheet and
tests with a PCA9450A.
Signed-off-by: Max Krummenacher
---
drivers/power/pmic/pca9450.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index 0c9d9a366e..c7f8b80954 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -80,7 +80,7 @@ static struct dm_pmic_ops pca9450_ops = {
};
static const struct udevice_id pca9450_ids[] = {
- { .compatible = "nxp,pca9450a", .data = 0x35, },
+ { .compatible = "nxp,pca9450a", .data = 0x25, },
{ .compatible = "nxp,pca9450b", .data = 0x25, },
{ }
};
--
2.17.1
[PATCH v1 4/9] ARM: dts: imx8mm-verdin: follow changed pmic
From: Max Krummenacher
The used PMIC has been changed from RHOM BD71837 to NXP PCA9450A.
Adjust the device tree accordingly.
Remove the old ADC node as the ADC has been changed and has no longer
a separate power rail.
Signed-off-by: Max Krummenacher
Signed-off-by: Igor Opaniuk
---
arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 5 +-
arch/arm/dts/imx8mm-verdin.dts | 154 +
2 files changed, 80 insertions(+), 79 deletions(-)
diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
index fe6bb9bf03..249b0f8f66 100644
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@@ -2,7 +2,6 @@
/*
* Copyright 2020 Toradex
*/
-
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -90,11 +89,11 @@
u-boot,dm-spl;
};
-&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+&{/soc@0/bus@3080/i2c@30a2/pmic} {
u-boot,dm-spl;
};
-&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+&{/soc@0/bus@3080/i2c@30a2/pmic/regulators} {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts
index 1c67c08c88..fb0756d6e1 100644
--- a/arch/arm/dts/imx8mm-verdin.dts
+++ b/arch/arm/dts/imx8mm-verdin.dts
@@ -203,115 +203,123 @@
pinctrl-0 = <_i2c1>;
status = "okay";
- pmic@4b {
- compatible = "rohm,bd71840", "rohm,bd71837";
- bd71837,pmic-buck2-uses-i2c-dvs;
- bd71837,pmic-buck2-dvs-voltage = <100>, <90>, <0>; /*
VDD_ARM: Run-Idle */
- gpio_intr = < 3 GPIO_ACTIVE_LOW>;
- /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
+ /* Assembled on V1.1 HW and later */
+ pmic {
+ reg = <0x25>;
+ u-boot,dm-spl;
+ compatible = "nxp,pca9450a";
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <_pmic>;
- reg = <0x4b>;
-
- gpo {
- rohm,drv = <0x0C>; /* 0b_1100 all gpos with
cmos output mode */
- };
+ gpio_intr = < 3 GPIO_ACTIVE_LOW>;
regulators {
- buck1_reg: BUCK1 {
- regulator-always-on;
- regulator-boot-on;
+ u-boot,dm-spl;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <95>, <85>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
regulator-compatible = "buck1";
- regulator-max-microvolt = <130>;
- regulator-min-microvolt = <70>;
- regulator-ramp-delay = <1250>;
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
};
- buck2_reg: BUCK2 {
- regulator-always-on;
- regulator-boot-on;
+ buck2_reg: regulator@1 {
+ reg = <1>;
regulator-compatible = "buck2";
- regulator-max-microvolt = <130>;
- regulator-min-microvolt = <70>;
- regulator-ramp-delay = <1250>;
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
};
- buck5_reg: BUCK5 {
- regulator-always-on;
+ buck3_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "buck3";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
- regulator-compatible = "buck5";
- regulator-max-microvolt = <135>;
- regulator-min-microvolt = <70>;
+ regulator-always-on;
};
- buck6_reg: BUCK6 {
-
[PATCH v1 1/9] toradex: tdx-cfg-clock: add new i.mx 8m mini/plus skus
From: Marcel Ziswiler
Add new i.MX 8M Mini/Plus SKUs to ConfigBlock handling:
0058: Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT
0059: Verdin iMX8M Mini Quad 2GB IT
0060: Verdin iMX8M Mini DualLite 1GB WB IT
0061: Verdin iMX8M Plus Quad 2GB
Rename existing SKU (use correct one):
Verdin iMX8M Nano SoloLite 1GB -> Verdin iMX8M Nano Quad 1GB Wi-Fi
Signed-off-by: Igor Opaniuk
Signed-off-by: Marcel Ziswiler
---
board/toradex/common/tdx-cfg-block.c | 42
board/toradex/common/tdx-cfg-block.h | 8 --
2 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/board/toradex/common/tdx-cfg-block.c
b/board/toradex/common/tdx-cfg-block.c
index bf27b2fa66..475abf78a7 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -16,7 +16,8 @@
defined(CONFIG_TARGET_COLIBRI_IMX6) || \
defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
- defined(CONFIG_TARGET_VERDIN_IMX8MN)
+ defined(CONFIG_TARGET_VERDIN_IMX8MN) || \
+ defined(CONFIG_TARGET_VERDIN_IMX8MP)
#include
#else
#define is_cpu_type(cpu) (0)
@@ -137,8 +138,12 @@ const char * const toradex_modules[] = {
[53] = "Apalis iMX8 QuadXPlus 2GB ECC IT",
[54] = "Apalis iMX8 DualXPlus 1GB",
[55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT",
- [56] = "Verdin iMX8M Nano SoloLite 1GB", /* not currently on sale */
+ [56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on
sale */
[57] = "Verdin iMX8M Mini DualLite 1GB",
+ [58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT",
+ [59] = "Verdin iMX8M Mini Quad 2GB IT",
+ [60] = "Verdin iMX8M Mini DualLite 1GB WB IT",
+ [61] = "Verdin iMX8M Plus Quad 2GB",
};
const char * const toradex_carrier_boards[] = {
@@ -361,21 +366,15 @@ static int get_cfgblock_interactive(void)
if (cpu_is_pxa27x())
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
-#if !defined(CONFIG_TARGET_VERDIN_IMX8MM) ||
!defined(CONFIG_TARGET_VERDIN_IMX8MN)
- else
- sprintf(message, "Is the module an IT version? [y/N] ");
-
- len = cli_readline(message);
- it = console_buffer[0];
-#else
else
it = 'y';
-#endif
#if defined(CONFIG_TARGET_APALIS_IMX8) || \
defined(CONFIG_TARGET_APALIS_IMX8X) || \
defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
- defined(CONFIG_TARGET_COLIBRI_IMX8X)
+ defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
+ defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
+ defined(CONFIG_TARGET_VERDIN_IMX8MP)
sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
len = cli_readline(message);
wb = console_buffer[0];
@@ -429,7 +428,7 @@ static int get_cfgblock_interactive(void)
else if (is_cpu_type(MXC_CPU_IMX8MMDL))
tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
else if (is_cpu_type(MXC_CPU_IMX8MN))
- tdx_hw_tag.prodid = VERDIN_IMX8MNSL;
+ tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
else if (is_cpu_type(MXC_CPU_IMX8QM)) {
if (it == 'y' || it == 'Y') {
if (wb == 'y' || wb == 'Y')
@@ -465,6 +464,25 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.prodid = COLIBRI_IMX8DX;
}
#endif
+ } else if (is_cpu_type(MXC_CPU_IMX8MM)) {
+ if (is_cpu_type(MXC_CPU_IMX8MMDL)) {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
+ } else {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
+ }
+ } else if (is_cpu_type(MXC_CPU_IMX8MN)) {
+ tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
+ } else if (is_cpu_type(MXC_CPU_IMX8MP)) {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ;
} else if (!strcmp("tegra20", soc)) {
if (it == 'y' || it == 'Y')
if (gd->ram_size == 0x1000)
diff --git a/board/toradex/common/tdx-cfg-block.h
b/board/toradex/common/tdx-cfg-block.h
index 8f91d9aec6..9debd5f046 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -75,9 +75,13 @@ enum {
COLIBRI_IMX8DX,
APALIS_IMX8QXP,
APALIS_IMX8DXP,
- VERDIN_IMX8MMQ_WIFI_BT_IT,
- VERDIN_IMX8MNSL,
+ VERDIN_IMX8MMQ_WIFI_BT_IT, /* 55 */
+
[PATCH v1 8/9] toradex: tdx-cfg-clock: fix i.mx 8m mini interactive
From: Marcel Ziswiler
Now with them first Verdin iMX8M Mini DualLite modules in for bring-up
we got clarity how is_cpu_type() actually behaves.
Signed-off-by: Marcel Ziswiler
---
board/toradex/common/tdx-cfg-block.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/board/toradex/common/tdx-cfg-block.c
b/board/toradex/common/tdx-cfg-block.c
index 475abf78a7..adab0a0802 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -423,12 +423,6 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.prodid = COLIBRI_IMX7D;
else if (!strcmp("imx7s", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7S;
- else if (is_cpu_type(MXC_CPU_IMX8MM))
- tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
- else if (is_cpu_type(MXC_CPU_IMX8MMDL))
- tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
- else if (is_cpu_type(MXC_CPU_IMX8MN))
- tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
else if (is_cpu_type(MXC_CPU_IMX8QM)) {
if (it == 'y' || it == 'Y') {
if (wb == 'y' || wb == 'Y')
@@ -464,18 +458,16 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.prodid = COLIBRI_IMX8DX;
}
#endif
+ } else if (is_cpu_type(MXC_CPU_IMX8MMDL)) {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
} else if (is_cpu_type(MXC_CPU_IMX8MM)) {
- if (is_cpu_type(MXC_CPU_IMX8MMDL)) {
- if (wb == 'y' || wb == 'Y')
- tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT;
- else
- tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
- } else {
- if (wb == 'y' || wb == 'Y')
- tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
- else
- tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
- }
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
} else if (is_cpu_type(MXC_CPU_IMX8MN)) {
tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
} else if (is_cpu_type(MXC_CPU_IMX8MP)) {
--
2.17.1
[PATCH v1 9/9] verdin-imx8mm: automatic ram size detection
From: Marcel Ziswiler
Implement board_phys_sdram_size() to automatically detect Verdin iMX8M
Mini DualLite 1GB vs. Verdin iMX8M Mini Quad 2GB.
Note: This only works if we keep using similar RAM chips!
Signed-off-by: Marcel Ziswiler
---
board/toradex/verdin-imx8mm/verdin-imx8mm.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 9c6f35e778..7cfae8767c 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -180,6 +180,16 @@ int board_late_init(void)
return 0;
}
+int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
--
2.17.1
[PATCH v1 3/9] power: pmic: add SPL_DM_PMIC_PCA9450 symbol to Kconfig
From: Igor Opaniuk Add SPL_DM_PMIC_PCA9450 symbol to Kconfig. Signed-off-by: Igor Opaniuk --- drivers/power/pmic/Kconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index a62aa38054..7d51510d1b 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -98,6 +98,13 @@ config DM_PMIC_PCA9450 This config enables implementation of driver-model pmic uclass features for PMIC PCA9450. The driver implements read/write operations. +config SPL_DM_PMIC_PCA9450 + bool "Enable Driver Model for PMIC PCA9450" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC PCA9450 in SPL. The driver implements read/write operations. + config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" depends on DM_PMIC -- 2.17.1
[PATCH v1 5/9] verdin-imx8mm: spl: switch to pca9450 pmic
From: Max Krummenacher
V1.1A HW switched the PMIC from BD71837 to PCA9450.
- Disable combined DVS in PCA9450_BUCK123_DVS.
- Increase DDR Voltage to 0.95V as we use a 1.5GHz RAM.
- Configure WDOG_B behaviour.
Signed-off-by: Max Krummenacher
Signed-off-by: Igor Opaniuk
---
board/toradex/verdin-imx8mm/spl.c | 42 +++
configs/verdin-imx8mm_defconfig | 2 +-
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/board/toradex/verdin-imx8mm/spl.c
b/board/toradex/verdin-imx8mm/spl.c
index cc78c5666b..9562cdeb35 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -21,12 +21,16 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
DECLARE_GLOBAL_DATA_PTR;
+#define I2C_PMIC_BUS_ID1
+
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -101,33 +105,27 @@ int power_init_board(void)
struct udevice *dev;
int ret;
- ret = pmic_get("pmic@4b", );
- if (ret == -ENODEV) {
- puts("No pmic\n");
- return 0;
- }
- if (ret != 0)
- return ret;
+ if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
+ ret = pmic_get("pmic", );
+ if (ret == -ENODEV) {
+ puts("No pmic found\n");
+ return ret;
+ }
- /* decrease RESET key long push time from the default 10s to 10ms */
- pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+ if (ret != 0)
+ return ret;
- /* unlock the PMIC regs */
- pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+ /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
- /* increase VDD_SOC to typical value 0.85v before first DRAM access */
- pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+ /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
- /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
- pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
-#ifndef CONFIG_IMX8M_LPDDR4
- /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
- pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
-#endif
-
- /* lock the PMIC regs */
- pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+ return 0;
+ }
return 0;
}
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 7ebfd6792f..d856e3a318 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -91,7 +91,7 @@ CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
-CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
--
2.17.1
[PATCH v1 6/9] verdin-imx8mm: implement hardware version detection
From: Max Krummenacher
And select the correct devicetree accordingly by setting the variant
environment variable.
Signed-off-by: Igor Opaniuk
Signed-off-by: Max Krummenacher
---
board/toradex/verdin-imx8mm/verdin-imx8mm.c | 71 +
1 file changed, 71 insertions(+)
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 66950ed218..9c6f35e778 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -8,12 +8,22 @@
#include
#include
#include
+#include
#include
#include
#include
+#include "../common/tdx-cfg-block.h"
+
DECLARE_GLOBAL_DATA_PTR;
+#define I2C_PMIC 0
+
+enum pcb_rev_t {
+ PCB_VERSION_1_0,
+ PCB_VERSION_1_1
+};
+
#if IS_ENABLED(CONFIG_FEC_MXC)
static int setup_fec(void)
{
@@ -104,8 +114,69 @@ int board_mmc_get_env_dev(int devno)
return devno;
}
+static enum pcb_rev_t get_pcb_revision(void)
+{
+ struct udevice *bus;
+ struct udevice *i2c_dev = NULL;
+ int ret;
+ u8 is_bd71837 = 0;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PMIC, );
+ if (!ret)
+ ret = dm_i2c_probe(bus, 0x4b, 0, _dev);
+ if (!ret)
+ ret = dm_i2c_read(i2c_dev, 0x0, _bd71837, 1);
+
+ /* BD71837_REV, High Nibble is major version, fix 1010 */
+ is_bd71837 = !ret && ((is_bd71837 & 0xf0) == 0xa0);
+ return is_bd71837 ? PCB_VERSION_1_0 : PCB_VERSION_1_1;
+}
+
+static void select_dt_from_module_version(void)
+{
+ char variant[32];
+ char *env_variant = env_get("variant");
+ int is_wifi = 0;
+
+ if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+ /*
+* If we have a valid config block and it says we are a
+* module with Wi-Fi/Bluetooth make sure we use the -wifi
+* device tree.
+*/
+ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT);
+ }
+
+ switch (get_pcb_revision()) {
+ case PCB_VERSION_1_0:
+ printf("Detected a V1.0 module\n");
+ if (is_wifi)
+ strncpy([0], "wifi", sizeof(variant));
+ else
+ strncpy([0], "nonwifi", sizeof(variant));
+ break;
+ default:
+ if (is_wifi)
+ strncpy([0], "wifi-v1.1", sizeof(variant));
+ else
+ strncpy([0], "nonwifi-v1.1", sizeof(variant));
+ break;
+ }
+
+ if (strcmp(variant, env_variant)) {
+ printf("Setting variant to %s\n", variant);
+ env_set("variant", variant);
+
+ if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+ env_save();
+ }
+}
+
int board_late_init(void)
{
+ select_dt_from_module_version();
+
return 0;
}
--
2.17.1
[PATCH v1 7/9] verdin-imx8mm: spl: enable pca9450 i2c level translator
From: Max Krummenacher Enable PCA9450 i2c level translator, as this is used for the on module ADC. Signed-off-by: Max Krummenacher --- board/toradex/verdin-imx8mm/spl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 9562cdeb35..72e2e09e25 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -124,6 +124,8 @@ int power_init_board(void) /* set WDOG_B_CFG to cold reset */ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); + return 0; } -- 2.17.1
[PATCH 0/8] Pin control support for RZ/G2[HN]
This patch series adds pin control support for RZ/G2[HN] SoC's. Also added pinctrl optimization for RZ/G2[HMN] SoC's. This patches are based on u-boot-sh/next. + Geert The last 3 patches in this series are RFC, which aims to optimize pinctrl size for RCar SoC 's( The u-boot size is reduced from 1025221 to 964365 bytes) The saving is around ~60K. Please share your comments. Note:- 1) I haven't tested the RFC changes on r-car boards due to unavailability of the boards. 2) Optimization is based on the fact that some pins are not enabled in board dts(like DRIF,MSIOF etc..) u-boot-sh\next -- $ size drivers/pinctrl/renesas/*.o textdata bss dec hex filename 151332 288 1 151621 25045 drivers/pinctrl/renesas/built-in.o 3811 288 141001004 drivers/pinctrl/renesas/pfc.o 48123 0 0 48123bbfb drivers/pinctrl/renesas/pfc-r8a7795.o 47939 0 0 47939bb43 drivers/pinctrl/renesas/pfc-r8a77965.o 47751 0 0 47751ba87 drivers/pinctrl/renesas/pfc-r8a7796.o $ ls -al u-boot.bin -rw-r--r-- 1 biju biju 1025221 Oct 28 08:48 u-boot.bin $ size u-boot textdata bss dec hex filename 942336 36208 71632 1050176 100640 u-boot After Applying patch 1-5 -- $ size drivers/pinctrl/renesas/*.o textdata bss dec hex filename 151868 288 1 152157 2525d drivers/pinctrl/renesas/built-in.o 3811 288 141001004 drivers/pinctrl/renesas/pfc.o 48375 0 0 48375bcf7 drivers/pinctrl/renesas/pfc-r8a7795.o 48191 0 0 48191bc3f drivers/pinctrl/renesas/pfc-r8a77965.o 47751 0 0 47751ba87 drivers/pinctrl/renesas/pfc-r8a7796.o $ ls -al u-boot.bin -rw-r--r-- 1 biju biju 1026621 Oct 28 08:42 u-boot.bin $ size u-boot textdata bss dec hex filename 943732 36208 71632 1051572 100bb4 u-boot After applying RFC patches -- $ size drivers/pinctrl/renesas/*.o textdata bss dec hex filename 125310 288 1 125599 1ea9f drivers/pinctrl/renesas/built-in.o 3811 288 141001004 drivers/pinctrl/renesas/pfc.o 40157 0 0 401579cdd drivers/pinctrl/renesas/pfc-r8a7795.o 39973 0 0 399739c25 drivers/pinctrl/renesas/pfc-r8a77965.o 39533 0 0 395339a6d drivers/pinctrl/renesas/pfc-r8a7796.o $ ls -al u-boot.bin -rw-r--r-- 1 biju biju 964365 Oct 28 09:32 u-boot.bin $ size u-boot textdata bss dec hex filename 881478 36208 71632 989318 f1886 u-boot Biju Das (8): pinctrl: renesas: r8a77965: Add R8A774B1 PFC support pinctrl: renesas: r8a77951: Add R8A774E1 PFC support pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1 pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1 pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1 pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A7796 pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A77965 pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A7795 arch/arm/mach-rmobile/Kconfig.64 | 2 + drivers/pinctrl/renesas/Kconfig| 26 + drivers/pinctrl/renesas/Makefile | 2 + drivers/pinctrl/renesas/pfc-r8a7795.c | 939 ++--- drivers/pinctrl/renesas/pfc-r8a7796.c | 36 + drivers/pinctrl/renesas/pfc-r8a77965.c | 931 +--- drivers/pinctrl/renesas/pfc.c | 22 + drivers/pinctrl/renesas/sh_pfc.h | 2 + 8 files changed, 1146 insertions(+), 814 deletions(-) -- 2.17.1
[PATCH 2/8] pinctrl: renesas: r8a77951: Add R8A774E1 PFC support
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951),
however it doesn't have several automotive specific peripherals. Add
a r8a77951 specific pin groups/functions along with common pin
groups/functions for supporting both r8a77951 and r8a774e1 SoC.
PFC changes are synced from mainline linux-5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
arch/arm/mach-rmobile/Kconfig.64 | 1 +
drivers/pinctrl/renesas/Kconfig | 10 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pfc-r8a7795.c | 905 ++
drivers/pinctrl/renesas/pfc.c | 11 +
drivers/pinctrl/renesas/sh_pfc.h | 1 +
6 files changed, 520 insertions(+), 409 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 91aa4ddbae..0ef6cf619b 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -17,6 +17,7 @@ config R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
imply CLK_R8A774E1
+ imply PINCTRL_PFC_R8A774E1
config R8A7795
bool "Renesas SoC R8A7795"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0d839eecad..d2be4c84ba 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -77,6 +77,16 @@ config PINCTRL_PFC_R8A774B1
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R8A774E1
+bool "Renesas RZ/G2 R8A774E1 pin control driver"
+depends on PINCTRL_PFC
+help
+ Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 59dfd05b2c..1d00752051 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c
b/drivers/pinctrl/renesas/pfc-r8a7795.c
index ba17a55775..b787c4883a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7795.c
@@ -683,7 +683,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,I2C_SEL_3_0,
SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0,
SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,I2C_SEL_3_0,
SEL_IEBUS_1),
- PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
+ PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,I2C_SEL_3_0,
SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,I2C_SEL_3_0,
SEL_HSCIF3_3),
@@ -3902,6 +3902,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
+/* - TPU --- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
/* - USB0 ---
*/
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4136,353 +4166,365 @@ static const unsigned int vin5_clk_mux[] = {
VI5_CLK_MARK,
};
-static const struct sh_pfc_pin_group pinmux_groups[] = {
- SH_PFC_PIN_GROUP(audio_clk_a_a),
- SH_PFC_PIN_GROUP(audio_clk_a_b),
- SH_PFC_PIN_GROUP(audio_clk_a_c),
- SH_PFC_PIN_GROUP(audio_clk_b_a),
- SH_PFC_PIN_GROUP(audio_clk_b_b),
- SH_PFC_PIN_GROUP(audio_clk_c_a),
- SH_PFC_PIN_GROUP(audio_clk_c_b),
-
[PATCH 3/8] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
(R8A7796[01]) is not enabled.
Based on the similar patch on Linux.
Signed-off-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a7796.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c
b/drivers/pinctrl/renesas/pfc-r8a7796.c
index a92c8ad18c..da7901ea6e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -1841,6 +1841,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#if defined(CONFIG_PINCTRL_PFC_R8A7796)
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2055,6 +2056,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -4113,7 +4115,9 @@ static const unsigned int vin5_clk_mux[] = {
static const struct {
struct sh_pfc_pin_group common[312];
+#if defined(CONFIG_PINCTRL_PFC_R8A7796)
struct sh_pfc_pin_group automotive[30];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4429,6 +4433,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
+#if defined(CONFIG_PINCTRL_PFC_R8A7796)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4461,6 +4466,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
};
static const char * const audio_clk_groups[] = {
@@ -4519,6 +4525,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#if defined(CONFIG_PINCTRL_PFC_R8A7796)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4560,6 +4567,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4966,7 +4974,9 @@ static const char * const vin5_groups[] = {
static const struct {
struct sh_pfc_function common[49];
+#if defined(CONFIG_PINCTRL_PFC_R8A7796)
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -5019,12 +5029,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#if defined(CONFIG_PINCTRL_PFC_R8A7796)
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.17.1
[PATCH 1/8] pinctrl: renesas: r8a77965: Add R8A774B1 PFC support
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965),
however it doesn't have several automotive specific peripherals. Add
a r8a77965 specific pin groups/functions along with common pin
groups/functions for supporting both r8a77965 and r8a774b1 SoC.
PFC changes are synced from mainline linux-5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
arch/arm/mach-rmobile/Kconfig.64 | 1 +
drivers/pinctrl/renesas/Kconfig| 10 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pfc-r8a77965.c | 895 ++---
drivers/pinctrl/renesas/pfc.c | 11 +
drivers/pinctrl/renesas/sh_pfc.h | 1 +
6 files changed, 514 insertions(+), 405 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index be3ea3c1a9..91aa4ddbae 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -8,6 +8,7 @@ config R8A774A1
config R8A774B1
bool "Renesas SoC R8A774B1"
imply CLK_R8A774B1
+ imply PINCTRL_PFC_R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index e14294b6e7..0d839eecad 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -67,6 +67,16 @@ config PINCTRL_PFC_R8A774A1
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R8A774B1
+bool "Renesas RZ/G2 R8A774B1 pin control driver"
+depends on PINCTRL_PFC
+help
+ Support pin multiplexing control on Renesas RZ/G2N R8A774B1 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index a4eb912d54..59dfd05b2c 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c
b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 2523904aec..387330e4a3 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -691,7 +691,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
- PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
+ PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
@@ -4118,6 +4118,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
+/* - TPU --- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
/* - USB0 ---
*/
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4358,351 +4388,362 @@ static const unsigned int vin5_clk_mux[] = {
VI5_CLK_MARK,
};
-static const struct sh_pfc_pin_group pinmux_groups[] = {
- SH_PFC_PIN_GROUP(audio_clk_a_a),
- SH_PFC_PIN_GROUP(audio_clk_a_b),
- SH_PFC_PIN_GROUP(audio_clk_a_c),
- SH_PFC_PIN_GROUP(audio_clk_b_a),
- SH_PFC_PIN_GROUP(audio_clk_b_b),
- SH_PFC_PIN_GROUP(audio_clk_c_a),
- SH_PFC_PIN_GROUP(audio_clk_c_b),
- SH_PFC_PIN_GROUP(audio_clkout_a),
- SH_PFC_PIN_GROUP(audio_clkout_b),
-
[PATCH RFC 6/8] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A7796
Optimize pinctrl image size by disabling pins which are not used
by u-boot (ie, not enabled in board dts file)
Signed-off-by: Biju Das
---
drivers/pinctrl/renesas/Kconfig | 6
drivers/pinctrl/renesas/pfc-r8a7796.c | 44 +--
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index d2be4c84ba..9a651c6280 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -7,6 +7,12 @@ config PINCTRL_PFC
help
Enable support for clock present on Renesas RCar SoCs.
+config PINCTRL_PFC_EXTRAS
+bool "Renesas pin control options for enabling extras"
+depends on PINCTRL_PFC
+help
+ Options for enabling pin control extras.
+
config PINCTRL_PFC_R8A7790
bool "Renesas RCar Gen2 R8A7790 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c
b/drivers/pinctrl/renesas/pfc-r8a7796.c
index da7901ea6e..6124361859 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -1841,7 +1841,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A7796) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2056,7 +2056,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /* CONFIG_PINCTRL_PFC_R8A7796 && CONFIG_PINCTRL_PFC_EXTRAS */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -2469,6 +2469,7 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
/* - MSIOF0 -
*/
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
@@ -3167,6 +3168,7 @@ static const unsigned int msiof3_rxd_e_pins[] = {
static const unsigned int msiof3_rxd_e_mux[] = {
MSIOF3_RXD_E_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
/* - PWM0
*/
static const unsigned int pwm0_pins[] = {
@@ -4114,10 +4116,14 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
struct sh_pfc_pin_group common[312];
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
struct sh_pfc_pin_group automotive[30];
-#endif
+#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#else /* CONFIG_PINCTRL_PFC_EXTRAS */
+ struct sh_pfc_pin_group common[213];
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4207,6 +4213,7 @@ static const struct {
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -4306,6 +4313,7 @@ static const struct {
SH_PFC_PIN_GROUP(msiof3_ss2_e),
SH_PFC_PIN_GROUP(msiof3_txd_e),
SH_PFC_PIN_GROUP(msiof3_rxd_e),
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
@@ -4433,7 +4441,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A7796) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4466,7 +4474,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /* CONFIG_PINCTRL_PFC_R8A7796 && CONFIG_PINCTRL_PFC_EXTRAS */
};
static const char * const audio_clk_groups[] = {
@@ -4525,7 +4533,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A7796) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4567,7 +4575,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /*
[PATCH 4/8] pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1
This driver supports both RZ/G2N and R-Car M3-N SoCs.
Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N
(R8A77965) is not enabled.
Based on the simialr patch on Linux.
Signed-off-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c
b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 387330e4a3..d143750c2d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -1857,6 +1857,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2130,6 +2131,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -4390,7 +4392,9 @@ static const unsigned int vin5_clk_mux[] = {
static const struct {
struct sh_pfc_pin_group common[318];
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_pin_group automotive[30];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4712,6 +4716,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4744,6 +4749,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
};
static const char * const audio_clk_groups[] = {
@@ -4802,6 +4808,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4843,6 +4850,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -5260,7 +5268,9 @@ static const char * const vin5_groups[] = {
static const struct {
struct sh_pfc_function common[51];
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -5315,12 +5325,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A77965
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.17.1
[PATCH RFC 8/8] pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A7795
Optimize pinctrl image size by disabling pins which are not used
by u-boot(ie, not enabled in board dts file).
Signed-off-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a7795.c | 52 +++
1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c
b/drivers/pinctrl/renesas/pfc-r8a7795.c
index 898f837950..eb178494a9 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7795.c
@@ -1836,7 +1836,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
-#ifdef CONFIG_PINCTRL_PFC_R8A7795
+#if defined(CONFIG_PINCTRL_PFC_R8A7795) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2051,7 +2051,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 && CONFIG_PINCTRL_PFC_EXTRAS */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -2464,6 +2464,7 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
/* - MSIOF0 -
*/
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
@@ -3161,6 +3162,7 @@ static const unsigned int msiof3_rxd_e_pins[] = {
static const unsigned int msiof3_rxd_e_mux[] = {
MSIOF3_RXD_E_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
/* - PWM0
*/
static const unsigned int pwm0_pins[] = {
@@ -4169,10 +4171,14 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
struct sh_pfc_pin_group common[320];
-#ifdef CONFIG_PINCTRL_PFC_R8A7795
+#if defined(CONFIG_PINCTRL_PFC_R8A7795)
struct sh_pfc_pin_group automotive[30];
-#endif
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
+#else /* CONFIG_PINCTRL_PFC_EXTRAS */
+ struct sh_pfc_pin_group common[221];
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4262,6 +4268,7 @@ static const struct {
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -4361,6 +4368,7 @@ static const struct {
SH_PFC_PIN_GROUP(msiof3_ss2_e),
SH_PFC_PIN_GROUP(msiof3_txd_e),
SH_PFC_PIN_GROUP(msiof3_rxd_e),
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
@@ -4496,7 +4504,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
-#ifdef CONFIG_PINCTRL_PFC_R8A7795
+#if defined(CONFIG_PINCTRL_PFC_R8A7795) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4529,7 +4537,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
-#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 && CONFIG_PINCTRL_PFC_EXTRAS */
};
static const char * const audio_clk_groups[] = {
@@ -4588,7 +4596,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
-#ifdef CONFIG_PINCTRL_PFC_R8A7795
+#if defined(CONFIG_PINCTRL_PFC_R8A7795) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4630,7 +4638,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 && CONFIG_PINCTRL_PFC_EXTRAS */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4723,6 +4731,7 @@ static const char * const intc_ex_groups[] = {
"intc_ex_irq5",
};
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
@@ -4833,6 +4842,7 @@ static const char * const msiof3_groups[] = {
"msiof3_txd_e",
"msiof3_rxd_e",
};
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
static const char * const pwm0_groups[] = {
"pwm0",
@@ -5056,10 +5066,14 @@ static const char * const vin5_groups[] = {
};
[PATCH RFC 7/8] pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A77965
Optimize pinctrl image size by disabling pins which are not used
by u-boot (ie, not enabled in board dts file).
Signed-off-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 48 +++---
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c
b/drivers/pinctrl/renesas/pfc-r8a77965.c
index d143750c2d..f8ad66841f 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -1857,7 +1857,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
-#ifdef CONFIG_PINCTRL_PFC_R8A77965
+#if defined(CONFIG_PINCTRL_PFC_R8A77965) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2131,7 +2131,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
-#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 && CONFIG_PINCTRL_PFC_EXTRAS */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -2621,6 +2621,7 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
/* - MSIOF0 -
*/
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
@@ -3318,6 +3319,7 @@ static const unsigned int msiof3_rxd_e_pins[] = {
static const unsigned int msiof3_rxd_e_mux[] = {
MSIOF3_RXD_E_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
/* - PWM0
*/
static const unsigned int pwm0_pins[] = {
@@ -4391,10 +4393,14 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
struct sh_pfc_pin_group common[318];
-#ifdef CONFIG_PINCTRL_PFC_R8A77965
+#if defined(CONFIG_PINCTRL_PFC_R8A77965)
struct sh_pfc_pin_group automotive[30];
-#endif
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
+#else /* CONFIG_PINCTRL_PFC_EXTRAS */
+ struct sh_pfc_pin_group common[219];
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4484,6 +4490,7 @@ static const struct {
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -4583,6 +4590,7 @@ static const struct {
SH_PFC_PIN_GROUP(msiof3_ss2_e),
SH_PFC_PIN_GROUP(msiof3_txd_e),
SH_PFC_PIN_GROUP(msiof3_rxd_e),
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
@@ -4716,7 +4724,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
-#ifdef CONFIG_PINCTRL_PFC_R8A77965
+#if defined(CONFIG_PINCTRL_PFC_R8A77965) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4749,7 +4757,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
-#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 && CONFIG_PINCTRL_PFC_EXTRAS */
};
static const char * const audio_clk_groups[] = {
@@ -4808,7 +4816,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
-#ifdef CONFIG_PINCTRL_PFC_R8A77965
+#if defined(CONFIG_PINCTRL_PFC_R8A77965) && defined(CONFIG_PINCTRL_PFC_EXTRAS)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4850,7 +4858,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
-#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77965 && CONFIG_PINCTRL_PFC_EXTRAS */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4943,6 +4951,7 @@ static const char * const intc_ex_groups[] = {
"intc_ex_irq5",
};
+#if defined(CONFIG_PINCTRL_PFC_EXTRAS)
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
@@ -5053,6 +5062,7 @@ static const char * const msiof3_groups[] = {
"msiof3_txd_e",
"msiof3_rxd_e",
};
+#endif /* CONFIG_PINCTRL_PFC_EXTRAS */
static const char * const pwm0_groups[] = {
"pwm0",
@@ -5267,10 +5277,14 @@ static const char * const
[PATCH 5/8] pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1
This driver supports both RZ/G2H and R-Car H3 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3
(R8A7795) is not enabled
Based on the similar patch on Linux.
Signed-off-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a7795.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c
b/drivers/pinctrl/renesas/pfc-r8a7795.c
index b787c4883a..898f837950 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7795.c
@@ -1836,6 +1836,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
/* - DRIF0 --- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2050,6 +2051,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
/* - DU -
*/
static const unsigned int du_rgb666_pins[] = {
@@ -4168,7 +4170,9 @@ static const unsigned int vin5_clk_mux[] = {
static const struct {
struct sh_pfc_pin_group common[320];
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
struct sh_pfc_pin_group automotive[30];
+#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4492,6 +4496,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4524,7 +4529,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
-
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
};
static const char * const audio_clk_groups[] = {
@@ -4583,6 +4588,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4624,6 +4630,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -5050,7 +5057,9 @@ static const char * const vin5_groups[] = {
static const struct {
struct sh_pfc_function common[53];
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
struct sh_pfc_function automotive[4];
+#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -5107,13 +5116,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
+#ifdef CONFIG_PINCTRL_PFC_R8A7795
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
-
+#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.17.1
RE: [Uboot-stm32] [PATCH 0/7] arm: cache: cp15: don't map reserved region with no-map property
Hi,
> From: Ard Biesheuvel
> Sent: mardi 27 octobre 2020 22:05
>
> On Tue, 27 Oct 2020 at 18:25, Tom Rini wrote:
> >
> > On Fri, Oct 09, 2020 at 05:00:44PM +, Patrick DELAUNAY wrote:
> > > Hi Ard,
> > >
> > > > From: Ard Biesheuvel
> > > > Sent: mercredi 7 octobre 2020 15:16
> > > >
> > > > On Wed, 7 Oct 2020 at 13:53, Ahmad Fatoum
> wrote:
> > > > >
> > > > > Hello,
> > > > >
> > > > > On 10/7/20 1:23 PM, Ahmad Fatoum wrote:
> > > > > > My findings[1] back then were that U-Boot did set the eXecute
> > > > > > Never bit only on OMAP, but not for other platforms. So I
> > > > > > could imagine this being the root cause of Patrick's issues as well:
> > > > >
> > > > > Rereading my own link, my memory is a little less fuzzy: eXecute
> > > > > Never was being set, but was without effect due Manager mode
> > > > > being set in the
> > > > DACR:
> > > > >
> > > > > > The ARM Architecture Reference Manual notes[1]:
> > > > > > > When using the Short-descriptor translation table format,
> > > > > > > the XN attribute is not checked for domains marked as Manager.
> > > > > > > Therefore, the system must not include read-sensitive memory
> > > > > > > in domains marked as Manager, because the XN bit does not
> > > > > > > prevent speculative fetches from a Manager domain.
> > > > >
> > > > > > To avoid speculative access to read-sensitive memory-mapped
> > > > > > peripherals on ARMv7, we'll need U-Boot to use client domain
> > > > > > permissions, so the XN bit can function.
> > > > >
> > > > > > This issue has come up before and was fixed in de63ac278
> > > > > > ("ARM: mmu: Set domain permissions to client access") for OMAP2
> only.
> > > > > > It's equally applicable to all ARMv7-A platforms where caches
> > > > > > are enabled.
> > > > > > [1]: B3.7.2 - Execute-never restrictions on instruction
> > > > > > fetching
> > > > >
> > > > > Hope this helps,
> > > > > Ahmad
> > > > >
> > > >
> > > > It most definitely does, thanks a lot.
> > > >
> > > > U-boot's mmu_setup() currently sets DACR to manager for all
> > > > domains, so this is broken for all non-LPAE configurations running
> > > > on v7 CPUs (except OMAP and perhaps others that fixed it
> > > > individually). This affects all device mappings: not just secure
> > > > DRAM for OP-TEE, but any MMIO register for any peripheral that is mapped
> into the CPU's address space.
> > > >
> > > > Patrick, could you please check whether this fixes the issue as well?
> > > >
> > > > --- a/arch/arm/lib/cache-cp15.c
> > > > +++ b/arch/arm/lib/cache-cp15.c
> > > > @@ -202,9 +202,9 @@ static inline void mmu_setup(void)
> > > > asm volatile("mcr p15, 0, %0, c2, c0, 0"
> > > > : : "r" (gd->arch.tlb_addr) : "memory"); #endif
> > > > - /* Set the access control to all-supervisor */
> > > > + /* Set the access control to client (0b01) for each of the
> > > > + 16 domains */
> > > > asm volatile("mcr p15, 0, %0, c3, c0, 0"
> > > > -: : "r" (~0));
> > > > +: : "r" (0x));
> > > >
> > > > arm_init_domains();
> > >
> > > The test will take some time to be sure that solve my remaining issue
> > > because
> issue is not always reproductible.
> > >
> > > At fist chek, I wasn't sure of DACR bahavior, but I found in [1] the line
> > > :
> > >
> > > The XN attribute is not checked for domains marked as Manager. Read-
> sensitive memory must
> > > not be included in domains marked as Manager, because the XN bit
> > > does
> not prevent prefetches
> > > in these cases.
> > >
> > > So, I need to test your patch + DCACHE_OFF instead of INVALID (to
> > > map with XN the OP-TEE region) in my patchset.
> > >
> > > FYI: I found the same DACR configuration is done in:
> > > arch/arm/cpu/armv7/ls102xa/cpu.c:199
> > >
> > > [1]
> > > https://developer.arm.com/documentation/ddi0406/b/System-Level-Archi
> > > tecture/Virtual-Memory-System-Architecture--VMSA-/Memory-access-cont
> > > rol/The-Execute-Never--XN--attribute-and-instruction-prefetching?lan
> > > g=en
> > >
> > > Patrick
> > >
> > > For information:
> > >
> > > At the beginning I wasn't sure that the current DACR configuration
> > > is an issue because in found in pseudo code of
> > > DDI0406B_arm_architecture_reference_manual_errata_markup_8_0.pdf
> > >
> > > B3.13.3 Address translation
> > > if CheckDomain(tlbrecord.domain, mva, tlbrecord.sectionnotpage,
> > > iswrite)
> then
> > > CheckPermission(tlbrecord.perms, mva,
> > > tlbrecord.sectionnotpage, iswrite, ispriv);
> > >
> > > B3.13.4 Domain checking
> > > boolean CheckDomain(bits(4) domain, bits(32) mva, boolean
> sectionnotpage, boolean iswrite)
> > > bitpos = 2*UInt(domain);
> > > case DACR of
> > > when ‘00’ DataAbort(mva, domain, sectionnotpage,
> > > iswrite,
> DAbort_Domain);
> > > when ‘01’ permissioncheck = TRUE;
> > >
Re: U-Boot i2c bus num 1 is broken on Nokia N900
On Wednesday 28 October 2020 06:42:39 Heiko Schocher wrote:
> Am 26.10.2020 um 22:48 schrieb Pali Rohár:
> > On Monday 27 April 2020 09:03:13 Heiko Schocher wrote:
> > > Am 26.04.2020 um 01:54 schrieb Pali Rohár:
> > > > On Saturday 25 April 2020 14:11:32 Pali Rohár wrote:
> > > > > On Saturday 25 April 2020 07:00:58 Adam Ford wrote:
> > > > > > On Sat, Apr 25, 2020 at 6:50 AM Pali Rohár wrote:
> > > > > > > On Saturday 25 April 2020 06:36:58 Adam Ford wrote:
> > > > > > > > On Sat, Apr 25, 2020 at 5:42 AM Pali Rohár
> > > > > > > > wrote:
> > > > > > > > > On Thursday 02 April 2020 20:42:31 Pali Rohár wrote:
> > > > > > > > > > On Wednesday 01 April 2020 12:32:29 Merlijn Wajer wrote:
> > > > > > > > > > > MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
> > > > > > > > > > > In:vga
> > > > > > > > > > > Out: vga
> > > > > > > > > > > Err: vga
> > > > > > > > > > > Timed out in wait_for_event: status=0100
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > Timed out in wait_for_event: status=
> > > > > > > > > > > Check if pads/pull-ups of bus are properly configured
> > > > > > > > > > > i2c_read (addr phase): pads on bus probably not
> > > > > > > > > > > configured (status=0x10)
> > > > > > > > > > > i2c_write: timed out writig last byte!
...
> > > > Now I was able to find commit which is causing above i2c problems:
> > > > "Check if pads/pull-ups of bus are properly configured"
> > > >
> > > > It is d5243359e1afc957acd373dbbde1cf6c70ee5485:
> > > >
> > > > OMAP24xx I2C: Add support for set-speed
> > > > Adds support for set-speed on the OMAP24xx I2C Adapter.
> > > > Changes to omap24_i2c_write(...) for polling ARDY Bit from
> > > > IRQ-Status.
> > > > Otherwise on a subsequent call the transfer of last byte from the
> > > > predecessor is aborted and therefore lost. For exmaple when
> > > > i2c_write(...) is followed by a i2c_setspeed(...) (which has to
> > > > deactivate and activate master for changing psc,...).
> > > > Minor cosmetical changes.
> > > > Signed-off-by: Hannes Petermaier
> > > > Cc: Heiko Schocher
> > > >
> > > > U-Boot version prior this command does not report those i2c errors.
...
> > I applied revert of above change on top of the master u-boot branch and
> > i2c bus num 1 (second) started working on N900 hw:
> >
> > diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> > index 0af4e333c4..a49cf89712 100644
> > --- a/drivers/i2c/omap24xx_i2c.c
> > +++ b/drivers/i2c/omap24xx_i2c.c
> > @@ -820,16 +820,6 @@ static int __omap24_i2c_write(void __iomem *i2c_base,
> > int ip_rev, int waitdelay,
> > }
> > }
> > - /*
> > -* poll ARDY bit for making sure that last byte really has been
> > -* transferred on the bus.
> > -*/
> > - do {
> > - status = wait_for_event(i2c_base,
[PATCH 2/2] pinctrl: stmfx: update pin name
Update pin name to avoid duplicated name with SOC GPIO
gpio0...gpio15 / agpio0agpio7: add a stmfx prefix.
This pin name can be used in pinmux command.
Signed-off-by: Patrick Delaunay
---
drivers/pinctrl/pinctrl-stmfx.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c
index b789f3686c..a62be44d2d 100644
--- a/drivers/pinctrl/pinctrl-stmfx.c
+++ b/drivers/pinctrl/pinctrl-stmfx.c
@@ -343,8 +343,8 @@ static int stmfx_pinctrl_get_pins_count(struct udevice *dev)
}
/*
- * STMFX pins[15:0] are called "gpio[15:0]"
- * and STMFX pins[23:16] are called "agpio[7:0]"
+ * STMFX pins[15:0] are called "stmfx_gpio[15:0]"
+ * and STMFX pins[23:16] are called "stmfx_agpio[7:0]"
*/
#define MAX_PIN_NAME_LEN 7
static char pin_name[MAX_PIN_NAME_LEN];
@@ -352,9 +352,9 @@ static const char *stmfx_pinctrl_get_pin_name(struct
udevice *dev,
unsigned int selector)
{
if (selector < STMFX_MAX_GPIO)
- snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_gpio%u", selector);
else
- snprintf(pin_name, MAX_PIN_NAME_LEN, "agpio%u", selector - 16);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "stmfx_agpio%u", selector
- 16);
return pin_name;
}
--
2.17.1
[PATCH 1/2] pinctrl: stmfx: update pincontrol and gpio device name
The device name is used in pinmux command and in log trace
so it is better to use the parent parent name ("stmfx@42" for
example) than a generic name ("pinctrl" or "stmfx-gpio")
to identify the device instance.
Signed-off-by: Patrick Delaunay
---
drivers/pinctrl/pinctrl-stmfx.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c
index c2ea82770e..b789f3686c 100644
--- a/drivers/pinctrl/pinctrl-stmfx.c
+++ b/drivers/pinctrl/pinctrl-stmfx.c
@@ -408,8 +408,11 @@ static int stmfx_pinctrl_bind(struct udevice *dev)
{
struct stmfx_pinctrl *plat = dev_get_platdata(dev);
+ /* subnode name is not explicit: use father name */
+ device_set_name(dev, dev->parent->name);
+
return device_bind_driver_to_node(dev->parent,
- "stmfx-gpio", "stmfx-gpio",
+ "stmfx-gpio", dev->parent->name,
dev_ofnode(dev), >gpio);
};
--
2.17.1
[PATCH 2/2] cmd: pinmux: support pin name in status command
Allow pin name parameter for pimux staus command,
as gpio command to get status of one pin.
The possible usage of the command is:
> pinmux dev pinctrl
> pinmux status
> pinmux status -a
> pinmux status
Signed-off-by: Patrick Delaunay
---
cmd/pinmux.c | 41 +---
test/py/tests/test_pinmux.py | 29 +
2 files changed, 58 insertions(+), 12 deletions(-)
diff --git a/cmd/pinmux.c b/cmd/pinmux.c
index af04c95a46..e096f16982 100644
--- a/cmd/pinmux.c
+++ b/cmd/pinmux.c
@@ -41,19 +41,20 @@ static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc,
return CMD_RET_SUCCESS;
}
-static void show_pinmux(struct udevice *dev)
+static bool show_pinmux(struct udevice *dev, char *name)
{
char pin_name[PINNAME_SIZE];
char pin_mux[PINMUX_SIZE];
int pins_count;
int i;
int ret;
+ bool found = false;
pins_count = pinctrl_get_pins_count(dev);
if (pins_count < 0) {
printf("Ops get_pins_count not supported by %s\n", dev->name);
- return;
+ return found;
}
for (i = 0; i < pins_count; i++) {
@@ -61,43 +62,59 @@ static void show_pinmux(struct udevice *dev)
if (ret) {
printf("Ops get_pin_name error (%d) by %s\n",
ret, dev->name);
- return;
+ return found;
}
-
+ if (name && strcmp(name, pin_name))
+ continue;
+ found = true;
ret = pinctrl_get_pin_muxing(dev, i, pin_mux, PINMUX_SIZE);
if (ret) {
printf("Ops get_pin_muxing error (%d) by %s in %s\n",
ret, pin_name, dev->name);
- return;
+ return found;
}
printf("%-*s: %-*s\n", PINNAME_SIZE, pin_name,
PINMUX_SIZE, pin_mux);
}
+
+ return found;
}
static int do_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct udevice *dev;
+ char *name;
+ bool found = false;
if (argc < 2) {
if (!currdev) {
printf("pin-controller device not selected\n");
return CMD_RET_FAILURE;
}
- show_pinmux(currdev);
+ show_pinmux(currdev, NULL);
return CMD_RET_SUCCESS;
}
if (strcmp(argv[1], "-a"))
- return CMD_RET_USAGE;
+ name = argv[1];
+ else
+ name = NULL;
uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
- /* insert a separator between each pin-controller display */
- printf("--\n");
- printf("%s:\n", dev->name);
- show_pinmux(dev);
+ if (!name) {
+ /* insert a separator between each pin-controller
display */
+ printf("--\n");
+ printf("%s:\n", dev->name);
+ }
+ if (show_pinmux(dev, name))
+ found = true;
+ }
+
+ if (name && !found) {
+ printf("%s not found\n", name);
+ return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
@@ -148,5 +165,5 @@ U_BOOT_CMD(pinmux, CONFIG_SYS_MAXARGS, 1, do_pinmux,
"show pin-controller muxing",
"list - list UCLASS_PINCTRL devices\n"
"pinmux dev [pincontroller-name] - select pin-controller device\n"
- "pinmux status [-a] - print pin-controller muxing [for
all]\n"
+ "pinmux status [-a | pin-name] - print pin-controller muxing [for
all | for pin-name]\n"
)
diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py
index b3ae2ab024..fbde1d99b1 100644
--- a/test/py/tests/test_pinmux.py
+++ b/test/py/tests/test_pinmux.py
@@ -82,3 +82,32 @@ def test_pinmux_status(u_boot_console):
assert ('P6: GPIO1 drive-open-drain.' in output)
assert ('P7: GPIO2 bias-pull-down input-enable.' in output)
assert ('P8: GPIO3 bias-disable.' in output)
+
+@pytest.mark.buildconfigspec('cmd_pinmux')
+@pytest.mark.boardspec('sandbox')
+def test_pinmux_status_pinname(u_boot_console):
+"""Test that 'pinmux status ' displays selected pin."""
+
+output = u_boot_console.run_command('pinmux status a5')
+assert ('a5: gpio output .' in output)
+assert (not 'pinctrl-gpio:' in output)
+assert (not 'pinctrl:' in output)
+assert (not 'a6' in output)
+assert (not 'P0' in output)
+assert (not 'P8' in output)
+
+output = u_boot_console.run_command('pinmux status P7')
+assert (not
[PATCH 1/2] cmd: pinmux: update result of do_status
Update the result of do_status and alway returns a CMD_RET_ value
(-ENOSYS was a possible result of show_pinmux).
This patch also adds pincontrol name in error messages (dev->name)
and treats correctly the status sub command when pin-controller device is
not selected.
Signed-off-by: Patrick Delaunay
---
cmd/pinmux.c | 44 +++-
test/py/tests/test_pinmux.py | 4 ++--
2 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/cmd/pinmux.c b/cmd/pinmux.c
index 9942b15419..af04c95a46 100644
--- a/cmd/pinmux.c
+++ b/cmd/pinmux.c
@@ -41,7 +41,7 @@ static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc,
return CMD_RET_SUCCESS;
}
-static int show_pinmux(struct udevice *dev)
+static void show_pinmux(struct udevice *dev)
{
char pin_name[PINNAME_SIZE];
char pin_mux[PINMUX_SIZE];
@@ -51,54 +51,56 @@ static int show_pinmux(struct udevice *dev)
pins_count = pinctrl_get_pins_count(dev);
- if (pins_count == -ENOSYS) {
- printf("Ops get_pins_count not supported\n");
- return pins_count;
+ if (pins_count < 0) {
+ printf("Ops get_pins_count not supported by %s\n", dev->name);
+ return;
}
for (i = 0; i < pins_count; i++) {
ret = pinctrl_get_pin_name(dev, i, pin_name, PINNAME_SIZE);
- if (ret == -ENOSYS) {
- printf("Ops get_pin_name not supported\n");
- return ret;
+ if (ret) {
+ printf("Ops get_pin_name error (%d) by %s\n",
+ ret, dev->name);
+ return;
}
ret = pinctrl_get_pin_muxing(dev, i, pin_mux, PINMUX_SIZE);
if (ret) {
- printf("Ops get_pin_muxing error (%d)\n", ret);
- return ret;
+ printf("Ops get_pin_muxing error (%d) by %s in %s\n",
+ ret, pin_name, dev->name);
+ return;
}
printf("%-*s: %-*s\n", PINNAME_SIZE, pin_name,
PINMUX_SIZE, pin_mux);
}
-
- return 0;
}
static int do_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct udevice *dev;
- int ret = CMD_RET_USAGE;
- if (currdev && (argc < 2 || strcmp(argv[1], "-a")))
- return show_pinmux(currdev);
+ if (argc < 2) {
+ if (!currdev) {
+ printf("pin-controller device not selected\n");
+ return CMD_RET_FAILURE;
+ }
+ show_pinmux(currdev);
+ return CMD_RET_SUCCESS;
+ }
- if (argc < 2 || strcmp(argv[1], "-a"))
- return ret;
+ if (strcmp(argv[1], "-a"))
+ return CMD_RET_USAGE;
uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
/* insert a separator between each pin-controller display */
printf("--\n");
printf("%s:\n", dev->name);
- ret = show_pinmux(dev);
- if (ret < 0)
- printf("Can't display pin muxing for %s\n",
- dev->name);
+ show_pinmux(dev);
}
- return ret;
+ return CMD_RET_SUCCESS;
}
static int do_list(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py
index 0cbbae000c..b3ae2ab024 100644
--- a/test/py/tests/test_pinmux.py
+++ b/test/py/tests/test_pinmux.py
@@ -13,9 +13,9 @@ def test_pinmux_usage_1(u_boot_console):
@pytest.mark.buildconfigspec('cmd_pinmux')
def test_pinmux_usage_2(u_boot_console):
"""Test that 'pinmux status' executed without previous "pinmux dev"
-command displays pinmux usage."""
+command displays error message."""
output = u_boot_console.run_command('pinmux status')
-assert 'Usage:' in output
+assert 'pin-controller device not selected' in output
@pytest.mark.buildconfigspec('cmd_pinmux')
@pytest.mark.boardspec('sandbox')
--
2.17.1
RE: [PATCH v2 3/5] pinctrl: renesas: r8a77965: Add R8A774B1 PFC support
Hi Marek, > Subject: RE: [PATCH v2 3/5] pinctrl: renesas: r8a77965: Add R8A774B1 PFC > support > > Hi Marek, > > > Subject: Re: [PATCH v2 3/5] pinctrl: renesas: r8a77965: Add R8A774B1 > > PFC support > > > > On 10/14/20 1:29 PM, Biju Das wrote: > > > > Hi, > > > > [...] > > > > Check with the linux maintainers please, surely there should be > > some way to separate the extras in a way that's not too hard to > > maintain, and thus reduce the resulting binary size. For U-Boot, > > that is quite important already, I think the TFA can only load 1 > > MiB > > binary in total. > > >>> > > >>> I agree for bootloader size is important. So I will add macros as > > >>> per your > > >> suggestion (we don't need to look into linux for this). > > >> > > >> The PFC tables and clock tables are the same between U-Boot and > > >> Linux, so if you only change them in U-Boot, it will make it hard > > >> to synchronize the tables later with Linux again. Please fix this > > >> in Linux and > > synchronize to U-Boot. > > > > > > I have posted a patch for optimizing pin control size for RZ/G2N in > > > Linux [1] > > > > > > [1] > > > https://patchwork.kernel.org/project/linux-renesas-soc/patch/2020101 > > > 41 10238.9600-1-biju.das...@bp.renesas.com/ > > > > > > This approach will save ~ 6KB=(3x 2KB/SoC) of memory on RZ/G2[HMN] > > > u- > > boot with multi dtb support. > > > > > > 1) By compiling out Automotive parts $ size > > > drivers/pinctrl/renesas/pfc-r8a77965.o > > >text data bss dec hex filename > > > 46141 0 0 46141b43d drivers/pinctrl/renesas/pfc- > > r8a77965.o > > > > > > 2) without patch > > > $ size drivers/pinctrl/renesas/pfc-r8a77965.o > > >text data bss dec hex filename > > > 48191 0 0 48191bc3f drivers/pinctrl/renesas/pfc- > > r8a77965.o > > > > Have a look at the size of the image of rcar3_salvator-x_defconfig , > > it is just a few kiB short of 1MiB , which is the hard limit. Any size > > reduction > helps. > > Yes I agree, we need to look into size reduction for Salvator-XS. But > currently > there is no issue. See the details below. I have sent a RFC patches to reduce pin control size for RCAR which saves 60KB. [1] https://patchwork.ozlabs.org/project/uboot/patch/20201028103429.3051-7-biju.das...@bp.renesas.com/ [2] https://patchwork.ozlabs.org/project/uboot/patch/20201028103429.3051-8-biju.das...@bp.renesas.com/ [3] https://patchwork.ozlabs.org/project/uboot/patch/20201028103429.3051-9-biju.das...@bp.renesas.com/ Regards, Biju
RE: [PATCH v9 0/2] Basic Kontron SMARC-sAL28 board support
>-Original Message- >From: Tom Rini >Sent: Wednesday, October 28, 2020 3:58 AM >To: Michael Walle >Cc: u-boot@lists.denx.de; Priyanka Jain ; Kuldeep >Singh ; Heiko Thiery >Subject: Re: [PATCH v9 0/2] Basic Kontron SMARC-sAL28 board support > >On Tue, Oct 27, 2020 at 11:23:23PM +0100, Michael Walle wrote: >> Hi Tom, Hi all, >> >> Am 2020-10-15 23:08, schrieb Michael Walle: >> > Add basic board support for the Kontron SMARC-sAL28 board. Please >> > note, that this board doesn't support TF-a (yet). Therefore, the >> > u-boot SPL is the first code which is run and it has to set up the RAM. >> >> With the merge window closing.. seems like this patch series will also >> miss this release. TBH this is really frustrating. >> The first version was posted on May this year. Most versions were just >> follow-ups by me because missing features used by this boards were >> already merged into u-boot and thus I've updated this patch series >> accordingly to use the new feature. > >I would really expect "just add a board" to be merged up until maybe >-rc3 or -rc4 is out, honestly. > >-- >Tom Michael, I am working on fsl-qoriq pull-request. And this is part of that. I have triggered travis. If no issue, it will pe pushed. And the earlier version was not included in last release because of build issue reported by travis. Regards Priyanka
Re: [PATCH v2 4/5] mtd: pxa3xx_nand: remove dead code
On 18.10.20 14:56, Baruch Siach wrote:
The kfree() call is unreachable, and is not needed. Remove this call and
the fail_disable_clk label.
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/mtd/nand/raw/pxa3xx_nand.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c
b/drivers/mtd/nand/raw/pxa3xx_nand.c
index 6f66db065357..635794b1691a 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
@@ -1768,7 +1768,7 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
struct pxa3xx_nand_host *host;
struct nand_chip *chip = NULL;
struct mtd_info *mtd;
- int ret, cs;
+ int cs;
pdata = info->pdata;
if (pdata->num_cs <= 0)
@@ -1804,19 +1804,13 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
/* Allocate a buffer to allow flash detection */
info->buf_size = INIT_BUFFER_SIZE;
info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
- if (info->data_buff == NULL) {
- ret = -ENOMEM;
- goto fail_disable_clk;
- }
+ if (info->data_buff == NULL)
+ return -ENOMEM;
/* initialize all interrupts to be disabled */
disable_int(info, NDSR_MASK);
return 0;
-
- kfree(info->data_buff);
-fail_disable_clk:
- return ret;
}
static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info *info)
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 5/5] mtd: nand: pxa3xx: enable NAND controller if the SoC needs it
On 18.10.20 14:56, Baruch Siach wrote:
From: Shmuel Hazan
Based on Linux kernel commit fc256f5789cb ("mtd: nand: pxa3xx: enable
NAND controller if the SoC needs it"). This commit adds support for the
Armada 8040 nand controller.
The kernel commit says this:
Marvell recent SoCs like A7k/A8k do not boot with NAND flash
controller activated by default. Enabling the controller is a matter
of writing in a system controller register that may also be used for
other NAND related choices.
Signed-off-by: Shmuel Hazan
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/mtd/nand/raw/pxa3xx_nand.c | 50 --
1 file changed, 41 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c
b/drivers/mtd/nand/raw/pxa3xx_nand.c
index 635794b1691a..beaa290f7480 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
@@ -22,6 +22,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -119,6 +121,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
+/* System control register and bit to enable NAND on some SoCs */
+#define GENCONF_SOC_DEVICE_MUX 0x208
+#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
+
/*
* This should be large enough to read 'ONFI' and 'JEDEC'.
* Let's use 7 bytes, which is the maximum ID count supported
@@ -159,6 +165,7 @@ enum {
enum pxa3xx_nand_variant {
PXA3XX_NAND_VARIANT_PXA,
PXA3XX_NAND_VARIANT_ARMADA370,
+ PXA3XX_NAND_VARIANT_ARMADA_8K,
};
struct pxa3xx_nand_host {
@@ -424,13 +431,16 @@ static const struct udevice_id pxa3xx_nand_dt_ids[] = {
.compatible = "marvell,mvebu-pxa3xx-nand",
.data = PXA3XX_NAND_VARIANT_ARMADA370,
},
+ {
+ .compatible = "marvell,armada-8k-nand-controller",
+ .data = PXA3XX_NAND_VARIANT_ARMADA_8K,
+ },
{}
};
-static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
+static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(struct udevice *dev)
{
- /* We only support the Armada 370/XP/38x for now */
- return PXA3XX_NAND_VARIANT_ARMADA370;
+ return dev_get_driver_data(dev);
}
static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
@@ -707,7 +717,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info
*info)
info->retcode = ERR_UNCORERR;
if (status & NDSR_CORERR) {
info->retcode = ERR_CORERR;
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
+ if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&
info->ecc_bch)
info->ecc_err_cnt = NDSR_ERR_CNT(status);
else
@@ -762,7 +773,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info
*info)
nand_writel(info, NDCB0, info->ndcb2);
/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+ info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
nand_writel(info, NDCB0, info->ndcb3);
}
@@ -1676,7 +1688,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
}
/* Device detection must be done with ECC disabled */
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+ info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
nand_writel(info, NDECCCTRL, 0x0);
if (nand_scan_ident(mtd, 1, NULL))
@@ -1726,7 +1739,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
* (aka split) command handling,
*/
if (mtd->writesize > info->chunk_size) {
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+ info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
chip->cmdfunc = nand_cmdfunc_extended;
} else {
dev_err(mtd->dev,
@@ -1762,7 +1776,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
return nand_scan_tail(mtd);
}
-static int alloc_nand_resource(struct pxa3xx_nand_info *info)
+static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info
*info)
{
struct pxa3xx_nand_platform_data *pdata;
struct pxa3xx_nand_host *host;
@@ -1774,7 +1788,7 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
if (pdata->num_cs <= 0)
return -ENODEV;
- info->variant = pxa3xx_nand_get_variant();
Re: [PATCH v2 3/5] mtd: pxa3xx_nand: port to use driver model
On 18.10.20 14:56, Baruch Siach wrote:
From: Shmuel Hazan
Please add at least a minimal commit text here.
Signed-off-by: Shmuel Hazan
Signed-off-by: Baruch Siach
---
drivers/mtd/nand/raw/Kconfig | 2 +
drivers/mtd/nand/raw/pxa3xx_nand.c | 117 +
2 files changed, 55 insertions(+), 64 deletions(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index cd7e598aa8a7..08df12a3daf9 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -195,6 +195,8 @@ endif
config NAND_PXA3XX
bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
select SYS_NAND_SELF_INIT
+ select DM_MTD
+ select SYSCON
imply CMD_NAND
help
This enables the driver for the NAND flash device found on
diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c
b/drivers/mtd/nand/raw/pxa3xx_nand.c
index 5fb3081c8390..6f66db065357 100644
--- a/drivers/mtd/nand/raw/pxa3xx_nand.c
+++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
@@ -22,6 +22,8 @@
#include
#include
#include
+#include
+#include
#include "pxa3xx_nand.h"
@@ -417,6 +419,14 @@ static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
/* convert nano-seconds to nand flash controller clock cycles */
#define ns2cycle(ns, clk) (int)((ns) * (clk / 100) / 1000)
+static const struct udevice_id pxa3xx_nand_dt_ids[] = {
+ {
+ .compatible = "marvell,mvebu-pxa3xx-nand",
+ .data = PXA3XX_NAND_VARIANT_ARMADA370,
+ },
+ {}
+};
+
static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
{
/* We only support the Armada 370/XP/38x for now */
@@ -1809,82 +1819,60 @@ fail_disable_clk:
return ret;
}
-static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info
*info)
{
struct pxa3xx_nand_platform_data *pdata;
- const void *blob = gd->fdt_blob;
- int node = -1;
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
- /* Get address decoding nodes from the FDT blob */
- do {
- node = fdt_node_offset_by_compatible(blob, node,
-
"marvell,mvebu-pxa3xx-nand");
- if (node < 0)
- break;
-
- /* Bypass disabeld nodes */
- if (!fdtdec_get_is_enabled(blob, node))
- continue;
-
- /* Get the first enabled NAND controler base address */
- info->mmio_base =
- (void __iomem *)fdtdec_get_addr_size_auto_noparent(
- blob, node, "reg", 0, NULL, true);
+ info->mmio_base = dev_read_addr_ptr(dev);
- pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
- if (pdata->num_cs != 1) {
- pr_err("pxa3xx driver supports single CS only\n");
- break;
- }
-
- if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
- pdata->enable_arbiter = 1;
+ pdata->num_cs = dev_read_u32_default(dev, "num-cs", 1);
+ if (pdata->num_cs != 1) {
+ pr_err("pxa3xx driver supports single CS only\n");
+ return -EINVAL;
+ }
- if (fdtdec_get_bool(blob, node, "nand-keep-config"))
- pdata->keep_config = 1;
+ if (dev_read_bool(dev, "nand-enable-arbiter"))
+ pdata->enable_arbiter = 1;
- /*
-* ECC parameters.
-* If these are not set, they will be selected according
-* to the detected flash type.
-*/
- /* ECC strength */
- pdata->ecc_strength = fdtdec_get_int(blob, node,
-"nand-ecc-strength", 0);
+ if (dev_read_bool(dev, "nand-keep-config"))
+ pdata->keep_config = 1;
- /* ECC step size */
- pdata->ecc_step_size = fdtdec_get_int(blob, node,
- "nand-ecc-step-size", 0);
-
- info->pdata = pdata;
+ /*
+* ECC parameters.
+* If these are not set, they will be selected according
+* to the detected flash type.
+*/
+ /* ECC strength */
+ pdata->ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 0);
- /* Currently support only a single NAND controller */
- return 0;
+ /* ECC step size */
+ pdata->ecc_step_size = dev_read_u32_default(dev, "nand-ecc-step-size",
+ 0);
- } while (node >= 0);
+ info->pdata = pdata;
- return -EINVAL;
+ return 0;
}
-static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_probe(struct udevice *dev)
Pull request for UEFI sub-system for efi-2021-01-rc2
The following changes since commit 986c980c8250849d9394fdf377a3de75edb11888: nokia_rx51: re-enable CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV (2020-10-27 10:48:08 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2021-01-rc2 for you to fetch changes up to 0eae552d18690a19cc714046fb1665138f5701f6: efi_loader: daylight saving time (2020-10-27 21:13:16 +0100) Gitlab CI showed not problem: https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/5148 Pull request for UEFI sub-system for efi-2021-01-rc2 A software RTC driver is supplied for UEFI SCT testing. The following UEFI related bugs are fixed: * correct handling of daylight saving time in GetTime() and SetTime() * handling of the gd register in function tracing on RISC-V * disable U-Boot devices in ExitBootServices() Heinrich Schuchardt (4): Makefile: provide constant with seconds since epoch rtc: provide an emulated RTC trace: conserve gd register on RISC-V efi_loader: daylight saving time Ilias Apalodimas (2): efi_loader: Sort header file ordering efi_loader: Disable devices before handing over control MAINTAINERS | 1 + Makefile | 2 ++ drivers/rtc/Kconfig | 11 ++ drivers/rtc/Makefile | 1 + drivers/rtc/emul_rtc.c| 80 +++ lib/efi_loader/efi_boottime.c | 13 --- lib/efi_loader/efi_runtime.c | 19 -- lib/trace.c | 2 +- 8 files changed, 121 insertions(+), 8 deletions(-) create mode 100644 drivers/rtc/emul_rtc.c
RE: [PATCH 00/33] stm32: enable logging features
Hi Simon, > From: Simon Glass > Sent: lundi 26 octobre 2020 20:23 > > Hi Patrick, > > On Thu, 15 Oct 2020 at 09:59, Patrick DELAUNAY > wrote: > > > > Hi Simon, > > > > > From: Simon Glass > > > Sent: jeudi 15 octobre 2020 17:06 > > > > > > Hi Patrick, > > > > > > On Wed, 14 Oct 2020 at 03:16, Patrick Delaunay > > > > > > wrote: > > > > > > > > > > > > This patch-set migrates several stm32 drivers to API compatible > > > > with logging features (use dev_...() or log_...() function) and > > > > activate the logging features in STM32MP15 boards. > > > > > > > > The size of U-Boot increased by 19kB (933026 to 952830 on > > > > STM32MP157C-EV1 board for basic defconfig) but the boot time don't > > > > change > > > drastically. > > > > > > > (...) > > > > For information even with all trace embbeded in U-Boot but not > > > > activated, MAX_LOG_LEVEL=8 and LOG_DEFAULT_LEVEL=6 > > > > > > > > Size increase by 190KB (952830 to 1147918) but boot time is stable > > > > (1,748s vs 1,696s). > > > > > > This seems pretty bad. Is this because of console output, or > > > something else? I understand the size increase, but not the boot time > increase. > > > > For this last point I just execute STM32MP157C-EV1 boot with a patch > > in configs/stm32mp15_basic_defconfig > > > > +CONFIG_LOGLEVEL=8 > > +CONFIG_LOG_MAX_LEVEL=8 > > +CONFIG_LOG_DEFAULT_LEVEL=6 > > +CONFIG_LOGF_FILE=y > > +CONFIG_LOGF_LINE=y > > +CONFIG_LOGF_FUNC=y > > > > And execute "bootstage report" after the second boot (the first boot > > is pertubated by env save) > > > > I think the delta is linked to > > 1/ size of U-Boot (SPL spent more time to load U-Boot) > > end of SPL 987,579 => 996,117 > > OK. > > > > > 2/ time to check for each debug trace: because I increase the log level > >(gd->default_log_level = 6 < MAX_LOG_LEVEL=8) > > This might be the biggest part. If you look at _log() it always does the > vsprintf() > even if in fact log_dispatch() does not dispatch it to anything. Yes, log_dispatch / log_passes_filter are called after vsnprintf > I suspect that could be refactored to move the checking to a separate > function, > and then call it before doing the expensive vsprintf(). Or save va_list, fmt in log_rec and call vsnprintf allow when needed in log_dispatch, just before emit > > > > 3/ treatment added in log_console_emit (some printf) and > > log_dispatch (processing_msg / gd->loghead) > > Likely this is fast. > > > > > 4/ lower cache performancy as trace code are pesent in memory even > > they are not used > > > > Can I do some check/experimentation on my side ? > > Yes, if you can use the bootstage_start() and bootstage_accum() within the > _log() > function to measure the total time take in the run. Ok, I add it in my TODO list > Regards, > Simon Regards Patrick
Re: [PATCH v2 1/5] arm: dts: armada-cp110-slave: add missing cps_nand
On 18.10.20 14:56, Baruch Siach wrote:
From: Shmuel Hazan
Align node properties to kernel dts node.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Signed-off-by: Shmuel Hazan
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-cp110-slave.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi
b/arch/arm/dts/armada-cp110-slave.dtsi
index b426a4eb6910..6cf217783709 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -267,6 +267,22 @@
utmi-port = ;
status = "disabled";
};
+
+ cps_nand: nand@72 {
+ compatible =
"marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x72 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clock-names = "core", "reg";
+ clocks = <_syscon0 1 2>,
+<_syscon0 1 17>;
+ marvell,system-controller = <_syscon0>;
+ nand-enable-arbiter;
+ num-cs = <1>;
+ status = "disabled";
+ };
};
cps_pcie0: pcie@f460 {
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v2 2/5] arm: dts: armada-cp110-master: update nand-controller
On 18.10.20 14:56, Baruch Siach wrote:
Align node properties to kernel dts node.
The change of compatible property does not affect any currently
supported board.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Signed-off-by: Baruch Siach
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-cp110-master.dtsi | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/armada-cp110-master.dtsi
b/arch/arm/dts/armada-cp110-master.dtsi
index cd5c974482e6..7d0d31da306d 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -285,15 +285,18 @@
};
cpm_nand: nand@72 {
- compatible = "marvell,mvebu-pxa3xx-nand";
- reg = <0x72 0x100>;
+ compatible =
"marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x72 0x54>;
#address-cells = <1>;
-
- clocks = <_syscon0 1 2>;
+ #size-cells = <0>;
+ interrupts = ;
+ clock-names = "core", "reg";
+ clocks = <_syscon0 1 2>,
+<_syscon0 1 17>;
+ marvell,system-controller = <_syscon0>;
nand-enable-arbiter;
num-cs = <1>;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
status = "disabled";
};
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
RE: [PATCH 2/2] gpio: stm32: correct the bias management
Hi Marek,
> From: Patrick DELAUNAY
> Sent: mercredi 28 octobre 2020 10:49
>
> Use the bias configuration for all the GPIO configurations and not only for
> input
> GPIO, as indicated in Reference manual (Table 81. Port bit configuration
> table).
>
> Fixes: 43efbb6a3ebf0223f9eab8d45916f602d876319f ("gpio: stm32: add ops
> get_dir_flags")
> Fixes: f13ff88b61c32ac8f0e9068c41328b265ef619eb ("gpio: stm32: add ops
> set_dir_flags")
> Signed-off-by: Patrick Delaunay
> ---
>
> drivers/gpio/stm32_gpio.c | 28 ++--
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
(...)
Can you test this patch on avenger board,
I expect it correct the SD card detect issue (pull-up not configurated).
Thanks.
Patrick
RE: [PATCH] ARM: dts: stm32: Reinstate card detect behavior on DHSOM
Hi Marek,
> From: Marek Vasut
> Sent: vendredi 23 octobre 2020 17:04
>
> On 10/23/20 4:39 PM, Patrick DELAUNAY wrote:
>
> Hi,
>
> [...]
>
> From: Marek Vasut
> Sent: lundi 19 octobre 2020 23:38
>
> The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
> unsupported, reinstate the old cd-gpios behavior until this
> handling is fully implemented. This permits the DHSOM to boot from
> SD again, without this patch the card detect fails.
> >>>
> >>> It is strange if it is not working... I will check why the
> >>> configuration is not managed correctly in stm32 gpio/pincontrol driver.
> >>>
> Signed-off-by: Marek Vasut
> Cc: Patrick Delaunay
> Cc: Patrice Chotard
> ---
> arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> index 92345b7ba3..73bb5f1c6d 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
> @@ -265,6 +265,9 @@
>
> {
> u-boot,dm-spl;
> +broken-cd;
> +/delete-property/ cd-gpios;
> +/delete-property/ disable-wp;
> };
>
> _b4_pins_a {
> --
> 2.28.0
> >>>
> >>> Reviewed-by: Patrick Delaunay
> >>>
> >>> But I will be try to fix the issue before to accept this patch.
> >>>
> >>> I will merge it only if I can't found the root cause for v2020.01-rc2
> >>
> >> Do you not see the same behavior on EV/DK ?
> >
> > No but I think we have pull-up on board.
> >
> > But after investigation the internall pull-up is not configurated in
> > stm32 pinctrol (cheked with pinmux command) even it is requested in device-
> tree of EV1/DK2.
> >
> > It is clearly a bug (I isolate the issue) and I am working on a patch
> > (it should be sent to u-boot mailing liste next week).
> >
> >> btw it is bugged in SPL.
> >
> > Ah, what is the issue.
> >
> > In the stm32 driver or in the framework ?
> >
> > I will cross-check it also on EV1/DK2.
>
> The card is not detected in SPL again, same fail mode as before.
> Now that I think about it, note to self, I should check whether the CD GPIO
> controller node is u-boot,dm-spl
I found a big issue in stm32 pincontrol: the bias configuration was only
managed for ouput pin.
With this serie [1], I checked the pull-up configuration (including in SPL by
adding a debug trace).
With [2], the bias configuration is now correct in DK2 / EV1 boards (even if
the pull-up configuration is not mandatory,
because I don't see cart detection issue on ST board).
I expect this patch correct the DHSOM issue.
[1]: http://patchwork.ozlabs.org/project/uboot/list/?series=210501
[2]: patch [2/2] gpio: stm32: correct the bias management
http://patchwork.ozlabs.org/project/uboot/patch/20201028094908.11031-2-patrick.delau...@st.com/
Regards,
Patrick
[PATCH 4/4] IPQ40xx: clk: add USB clock handling
USB clocks were completely forgotten as driver would always return 0 even if
clock ID was unknown.
This behaviour changed with "IPQ40xx: clk: dont always return 0" and this will
now causes the USB-s to fail probing as clock enable will return -EINVAL.
So to fix that lets add all of the USB clocks to the driver.
Fixes: 430e1dcf ("IPQ40xx: Add USB nodes")
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
arch/arm/mach-ipq40xx/clock-ipq4019.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c
b/arch/arm/mach-ipq40xx/clock-ipq4019.c
index 7308563ad1..a3f872947d 100644
--- a/arch/arm/mach-ipq40xx/clock-ipq4019.c
+++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c
@@ -55,6 +55,14 @@ static int msm_enable(struct clk *clk)
case GCC_PRNG_AHB_CLK: /*PRNG*/
/* This clock is already initialized by SBL1 */
return 0;
+ case GCC_USB3_MASTER_CLK:
+ case GCC_USB3_SLEEP_CLK:
+ case GCC_USB3_MOCK_UTMI_CLK:
+ case GCC_USB2_MASTER_CLK:
+ case GCC_USB2_SLEEP_CLK:
+ case GCC_USB2_MOCK_UTMI_CLK:
+ /* These clocks is already initialized by SBL1 */
+ return 0;
default:
return -EINVAL;
}
--
2.28.0
[PATCH v4 0/8] rockchip: Add Engicam PX30.Core support
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 Starter Kit - C.TOUCH 2.0 Note: dts patches are in Linux mailing-list. Changes for v4: - rebase on master - on top of Heiko, ram patch https://patchwork.ozlabs.org/project/uboot/patch/20201001184003.3704604-1-he...@sntech.det/ thanks, Jagan. Jagan Teki (7): arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit rockchip: px30: Add EVB_PX30 Kconfig help board: engicam: Attach i.MX6 common code rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 rockchip: Add Engicam PX30.Core C.TOUCH 2.0 doc: rockchip: Document Rockchip miniloader flashing Michael Trimarchi (1): arm64: dts: rockchip: Add Engicam PX30.Core SOM arch/arm/dts/Makefile | 2 + arch/arm/dts/px30-engicam-common.dtsi | 39 arch/arm/dts/px30-engicam-ctouch2.dtsi| 8 + arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 + arch/arm/dts/px30-px30-core-ctouch2.dts | 22 ++ arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 ++ arch/arm/dts/px30-px30-core.dtsi | 232 ++ arch/arm/mach-rockchip/px30/Kconfig | 22 ++ board/engicam/common/Kconfig | 8 + board/engicam/common/Makefile | 7 +- board/engicam/imx6q/Kconfig | 2 + board/engicam/imx6ul/Kconfig | 2 + board/engicam/px30_core/Kconfig | 16 ++ board/engicam/px30_core/MAINTAINERS | 13 ++ board/engicam/px30_core/Makefile | 7 + board/engicam/px30_core/px30_core.c | 4 + configs/px30-core-ctouch2-px30_defconfig | 108 ++ configs/px30-core-edimm2.2-px30_defconfig | 108 ++ doc/board/rockchip/rockchip.rst | 40 +++- include/configs/px30_core.h | 15 ++ 20 files changed, 680 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/px30-engicam-common.dtsi create mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi create mode 100644 arch/arm/dts/px30-px30-core-ctouch2.dts create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts create mode 100644 arch/arm/dts/px30-px30-core.dtsi create mode 100644 board/engicam/common/Kconfig create mode 100644 board/engicam/px30_core/Kconfig create mode 100644 board/engicam/px30_core/MAINTAINERS create mode 100644 board/engicam/px30_core/Makefile create mode 100644 board/engicam/px30_core/px30_core.c create mode 100644 configs/px30-core-ctouch2-px30_defconfig create mode 100644 configs/px30-core-edimm2.2-px30_defconfig create mode 100644 include/configs/px30_core.h -- 2.25.1
[PATCH 3/4] IPQ40xx: clk: dont always return 0
Currently the driver will go through the clock ID-s and set/enable them as needed. But if the ID is unknown it will fall through the switch case to the default case which will always return 0. This is not correct and default cases should return a error code since clock ID is unknown. So lets return -EINVAL instead. Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/mach-ipq40xx/clock-ipq4019.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c index ac2b830353..7308563ad1 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c @@ -26,7 +26,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate) /* This clock is already initialized by SBL1 */ return 0; default: - return 0; + return -EINVAL; } } @@ -56,7 +56,7 @@ static int msm_enable(struct clk *clk) /* This clock is already initialized by SBL1 */ return 0; default: - return 0; + return -EINVAL; } } -- 2.28.0
[PATCH 1/4] IPQ40xx: clk: use dev_read_addr()
Lets convert the driver to use dev_read_addr() instead of the devfdt_get_addr().
While we are here, lets also alphabetise the includes.
Signed-off-by: Robert Marko
Cc: Luka Perkov
---
arch/arm/mach-ipq40xx/clock-ipq4019.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c
b/arch/arm/mach-ipq40xx/clock-ipq4019.c
index 31ae9719e8..1f385665cc 100644
--- a/arch/arm/mach-ipq40xx/clock-ipq4019.c
+++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c
@@ -8,8 +8,8 @@
*
*/
-#include
#include
+#include
#include
#include
@@ -35,7 +35,7 @@ static int msm_clk_probe(struct udevice *dev)
{
struct msm_clk_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
--
2.28.0
[PATCH 2/4] IPQ40xx: clk: drop breaks in switch case
There is no point in having break statements in the switch case as there is already a return before break. So lets drop them from the driver. Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/mach-ipq40xx/clock-ipq4019.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c index 1f385665cc..ac2b830353 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c @@ -25,7 +25,6 @@ ulong msm_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ return 0; - break; default: return 0; } @@ -53,11 +52,9 @@ static int msm_enable(struct clk *clk) case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ /* This clock is already initialized by SBL1 */ return 0; - break; case GCC_PRNG_AHB_CLK: /*PRNG*/ /* This clock is already initialized by SBL1 */ return 0; - break; default: return 0; } -- 2.28.0
Re: [PATCH] ram: rockchip: px30: add a config-based ddr selection
On Fri, Oct 2, 2020 at 12:10 AM Heiko Stuebner wrote: > > From: Heiko Stuebner > > The SRAM on the PX30 is not big enough to hold multiple DDR configs > so it needs to be selected during build. > > So far simply the DDR3 config was always selected and getting DDR4 > or LPDDR2/3 initialized would require a code modification. > > So add Kconfig options similar to RK3399 to allow selecting the DDR4 > and LPDDR2/3 options instead, while DDR3 stays the default as before. > > Signed-off-by: Heiko Stuebner > --- Reviewed-by: Jagan Teki
[PATCH 5/5 v2] mips: octeon: tools: Add update_octeon_header tool
Add a tool to update or insert an Octeon specific header into the U-Boot
image. This is needed e.g. for booting via SPI NOR, eMMC and NAND.
While working on this, move enum cvmx_board_types_enum and
cvmx_board_type_to_string() to cvmx-bootloader.h and remove the
unreferenced (unsupported) board definition.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
v2:
- No change
- Azure build success here:
https://dev.azure.com/sr0718/u-boot/_build/results?buildId=59=results
.../mach-octeon/include/mach/cvmx-bootinfo.h | 222 -
.../include/mach/cvmx-bootloader.h| 172 +++
tools/Makefile| 3 +
tools/update_octeon_header.c | 450 ++
4 files changed, 625 insertions(+), 222 deletions(-)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootloader.h
create mode 100644 tools/update_octeon_header.c
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
index 337987178f..97438ff787 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
@@ -125,226 +125,4 @@ struct cvmx_bootinfo {
#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
-/* Type defines for board and chip types */
-enum cvmx_board_types_enum {
- CVMX_BOARD_TYPE_NULL = 0,
- CVMX_BOARD_TYPE_SIM = 1,
- CVMX_BOARD_TYPE_EBT3000 = 2,
- CVMX_BOARD_TYPE_KODAMA = 3,
- CVMX_BOARD_TYPE_NIAGARA = 4,
- CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
- CVMX_BOARD_TYPE_THUNDER = 6,
- CVMX_BOARD_TYPE_TRANTOR = 7,
- CVMX_BOARD_TYPE_EBH3000 = 8,
- CVMX_BOARD_TYPE_EBH3100 = 9,
- CVMX_BOARD_TYPE_HIKARI = 10,
- CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
- CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
- CVMX_BOARD_TYPE_KBP = 13,
- /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
- CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
- CVMX_BOARD_TYPE_EBT5800 = 15,
- CVMX_BOARD_TYPE_NICPRO2 = 16,
- CVMX_BOARD_TYPE_EBH5600 = 17,
- CVMX_BOARD_TYPE_EBH5601 = 18,
- CVMX_BOARD_TYPE_EBH5200 = 19,
- CVMX_BOARD_TYPE_BBGW_REF = 20,
- CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
- CVMX_BOARD_TYPE_EBT5600 = 22,
- CVMX_BOARD_TYPE_EBH5201 = 23,
- CVMX_BOARD_TYPE_EBT5200 = 24,
- CVMX_BOARD_TYPE_CB5600 = 25,
- CVMX_BOARD_TYPE_CB5601 = 26,
- CVMX_BOARD_TYPE_CB5200 = 27,
- /* Special 'generic' board type, supports many boards */
- CVMX_BOARD_TYPE_GENERIC = 28,
- CVMX_BOARD_TYPE_EBH5610 = 29,
- CVMX_BOARD_TYPE_LANAI2_A = 30,
- CVMX_BOARD_TYPE_LANAI2_U = 31,
- CVMX_BOARD_TYPE_EBB5600 = 32,
- CVMX_BOARD_TYPE_EBB6300 = 33,
- CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
- CVMX_BOARD_TYPE_LANAI2_G = 35,
- CVMX_BOARD_TYPE_EBT5810 = 36,
- CVMX_BOARD_TYPE_NIC10E = 37,
- CVMX_BOARD_TYPE_EP6300C = 38,
- CVMX_BOARD_TYPE_EBB6800 = 39,
- CVMX_BOARD_TYPE_NIC4E = 40,
- CVMX_BOARD_TYPE_NIC2E = 41,
- CVMX_BOARD_TYPE_EBB6600 = 42,
- CVMX_BOARD_TYPE_REDWING = 43,
- CVMX_BOARD_TYPE_NIC68_4 = 44,
- CVMX_BOARD_TYPE_NIC10E_66 = 45,
- CVMX_BOARD_TYPE_MAX,
-
- /*
-* The range from CVMX_BOARD_TYPE_MAX to
-* CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
-* SDK use.
-*/
-
- /*
-* Set aside a range for customer boards. These numbers are managed
-* by Cavium.
-*/
- CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 1,
- CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
- CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
- CVMX_BOARD_TYPE_CUST_NB5 = 10003,
- CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
- CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
- CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
- CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
- CVMX_BOARD_TYPE_CUST_GST104 = 10008,
- CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
- CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
- CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
- CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
- CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
- CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
- CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
- CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
- CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
- CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
- CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
- CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
- CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
- CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 2,
-
- /*
-* Set aside a range for customer private use. The SDK won't
-* use any numbers in this range.
-*/
- CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
- CVMX_BOARD_TYPE_UBNT_E100 = 20002,
- CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
-
[PATCH 1/5 v2] mips: start.S: Add Octeon boot header compatibility
Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck --- v2: - Enhance comment - Fix delay slot indentation arch/mips/cpu/start.S | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index d0c412236d..335aafa6a8 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -74,9 +74,14 @@ .endm ENTRY(_start) - /* U-Boot entry point */ + /* +* U-Boot entry point. +* Do not add instructions to the branch delay slot! Some SoC's +* like Octeon might patch the final U-Boot binary at this location +* with additional boot headers. +*/ b reset -mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing +nop #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) /* @@ -123,6 +128,7 @@ ENTRY(_start) #endif reset: + mtc0zero, CP0_COUNT # clear cp0 count for most accurate boot timing #if __mips_isa_rev >= 6 mfc0t0, CP0_CONFIG, 5 and t0, t0, MIPS_CONF5_VP -- 2.29.1
[PATCH 3/5 v2] mips: octeon: Report full DDR size in dram_init() to gd->ram_size
With this patch, gd->ram_size now holds to full RAM size detected by the
DDR init code. It introduces the get_effective_memsize() function to
report the maximum usable RAM size in U-Boot to the system instead.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
v2:
- No change
arch/mips/mach-octeon/dram.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
index 6dc08e19da..4679260f17 100644
--- a/arch/mips/mach-octeon/dram.c
+++ b/arch/mips/mach-octeon/dram.c
@@ -33,7 +33,7 @@ int dram_init(void)
return ret;
}
- gd->ram_size = min_t(size_t, ram.size, UBOOT_RAM_SIZE_MAX);
+ gd->ram_size = ram.size;
debug("SDRAM base=%lx, size=%lx\n",
(unsigned long)ram.base, (unsigned long)ram.size);
} else {
@@ -72,6 +72,11 @@ void board_add_ram_info(int use_default)
}
}
+phys_size_t get_effective_memsize(void)
+{
+ return UBOOT_RAM_SIZE_MAX;
+}
+
ulong board_get_usable_ram_top(ulong total_size)
{
if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
--
2.29.1
[PATCH 4/5 v2] mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info()
Using ram_get_info() is complicated and does not work after relocation.
Now that gd->ram_size holds the full RAM size, let's use it instead and
remove the ram_get_size logic completely.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
v2:
- No change
arch/mips/mach-octeon/bootoctlinux.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
diff --git a/arch/mips/mach-octeon/bootoctlinux.c
b/arch/mips/mach-octeon/bootoctlinux.c
index 75d7e83bd7..26136902f3 100644
--- a/arch/mips/mach-octeon/bootoctlinux.c
+++ b/arch/mips/mach-octeon/bootoctlinux.c
@@ -9,7 +9,6 @@
#include
#include
#include
-#include
#include
#include
@@ -370,8 +369,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
struct cvmx_coremask avail_coremask;
int first_core;
int core;
- struct ram_info ram;
- struct udevice *dev;
const u64 *nmi_code;
int num_dwords;
u8 node_mask = 0x01;
@@ -470,19 +467,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
*/
cvmx_coremask_or(_to_run, _to_run, _mask);
- /* Get RAM size */
- ret = uclass_get_device(UCLASS_RAM, 0, );
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
-
- ret = ram_get_info(dev, );
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
-
/*
* Load kernel ELF image, or try binary if ELF is not detected.
* This way the much smaller vmlinux.bin can also be started but
@@ -498,7 +482,7 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
/* Init bootmem list for Linux kernel booting */
if (!cvmx_bootmem_phy_mem_list_init(
- ram.size, OCTEON_RESERVED_LOW_MEM_SIZE,
+ gd->ram_size, OCTEON_RESERVED_LOW_MEM_SIZE,
(void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_SPACE))) {
printf("FATAL: Error initializing free memory list\n");
return 0;
@@ -517,7 +501,8 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
if (core == first_core)
cvmx_bootinfo_array[core].flags |= BOOT_FLAG_INIT_CORE;
- cvmx_bootinfo_array[core].dram_size = ram.size / (1024 * 1024);
+ cvmx_bootinfo_array[core].dram_size = gd->ram_size /
+ (1024 * 1024);
cvmx_bootinfo_array[core].dclock_hz = gd->mem_clk * 100;
cvmx_bootinfo_array[core].eclock_hz = gd->cpu_clk;
--
2.29.1
[PATCH 2/5 v2] mips: octeon: Fix Octeon DDR driver to use the correct struct
Don't use "platdata_auto_alloc_size" but "priv_auto_alloc_size" instead
to auto allocate the private data struct, which is referenced via
dev_get_priv() in this driver. This fixes an ugly bug detected while
trying to boot via SPI NOR.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
v2:
- No change
drivers/ram/octeon/octeon_ddr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index 757436b9d3..aaff9c3687 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -2724,5 +2724,5 @@ U_BOOT_DRIVER(octeon_ddr) = {
.of_match = octeon_ids,
.ops = _ops,
.probe = octeon_ddr_probe,
- .platdata_auto_alloc_size = sizeof(struct ddr_priv),
+ .priv_auto_alloc_size = sizeof(struct ddr_priv),
};
--
2.29.1
[PATCH v4 2/8] arm64: dts: rockchip: Add Engicam PX30.Core SOM
From: Michael Trimarchi
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features
PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.
Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Michael Trimarchi
Reviewed-by: Kever Yang
---
Changes for v4:
- none
arch/arm/dts/px30-px30-core.dtsi | 232 +++
1 file changed, 232 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core.dtsi
diff --git a/arch/arm/dts/px30-px30-core.dtsi b/arch/arm/dts/px30-px30-core.dtsi
new file mode 100644
index 00..16e6cf28a4
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core.dtsi
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+#include
+#include
+
+/ {
+ compatible = "engicam,px30-px30-core", "rockchip,px30";
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <>;
+ interrupts = ;
+ pinctrl-names = "default";
+ pinctrl-0 = <_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ vcc1-supply = <_sys>;
+ vcc2-supply = <_sys>;
+ vcc3-supply = <_sys>;
+ vcc4-supply = <_sys>;
+ vcc5-supply = <_sys>;
+ vcc6-supply = <_sys>;
+ vcc7-supply = <_sys>;
+ vcc8-supply = <_sys>;
+ vcc9-supply = <_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <95>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <95>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <95>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <95>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG5 {
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+
+
[PATCH v4 3/8] rockchip: px30: Add EVB_PX30 Kconfig help
TARGET_EVB_PX30 can be possible to use other px30 boards. Add the help text for existing EVB, so-that the new boards which are resuing this config option can mention their board help text. This would help to track which boards are using EVB_PX30 config. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Changes for v4: - none arch/arm/mach-rockchip/px30/Kconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index f5373c6f9f..6cd65dfa97 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -2,6 +2,11 @@ if ROCKCHIP_PX30 config TARGET_EVB_PX30 bool "EVB_PX30" + help + This target config option used for below listed px30 boards. + + EVB_PX30: + * EVB_PX30 is an evaluation board for Rockchip PX30. config TARGET_ODROID_GO2 bool "ODROID_GO2" -- 2.25.1
[PATCH v4 1/8] arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Michael Trimarchi
Reviewed-by: Kever Yang
---
Changes for v4:
- none
arch/arm/dts/px30-engicam-common.dtsi | 39 +
arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 +
2 files changed, 46 insertions(+)
create mode 100644 arch/arm/dts/px30-engicam-common.dtsi
create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi
diff --git a/arch/arm/dts/px30-engicam-common.dtsi
b/arch/arm/dts/px30-engicam-common.dtsi
new file mode 100644
index 00..bd5bde989e
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-common.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/ {
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys"; /* +5V */
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+};
+
+ {
+ clock_in_out = "output";
+ phy-supply = <_3v3>;/* +3V3_SOM */
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 5 5>;
+ snps,reset-gpio = < RK_PB5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+ {
+ cap-sd-highspeed;
+ card-detect-delay = <800>;
+ vmmc-supply = <_3v3>; /* +3V3_SOM */
+ vqmmc-supply = <_3v3>;
+ status = "okay";
+};
+
+ {
+ pinctrl-0 = <_xfer>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
new file mode 100644
index 00..cb00988953
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "px30-engicam-common.dtsi"
--
2.25.1
[PATCH v4 4/8] board: engicam: Attach i.MX6 common code
The existing common code for Engicam boards uses i.MX6, so attach that into i.MX6 Engicam boards so-that adding new SoC variants of Engicam boards become meaningful. Add support for it. Cc: Stefano Babic Signed-off-by: Jagan Teki --- Changes for v4: - none board/engicam/common/Kconfig | 8 board/engicam/common/Makefile | 7 +-- board/engicam/imx6q/Kconfig | 2 ++ board/engicam/imx6ul/Kconfig | 2 ++ 4 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 board/engicam/common/Kconfig diff --git a/board/engicam/common/Kconfig b/board/engicam/common/Kconfig new file mode 100644 index 00..38328fd5ea --- /dev/null +++ b/board/engicam/common/Kconfig @@ -0,0 +1,8 @@ +config IMX6_ENGICAM_COMMON + bool "Engicam i.MX6 Common code" + depends on SPL && MX6 + default y if TARGET_MX6Q_ENGICAM || TARGET_MX6UL_ENGICAM + help + Common SPL and U-Boot proper code for Engicam i.MX6 targets. + + Enable it in board Kconfig if it uses i.MX6 variant Engicam boards. diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile index b392bf6cb1..15f0eaa1ec 100644 --- a/board/engicam/common/Makefile +++ b/board/engicam/common/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2016 Amarula Solutions B.V. -obj-y := board.o -obj-$(CONFIG_SPL_BUILD) += spl.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o +else +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o +endif diff --git a/board/engicam/imx6q/Kconfig b/board/engicam/imx6q/Kconfig index 48eb60c09a..fab8da0e73 100644 --- a/board/engicam/imx6q/Kconfig +++ b/board/engicam/imx6q/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif diff --git a/board/engicam/imx6ul/Kconfig b/board/engicam/imx6ul/Kconfig index e91dd15970..58f25d0623 100644 --- a/board/engicam/imx6ul/Kconfig +++ b/board/engicam/imx6ul/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif -- 2.25.1
[PATCH v4 5/8] rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.
PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Suniel Mahesh
---
Changes for v4:
- drop ram change
- on top of
https://patchwork.ozlabs.org/project/uboot/patch/20201001184003.3704604-1-he...@sntech.de/
arch/arm/dts/Makefile | 1 +
arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 +
arch/arm/mach-rockchip/px30/Kconfig | 10 ++
board/engicam/px30_core/Kconfig | 16
board/engicam/px30_core/MAINTAINERS | 7 ++
board/engicam/px30_core/Makefile | 7 ++
board/engicam/px30_core/px30_core.c | 4 +
configs/px30-core-edimm2.2-px30_defconfig | 108 ++
include/configs/px30_core.h | 15 +++
9 files changed, 189 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts
create mode 100644 board/engicam/px30_core/Kconfig
create mode 100644 board/engicam/px30_core/MAINTAINERS
create mode 100644 board/engicam/px30_core/Makefile
create mode 100644 board/engicam/px30_core/px30_core.c
create mode 100644 configs/px30-core-edimm2.2-px30_defconfig
create mode 100644 include/configs/px30_core.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b195723f16..b87f4334a5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
+ px30-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts
b/arch/arm/dts/px30-px30-core-edimm2.2.dts
new file mode 100644
index 00..c36280ce7f
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core-edimm2.2.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-edimm2.2.dtsi"
+#include "px30-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
+"rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig
b/arch/arm/mach-rockchip/px30/Kconfig
index 6cd65dfa97..5d014f6561 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -11,6 +11,15 @@ config TARGET_EVB_PX30
config TARGET_ODROID_GO2
bool "ODROID_GO2"
+config TARGET_PX30_CORE
+ bool "Engicam PX30.Core"
+ help
+ PX30.Core EDIMM2.2:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.
+ * PX30.Core needs to mount on top of EDIMM2.2 for creating complete
+ PX30.Core EDIMM2.2 Starter Kit.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
@@ -44,6 +53,7 @@ config DEBUG_UART_CHANNEL
For using the UART for early debugging the route to use needs
to be declared (0 or 1).
+source "board/engicam/px30_core/Kconfig"
source "board/hardkernel/odroid_go2/Kconfig"
source "board/rockchip/evb_px30/Kconfig"
diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30_core/Kconfig
new file mode 100644
index 00..a03be78369
--- /dev/null
+++ b/board/engicam/px30_core/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_PX30_CORE
+
+config SYS_BOARD
+ default "px30_core"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "px30_core"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select RAM_PX30_DDR4
+
+endif
diff --git a/board/engicam/px30_core/MAINTAINERS
b/board/engicam/px30_core/MAINTAINERS
new file mode 100644
index 00..f98a84450a
--- /dev/null
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -0,0 +1,7 @@
+PX30-Core-EDIMM2.2
+M: Jagan Teki
+M: Suniel Mahesh
+S: Maintained
+F: board/engicam/px30_core
+F: include/configs/px30_core.h
+F: configs/px30-core-edimm2.2-px30_defconfig
diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30_core/Makefile
new file mode 100644
index 00..321fdb0173
--- /dev/null
+++ b/board/engicam/px30_core/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2020 Amarula Solutions(India)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += px30_core.o
diff --git a/board/engicam/px30_core/px30_core.c
b/board/engicam/px30_core/px30_core.c
new file mode 100644
index 00..3adc2f11de
--- /dev/null
+++
[PATCH v4 6/8] arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi --- Changes for v4: - none arch/arm/dts/px30-engicam-ctouch2.dtsi | 8 1 file changed, 8 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi new file mode 100644 index 00..58425b1e55 --- /dev/null +++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" -- 2.25.1
[PATCH v4 7/8] rockchip: Add Engicam PX30.Core C.TOUCH 2.0
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Suniel Mahesh
---
Changes for v4:
- none
arch/arm/dts/Makefile| 1 +
arch/arm/dts/px30-px30-core-ctouch2.dts | 22 +
arch/arm/mach-rockchip/px30/Kconfig | 7 ++
board/engicam/px30_core/MAINTAINERS | 6 ++
configs/px30-core-ctouch2-px30_defconfig | 108 +++
5 files changed, 144 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core-ctouch2.dts
create mode 100644 configs/px30-core-ctouch2-px30_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b87f4334a5..658617d4dc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
+ px30-px30-core-ctouch2.dtb \
px30-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts
b/arch/arm/dts/px30-px30-core-ctouch2.dts
new file mode 100644
index 00..2da0128188
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core-ctouch2.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core C.TOUCH 2.0";
+ compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
+"rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig
b/arch/arm/mach-rockchip/px30/Kconfig
index 5d014f6561..16090f5b08 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -20,6 +20,13 @@ config TARGET_PX30_CORE
* PX30.Core needs to mount on top of EDIMM2.2 for creating complete
PX30.Core EDIMM2.2 Starter Kit.
+ PX30.Core CTOUCH2:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * CTOUCH2.0 is a general purpose Carrier board with capacitive
+ touch interface support.
+ * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
+ PX30.Core C.TOUCH Carrier board.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
diff --git a/board/engicam/px30_core/MAINTAINERS
b/board/engicam/px30_core/MAINTAINERS
index f98a84450a..b87ca22207 100644
--- a/board/engicam/px30_core/MAINTAINERS
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -1,3 +1,9 @@
+PX30-Core-CTOUCH2.0
+M: Jagan Teki
+M: Suniel Mahesh
+S: Maintained
+F: configs/px30-core-ctouch2-px30_defconfig
+
PX30-Core-EDIMM2.2
M: Jagan Teki
M: Suniel Mahesh
diff --git a/configs/px30-core-ctouch2-px30_defconfig
b/configs/px30-core-ctouch2-px30_defconfig
new file mode 100644
index 00..d64f05d8c0
--- /dev/null
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_TEXT_BASE=0x
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_PX30_CORE=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_DEBUG_UART_BASE=0xFF16
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+#
[PATCH v4 8/8] doc: rockchip: Document Rockchip miniloader flashing
This would be useful and recommended boot flow for new boards
which has doesn't have the DDR support yet in mainline.
Sometimes it is very useful for debugging mainline DDR support.
Documen it for px30 boot flow.
Signed-off-by: Jagan Teki
---
Changes for v4:
- none
doc/board/rockchip/rockchip.rst | 40 -
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 8c92de0c92..955e6858f2 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -123,6 +123,9 @@ To build rk3399 boards::
Flashing
+1. Package the image with U-Boot TPL/SPL
+-
+
SD Card
^^^
@@ -187,6 +190,39 @@ Copy SPI boot images into SD card and boot from SD::
sf erase 0x6 +$filesize
sf write $kernel_addr_r 0x6 ${filesize}
+2. Package the image with Rockchip miniloader
+-
+
+Image package with Rockchip miniloader requires robin [1].
+
+Create idbloader.img
+
+.. code-block:: none
+
+ cd u-boot
+ ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin
idbloader.img
+ cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img
+ sudo dd if=idbloader.img of=/dev/sda seek=64
+
+Create trust.img
+
+.. code-block:: none
+
+ cd rkbin
+ ./tools/trust_merger RKTRUST/PX30TRUST.ini
+ sudo dd if=trust.img of=/dev/sda seek=24576
+
+Create uboot.img
+
+.. code-block:: none
+
+ rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x20
+ sudo dd if=uboot.img of=/dev/sda seek=16384
+
+Note:
+1. 0x20 is load address and it's an optional in some platforms.
+2. rkbin binaries are kept on updating, so would recommend to use the latest
versions.
+
TODO
@@ -195,5 +231,7 @@ TODO
- Document SPI flash boot
- Add missing SoC's with it boards list
+[1] https://github.com/rockchip-linux/rkbin
+
.. Jagan Teki
-.. Tuesday 02 June 2020 12:18:57 AM IST
+.. Wednesday 28 October 2020 06:47:26 PM IST
--
2.25.1
Re: [PATCH 1/2] Add HMAC-SHA-256
Dear GlovePuppet, In message <1603813411162-0.p...@n7.nabble.com> you wrote: > Required by TPM2 Extended Auth, cloned from sha1.c > > Signed-off-by: GlovePuppet NAK. The Submitting Patches rules require using your real name (sorry, no pseudonyms or anonymous contributions.) See [1] for reference. [1] https://github.com/torvalds/linux/blob/master/Documentation/process/submitting-patches.rst Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Some programming languages manage to absorb change, but withstand progress. -- Epigrams in Programming, ACM SIGPLAN Sept. 1982
Re: [PATCH 2/2] Add TPM2 Unseal command and supporting functions
Dear GlovePuppet, In message <1603813495996-0.p...@n7.nabble.com> you wrote: > Unseals a loaded object, identified by handle, and returns > data at a memory location or in an environment variable > > Caveats > > -The PolicyPCR command only supports one PCR > -The auth request code only supports one handle > > Signed-off-by: GlovePuppet NAK. The Submitting Patches rules require using your real name (sorry, no pseudonyms or anonymous contributions.) See [1] for reference. [1] https://github.com/torvalds/linux/blob/master/Documentation/process/submitting-patches.rst Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Some programming languages manage to absorb change, but withstand progress. -- Epigrams in Programming, ACM SIGPLAN Sept. 1982
[PATCH] imx8mp_evk: README instruction fixes
Use the full name of firmware self extracting file to make it run. Also, don't use sudo when not needed. Signed-off-by: Baruch Siach --- This time add the u-boot list to Cc. --- board/freescale/imx8mp_evk/README | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/freescale/imx8mp_evk/README b/board/freescale/imx8mp_evk/README index 7dd3a9352a57..0c65a894bb1a 100644 --- a/board/freescale/imx8mp_evk/README +++ b/board/freescale/imx8mp_evk/README @@ -13,17 +13,17 @@ Note: $(srctree) is the U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf branch: imx_5.4.3_2.0.0 $ make PLAT=imx8mp bl31 -$ sudo cp build/imx8mp/release/bl31.bin $(srctree) +$ cp build/imx8mp/release/bl31.bin $(srctree) Get the ddr firmware $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin $ chmod +x firmware-imx-8.7.bin -$ ./firmware-imx-8.7 -$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin -$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin -$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin -$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin +$ ./firmware-imx-8.7.bin +$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin +$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin +$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin +$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin Build U-Boot -- 2.28.0
Re: [PATCH 5/5] mips: octeon: tools: Add update_octeon_header tool
Hi Daniel, On 26.10.20 14:31, Daniel Schwierzeck wrote: diff --git a/tools/update_octeon_header.c b/tools/update_octeon_header.c new file mode 100644 index 00..964036216d --- /dev/null +++ b/tools/update_octeon_header.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "mkimage.h" + +#include "../arch/mips/mach-octeon/include/mach/cvmx-bootloader.h" have you tried with just "mach/cvmx-bootloader.h"? I'm afraid this breaks out-of-tree builds. No, this does not work. I just started a full world build on Azure and had no build issue with these patches. So there does not seem to be such a OOT build issue AFAICT. BTW: tools/mksunxiboot.c also uses a similar header inclusion: #include "../arch/arm/include/asm/arch-sunxi/spl.h" Thanks, Stefan
Re: Pull request for UEFI sub-system for efi-2021-01-rc2
On Wed, Oct 28, 2020 at 12:43:43PM +0100, Heinrich Schuchardt wrote: > The following changes since commit 986c980c8250849d9394fdf377a3de75edb11888: > > nokia_rx51: re-enable CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV > (2020-10-27 10:48:08 -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2021-01-rc2 > > for you to fetch changes up to 0eae552d18690a19cc714046fb1665138f5701f6: > > efi_loader: daylight saving time (2020-10-27 21:13:16 +0100) > > > Gitlab CI showed not problem: > https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/5148 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 1/3] log: move processing_msg to global data
On Sat, Oct 17, 2020 at 02:31:57PM +0200, Heinrich Schuchardt wrote: > Replace the static variable processing_msg by a field in the global data. > Make the field bool at it can only be true or false. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 2/3] log: allow for message continuation
On Sat, Oct 17, 2020 at 02:31:58PM +0200, Heinrich Schuchardt wrote: > Some drivers use macro pr_cont() for continuing a message sent via printk. > Hence if we want to convert printk messaging to using the logging system, > we must support continuation of log messages too. > > As pr_cont() does not provide a message level we need a means of > remembering the last log level. > > With the patch a pseudo log level LOGL_CONT as well as a pseudo log > category LOGC_CONT are introduced. Using these results in the application > of the same log level and category as in the previous log message. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Speed/mode setting via "sf probe" command
Dear maintainers,
Any thoughts on this? It seems that "sf probe" behaviour should either
get fixed, or we should remove the "hz" and "mode" arguments entirely,
since they don't work anymore.
Regards,
Ralph
On Thu, Oct 15, 2020 at 12:25:41PM -0400, Ralph Siemsen wrote:
Hi,
The "sf probe" command is documented to take optional speed/mode args:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
and chip select
This worked correctly in older u-boot versions, but as of 2019.07 the
speed/mode arguments appear to be effectively ignored. As this feature
is quite useful for testing purposes, I would like to find a way to
support it again. But the logic is surprisingly complicated, so I
would like to get some advice/ideas.
The user-specified speed/mode are parsed in do_spi_flash_probe() and
eventually are passed to spi_get_bus_and_cs(). In 2019.04 and earlier,
the logic here was pretty straightforward:
plat = dev_get_parent_platdata(dev);
if (!speed) {
speed = plat->max_hz;
mode = plat->mode;
}
ret = spi_set_speed_mode(bus, speed, mode);
if (ret)
goto err;
So this calls spi_set_speed_mode() with the user-specified speed, or a
default value.
As of commit 0cc1b846fcb310c0ac2f8cbeb4ed5947dc52912 ("dm: spi: Read default speed
and mode values from DT")
the logic has changed. The user-specified speed value is now stored
into plat->max_hz, but *only* when no chip select has been configured.
In practice this means only the first call to spi_get_bus_and_cs()
uses the speed parameter. Thereafter the speed will not change.
Related commit f7dd5370986087af9b9cfa601f34b344ec910b87 ("spi: prevent overriding
established bus settings")
removes the call to spi_set_speed_mode() entirely. So the speed is now
set by dm_spi_claim_bus() which uses slave->max_hz, which in turn is
set from plat->max_hz in the spi_child_pre_probe() function.
The first call to spi_get_bus_and_cs() typically occurs when searching
for u-boot environment, and uses the speed specified in DT. This
becomes the only speed, as subsequent "sf probe" do not update
plat->max_hz.
One potential work-around would be to clear the chip select prior to
re-binding the device. This allows plat->max_hz to be updated, andalso
means that device_bind_driver() will be repeateed. However I am not
entirely certain if this is correct approach. In particular, is using
-1 for the cs appropriate in all cases? It seems it can come from DT.
diff --git a/cmd/sf.c b/cmd/sf.c
index d18f6a888c..8cb70f6487 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -128,6 +128,9 @@ static int do_spi_flash_probe(int argc, char *const argv[])
/* Remove the old device, otherwise probe will just be a nop */
ret = spi_find_bus_and_cs(bus, cs, _dev, );
if (!ret) {
+ struct dm_spi_slave_platdata *plat;
+ plat = dev_get_parent_platdata(new);
+ plat->cs = -1;
device_remove(new, DM_REMOVE_NORMAL);
}
flash = NULL;
Re: [PATCH 1/1] log: correct and check array size of log categories
On Fri, Oct 23, 2020 at 01:00:01PM +0200, Heinrich Schuchardt wrote: > The log command has led to NULL dereferences if an unknown category name > name was used due to missing entries in the list of category names. > > Add compile time checks for the array sizes of log_cat_name and > log_lvl_name to avoid future mishaps. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 3/3] test: log: test message continuation
On Sat, Oct 17, 2020 at 02:31:59PM +0200, Heinrich Schuchardt wrote: > Provide a unit test checking that a continuation message will use the same > log level and log category as the previous message. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH] ARM: dts: stm32: Fix uSD card-detect GPIO on DHCOM
The uSD slot card-detect GPIO is connected to PG1, fix it. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index 18c08c9435..1081d0c069 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -329,7 +329,7 @@ pinctrl-0 = <_b4_pins_a _dir_pins_a>; pinctrl-1 = <_b4_od_pins_a _dir_pins_a>; pinctrl-2 = <_b4_sleep_pins_a _dir_sleep_pins_a>; - cd-gpios = < 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + cd-gpios = < 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,sig-dir; st,neg-edge; -- 2.28.0
[PATCH] ARM: dts: stm32: Drop QSPI CS2 on DHCOM
The QSPI CS2 is not used on DHCOM, remove the pinmux and flash@1.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arch/arm/dts/stm32mp15xx-dhcom.dtsi | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
index 8782a3b78d..18c08c9435 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -299,8 +299,8 @@
{
pinctrl-names = "default", "sleep";
- pinctrl-0 = <_clk_pins_a _bk1_pins_a _bk2_pins_a>;
- pinctrl-1 = <_clk_sleep_pins_a _bk1_sleep_pins_a
_bk2_sleep_pins_a>;
+ pinctrl-0 = <_clk_pins_a _bk1_pins_a>;
+ pinctrl-1 = <_clk_sleep_pins_a _bk1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x7000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
@@ -314,15 +314,6 @@
#address-cells = <1>;
#size-cells = <1>;
};
-
- flash1: mx66l51235l@1 {
- compatible = "jedec,spi-nor";
- reg = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <10800>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
};
{
--
2.28.0
Re: [PATCH] ARM: dts: stm32: Reinstate card detect behavior on DHSOM
On 10/28/20 11:20 AM, Patrick DELAUNAY wrote: > Hi Marek, Hello Patrick, [...] >>> But after investigation the internall pull-up is not configurated in >>> stm32 pinctrol (cheked with pinmux command) even it is requested in device- >> tree of EV1/DK2. >>> >>> It is clearly a bug (I isolate the issue) and I am working on a patch >>> (it should be sent to u-boot mailing liste next week). >>> btw it is bugged in SPL. >>> >>> Ah, what is the issue. >>> >>> In the stm32 driver or in the framework ? >>> >>> I will cross-check it also on EV1/DK2. >> >> The card is not detected in SPL again, same fail mode as before. >> Now that I think about it, note to self, I should check whether the CD GPIO >> controller node is u-boot,dm-spl > > I found a big issue in stm32 pincontrol: the bias configuration was only > managed for ouput pin. > > With this serie [1], I checked the pull-up configuration (including in SPL by > adding a debug trace). > > With [2], the bias configuration is now correct in DK2 / EV1 boards (even if > the pull-up configuration is not mandatory, > because I don't see cart detection issue on ST board). > > I expect this patch correct the DHSOM issue. It does not, but the following does: [PATCH] ARM: dts: stm32: Fix uSD card-detect GPIO on DHCOM So it's a bug on both ends, good thing we found them. Thanks!
[PATCH] imx: mx6cuboxi: Disable CONFIG_IMX_THERMAL
This feature is incompatble with of-platdata since it uses the U_BOOT_DEVICE() macro. With of-platdata the only devices permitted are those created by dtoc. Drop this option for now, until the driver can be corrected. Signed-off-by: Simon Glass --- include/configs/mx6cuboxi.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index cfab9a7fc02..55717c77ab3 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -13,8 +13,6 @@ #include "imx6_spl.h" -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) /* MMC Configs */ -- 2.29.1.341.ge80a0c044ae-goog
Failed to make encrypt amlogic vim3
Dear Neil I have a question about vim3 board. When i have build with mainline u-boot, i have faced on below problem. (I have referred to doc/board/amlogic/khadas-vim3.rst) Do you know why failed like below? $fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig fip/aml_encrypt_g12b bl2sig fail[15208]! Best Regards, Jaehoon Chung
[RESEND PATCH v6 15/17] tools: add mkeficapsule command for UEFI capsule update
This is a utility mainly for test purpose.
mkeficapsule -f: create a test capsule file for FIT image firmware
Having said that, you will be able to customize the code to fit
your specific requirements for your platform.
Signed-off-by: AKASHI Takahiro
---
tools/Makefile | 2 +
tools/mkeficapsule.c | 238 +++
2 files changed, 240 insertions(+)
create mode 100644 tools/mkeficapsule.c
diff --git a/tools/Makefile b/tools/Makefile
index 51123fd92983..66d9376803e3 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -218,6 +218,8 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs
hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler
HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
+hostprogs-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += mkeficapsule
+
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
# exceptions for files that aren't complaint.
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
new file mode 100644
index ..db95426457cc
--- /dev/null
+++ b/tools/mkeficapsule.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+typedef __u8 u8;
+typedef __u16 u16;
+typedef __u32 u32;
+typedef __u64 u64;
+typedef __s16 s16;
+typedef __s32 s32;
+
+#define aligned_u64 __aligned_u64
+
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+#include
+#include
+
+static const char *tool_name = "mkeficapsule";
+
+efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
+efi_guid_t efi_guid_image_type_uboot_fit =
+ EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
+efi_guid_t efi_guid_image_type_uboot_raw =
+ EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID;
+
+static struct option options[] = {
+ {"fit", required_argument, NULL, 'f'},
+ {"raw", required_argument, NULL, 'r'},
+ {"index", required_argument, NULL, 'i'},
+ {"instance", required_argument, NULL, 'I'},
+ {"version", required_argument, NULL, 'v'},
+ {"help", no_argument, NULL, 'h'},
+ {NULL, 0, NULL, 0},
+};
+
+static void print_usage(void)
+{
+ printf("Usage: %s [options] \n"
+ "Options:\n"
+ "\t--fit new FIT image file\n"
+ "\t--raw new raw image file\n"
+ "\t--index update image index\n"
+ "\t--instance update hardware instance\n"
+ "\t--version firmware version\n"
+ "\t--help print a help message\n",
+ tool_name);
+}
+
+static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
+ unsigned long version, unsigned long index,
+ unsigned long instance)
+{
+ struct efi_capsule_header header;
+ struct efi_firmware_management_capsule_header capsule;
+ struct efi_firmware_management_capsule_image_header image;
+ FILE *f, *g;
+ struct stat bin_stat;
+ u8 *data;
+ size_t size;
+
+#ifdef DEBUG
+ printf("For output: %s\n", path);
+ printf("\tbin: %s\n\ttype: %pUl\n" bin, guid);
+ printf("\tversion: %ld\n\tindex: %ld\n\tinstance: %ld\n",
+ version, index, instance);
+#endif
+
+ g = fopen(bin, "r");
+ if (!g) {
+ printf("cannot open %s\n", bin);
+ return -1;
+ }
+ if (stat(bin, _stat) < 0) {
+ printf("cannot determine the size of %s\n", bin);
+ goto err_1;
+ }
+ data = malloc(bin_stat.st_size);
+ if (!data) {
+ printf("cannot allocate memory: %lx\n", bin_stat.st_size);
+ goto err_1;
+ }
+ f = fopen(path, "w");
+ if (!f) {
+ printf("cannot open %s\n", path);
+ goto err_2;
+ }
+ header.capsule_guid = efi_guid_fm_capsule;
+ header.header_size = sizeof(header);
+ header.flags = CAPSULE_FLAGS_PERSIST_ACROSS_RESET; /* TODO */
+ header.capsule_image_size = sizeof(header)
+ + sizeof(capsule) + sizeof(u64)
+ + sizeof(image)
+ + bin_stat.st_size;
+
+ size = fwrite(, 1, sizeof(header), f);
+ if (size < sizeof(header)) {
+ printf("write failed (%lx)\n", size);
+ goto err_3;
+ }
+
+ capsule.version = 0x0001;
+ capsule.embedded_driver_count = 0;
+ capsule.payload_item_count = 1;
+ capsule.item_offset_list[0] = sizeof(capsule) + sizeof(u64);
+ size = fwrite(, 1, sizeof(capsule) + sizeof(u64), f);
+ if (size < (sizeof(capsule) + sizeof(u64))) {
+ printf("write failed
Re: [RESEND PATCH v6 00/17] efi_loader: add capsule update support
On Thu, Oct 29, 2020 at 09:25:11AM +0900, AKASHI Takahiro wrote: > # > # This is a reminder. Nothing changed, but rebasing. > # Wasn't one of the outstanding requests to make the DFU related changes less intrusive and thus easier to review by someone (me) who is not the primary author of the DFU code but does want to unblock this overall series right here? -- Tom signature.asc Description: PGP signature
[RESEND PATCH v6 17/17] test/py: efi_capsule: test for raw image capsule
The test can run on sandbox build and it attempts to execute a firmware
update via a capsule-on-disk, using a raw image capsule,
CONFIG_EFI_CAPSULE_RAW.
To run this test successfully, you need configure U-Boot specifically;
See test_capsule_firmware.py for requirements, and hence it won't run
on Travis CI, at least, for now.
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_capsule/conftest.py| 3 +
.../test_efi_capsule/test_capsule_firmware.py | 63 +++
2 files changed, 66 insertions(+)
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index 4e7c36f04ba5..4544a24d5351 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -51,6 +51,9 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkeficapsule --fit uboot_bin_env.itb
--version 1 --index 1 Test01' %
(data_dir, u_boot_config.build_dir),
shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new
--version 1 --index 1 Test02' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
# Create a disk image with EFI system partition
check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s'
%
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
index ab7c2a7d6bea..c9b180ac65e8 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
@@ -15,6 +15,7 @@ from defs import *
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('efi_capsule_firmware_fit')
+@pytest.mark.buildconfigspec('efi_capsule_firmware_raw')
@pytest.mark.buildconfigspec('efi_capsule_on_disk')
@pytest.mark.buildconfigspec('dfu')
@pytest.mark.buildconfigspec('dfu_sf')
@@ -176,3 +177,65 @@ class TestEfiCapsuleFirmwareFit(object):
'sf read 400 15 10',
'md.b 400 10'])
assert 'u-boot-env:New' in ''.join(output)
+
+def test_efi_capsule_fw3(
+self, u_boot_config, u_boot_console, efi_capsule_data):
+"""
+Test Case 3 - Update U-Boot on SPI Flash, raw image format
+ 0x10-0x15: U-Boot binary (but dummy)
+"""
+disk_img = efi_capsule_data
+with u_boot_console.log.section('Test Case 3-a, before reboot'):
+output = u_boot_console.run_command_list([
+'host bind 0 %s' % disk_img,
+'efidebug boot add 1 TEST host 0:1 /helloworld.efi ""',
+'efidebug boot order 1',
+'env set -e -nv -bs -rt OsIndications =0x0004',
+'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x10
0x5;u-boot-env raw 0x15 0x20"',
+'env save'])
+
+# initialize content
+output = u_boot_console.run_command_list([
+'sf probe 0:0',
+'fatload host 0:1 400 %s/u-boot.bin.old' %
CAPSULE_DATA_DIR,
+'sf write 400 10 10',
+'sf read 500 10 10',
+'md.b 500 10'])
+assert 'Old' in ''.join(output)
+
+# place a capsule file
+output = u_boot_console.run_command_list([
+'fatload host 0:1 400 %s/Test02' % CAPSULE_DATA_DIR,
+'fatwrite host 0:1 400 %s/Test02 $filesize' %
CAPSULE_INSTALL_DIR,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test02' in ''.join(output)
+
+# reboot
+u_boot_console.restart_uboot()
+
+capsule_early = u_boot_config.buildconfig.get(
+'config_efi_capsule_on_disk_early')
+with u_boot_console.log.section('Test Case 3-b, after reboot'):
+if not capsule_early:
+# make sure that dfu_alt_info exists even persistent variables
+# are not available.
+output = u_boot_console.run_command_list([
+'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x10
0x5;u-boot-env raw 0x15 0x20"',
+'host bind 0 %s' % disk_img,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test02' in ''.join(output)
+
+# need to run uefi command to initiate capsule handling
+output = u_boot_console.run_command(
+'env print -e -all Capsule')
+
+output = u_boot_console.run_command_list([
+'host bind 0 %s' % disk_img,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test02' not in ''.join(output)
+
+output = u_boot_console.run_command_list([
+'sf probe 0:0',
+'sf read
[PATCH] MAINTAINERS, git-mailrc: Update sunxi maintainers
Maxime mentioned that he feels not having the time to be an Allwinner maintainer anymore. Take over from him. Maxime, many thanks for your great work in the past! I hope I can still relay the occasional technical question to you in the future. Cc: Maxime Ripard Signed-off-by: Andre Przywara --- MAINTAINERS| 2 +- doc/git-mailrc | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d9f80325f57..857e236aa42 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -462,7 +462,7 @@ F: arch/arm/include/asm/arch-stv0991/ ARM SUNXI M: Jagan Teki -M: Maxime Ripard +M: Andre Przywara S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git F: arch/arm/cpu/armv7/sunxi/ diff --git a/doc/git-mailrc b/doc/git-mailrc index bbca3a9a373..f520ff89b39 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -18,6 +18,7 @@ alias agraf Alexander Graf alias alexnemirovsky Alex Nemirovsky alias alisonwang Alison Wang alias angelo_ts Angelo Dureghello +alias apritzel Andre Przywara alias bmeng Bin Meng alias danielschwierzeck Daniel Schwierzeck alias dinh Dinh Nguyen @@ -36,7 +37,6 @@ alias marex Marek Vasut alias mariosix Mario Six alias masahiro Masahiro Yamada alias mateuszMateusz Kulikowski -alias maxime Maxime Ripard alias mbrugger Matthias Brugger alias monstr Michal Simek alias prom Minkyu Kang @@ -70,7 +70,7 @@ alias s5pc samsung alias samsunguboot, prom alias snapdragon uboot, mateusz alias socfpgauboot, marex, dinh, simongoldschmidt, leyfoon -alias sunxi uboot, jagan, maxime +alias sunxi uboot, jagan, apritzel alias tegra uboot, sjg, Tom Warren , Stephen Warren alias tegra2 tegra alias ti uboot, lokeshvutla -- 2.17.5
[RESEND PATCH v6 02/17] dfu: modify an argument type for an address
The range of an addressable pointer can go beyond 'integer'.
So change the argument type to a void pointer.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Heinrich Schuchardt
---
common/update.c | 3 ++-
drivers/dfu/dfu_alt.c | 6 +++---
include/dfu.h | 4 ++--
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/common/update.c b/common/update.c
index 39946776d74f..8dd6ee8b7ddb 100644
--- a/common/update.c
+++ b/common/update.c
@@ -324,7 +324,8 @@ got_update_file:
}
} else if (fit_image_check_type(fit, noffset,
IH_TYPE_FIRMWARE)) {
- ret = dfu_write_by_name(fit_image_name, update_addr,
+ ret = dfu_write_by_name(fit_image_name,
+ (void *)update_addr,
update_size, interface,
devstring);
if (ret)
diff --git a/drivers/dfu/dfu_alt.c b/drivers/dfu/dfu_alt.c
index 5b1b13d7170d..7528806cd163 100644
--- a/drivers/dfu/dfu_alt.c
+++ b/drivers/dfu/dfu_alt.c
@@ -23,14 +23,14 @@
*
* Return: 0 - on success, error code - otherwise
*/
-int dfu_write_by_name(char *dfu_entity_name, unsigned int addr,
+int dfu_write_by_name(char *dfu_entity_name, void *addr,
unsigned int len, char *interface, char *devstring)
{
char *s, *sb;
int alt_setting_num, ret;
struct dfu_entity *dfu;
- debug("%s: name: %s addr: 0x%x len: %d device: %s:%s\n", __func__,
+ debug("%s: name: %s addr: 0x%p len: %d device: %s:%s\n", __func__,
dfu_entity_name, addr, len, interface, devstring);
ret = dfu_init_env_entities(interface, devstring);
@@ -69,7 +69,7 @@ int dfu_write_by_name(char *dfu_entity_name, unsigned int
addr,
goto done;
}
- ret = dfu_write_from_mem_addr(dfu, (void *)(uintptr_t)addr, len);
+ ret = dfu_write_from_mem_addr(dfu, (void *)addr, len);
done:
dfu_free_entities();
diff --git a/include/dfu.h b/include/dfu.h
index cecfbd76597b..2299a83a3d94 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -507,10 +507,10 @@ static inline int dfu_fill_entity_virt(struct dfu_entity
*dfu, char *devstr,
* Return: 0 - on success, error code - otherwise
*/
#if CONFIG_IS_ENABLED(DFU_ALT)
-int dfu_write_by_name(char *dfu_entity_name, unsigned int addr,
+int dfu_write_by_name(char *dfu_entity_name, void *addr,
unsigned int len, char *interface, char *devstring);
#else
-static inline int dfu_write_by_name(char *dfu_entity_name, unsigned int addr,
+static inline int dfu_write_by_name(char *dfu_entity_name, void *addr,
unsigned int len, char *interface,
char *devstring)
{
--
2.28.0
[RESEND PATCH v6 03/17] common: update: add a generic interface for FIT image
The main purpose of this patch is to separate a generic interface for
updating firmware using DFU drivers from "auto-update" via tftp.
This function will also be used in implementing UEFI capsule update
in a later commit.
Signed-off-by: AKASHI Takahiro
---
common/Kconfig | 15 ++
common/Makefile | 3 +-
common/update.c | 71 +
drivers/dfu/Kconfig | 1 +
include/image.h | 12
5 files changed, 100 insertions(+), 2 deletions(-)
diff --git a/common/Kconfig b/common/Kconfig
index 318d372a481b..787d203d0aea 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -599,9 +599,15 @@ endmenu
menu "Update support"
+config UPDATE_COMMON
+ bool
+ default n
+ select DFU_ALT
+
config UPDATE_TFTP
bool "Auto-update using fitImage via TFTP"
depends on FIT
+ select UPDATE_COMMON
help
This option allows performing update of NOR with data in fitImage
sent via TFTP boot.
@@ -616,6 +622,15 @@ config UPDATE_TFTP_MSEC_MAX
default 100
depends on UPDATE_TFTP
+config UPDATE_FIT
+ bool "Firmware update using fitImage"
+ depends on FIT
+ depends on DFU
+ select UPDATE_COMMON
+ help
+ This option allows performing update of DFU-capable storage with
+ data in fitImage.
+
config ANDROID_AB
bool "Android A/B updates"
default n
diff --git a/common/Makefile b/common/Makefile
index 2e7a090588d9..bcf352d01652 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -53,8 +53,7 @@ obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o
obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
obj-$(CONFIG_LYNXKDI) += lynxkdi.o
obj-$(CONFIG_MENU) += menu.o
-obj-$(CONFIG_UPDATE_TFTP) += update.o
-obj-$(CONFIG_DFU_TFTP) += update.o
+obj-$(CONFIG_UPDATE_COMMON) += update.o
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
obj-$(CONFIG_CMDLINE) += cli_readline.o cli_simple.o
diff --git a/common/update.c b/common/update.c
index 8dd6ee8b7ddb..808be0880dfd 100644
--- a/common/update.c
+++ b/common/update.c
@@ -29,6 +29,7 @@
#include
#include
+#ifdef CONFIG_DFU_TFTP
/* env variable holding the location of the update file */
#define UPDATE_FILE_ENV"updatefile"
@@ -98,6 +99,7 @@ static int update_load(char *filename, ulong msec_max, int
cnt_max, ulong addr)
return rv;
}
+#endif /* CONFIG_DFU_TFTP */
#ifdef CONFIG_MTD_NOR_FLASH
static int update_flash_protect(int prot, ulong addr_first, ulong addr_last)
@@ -231,6 +233,7 @@ static int update_fit_getparams(const void *fit, int
noffset, ulong *addr,
return 0;
}
+#ifdef CONFIG_DFU_TFTP
int update_tftp(ulong addr, char *interface, char *devstring)
{
char *filename, *env_addr, *fit_image_name;
@@ -337,3 +340,71 @@ next_node:
return ret;
}
+#endif /* CONFIG_DFU_UPDATE */
+
+#ifdef CONFIG_UPDATE_FIT
+/**
+ * fit_update - update storage with FIT image
+ * @fit: Pointer to FIT image
+ *
+ * Update firmware on storage using FIT image as input.
+ * The storage area to be update will be identified by the name
+ * in FIT and matching it to "dfu_alt_info" variable.
+ *
+ * Return: 0 - on success, non-zero - otherwise
+ */
+int fit_update(const void *fit)
+{
+ char *fit_image_name;
+ ulong update_addr, update_fladdr, update_size;
+ int images_noffset, ndepth, noffset;
+ int ret = 0;
+
+ if (!fit)
+ return -EINVAL;
+
+ if (!fit_check_format((void *)fit)) {
+ printf("Bad FIT format of the update file, aborting
auto-update\n");
+ return -EINVAL;
+ }
+
+ /* process updates */
+ images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+
+ ndepth = 0;
+ noffset = fdt_next_node(fit, images_noffset, );
+ while (noffset >= 0 && ndepth > 0) {
+ if (ndepth != 1)
+ goto next_node;
+
+ fit_image_name = (char *)fit_get_name(fit, noffset, NULL);
+ printf("Processing update '%s' :", fit_image_name);
+
+ if (!fit_image_verify(fit, noffset)) {
+ printf("Error: invalid update hash, aborting\n");
+ ret = 1;
+ goto next_node;
+ }
+
+ printf("\n");
+ if (update_fit_getparams(fit, noffset, _addr,
+_fladdr, _size)) {
+ printf("Error: can't get update parameters,
aborting\n");
+ ret = 1;
+ goto next_node;
+ }
+
+ if (fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE)) {
+ ret = dfu_write_by_name(fit_image_name,
+ (void *)update_addr,
+ update_size, NULL, NULL);
+ if (ret)
+
[RESEND PATCH v6 01/17] dfu: rename dfu_tftp_write() to dfu_write_by_name()
This function is essentially independent from tftp, and will also be
utilised in implementing UEFI capsule update in a later commit.
So just give it a more generic name.
In addition, a new configuration option, CONFIG_DFU_ALT, was introduced
so that the file will be compiled with different options, particularly
one added in a later commit.
Signed-off-by: AKASHI Takahiro
---
common/update.c | 5 +++--
drivers/dfu/Kconfig | 5 +
drivers/dfu/Makefile | 2 +-
drivers/dfu/{dfu_tftp.c => dfu_alt.c} | 17 --
include/dfu.h | 32 +--
5 files changed, 40 insertions(+), 21 deletions(-)
rename drivers/dfu/{dfu_tftp.c => dfu_alt.c} (67%)
diff --git a/common/update.c b/common/update.c
index 36b6b7523d50..39946776d74f 100644
--- a/common/update.c
+++ b/common/update.c
@@ -324,8 +324,9 @@ got_update_file:
}
} else if (fit_image_check_type(fit, noffset,
IH_TYPE_FIRMWARE)) {
- ret = dfu_tftp_write(fit_image_name, update_addr,
-update_size, interface, devstring);
+ ret = dfu_write_by_name(fit_image_name, update_addr,
+ update_size, interface,
+ devstring);
if (ret)
return ret;
}
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 0eec00ba734d..78f901ff348a 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -14,8 +14,13 @@ config DFU_OVER_TFTP
depends on NET
if DFU
+config DFU_ALT
+ bool
+ default n
+
config DFU_TFTP
bool "DFU via TFTP"
+ select DFU_ALT
select DFU_OVER_TFTP
help
This option allows performing update of DFU-managed medium with data
diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile
index 0d7925c083ef..cc7de1d3ed9b 100644
--- a/drivers/dfu/Makefile
+++ b/drivers/dfu/Makefile
@@ -9,5 +9,5 @@ obj-$(CONFIG_$(SPL_)DFU_MTD) += dfu_mtd.o
obj-$(CONFIG_$(SPL_)DFU_NAND) += dfu_nand.o
obj-$(CONFIG_$(SPL_)DFU_RAM) += dfu_ram.o
obj-$(CONFIG_$(SPL_)DFU_SF) += dfu_sf.o
-obj-$(CONFIG_$(SPL_)DFU_TFTP) += dfu_tftp.o
+obj-$(CONFIG_$(SPL_)DFU_ALT) += dfu_alt.o
obj-$(CONFIG_$(SPL_)DFU_VIRT) += dfu_virt.o
diff --git a/drivers/dfu/dfu_tftp.c b/drivers/dfu/dfu_alt.c
similarity index 67%
rename from drivers/dfu/dfu_tftp.c
rename to drivers/dfu/dfu_alt.c
index ffae4bb54f80..5b1b13d7170d 100644
--- a/drivers/dfu/dfu_tftp.c
+++ b/drivers/dfu/dfu_alt.c
@@ -10,8 +10,21 @@
#include
#include
-int dfu_tftp_write(char *dfu_entity_name, unsigned int addr, unsigned int len,
- char *interface, char *devstring)
+/**
+ * dfu_write_by_name() - write data to DFU medium
+ * @dfu_entity_name:Name of DFU entity to write
+ * @addr: Address of data buffer to write
+ * @len:Number of bytes
+ * @interface: Destination DFU medium (e.g. "mmc")
+ * @devstring: Instance number of destination DFU medium (e.g. "1")
+ *
+ * This function is storing data received on DFU supported medium which
+ * is specified by @dfu_entity_name.
+ *
+ * Return: 0 - on success, error code - otherwise
+ */
+int dfu_write_by_name(char *dfu_entity_name, unsigned int addr,
+ unsigned int len, char *interface, char *devstring)
{
char *s, *sb;
int alt_setting_num, ret;
diff --git a/include/dfu.h b/include/dfu.h
index 84abdc79acd1..cecfbd76597b 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -494,27 +494,27 @@ static inline int dfu_fill_entity_virt(struct dfu_entity
*dfu, char *devstr,
#endif
/**
- * dfu_tftp_write() - write TFTP data to DFU medium
+ * dfu_write_by_name() - write data to DFU medium
+ * @dfu_entity_name: Name of DFU entity to write
+ * @addr: Address of data buffer to write
+ * @len: Number of bytes
+ * @interface: Destination DFU medium (e.g. "mmc")
+ * @devstring: Instance number of destination DFU medium (e.g. "1")
*
- * This function is storing data received via TFTP on DFU supported medium.
+ * This function is storing data received on DFU supported medium which
+ * is specified by @dfu_entity_name.
*
- * @dfu_entity_name: name of DFU entity to write
- * @addr: address of data buffer to write
- * @len: number of bytes
- * @interface: destination DFU medium (e.g. "mmc")
- * @devstring: instance number of destination DFU medium (e.g. "1")
- *
- * Return: 0 on success, otherwise error code
+ * Return: 0 - on success, error code - otherwise
*/
-#if CONFIG_IS_ENABLED(DFU_TFTP)
-int dfu_tftp_write(char *dfu_entity_name, unsigned int addr, unsigned int len,
-
Re: [RESEND PATCH v6 00/17] efi_loader: add capsule update support
On Thu, Oct 29, 2020 at 09:59:12AM +0900, AKASHI Takahiro wrote: > Tom, > > On Wed, Oct 28, 2020 at 08:30:49PM -0400, Tom Rini wrote: > > On Thu, Oct 29, 2020 at 09:25:11AM +0900, AKASHI Takahiro wrote: > > > > > # > > > # This is a reminder. Nothing changed, but rebasing. > > > # > > > > Wasn't one of the outstanding requests to make the DFU related changes > > less intrusive and thus easier to review > > I don't know what you're talking about. > I believe that I have addressed all the comments made on DFU stuff. Please go back and re-read the v5 thread then. What you're doing today causes odroid, trats, trats2 and s5p_goni to fail to build now and I believe there was a suggestion what to do to fix that, previously. > > There used to be a prerequisite patch from Heinrich, but he decided > to drop it. Necessary modification was done in v5. > > > by someone (me) who is not the > > primary author of the DFU code but does want to unblock this overall > > series right here? > > So you can review DFU part now (or even against the original v6). > # Another minor issue: the name of file, dfu_alt.c > # It will never be a blocking factor of your review, though. > > The only outstanding issue is on make-virt-fs[1]. > Here, my standpoint is clear: Heinrich's patch. > It is the only solution as far as Heinrich does reject any other solution > using 'sudo' in python scripts. Which is I guess why the tests fail to run here: https://gitlab.denx.de/u-boot/u-boot/-/jobs/171480 and why I think I had suggested that you need to do some try/catch logic so that if one set of tools isn't available, the other set of tools will be used. -- Tom signature.asc Description: PGP signature
Re: [RESEND PATCH v6 00/17] efi_loader: add capsule update support
Tom, On Wed, Oct 28, 2020 at 11:22:29PM -0400, Tom Rini wrote: > On Thu, Oct 29, 2020 at 09:59:12AM +0900, AKASHI Takahiro wrote: > > Tom, > > > > On Wed, Oct 28, 2020 at 08:30:49PM -0400, Tom Rini wrote: > > > On Thu, Oct 29, 2020 at 09:25:11AM +0900, AKASHI Takahiro wrote: > > > > > > > # > > > > # This is a reminder. Nothing changed, but rebasing. > > > > # > > > > > > Wasn't one of the outstanding requests to make the DFU related changes > > > less intrusive and thus easier to review > > > > I don't know what you're talking about. > > I believe that I have addressed all the comments made on DFU stuff. > > Please go back and re-read the v5 thread then. What you're doing today > causes odroid, trats, trats2 and s5p_goni to fail to build now and I > believe there was a suggestion what to do to fix that, previously. > > > > > There used to be a prerequisite patch from Heinrich, but he decided > > to drop it. Necessary modification was done in v5. > > > > > by someone (me) who is not the > > > primary author of the DFU code but does want to unblock this overall > > > series right here? > > > > So you can review DFU part now (or even against the original v6). > > # Another minor issue: the name of file, dfu_alt.c > > # It will never be a blocking factor of your review, though. > > > > The only outstanding issue is on make-virt-fs[1]. > > Here, my standpoint is clear: Heinrich's patch. > > It is the only solution as far as Heinrich does reject any other solution > > using 'sudo' in python scripts. > > Which is I guess why the tests fail to run here: > https://gitlab.denx.de/u-boot/u-boot/-/jobs/171480 > and why I think I had suggested that you need to do some try/catch logic > so that if one set of tools isn't available, the other set of tools will > be used. I think you misunderstand my point. Whatever logic I add, Heinrich will reject that solution if it includes "sudo". As far as I can imagine, "sudo" is necessary to workaround the issue because we need some way to create a filesystem with partitions. Whether a tool, make-virt-fs in this case, is available or not doesn't matter. -Takahiro Akashi > -- > Tom
Re: [RESEND PATCH v6 00/17] efi_loader: add capsule update support
Tom, On Wed, Oct 28, 2020 at 08:30:49PM -0400, Tom Rini wrote: > On Thu, Oct 29, 2020 at 09:25:11AM +0900, AKASHI Takahiro wrote: > > > # > > # This is a reminder. Nothing changed, but rebasing. > > # > > Wasn't one of the outstanding requests to make the DFU related changes > less intrusive and thus easier to review I don't know what you're talking about. I believe that I have addressed all the comments made on DFU stuff. There used to be a prerequisite patch from Heinrich, but he decided to drop it. Necessary modification was done in v5. > by someone (me) who is not the > primary author of the DFU code but does want to unblock this overall > series right here? So you can review DFU part now (or even against the original v6). # Another minor issue: the name of file, dfu_alt.c # It will never be a blocking factor of your review, though. The only outstanding issue is on make-virt-fs[1]. Here, my standpoint is clear: Heinrich's patch. It is the only solution as far as Heinrich does reject any other solution using 'sudo' in python scripts. -Takahiro Akashi [1] https://lists.denx.de/pipermail/u-boot/2020-September/426250.html > -- > Tom
Re: Failed to make encrypt amlogic vim3
I found why failed. Discard this mail. Best Regards, Jaehoon Chung On 10/29/20 9:11 AM, Jaehoon Chung wrote: > Dear Neil > > I have a question about vim3 board. > When i have build with mainline u-boot, i have faced on below problem. > (I have referred to doc/board/amlogic/khadas-vim3.rst) > > > Do you know why failed like below? > > $fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin --output > fip/bl2.n.bin.sig > fip/aml_encrypt_g12b bl2sig fail[15208]! > > Best Regards, > Jaehoon Chung >
Re: [RESEND PATCH v6 00/17] efi_loader: add capsule update support
On Wed, Oct 28, 2020 at 11:22:29PM -0400, Tom Rini wrote: > On Thu, Oct 29, 2020 at 09:59:12AM +0900, AKASHI Takahiro wrote: > > Tom, > > > > On Wed, Oct 28, 2020 at 08:30:49PM -0400, Tom Rini wrote: > > > On Thu, Oct 29, 2020 at 09:25:11AM +0900, AKASHI Takahiro wrote: > > > > > > > # > > > > # This is a reminder. Nothing changed, but rebasing. > > > > # > > > > > > Wasn't one of the outstanding requests to make the DFU related changes > > > less intrusive and thus easier to review > > > > I don't know what you're talking about. > > I believe that I have addressed all the comments made on DFU stuff. > > Please go back and re-read the v5 thread then. What you're doing today > causes odroid, trats, trats2 and s5p_goni to fail to build now and I > believe there was a suggestion what to do to fix that, previously. Okay, I have missed it. Is this the reason that I have seen your review comments in more than one month? Anyhow, I will post v7 right after this. -Takahiro Akashi > > > > There used to be a prerequisite patch from Heinrich, but he decided > > to drop it. Necessary modification was done in v5. > > > > > by someone (me) who is not the > > > primary author of the DFU code but does want to unblock this overall > > > series right here? > > > > So you can review DFU part now (or even against the original v6). > > # Another minor issue: the name of file, dfu_alt.c > > # It will never be a blocking factor of your review, though. > > > > The only outstanding issue is on make-virt-fs[1]. > > Here, my standpoint is clear: Heinrich's patch. > > It is the only solution as far as Heinrich does reject any other solution > > using 'sudo' in python scripts. > > Which is I guess why the tests fail to run here: > https://gitlab.denx.de/u-boot/u-boot/-/jobs/171480 > and why I think I had suggested that you need to do some try/catch logic > so that if one set of tools isn't available, the other set of tools will > be used. > > -- > Tom
Re: [PATCH] imx: mx6cuboxi: Disable CONFIG_IMX_THERMAL
Hi Simon,
Adding Walter to Cc.
On Thu, Oct 29 2020, Simon Glass wrote:
> This feature is incompatble with of-platdata since it uses the
> U_BOOT_DEVICE() macro. With of-platdata the only devices permitted are
> those created by dtoc.
>
> Drop this option for now, until the driver can be corrected.
As I understand, of-platdata is only enabled in SPL. Is there a way to
limit imx_thermal drop to SPL? The thermal driver in not very useful in
SPL anyway, right?
Thanks,
baruch
> Signed-off-by: Simon Glass
> ---
>
> include/configs/mx6cuboxi.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
> index cfab9a7fc02..55717c77ab3 100644
> --- a/include/configs/mx6cuboxi.h
> +++ b/include/configs/mx6cuboxi.h
> @@ -13,8 +13,6 @@
>
> #include "imx6_spl.h"
>
> -#define CONFIG_IMX_THERMAL
> -
> #define CONFIG_SYS_MALLOC_LEN(10 * SZ_1M)
>
> /* MMC Configs */
--
~. .~ Tk Open Systems
=}ooO--U--Ooo{=
- bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
[PATCH v7 11/17] efi_loader: add firmware management protocol for FIT image
In this commit, a very simple firmware management protocol driver
is implemented. It will take a common FIT image firmware in a capsule
file and apply the data using dfu backend storage drivers via
update_fit() interface.
So "dfu_alt_info" variable should be properly set to specify a device
and location to be updated. Please read README.dfu.
Fit image is a common file format for firmware update on U-Boot, and
this protocol works neatly just as a wrapper for one.
Signed-off-by: AKASHI Takahiro
---
include/efi_api.h | 4 +
include/efi_loader.h | 2 +
lib/efi_loader/Kconfig| 11 ++
lib/efi_loader/Makefile | 1 +
lib/efi_loader/efi_capsule.c | 12 +-
lib/efi_loader/efi_firmware.c | 291 ++
6 files changed, 320 insertions(+), 1 deletion(-)
create mode 100644 lib/efi_loader/efi_firmware.c
diff --git a/include/efi_api.h b/include/efi_api.h
index 966bc6e590bf..071d0ba866c7 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -1849,6 +1849,10 @@ struct efi_signature_list {
EFI_GUID(0x86c77a67, 0x0b97, 0x4633, 0xa1, 0x87, \
0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7)
+#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID \
+ EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \
+0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47)
+
#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE0x0001
#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0002
#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED0x0004
diff --git a/include/efi_loader.h b/include/efi_loader.h
index b3b575f10c6a..de6d353de3b1 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -811,6 +811,8 @@ void efi_memcpy_runtime(void *dest, const void *src, size_t
n);
/* commonly used helper function */
u16 *efi_create_indexed_name(u16 *buffer, const u16 *name, unsigned int index);
+extern const struct efi_firmware_management_protocol efi_fmp_fit;
+
/* Capsule update */
efi_status_t EFIAPI efi_update_capsule(
struct efi_capsule_header **capsule_header_array,
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 6ae18a422071..94c1ad2af097 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -134,6 +134,17 @@ config EFI_CAPSULE_FIRMWARE_MANAGEMENT
Select this option if you want to enable capsule-based
firmware update using Firmware Management Protocol.
+config EFI_CAPSULE_FIRMWARE_FIT
+ bool "FMP driver for FIT image"
+ depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
+ depends on FIT
+ select UPDATE_FIT
+ select DFU
+ default n
+ help
+ Select this option if you want to enable firmware management protocol
+ driver for FIT image
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index c7d231f0e57d..23b1828b0fe0 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_bootmgr.o
obj-y += efi_boottime.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
+obj-$(CONFIG_EFI_CAPSULE_FIRMWARE_FIT) += efi_firmware.o
obj-y += efi_console.o
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 2015929e3708..a44f81daaee9 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -804,7 +804,17 @@ static void efi_capsule_scan_done(void)
*/
efi_status_t __weak arch_efi_load_capsule_drivers(void)
{
- return EFI_SUCCESS;
+ __maybe_unused efi_handle_t handle;
+ efi_status_t ret = EFI_SUCCESS;
+
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_FIT)) {
+ handle = NULL;
+ ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
+ , _guid_firmware_management_protocol,
+ _fmp_fit, NULL));
+ }
+
+ return ret;
}
/**
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
new file mode 100644
index ..4c395f4eb5d9
--- /dev/null
+++ b/lib/efi_loader/efi_firmware.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * EFI Firmware management protocol
+ *
+ * Copyright (c) 2020 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * This FIRMWARE_MANAGEMENT_PROTOCOL driver provides a firmware update
+ * method with existing FIT image format, and handles
+ * - multiple regions of firmware via DFU
+ * but doesn't support
+ * - versioning of firmware image
+ * - package information
+ */
+const efi_guid_t efi_firmware_image_type_uboot_fit =
+ EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
+
+/**
+ *
[PATCH v7 10/17] efi_loader: capsule: support firmware update
A capsule tagged with the guid, EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID,
is handled as a firmware update object.
What efi_update_capsule() basically does is to load any firmware management
protocol (or fmp) drivers contained in a capsule, find out an appropriate
fmp driver and then invoke its set_image() interface against each binary
in a capsule.
In this commit, however, loading drivers is not supported.
The result of applying a capsule is set to be stored in "Capsule"
variable, but its implementation is deferred to a fmp driver.
Signed-off-by: AKASHI Takahiro
---
include/efi_api.h| 129 +++
include/efi_loader.h | 2 +
lib/efi_loader/Kconfig | 8 ++
lib/efi_loader/efi_capsule.c | 238 ++-
lib/efi_loader/efi_setup.c | 4 +
5 files changed, 380 insertions(+), 1 deletion(-)
diff --git a/include/efi_api.h b/include/efi_api.h
index 7a2a087c60ed..966bc6e590bf 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -217,6 +217,9 @@ enum efi_reset_type {
#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE0x0002
#define CAPSULE_FLAGS_INITIATE_RESET 0x0004
+#define CAPSULE_SUPPORT_AUTHENTICATION 0x0001
+#define CAPSULE_SUPPORT_DEPENDENCY 0x0002
+
#define EFI_CAPSULE_REPORT_GUID \
EFI_GUID(0x39b68c46, 0xf7fb, 0x441b, 0xb6, 0xec, \
0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3)
@@ -225,6 +228,10 @@ enum efi_reset_type {
EFI_GUID(0xde9f0ec, 0x88b6, 0x428f, 0x97, 0x7a, \
0x25, 0x8f, 0x1d, 0xe, 0x5e, 0x72)
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
+ EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \
+0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a)
+
struct efi_capsule_header {
efi_guid_t capsule_guid;
u32 header_size;
@@ -253,6 +260,33 @@ struct efi_memory_range_capsule {
struct efi_memory_range memory_ranges[];
} __packed;
+struct efi_firmware_management_capsule_header {
+ u32 version;
+ u16 embedded_driver_count;
+ u16 payload_item_count;
+ u64 item_offset_list[];
+} __packed;
+
+struct efi_firmware_management_capsule_image_header {
+ u32 version;
+ efi_guid_t update_image_type_id;
+ u8 update_image_index;
+ u8 reserved[3];
+ u32 update_image_size;
+ u32 update_vendor_code_size;
+ u64 update_hardware_instance;
+ u64 image_capsule_support;
+} __packed;
+
+struct efi_capsule_result_variable_fmp {
+ u16 version;
+ u8 payload_index;
+ u8 update_image_index;
+ efi_guid_t update_image_type_id;
+ // u16 capsule_file_name[];
+ // u16 capsule_target[];
+} __packed;
+
#define EFI_RT_SUPPORTED_GET_TIME 0x0001
#define EFI_RT_SUPPORTED_SET_TIME 0x0002
#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004
@@ -1808,4 +1842,99 @@ struct efi_signature_list {
/* struct efi_signature_data signatures[...][signature_size]; */
} __attribute__((__packed__));
+/*
+ * Firmware management protocol
+ */
+#define EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID \
+ EFI_GUID(0x86c77a67, 0x0b97, 0x4633, 0xa1, 0x87, \
+0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7)
+
+#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE0x0001
+#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0002
+#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED0x0004
+#define IMAGE_ATTRIBUTE_IN_USE 0x0008
+#define IMAGE_ATTRIBUTE_UEFI_IMAGE 0x0010
+#define IMAGE_ATTRIBUTE_DEPENDENCY 0x0020
+
+#define IMAGE_COMPATIBILITY_CHECK_SUPPORTED0x0001
+
+#define IMAGE_UPDATABLE_VALID 0x0001
+#define IMAGE_UPDATABLE_INVALID0x0002
+#define IMAGE_UPDATABLE_INVALID_TYPE 0x0004
+#define IMAGE_UPDATABLE_INVALID_OLLD 0x0008
+#define IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE 0x0010
+
+#define PACKAGE_ATTRIBUTE_VERSION_UPDATABLE0x0001
+#define PACKAGE_ATTRIBUTE_RESET_REQUIRED 0x0002
+#define PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0004
+
+#define EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 4
+
+typedef struct efi_firmware_image_dependencies {
+ u8 dependencies[0];
+} efi_firmware_image_dep_t;
+
+struct efi_firmware_image_descriptor {
+ u8 image_index;
+ efi_guid_t image_type_id;
+ u64 image_id;
+ u16 *image_id_name;
+ u32 version;
+ u16 *version_name;
+ efi_uintn_t size;
+ u64 attributes_supported;
+ u64 attributes_setting;
+ u64 compatibilities;
+ u32 lowest_supported_image_version;
+ u32 last_attempt_version;
+ u32 last_attempt_status;
+ u64 hardware_instance;
+
[PATCH v7 09/17] efi_loader: capsule: add memory range capsule definitions
Memory range capsule gives us a way to notify that some memory regions
should be left untouched across the next reset.
See UEFI specification, section 8.5.3.
Since how we should handle this kind of capsule is totally up to
the system, no implementation will be added in this commit.
Signed-off-by: AKASHI Takahiro
---
include/efi_api.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/efi_api.h b/include/efi_api.h
index c128a0a66ce8..7a2a087c60ed 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -221,6 +221,10 @@ enum efi_reset_type {
EFI_GUID(0x39b68c46, 0xf7fb, 0x441b, 0xb6, 0xec, \
0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3)
+#define EFI_MEMORY_RANGE_CAPSULE_GUID \
+ EFI_GUID(0xde9f0ec, 0x88b6, 0x428f, 0x97, 0x7a, \
+0x25, 0x8f, 0x1d, 0xe, 0x5e, 0x72)
+
struct efi_capsule_header {
efi_guid_t capsule_guid;
u32 header_size;
@@ -236,6 +240,19 @@ struct efi_capsule_result_variable_header {
efi_status_t capsule_status;
} __packed;
+struct efi_memory_range {
+ efi_physical_addr_t address;
+ u64 length;
+};
+
+struct efi_memory_range_capsule {
+ struct efi_capsule_header *header;
+ /* EFI_MEMORY_TYPE: 0x8000-0x */
+ enum efi_mem_type os_requested_memory_type;
+ u64 number_of_memory_ranges;
+ struct efi_memory_range memory_ranges[];
+} __packed;
+
#define EFI_RT_SUPPORTED_GET_TIME 0x0001
#define EFI_RT_SUPPORTED_SET_TIME 0x0002
#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004
--
2.28.0
[PATCH v7 13/17] efi_loader: add firmware management protocol for raw image
In this commit, a very simple firmware management protocol driver
is implemented. It will take a binary image in a capsule file and
apply the data using dfu backend storage drivers via dfu_write_by_alt()
interface.
So "dfu_alt_info" variable should be properly set to specify a device
and location to be updated. Please read README.dfu.
Signed-off-by: AKASHI Takahiro
---
include/efi_api.h | 4 +
include/efi_loader.h | 1 +
lib/efi_loader/Kconfig| 16 +++
lib/efi_loader/Makefile | 2 +-
lib/efi_loader/efi_capsule.c | 8 ++
lib/efi_loader/efi_firmware.c | 226 +-
6 files changed, 199 insertions(+), 58 deletions(-)
diff --git a/include/efi_api.h b/include/efi_api.h
index 071d0ba866c7..c7038f863ab2 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -1853,6 +1853,10 @@ struct efi_signature_list {
EFI_GUID(0xae13ff2d, 0x9ad4, 0x4e25, 0x9a, 0xc8, \
0x6d, 0x80, 0xb3, 0xb2, 0x21, 0x47)
+#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \
+ EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \
+0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f)
+
#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE0x0001
#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0002
#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED0x0004
diff --git a/include/efi_loader.h b/include/efi_loader.h
index de6d353de3b1..0f85873a72f8 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -812,6 +812,7 @@ void efi_memcpy_runtime(void *dest, const void *src, size_t
n);
u16 *efi_create_indexed_name(u16 *buffer, const u16 *name, unsigned int index);
extern const struct efi_firmware_management_protocol efi_fmp_fit;
+extern const struct efi_firmware_management_protocol efi_fmp_raw;
/* Capsule update */
efi_status_t EFIAPI efi_update_capsule(
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 94c1ad2af097..25b4ef12000d 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -126,6 +126,10 @@ config EFI_CAPSULE_ON_DISK_EARLY
executed as part of U-Boot initialisation so that they will
surely take place whatever is set to distro_bootcmd.
+config EFI_CAPSULE_FIRMWARE
+ bool
+ default n
+
config EFI_CAPSULE_FIRMWARE_MANAGEMENT
bool "Capsule: Firmware Management Protocol"
depends on EFI_HAVE_CAPSULE_SUPPORT
@@ -140,11 +144,23 @@ config EFI_CAPSULE_FIRMWARE_FIT
depends on FIT
select UPDATE_FIT
select DFU
+ select EFI_CAPSULE_FIRMWARE
default n
help
Select this option if you want to enable firmware management protocol
driver for FIT image
+config EFI_CAPSULE_FIRMWARE_RAW
+ bool "FMP driver for raw image"
+ depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
+ select DFU
+ select DFU_WRITE_ALT
+ select EFI_CAPSULE_FIRMWARE
+ default n
+ help
+ Select this option if you want to enable firmware management protocol
+ driver for raw image
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 23b1828b0fe0..a7631d92a3b0 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_bootmgr.o
obj-y += efi_boottime.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
-obj-$(CONFIG_EFI_CAPSULE_FIRMWARE_FIT) += efi_firmware.o
+obj-$(CONFIG_EFI_CAPSULE_FIRMWARE) += efi_firmware.o
obj-y += efi_console.o
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index a44f81daaee9..af40b4a1599e 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -814,6 +814,14 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void)
_fmp_fit, NULL));
}
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) {
+ handle = NULL;
+ ret = EFI_CALL(efi_install_multiple_protocol_interfaces(
+ _root,
+ _guid_firmware_management_protocol,
+ _fmp_raw, NULL));
+ }
+
return ret;
}
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 4c395f4eb5d9..7e5607738319 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -13,16 +13,66 @@
#include
#include
-/*
- * This FIRMWARE_MANAGEMENT_PROTOCOL driver provides a firmware update
- * method with existing FIT image format, and handles
- * - multiple regions of firmware via DFU
- * but doesn't support
- * - versioning of firmware image
- * - package information
- */
-const efi_guid_t
[PATCH v7 14/17] cmd: add "efidebug capsule" command
"efidebug capsule" is more or less a debugging utility.
efidebug capsule update: invoke UpdateCapsule against data on memory
efidebug capsule show: show a capsule header
efidebug capsule result: dump a capsule result variable
Signed-off-by: AKASHI Takahiro
---
cmd/efidebug.c | 235 +
1 file changed, 235 insertions(+)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 5288b9920b4d..7d327c82681f 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -19,6 +19,228 @@
#include
#define BS systab.boottime
+#define RT systab.runtime
+
+#ifdef CONFIG_EFI_HAVE_CAPSULE_SUPPORT
+/**
+ * do_efi_capsule_update() - process a capsule update
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "capsule update" sub-command.
+ * process a capsule update.
+ *
+ * efidebug capsule update [-v]
+ */
+static int do_efi_capsule_update(struct cmd_tbl *cmdtp, int flag,
+int argc, char * const argv[])
+{
+ struct efi_capsule_header *capsule;
+ int verbose = 0;
+ char *endp;
+ efi_status_t ret;
+
+ if (argc != 2 && argc != 3)
+ return CMD_RET_USAGE;
+
+ if (argc == 3) {
+ if (strcmp(argv[1], "-v"))
+ return CMD_RET_USAGE;
+
+ verbose = 1;
+ argc--;
+ argv++;
+ }
+
+ capsule = (typeof(capsule))simple_strtoul(argv[1], , 16);
+ if (endp == argv[1]) {
+ printf("Invalid address: %s", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ if (verbose) {
+ printf("Capsule guid: %pUl\n", >capsule_guid);
+ printf("Capsule flags: 0x%x\n", capsule->flags);
+ printf("Capsule header size: 0x%x\n", capsule->header_size);
+ printf("Capsule image size: 0x%x\n",
+ capsule->capsule_image_size);
+ }
+
+ ret = EFI_CALL(RT->update_capsule(, 1, (u64)NULL));
+ if (ret) {
+ printf("Cannot handle a capsule at %p", capsule);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_efi_capsule_show() - show capsule information
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "capsule show" sub-command.
+ * show capsule information.
+ *
+ * efidebug capsule show
+ */
+static int do_efi_capsule_show(struct cmd_tbl *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct efi_capsule_header *capsule;
+ char *endp;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ capsule = (typeof(capsule))simple_strtoul(argv[1], , 16);
+ if (endp == argv[1]) {
+ printf("Invalid address: %s", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Capsule guid: %pUl\n", >capsule_guid);
+ printf("Capsule flags: 0x%x\n", capsule->flags);
+ printf("Capsule header size: 0x%x\n", capsule->header_size);
+ printf("Capsule image size: 0x%x\n",
+ capsule->capsule_image_size);
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_efi_capsule_res() - show a capsule update result
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "capsule result" sub-command.
+ * show a capsule update result.
+ * If result number is not specified, CapsuleLast will be shown.
+ *
+ * efidebug capsule result []
+ */
+static int do_efi_capsule_res(struct cmd_tbl *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int capsule_id;
+ char *endp;
+ char var_name[12];
+ u16 var_name16[12], *p;
+ efi_guid_t guid;
+ struct efi_capsule_result_variable_header *result = NULL;
+ efi_uintn_t size;
+ efi_status_t ret;
+
+ if (argc != 1 && argc != 2)
+ return CMD_RET_USAGE;
+
+ guid = efi_guid_capsule_report;
+ if (argc == 1) {
+ size = sizeof(var_name16);
+ ret = EFI_CALL(RT->get_variable(L"CapsuleLast", , NULL,
+ , var_name16));
+ if (ret != EFI_SUCCESS) {
+ if (ret == EFI_NOT_FOUND)
+ printf("CapsuleLast doesn't exist\n");
+ else
+ printf("Failed to get CapsuleLast\n");
+
+ return CMD_RET_FAILURE;
+
[PATCH v7 16/17] test/py: efi_capsule: test for FIT image capsule
The test can run on sandbox build and it attempts to execute a firmware
update via a capsule-on-disk, using a FIT image capsule,
CONFIG_EFI_CAPSULE_FIT.
To run this test successfully, you need configure U-Boot specifically;
See test_capsule_firmware.py for requirements, and hence it won't run
on Travis CI, at least, for now.
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_capsule/conftest.py| 69 +++
test/py/tests/test_efi_capsule/defs.py| 12 ++
.../test_efi_capsule/test_capsule_firmware.py | 178 ++
.../tests/test_efi_capsule/uboot_bin_env.its | 36
tools/mkeficapsule.c | 3 +-
5 files changed, 297 insertions(+), 1 deletion(-)
create mode 100644 test/py/tests/test_efi_capsule/conftest.py
create mode 100644 test/py/tests/test_efi_capsule/defs.py
create mode 100644 test/py/tests/test_efi_capsule/test_capsule_firmware.py
create mode 100644 test/py/tests/test_efi_capsule/uboot_bin_env.its
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
new file mode 100644
index ..4e7c36f04ba5
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2020, Linaro Limited
+# Author: AKASHI Takahiro
+
+import os
+import os.path
+import re
+from subprocess import call, check_call, check_output, CalledProcessError
+import pytest
+from defs import *
+
+#
+# Fixture for UEFI secure boot test
+#
+
+
+@pytest.fixture(scope='session')
+def efi_capsule_data(request, u_boot_config):
+"""Set up a file system to be used in UEFI capsule test.
+
+Args:
+request: Pytest request object.
+u_boot_config: U-boot configuration.
+
+Return:
+A path to disk image to be used for testing
+"""
+mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
+data_dir = mnt_point + CAPSULE_DATA_DIR
+install_dir = mnt_point + CAPSULE_INSTALL_DIR
+image_path = u_boot_config.persistent_data_dir + '/test_efi_capsule.img'
+
+try:
+# Create a target device
+check_call('dd if=/dev/zero of=./spi.bin bs=1MiB count=16', shell=True)
+
+check_call('rm -rf %s' % mnt_point, shell=True)
+check_call('mkdir -p %s' % data_dir, shell=True)
+check_call('mkdir -p %s' % install_dir, shell=True)
+
+# Create capsule files
+# two regions: one for u-boot.bin and the other for u-boot.env
+check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n
u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old -> u-boot.env.old; echo -n
u-boot-env:New > u-boot.env.new' % data_dir,
+ shell=True)
+check_call('sed -e \"s?BINFILE1?u-boot.bin.new?\" -e
\"s?BINFILE2?u-boot.env.new?\"
%s/test/py/tests/test_efi_capsule/uboot_bin_env.its > %s/uboot_bin_env.its' %
+ (u_boot_config.source_dir, data_dir),
+ shell=True)
+check_call('cd %s; %s/tools/mkimage -f uboot_bin_env.its
uboot_bin_env.itb' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --fit uboot_bin_env.itb
--version 1 --index 1 Test01' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+
+# Create a disk image with EFI system partition
+check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s'
%
+ (mnt_point, image_path), shell=True)
+check_call('sgdisk %s -A 1:set:0 -t
1:C12A7328-F81F-11D2-BA4B-00A0C93EC93B' %
+ image_path, shell=True)
+
+except CalledProcessError as exception:
+pytest.skip('Setup failed: %s' % exception.cmd)
+return
+else:
+yield image_path
+finally:
+call('rm -rf %s' % mnt_point, shell=True)
+call('rm -f %s' % image_path, shell=True)
+call('rm -f ./spi.bin', shell=True)
diff --git a/test/py/tests/test_efi_capsule/defs.py
b/test/py/tests/test_efi_capsule/defs.py
new file mode 100644
index ..2c5b0ee49beb
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/defs.py
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+# Size in MiB
+EFI_BOOTDEV_IMAGE_SIZE = 16
+EFI_BOOTDEV_PART_SIZE = 8
+
+# Owner guid
+GUID = '----123456789abc'
+
+# Directories
+CAPSULE_DATA_DIR = '/EFI/CapsuleTestData'
+CAPSULE_INSTALL_DIR = '/EFI/UpdateCapsule'
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
new file mode 100644
index ..ab7c2a7d6bea
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2020, Linaro Limited
+# Author: AKASHI Takahiro
+#
+# U-Boot UEFI: Firmware Update Test
+
+"""
+This test verifies capsule-on-disk
[PATCH v7 15/17] tools: add mkeficapsule command for UEFI capsule update
This is a utility mainly for test purpose.
mkeficapsule -f: create a test capsule file for FIT image firmware
Having said that, you will be able to customize the code to fit
your specific requirements for your platform.
Signed-off-by: AKASHI Takahiro
---
tools/Makefile | 2 +
tools/mkeficapsule.c | 238 +++
2 files changed, 240 insertions(+)
create mode 100644 tools/mkeficapsule.c
diff --git a/tools/Makefile b/tools/Makefile
index 51123fd92983..66d9376803e3 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -218,6 +218,8 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs
hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler
HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
+hostprogs-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += mkeficapsule
+
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
# exceptions for files that aren't complaint.
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
new file mode 100644
index ..db95426457cc
--- /dev/null
+++ b/tools/mkeficapsule.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+typedef __u8 u8;
+typedef __u16 u16;
+typedef __u32 u32;
+typedef __u64 u64;
+typedef __s16 s16;
+typedef __s32 s32;
+
+#define aligned_u64 __aligned_u64
+
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+#include
+#include
+
+static const char *tool_name = "mkeficapsule";
+
+efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
+efi_guid_t efi_guid_image_type_uboot_fit =
+ EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
+efi_guid_t efi_guid_image_type_uboot_raw =
+ EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID;
+
+static struct option options[] = {
+ {"fit", required_argument, NULL, 'f'},
+ {"raw", required_argument, NULL, 'r'},
+ {"index", required_argument, NULL, 'i'},
+ {"instance", required_argument, NULL, 'I'},
+ {"version", required_argument, NULL, 'v'},
+ {"help", no_argument, NULL, 'h'},
+ {NULL, 0, NULL, 0},
+};
+
+static void print_usage(void)
+{
+ printf("Usage: %s [options] \n"
+ "Options:\n"
+ "\t--fit new FIT image file\n"
+ "\t--raw new raw image file\n"
+ "\t--index update image index\n"
+ "\t--instance update hardware instance\n"
+ "\t--version firmware version\n"
+ "\t--help print a help message\n",
+ tool_name);
+}
+
+static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
+ unsigned long version, unsigned long index,
+ unsigned long instance)
+{
+ struct efi_capsule_header header;
+ struct efi_firmware_management_capsule_header capsule;
+ struct efi_firmware_management_capsule_image_header image;
+ FILE *f, *g;
+ struct stat bin_stat;
+ u8 *data;
+ size_t size;
+
+#ifdef DEBUG
+ printf("For output: %s\n", path);
+ printf("\tbin: %s\n\ttype: %pUl\n" bin, guid);
+ printf("\tversion: %ld\n\tindex: %ld\n\tinstance: %ld\n",
+ version, index, instance);
+#endif
+
+ g = fopen(bin, "r");
+ if (!g) {
+ printf("cannot open %s\n", bin);
+ return -1;
+ }
+ if (stat(bin, _stat) < 0) {
+ printf("cannot determine the size of %s\n", bin);
+ goto err_1;
+ }
+ data = malloc(bin_stat.st_size);
+ if (!data) {
+ printf("cannot allocate memory: %lx\n", bin_stat.st_size);
+ goto err_1;
+ }
+ f = fopen(path, "w");
+ if (!f) {
+ printf("cannot open %s\n", path);
+ goto err_2;
+ }
+ header.capsule_guid = efi_guid_fm_capsule;
+ header.header_size = sizeof(header);
+ header.flags = CAPSULE_FLAGS_PERSIST_ACROSS_RESET; /* TODO */
+ header.capsule_image_size = sizeof(header)
+ + sizeof(capsule) + sizeof(u64)
+ + sizeof(image)
+ + bin_stat.st_size;
+
+ size = fwrite(, 1, sizeof(header), f);
+ if (size < sizeof(header)) {
+ printf("write failed (%lx)\n", size);
+ goto err_3;
+ }
+
+ capsule.version = 0x0001;
+ capsule.embedded_driver_count = 0;
+ capsule.payload_item_count = 1;
+ capsule.item_offset_list[0] = sizeof(capsule) + sizeof(u64);
+ size = fwrite(, 1, sizeof(capsule) + sizeof(u64), f);
+ if (size < (sizeof(capsule) + sizeof(u64))) {
+ printf("write failed
[PATCH v7 17/17] test/py: efi_capsule: test for raw image capsule
The test can run on sandbox build and it attempts to execute a firmware
update via a capsule-on-disk, using a raw image capsule,
CONFIG_EFI_CAPSULE_RAW.
To run this test successfully, you need configure U-Boot specifically;
See test_capsule_firmware.py for requirements, and hence it won't run
on Travis CI, at least, for now.
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_capsule/conftest.py| 3 +
.../test_efi_capsule/test_capsule_firmware.py | 63 +++
2 files changed, 66 insertions(+)
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index 4e7c36f04ba5..4544a24d5351 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -51,6 +51,9 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkeficapsule --fit uboot_bin_env.itb
--version 1 --index 1 Test01' %
(data_dir, u_boot_config.build_dir),
shell=True)
+check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new
--version 1 --index 1 Test02' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
# Create a disk image with EFI system partition
check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s'
%
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
index ab7c2a7d6bea..c9b180ac65e8 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware.py
@@ -15,6 +15,7 @@ from defs import *
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('efi_capsule_firmware_fit')
+@pytest.mark.buildconfigspec('efi_capsule_firmware_raw')
@pytest.mark.buildconfigspec('efi_capsule_on_disk')
@pytest.mark.buildconfigspec('dfu')
@pytest.mark.buildconfigspec('dfu_sf')
@@ -176,3 +177,65 @@ class TestEfiCapsuleFirmwareFit(object):
'sf read 400 15 10',
'md.b 400 10'])
assert 'u-boot-env:New' in ''.join(output)
+
+def test_efi_capsule_fw3(
+self, u_boot_config, u_boot_console, efi_capsule_data):
+"""
+Test Case 3 - Update U-Boot on SPI Flash, raw image format
+ 0x10-0x15: U-Boot binary (but dummy)
+"""
+disk_img = efi_capsule_data
+with u_boot_console.log.section('Test Case 3-a, before reboot'):
+output = u_boot_console.run_command_list([
+'host bind 0 %s' % disk_img,
+'efidebug boot add 1 TEST host 0:1 /helloworld.efi ""',
+'efidebug boot order 1',
+'env set -e -nv -bs -rt OsIndications =0x0004',
+'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x10
0x5;u-boot-env raw 0x15 0x20"',
+'env save'])
+
+# initialize content
+output = u_boot_console.run_command_list([
+'sf probe 0:0',
+'fatload host 0:1 400 %s/u-boot.bin.old' %
CAPSULE_DATA_DIR,
+'sf write 400 10 10',
+'sf read 500 10 10',
+'md.b 500 10'])
+assert 'Old' in ''.join(output)
+
+# place a capsule file
+output = u_boot_console.run_command_list([
+'fatload host 0:1 400 %s/Test02' % CAPSULE_DATA_DIR,
+'fatwrite host 0:1 400 %s/Test02 $filesize' %
CAPSULE_INSTALL_DIR,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test02' in ''.join(output)
+
+# reboot
+u_boot_console.restart_uboot()
+
+capsule_early = u_boot_config.buildconfig.get(
+'config_efi_capsule_on_disk_early')
+with u_boot_console.log.section('Test Case 3-b, after reboot'):
+if not capsule_early:
+# make sure that dfu_alt_info exists even persistent variables
+# are not available.
+output = u_boot_console.run_command_list([
+'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x10
0x5;u-boot-env raw 0x15 0x20"',
+'host bind 0 %s' % disk_img,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test02' in ''.join(output)
+
+# need to run uefi command to initiate capsule handling
+output = u_boot_console.run_command(
+'env print -e -all Capsule')
+
+output = u_boot_console.run_command_list([
+'host bind 0 %s' % disk_img,
+'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR])
+assert 'Test02' not in ''.join(output)
+
+output = u_boot_console.run_command_list([
+'sf probe 0:0',
+'sf read
[PATCH v7 12/17] dfu: add dfu_write_by_alt()
This function is a variant of dfu_write_by_name() and takes a DFU alt
setting number for dfu configuration.
It will be utilised to implement UEFI capsule management protocol for
raw image in a later commit.
Signed-off-by: AKASHI Takahiro
---
drivers/dfu/dfu_alt.c | 47 +++
include/dfu.h | 26 +++-
2 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu_alt.c b/drivers/dfu/dfu_alt.c
index 7528806cd163..d5827812070c 100644
--- a/drivers/dfu/dfu_alt.c
+++ b/drivers/dfu/dfu_alt.c
@@ -76,3 +76,50 @@ done:
return ret;
}
+
+/**
+ * dfu_write_by_alt() - write data to DFU medium
+ * @dfu_alt_num:DFU alt setting number
+ * @addr: Address of data buffer to write
+ * @len:Number of bytes
+ * @interface: Destination DFU medium (e.g. "mmc")
+ * @devstring: Instance number of destination DFU medium (e.g. "1")
+ *
+ * This function is storing data received on DFU supported medium which
+ * is specified by @dfu_alt_name.
+ *
+ * Return: 0 - on success, error code - otherwise
+ */
+int dfu_write_by_alt(int dfu_alt_num, void *addr, unsigned int len,
+char *interface, char *devstring)
+{
+ struct dfu_entity *dfu;
+ int ret;
+
+ debug("%s: alt: %d addr: 0x%p len: %d device: %s:%s\n", __func__,
+ dfu_alt_num, addr, len, interface, devstring);
+
+ ret = dfu_init_env_entities(interface, devstring);
+ if (ret)
+ goto done;
+
+ if (dfu_alt_num < 0) {
+ pr_err("Invalid alt number: %d", dfu_alt_num);
+ ret = -ENODEV;
+ goto done;
+ }
+
+ dfu = dfu_get_entity(dfu_alt_num);
+ if (!dfu) {
+ pr_err("DFU entity for alt: %d not found!", dfu_alt_num);
+ ret = -ENODEV;
+ goto done;
+ }
+
+ ret = dfu_write_from_mem_addr(dfu, (void *)(uintptr_t)addr, len);
+
+done:
+ dfu_free_entities();
+
+ return ret;
+}
diff --git a/include/dfu.h b/include/dfu.h
index eaf4bfc0d5ed..a767adee4107 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -496,6 +496,7 @@ static inline int dfu_fill_entity_virt(struct dfu_entity
*dfu, char *devstr,
}
#endif
+#if CONFIG_IS_ENABLED(DFU_WRITE_ALT)
/**
* dfu_write_by_name() - write data to DFU medium
* @dfu_entity_name: Name of DFU entity to write
@@ -509,9 +510,24 @@ static inline int dfu_fill_entity_virt(struct dfu_entity
*dfu, char *devstr,
*
* Return: 0 - on success, error code - otherwise
*/
-#if CONFIG_IS_ENABLED(DFU_WRITE_ALT)
int dfu_write_by_name(char *dfu_entity_name, void *addr,
unsigned int len, char *interface, char *devstring);
+
+/**
+ * dfu_write_by_alt() - write data to DFU medium
+ * @dfu_alt_num: DFU alt setting number
+ * @addr: Address of data buffer to write
+ * @len: Number of bytes
+ * @interface: Destination DFU medium (e.g. "mmc")
+ * @devstring: Instance number of destination DFU medium (e.g. "1")
+ *
+ * This function is storing data received on DFU supported medium which
+ * is specified by @dfu_alt_name.
+ *
+ * Return: 0 - on success, error code - otherwise
+ */
+int dfu_write_by_alt(int dfu_alt_num, void *addr, unsigned int len,
+char *interface, char *devstring);
#else
static inline int dfu_write_by_name(char *dfu_entity_name, void *addr,
unsigned int len, char *interface,
@@ -520,6 +536,14 @@ static inline int dfu_write_by_name(char *dfu_entity_name,
void *addr,
puts("write support for DFU not available!\n");
return -ENOSYS;
}
+
+static inline int dfu_write_by_alt(int dfu_alt_num, void *addr,
+ unsigned int len, char *interface,
+ char *devstring)
+{
+ puts("write support for DFU not available!\n");
+ return -ENOSYS;
+}
#endif
int dfu_add(struct usb_configuration *c);
--
2.28.0
[PATCH v7 08/17] efi_loader: capsule: add capsule_on_disk support
Capsule data can be loaded into the system either via UpdateCapsule
runtime service or files on a file system (of boot device).
The latter case is called "capsules on disk", and actual updates will
take place at the next boot time.
In this commit, we will support capsule on disk mechanism.
Please note that U-Boot itself has no notion of "boot device" and
all the capsule files to be executed will be detected only if they
are located in a specific directory, \EFI\UpdateCapsule, on a device
that is identified as a boot device by "Boot" variables.
Signed-off-by: AKASHI Takahiro
---
common/main.c| 4 +
include/efi_loader.h | 9 +
lib/efi_loader/Kconfig | 22 ++
lib/efi_loader/efi_capsule.c | 498 +++
lib/efi_loader/efi_setup.c | 8 +
5 files changed, 541 insertions(+)
diff --git a/common/main.c b/common/main.c
index 4b3cd302c3e2..ae5bcdb32f8b 100644
--- a/common/main.c
+++ b/common/main.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
static void run_preboot_environment_command(void)
{
@@ -53,6 +54,9 @@ void main_loop(void)
if (IS_ENABLED(CONFIG_UPDATE_TFTP))
update_tftp(0UL, NULL, NULL);
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_ON_DISK_EARLY))
+ efi_launch_capsules();
+
s = bootdelay_process();
if (cli_process_fdt())
cli_secure_boot_cmd(s);
diff --git a/include/efi_loader.h b/include/efi_loader.h
index ffe772866675..572cfadd491a 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -820,6 +820,11 @@ efi_status_t EFIAPI efi_query_capsule_caps(
u64 *maximum_capsule_size,
u32 *reset_type);
+#define EFI_CAPSULE_DIR L"\\EFI\\UpdateCapsule\\"
+
+/* Hook at initialization */
+efi_status_t efi_launch_capsules(void);
+
#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
@@ -836,6 +841,10 @@ static inline void efi_set_bootdev(const char *dev, const
char *devnr,
const char *path) { }
static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
static inline void efi_print_image_infos(void *pc) { }
+static inline efi_status_t efi_launch_capsules(void)
+{
+ return EFI_SUCCESS;
+}
#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 3ca396df3646..a2a015225a10 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -104,6 +104,28 @@ config EFI_RUNTIME_UPDATE_CAPSULE
Select this option if you want to use UpdateCapsule and
QueryCapsuleCapabilities API's.
+config EFI_CAPSULE_ON_DISK
+ bool "Enable capsule-on-disk support"
+ select EFI_HAVE_CAPSULE_SUPPORT
+ default n
+ help
+ Select this option if you want to use capsule-on-disk feature,
+ that is, capsules can be fetched and executed from files
+ under a specific directory on UEFI system partition instead of
+ via UpdateCapsule API.
+
+config EFI_CAPSULE_ON_DISK_EARLY
+ bool "Initiate capsule-on-disk at U-Boot boottime"
+ depends on EFI_CAPSULE_ON_DISK
+ default y
+ select EFI_SETUP_EARLY
+ help
+ Normally, without this option enabled, capsules will be
+ executed only at the first time of invoking one of efi command.
+ If this option is enabled, capsules will be enforced to be
+ executed as part of U-Boot initialisation so that they will
+ surely take place whatever is set to distro_bootcmd.
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 02a8435cd3d1..2259bfbf3d19 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -11,10 +11,16 @@
#include
#include
#include
+#include
#include
const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
+#ifdef CONFIG_EFI_CAPSULE_ON_DISK
+/* for file system access */
+static struct efi_file_handle *bootdev_root;
+#endif
+
/**
* get_last_capsule - get the last capsule index
*
@@ -163,3 +169,495 @@ efi_status_t EFIAPI efi_query_capsule_caps(
out:
return EFI_EXIT(ret);
}
+
+#ifdef CONFIG_EFI_CAPSULE_ON_DISK
+/**
+ * get_dp_device - retrieve a device path from boot variable
+ * @boot_var: Boot variable name
+ * @device_dp Device path
+ *
+ * Retrieve a device patch from boot variable, @boot_var.
+ *
+ * Return: status code
+ */
+static efi_status_t get_dp_device(u16 *boot_var,
+ struct efi_device_path **device_dp)
+{
+ void *buf = NULL;
+ efi_uintn_t size;
+ struct efi_load_option lo;
+ struct efi_device_path *file_dp;
+ efi_status_t ret;
+
+ size = 0;
+ ret = efi_get_variable_int(boot_var, _global_variable_guid,
+
[PATCH v7 07/17] efi_loader: define UpdateCapsule api
In this commit, skeleton functions for capsule-related API's are
added under CONFIG_EFI_UPDATE_CAPSULE configuration.
Detailed implementation for a specific capsule type will be added
in the succeeding patches.
Signed-off-by: AKASHI Takahiro
---
include/efi_api.h| 12 +++
include/efi_loader.h | 13 +++
lib/efi_loader/Kconfig | 11 +++
lib/efi_loader/Makefile | 1 +
lib/efi_loader/efi_capsule.c | 165 +++
lib/efi_loader/efi_runtime.c | 104 --
lib/efi_loader/efi_setup.c | 64 +++---
7 files changed, 316 insertions(+), 54 deletions(-)
create mode 100644 lib/efi_loader/efi_capsule.c
diff --git a/include/efi_api.h b/include/efi_api.h
index 5744f6aed86d..c128a0a66ce8 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -217,6 +217,10 @@ enum efi_reset_type {
#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE0x0002
#define CAPSULE_FLAGS_INITIATE_RESET 0x0004
+#define EFI_CAPSULE_REPORT_GUID \
+ EFI_GUID(0x39b68c46, 0xf7fb, 0x441b, 0xb6, 0xec, \
+0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3)
+
struct efi_capsule_header {
efi_guid_t capsule_guid;
u32 header_size;
@@ -224,6 +228,14 @@ struct efi_capsule_header {
u32 capsule_image_size;
} __packed;
+struct efi_capsule_result_variable_header {
+ u32 variable_total_size;
+ u32 reserved;
+ efi_guid_t capsule_guid;
+ struct efi_time capsule_processed;
+ efi_status_t capsule_status;
+} __packed;
+
#define EFI_RT_SUPPORTED_GET_TIME 0x0001
#define EFI_RT_SUPPORTED_SET_TIME 0x0002
#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 6865a4847d53..ffe772866675 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -207,6 +207,8 @@ extern const efi_guid_t efi_guid_cert_type_pkcs7;
/* GUID of RNG protocol */
extern const efi_guid_t efi_guid_rng_protocol;
+/* GUID of capsule update result */
+extern const efi_guid_t efi_guid_capsule_report;
extern unsigned int __efi_runtime_start, __efi_runtime_stop;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
@@ -807,6 +809,17 @@ void efi_memcpy_runtime(void *dest, const void *src,
size_t n);
/* commonly used helper function */
u16 *efi_create_indexed_name(u16 *buffer, const u16 *name, unsigned int index);
+/* Capsule update */
+efi_status_t EFIAPI efi_update_capsule(
+ struct efi_capsule_header **capsule_header_array,
+ efi_uintn_t capsule_count,
+ u64 scatter_gather_list);
+efi_status_t EFIAPI efi_query_capsule_caps(
+ struct efi_capsule_header **capsule_header_array,
+ efi_uintn_t capsule_count,
+ u64 *maximum_capsule_size,
+ u32 *reset_type);
+
#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 075481428cdf..3ca396df3646 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -93,6 +93,17 @@ config EFI_SET_TIME
Provide the SetTime() runtime service at boottime. This service
can be used by an EFI application to adjust the real time clock.
+config EFI_HAVE_CAPSULE_SUPPORT
+ bool
+
+config EFI_RUNTIME_UPDATE_CAPSULE
+ bool "UpdateCapsule() runtime service"
+ default n
+ select EFI_HAVE_CAPSULE_SUPPORT
+ help
+ Select this option if you want to use UpdateCapsule and
+ QueryCapsuleCapabilities API's.
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 9bad1d159b03..c7d231f0e57d 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -23,6 +23,7 @@ endif
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_bootmgr.o
obj-y += efi_boottime.o
+obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
obj-y += efi_console.o
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
new file mode 100644
index ..02a8435cd3d1
--- /dev/null
+++ b/lib/efi_loader/efi_capsule.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * EFI Capsule
+ *
+ * Copyright (c) 2018 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
+
+/**
+ * get_last_capsule - get the last capsule index
+ *
+ * Retrieve the index of the capsule invoked last time from "CapsuleLast"
+ * variable.
+ *
+ * Return:
+ * * > 0 - the last capsule index invoked
+ * * 0x- on error, or no
[PATCH v7 04/17] dfu: export dfu_list
This variable will be utilized to enumerate all dfu entities
for UEFI capsule firmware update in a later commit.
Signed-off-by: AKASHI Takahiro
---
drivers/dfu/dfu.c | 2 +-
include/dfu.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index a298c2c43999..501a60b34400 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -18,7 +18,7 @@
#include
#include
-static LIST_HEAD(dfu_list);
+LIST_HEAD(dfu_list);
static int dfu_alt_num;
static int alt_num_cnt;
static struct hash_algo *dfu_hash_algo;
diff --git a/include/dfu.h b/include/dfu.h
index d3d7e07b60d8..eaf4bfc0d5ed 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -158,6 +158,9 @@ struct dfu_entity {
unsigned int inited:1;
};
+struct list_head;
+extern struct list_head dfu_list;
+
#ifdef CONFIG_SET_DFU_ALT_INFO
/**
* set_dfu_alt_info() - set dfu_alt_info environment variable
--
2.28.0
[PATCH v7 06/17] efi_loader: add efi_create_indexed_name()
This function will be used from several places in UEFI subsystem
to generate some specific form of utf-16 variable name.
For example, L"Capsule0001"
Signed-off-by: AKASHI Takahiro
---
include/efi_loader.h | 3 +++
lib/efi_loader/efi_setup.c | 30 ++
2 files changed, 33 insertions(+)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 7eea5566fdc9..6865a4847d53 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -804,6 +804,9 @@ bool efi_image_parse(void *efi, size_t len, struct
efi_image_regions **regp,
/* runtime implementation of memcpy() */
void efi_memcpy_runtime(void *dest, const void *src, size_t n);
+/* commonly used helper function */
+u16 *efi_create_indexed_name(u16 *buffer, const u16 *name, unsigned int index);
+
#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 45226c5c1a53..6346eda771d0 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
#include
@@ -235,3 +236,32 @@ out:
efi_obj_list_initialized = ret;
return ret;
}
+
+/**
+ * efi_create_indexed_name - create a string name with an index
+ * @buffer:Buffer
+ * @name: Name string
+ * @index: Index
+ *
+ * Create a utf-16 string with @name, appending @index.
+ * For example, L"Capsule0001"
+ * This function is expected to be called only from several places
+ * in EFI subsystem. A caller should ensure that the buffer have
+ * enough space for a resulting string, including L"\0".
+ * No strict check against the length will be done here.
+ *
+ * Return: A pointer to the next position after the created string
+ * in @buffer, or NULL otherwise
+ */
+u16 *efi_create_indexed_name(u16 *buffer, const u16 *name, unsigned int index)
+{
+ u16 *p;
+ char index_buf[5];
+
+ u16_strcpy(buffer, name);
+ p = buffer + utf16_strnlen(name, SIZE_MAX);
+ sprintf(index_buf, "%04X", index);
+ utf8_utf16_strcpy(, index_buf);
+
+ return p;
+}
--
2.28.0
[RESEND PATCH v6 08/17] efi_loader: capsule: add capsule_on_disk support
Capsule data can be loaded into the system either via UpdateCapsule
runtime service or files on a file system (of boot device).
The latter case is called "capsules on disk", and actual updates will
take place at the next boot time.
In this commit, we will support capsule on disk mechanism.
Please note that U-Boot itself has no notion of "boot device" and
all the capsule files to be executed will be detected only if they
are located in a specific directory, \EFI\UpdateCapsule, on a device
that is identified as a boot device by "Boot" variables.
Signed-off-by: AKASHI Takahiro
---
common/main.c| 4 +
include/efi_loader.h | 9 +
lib/efi_loader/Kconfig | 22 ++
lib/efi_loader/efi_capsule.c | 498 +++
lib/efi_loader/efi_setup.c | 8 +
5 files changed, 541 insertions(+)
diff --git a/common/main.c b/common/main.c
index 4b3cd302c3e2..ae5bcdb32f8b 100644
--- a/common/main.c
+++ b/common/main.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
static void run_preboot_environment_command(void)
{
@@ -53,6 +54,9 @@ void main_loop(void)
if (IS_ENABLED(CONFIG_UPDATE_TFTP))
update_tftp(0UL, NULL, NULL);
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_ON_DISK_EARLY))
+ efi_launch_capsules();
+
s = bootdelay_process();
if (cli_process_fdt())
cli_secure_boot_cmd(s);
diff --git a/include/efi_loader.h b/include/efi_loader.h
index ffe772866675..572cfadd491a 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -820,6 +820,11 @@ efi_status_t EFIAPI efi_query_capsule_caps(
u64 *maximum_capsule_size,
u32 *reset_type);
+#define EFI_CAPSULE_DIR L"\\EFI\\UpdateCapsule\\"
+
+/* Hook at initialization */
+efi_status_t efi_launch_capsules(void);
+
#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
@@ -836,6 +841,10 @@ static inline void efi_set_bootdev(const char *dev, const
char *devnr,
const char *path) { }
static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
static inline void efi_print_image_infos(void *pc) { }
+static inline efi_status_t efi_launch_capsules(void)
+{
+ return EFI_SUCCESS;
+}
#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 3ca396df3646..a2a015225a10 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -104,6 +104,28 @@ config EFI_RUNTIME_UPDATE_CAPSULE
Select this option if you want to use UpdateCapsule and
QueryCapsuleCapabilities API's.
+config EFI_CAPSULE_ON_DISK
+ bool "Enable capsule-on-disk support"
+ select EFI_HAVE_CAPSULE_SUPPORT
+ default n
+ help
+ Select this option if you want to use capsule-on-disk feature,
+ that is, capsules can be fetched and executed from files
+ under a specific directory on UEFI system partition instead of
+ via UpdateCapsule API.
+
+config EFI_CAPSULE_ON_DISK_EARLY
+ bool "Initiate capsule-on-disk at U-Boot boottime"
+ depends on EFI_CAPSULE_ON_DISK
+ default y
+ select EFI_SETUP_EARLY
+ help
+ Normally, without this option enabled, capsules will be
+ executed only at the first time of invoking one of efi command.
+ If this option is enabled, capsules will be enforced to be
+ executed as part of U-Boot initialisation so that they will
+ surely take place whatever is set to distro_bootcmd.
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 02a8435cd3d1..2259bfbf3d19 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -11,10 +11,16 @@
#include
#include
#include
+#include
#include
const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
+#ifdef CONFIG_EFI_CAPSULE_ON_DISK
+/* for file system access */
+static struct efi_file_handle *bootdev_root;
+#endif
+
/**
* get_last_capsule - get the last capsule index
*
@@ -163,3 +169,495 @@ efi_status_t EFIAPI efi_query_capsule_caps(
out:
return EFI_EXIT(ret);
}
+
+#ifdef CONFIG_EFI_CAPSULE_ON_DISK
+/**
+ * get_dp_device - retrieve a device path from boot variable
+ * @boot_var: Boot variable name
+ * @device_dp Device path
+ *
+ * Retrieve a device patch from boot variable, @boot_var.
+ *
+ * Return: status code
+ */
+static efi_status_t get_dp_device(u16 *boot_var,
+ struct efi_device_path **device_dp)
+{
+ void *buf = NULL;
+ efi_uintn_t size;
+ struct efi_load_option lo;
+ struct efi_device_path *file_dp;
+ efi_status_t ret;
+
+ size = 0;
+ ret = efi_get_variable_int(boot_var, _global_variable_guid,
+
[RESEND PATCH v6 07/17] efi_loader: define UpdateCapsule api
In this commit, skeleton functions for capsule-related API's are
added under CONFIG_EFI_UPDATE_CAPSULE configuration.
Detailed implementation for a specific capsule type will be added
in the succeeding patches.
Signed-off-by: AKASHI Takahiro
---
include/efi_api.h| 12 +++
include/efi_loader.h | 13 +++
lib/efi_loader/Kconfig | 11 +++
lib/efi_loader/Makefile | 1 +
lib/efi_loader/efi_capsule.c | 165 +++
lib/efi_loader/efi_runtime.c | 104 --
lib/efi_loader/efi_setup.c | 64 +++---
7 files changed, 316 insertions(+), 54 deletions(-)
create mode 100644 lib/efi_loader/efi_capsule.c
diff --git a/include/efi_api.h b/include/efi_api.h
index 5744f6aed86d..c128a0a66ce8 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -217,6 +217,10 @@ enum efi_reset_type {
#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE0x0002
#define CAPSULE_FLAGS_INITIATE_RESET 0x0004
+#define EFI_CAPSULE_REPORT_GUID \
+ EFI_GUID(0x39b68c46, 0xf7fb, 0x441b, 0xb6, 0xec, \
+0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3)
+
struct efi_capsule_header {
efi_guid_t capsule_guid;
u32 header_size;
@@ -224,6 +228,14 @@ struct efi_capsule_header {
u32 capsule_image_size;
} __packed;
+struct efi_capsule_result_variable_header {
+ u32 variable_total_size;
+ u32 reserved;
+ efi_guid_t capsule_guid;
+ struct efi_time capsule_processed;
+ efi_status_t capsule_status;
+} __packed;
+
#define EFI_RT_SUPPORTED_GET_TIME 0x0001
#define EFI_RT_SUPPORTED_SET_TIME 0x0002
#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 6865a4847d53..ffe772866675 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -207,6 +207,8 @@ extern const efi_guid_t efi_guid_cert_type_pkcs7;
/* GUID of RNG protocol */
extern const efi_guid_t efi_guid_rng_protocol;
+/* GUID of capsule update result */
+extern const efi_guid_t efi_guid_capsule_report;
extern unsigned int __efi_runtime_start, __efi_runtime_stop;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
@@ -807,6 +809,17 @@ void efi_memcpy_runtime(void *dest, const void *src,
size_t n);
/* commonly used helper function */
u16 *efi_create_indexed_name(u16 *buffer, const u16 *name, unsigned int index);
+/* Capsule update */
+efi_status_t EFIAPI efi_update_capsule(
+ struct efi_capsule_header **capsule_header_array,
+ efi_uintn_t capsule_count,
+ u64 scatter_gather_list);
+efi_status_t EFIAPI efi_query_capsule_caps(
+ struct efi_capsule_header **capsule_header_array,
+ efi_uintn_t capsule_count,
+ u64 *maximum_capsule_size,
+ u32 *reset_type);
+
#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 075481428cdf..3ca396df3646 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -93,6 +93,17 @@ config EFI_SET_TIME
Provide the SetTime() runtime service at boottime. This service
can be used by an EFI application to adjust the real time clock.
+config EFI_HAVE_CAPSULE_SUPPORT
+ bool
+
+config EFI_RUNTIME_UPDATE_CAPSULE
+ bool "UpdateCapsule() runtime service"
+ default n
+ select EFI_HAVE_CAPSULE_SUPPORT
+ help
+ Select this option if you want to use UpdateCapsule and
+ QueryCapsuleCapabilities API's.
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 9bad1d159b03..c7d231f0e57d 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -23,6 +23,7 @@ endif
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-y += efi_bootmgr.o
obj-y += efi_boottime.o
+obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
obj-y += efi_console.o
obj-y += efi_device_path.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
new file mode 100644
index ..02a8435cd3d1
--- /dev/null
+++ b/lib/efi_loader/efi_capsule.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * EFI Capsule
+ *
+ * Copyright (c) 2018 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
+
+/**
+ * get_last_capsule - get the last capsule index
+ *
+ * Retrieve the index of the capsule invoked last time from "CapsuleLast"
+ * variable.
+ *
+ * Return:
+ * * > 0 - the last capsule index invoked
+ * * 0x- on error, or no
