Hi Simon,
On Tue, Nov 11, 2014 at 2:53 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 07:18, Bin Meng bmeng...@gmail.com wrote:
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.
Signed-off-by: Bin
Hi Simon,
On Tue, Nov 11, 2014 at 2:54 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 07:19, Bin Meng bmeng...@gmail.com wrote:
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
Hi John,
On 10/11/2014 00:53, John Tobias wrote:
@@ -29,7 +29,9 @@
#define CONFIG_SPL_TEXT_BASE 0x00908000
#define CONFIG_SPL_MAX_SIZE 0x1
#define CONFIG_SPL_START_S_PATH arch/arm/cpu/armv7
+#ifndef CONFIG_SPL_STACK
#define CONFIG_SPL_STACK
Hi Simon,
On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
[snip]
+ $(srctree)/board/$(BOARDDIR)/descriptor.bin
I don't see where the descriptor.bin is created?
This needs to be downloaded and provided, as with mrc.bin, etc.
I thought the
Hi Simon,
On Tue, Nov 11, 2014 at 8:29 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 23:49, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Implement SDRAM init using the Memory Reference Code (mrc.bin)
Hi,
On 11/11/2014 12:28 AM, Zoltan HERPAI wrote:
Hi Hans,
Sorry for the noise, I screwed up the pull request. All it was meant to be is
to fix up the bananapi gmac magic bit toucher - please ignore/drop, I'll redo
it.
Thanks for catching this, note we don't do pull-reqs for u-boot, other
Hi John,
On 10/11/2014 01:23, John Tobias wrote:
Hi Stefano,
On Sun, Nov 9, 2014 at 1:16 PM, Stefano Babic sba...@denx.de wrote:
Hi John,
On 08/11/2014 22:27, John Tobias wrote:
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
Many of the x86 CONFIG options will be common across different boards. Move
them to a common file.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Move some features out of the common file
Hi Tom,
we have equipped some of our am335x boards (draco from mainline U-Boot)
with NAND devices from Hynix. And as it seems, the BootROM passes
now a different bootdevice number to SPL. Its not 5 as it used to be
for NAND but 6 instead. So SPL hangs of course as this boot-device is
not
Reviewed-by: Bin Meng bmeng...@gmail.com
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
Add a function to get the stack pointer and another to halt the CPU.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove the cpuid functions since they were
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
These are no-longer needed so drop them.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove definition of find_fdt() also
- Remove prepare_fdt() also
arch/x86/include/asm/init_helpers.h | 2 --
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to replace fill_processor_name()
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We can use an MSR to obtain the time base. Add this back in and consolidate
the code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to tidy up timer code for Intel core
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post
Hi Tom, [cc: Albert]
please pull these 4 patches to your tree.
It adds support for Zybo board and add support for new ps7_init_gpl file.
Thanks,
Michal
The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc:
Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh
If print_mmc_devices() was called with a '\n' separator (as done
for example by the mmc list command), it offset the 2-nd and
all subsequent lines by one space. Fixing this.
Signed-off-by: Lubomir Popov l-po...@ti.com
---
drivers/mmc/mmc.c |7 +--
1 file changed, 5 insertions(+), 2
On 10/30/2014 06:52 PM, Soren Brinkmann wrote:
The latest Xilinx tools generate ps7_init files that are explicitly
available under GPL. Change the makefile to allow drop in of those files
for building the SPL.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Acked-by: Jagannadha
On Mon, 10 Nov 2014 16:29:38 -0500
Tom Rini tr...@ti.com wrote:
Hey all,
I've pushed v2015.01-rc1 out to the repository and tarballs should exist
soon.
Half a day has passed since Tom's I've pushed v2015.rc-rc1 mail,
but I still don't see it.
I have been often wondering why we can see
Today I got the final board and found out that a different
connector is used as the one on my development board. The
new connector has swaped pins for cd and wp.
This change is tested on a production ready baord.
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
Le lundi 10 novembre 2014 à 13:46 -0500, Tom Rini a écrit :
On Sat, Nov 08, 2014 at 10:29:24PM +0100, Paul Kocialkowski wrote:
Le samedi 08 novembre 2014 à 20:55 +0100, Paul Kocialkowski a écrit :
Boards using the TWL4030 regulator may not all use the LDOs the same way
(e.g. MMC2 power
On Tue, Nov 11, 2014 at 10:10:41AM +0100, Stefan Roese wrote:
Hi Tom,
we have equipped some of our am335x boards (draco from mainline U-Boot)
with NAND devices from Hynix. And as it seems, the BootROM passes
now a different bootdevice number to SPL. Its not 5 as it used to be
for NAND but 6
Hi
2014-11-03 22:00 GMT+01:00 Stephen Warren swar...@wwwdotorg.org:
On 10/31/2014 09:08 AM, Christian Gmeiner wrote:
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID.
Hit any key
Hi
2014-11-04 7:31 GMT+01:00 Simon Glass s...@chromium.org:
Hi Christian,
On 31 October 2014 09:08, Christian Gmeiner christian.gmei...@gmail.com
wrote:
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to
Hi
2014-11-04 19:41 GMT+01:00 Simon Glass s...@chromium.org:
Hi Christian,
On 3 November 2014 02:47, Christian Gmeiner christian.gmei...@gmail.com
wrote:
Hi Simon,
[snip]
+
+ if (argc == 4)
+ setenv(argv[3], uuid);
+ else
+ printf(%s\n, uuid);
On Tue, Nov 11, 2014 at 12:57:45PM +0100, Paul Kocialkowski wrote:
Le lundi 10 novembre 2014 à 13:46 -0500, Tom Rini a écrit :
On Sat, Nov 08, 2014 at 10:29:24PM +0100, Paul Kocialkowski wrote:
Le samedi 08 novembre 2014 à 20:55 +0100, Paul Kocialkowski a écrit :
Boards using the TWL4030
In the current implementation of the boot sequence of UniPhier
platform, 32KB temporary RAM is available before relocation.
The malloc area and the stack shares the 32KB area.
With CONFIG_SYS_MALLOC_F_LEN set to 0x7000 (28KB), only 0x1000 (4KB)
is left for the stack. In some use cases, the
On 10 November 2014 10:41, Hyungwon Hwang human.hw...@samsung.com wrote:
This is v6 of the patchset adding support Odroud XU3 board.
link to the previous version:
v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html
v3:
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID.
changes rfc - v1:
- make the environment variable an option parameter. If not
given, the UUID is printed out. If given, it is stored
Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc. Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND
This patch series is here because Scott Wood recommended me
to use CONFIG_SYS_NAND_SELF_INIT to solve my problem:
http://patchwork.ozlabs.org/patch/402462/
Masahiro Yamada (2):
mtd: denali: use CONFIG_SYS_NAND_SELF_INIT
mtd: denali: set some registers after nand_scan_ident()
Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().
CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce
the
Hi Scott,
On Tue, 4 Nov 2014 23:45:44 -0600
Scott Wood scottw...@freescale.com wrote:
On Wed, 2014-11-05 at 12:39 +0900, Masahiro Yamada wrote:
[2] There is no good place to insert a callback to an SoC file.
I need to write parameters such as page_size to hardware registers.
(You can see
Le mardi 11 novembre 2014 à 07:33 -0500, Tom Rini a écrit :
On Tue, Nov 11, 2014 at 12:57:45PM +0100, Paul Kocialkowski wrote:
Le lundi 10 novembre 2014 à 13:46 -0500, Tom Rini a écrit :
On Sat, Nov 08, 2014 at 10:29:24PM +0100, Paul Kocialkowski wrote:
Le samedi 08 novembre 2014 à 20:55
This commit merges
arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c
to
arch/arm/cpu/armv7/uniphier/board_postclk_init.c
Because PH1-Pro4 does not have the BCU block, add __weak to
bcu_init().
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and
it is defined in ./.config but not in spl/.config,
so pin_init() should be called from the normal image
so that UART works correctly.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
arch/arm/cpu/armv7/uniphier/Kconfig
Masahiro Yamada (2):
ARM: UniPhier: consolidate board_postclk_init() function
ARM: UniPhier: call pin_init() also in the normal boot
arch/arm/cpu/armv7/uniphier/Kconfig| 4 +++
arch/arm/cpu/armv7/uniphier/Makefile | 1 +
.../uniphier/{ph1-ld4 =
mcc200 and prs200 are old and have no maintainer. Remove the boards.
This also removes the mcc200 specific 1bpp BMP support from
common/lcd.c
Cc: Wolfgang Denk w...@denx.de
Cc: Anatolij Gustschin ag...@denx.de
Cc: Masahiro Yamada yamad...@jp.panasonic.com
Cc: York Sun york...@freescale.com
Hi Christian,
On 11/11/2014 12:57, Christian Gmeiner wrote:
Today I got the final board and found out that a different
connector is used as the one on my development board. The
new connector has swaped pins for cd and wp.
It is always so..final board is different from development board ;-)
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Hi Simon,
I am not sure if there is anything I missed but when I look at the
u-boot-x86/working, the repo content does not match the patch v2 here.
And seems you missed my previous comments @
This reverts commit 1e96220a5687efae2aed45ce56e143336c40d0a7.
Remove duplicated vxworks.h header.
The same change was done by
ARM: prevent compiler warnings from bootm.c
(sha1: 8d196e52b58d1e50a80c2f5067b201cda521c75c)
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1
Gentle ping.
On 10/29/2014 07:28 PM, Nikita Kiryanov wrote:
The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of
2014-10-30 12:11 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
The same bit-field macros are defined in include/linux/serial_reg.h
so let's include it and delete duplicated defines.
Also, remove unnecessary inclusion of common.h.
Signed-off-by: Masahiro Yamada
2014-11-05 14:25 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
If a support card is attached to the main board, the on-board
SMSC9118 LAN controller is available. It must be kept in reset
state for a while on start-up.
When the board is kicked via a debbuger rather than pushing the
2014-11-06 20:16 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Applied to u-boot-uniphier/master.
--
Best Regards
Masahiro Yamada
___
U-Boot mailing list
U-Boot@lists.denx.de
2014-11-07 18:33 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
These IO pins are necessary for port power control and
over current detect.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Applied to u-boot-uniphier/master.
--
Best Regards
Masahiro Yamada
2014-11-07 18:48 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
This series includes both USB parts and Panasonic SoC-specific parts
to resolve the patch dependency.
Marek,
please review at least 3/4 and issue your Ack if it is OK.
After it is Ack'ed, I will apply this series to my
2014-11-07 21:08 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code. This commit adds a simple
macro that is available in asm code.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
2014-11-11 21:50 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
In the current implementation of the boot sequence of UniPhier
platform, 32KB temporary RAM is available before relocation.
The malloc area and the stack shares the 32KB area.
With CONFIG_SYS_MALLOC_F_LEN set to 0x7000
2014-11-11 22:18 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com:
Masahiro Yamada (2):
ARM: UniPhier: consolidate board_postclk_init() function
ARM: UniPhier: call pin_init() also in the normal boot
Series, applied to u-boot-uniphier/master.
--
Best Regards
Masahiro Yamada
Hi Heiko,
On 10 November 2014 00:16, Heiko Schocher h...@denx.de wrote:
Hello Simon,
sorry for the long delay...
Am 13.10.2014 07:39, schrieb Simon Glass:
(Note this is RFC since the uclass interface needs discussion and also
because only sandbox is implemented so far. But I thought it
Hi Tom,
The following changes since commit 9906090f527153afddc5aa64d37cb5f89c6ee129:
Prepare v2015.01-rc1 (2014-11-10 16:25:29 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-uniphier.git master
for you to fetch changes up to
We had the problem on an AM33xx platform, that SPL detected an
unsupported boot-device. But since this message is a debug message
it took a bit of time to really know, where the hangup in SPL
resulted from. So let's change this debug message to a printf
and also print the detected boot-device that
Hi Bin,
On 11 November 2014 01:25, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 2:54 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 07:19, Bin Meng bmeng...@gmail.com wrote:
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
Hi Bin,
On 11 November 2014 03:05, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We can use an MSR to obtain the time base. Add this back in and consolidate
the code.
Signed-off-by: Simon Glass s...@chromium.org
---
Hi Bin,
On 11 November 2014 01:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
[snip]
+ $(srctree)/board/$(BOARDDIR)/descriptor.bin
I don't see where the descriptor.bin is created?
This
Hi Bin,
On 11 November 2014 07:52, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass
On Tue, Nov 11, 2014 at 04:59:13PM +0100, Stefan Roese wrote:
We had the problem on an AM33xx platform, that SPL detected an
unsupported boot-device. But since this message is a debug message
it took a bit of time to really know, where the hangup in SPL
resulted from. So let's change this
Hi Bin,
On 11 November 2014 07:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
I am not sure if there is anything I missed but when I look at the
u-boot-x86/working, the repo content does not match the patch v2 here.
And seems you missed my previous comments @
On 11.11.2014 17:16, Tom Rini wrote:
On Tue, Nov 11, 2014 at 04:59:13PM +0100, Stefan Roese wrote:
We had the problem on an AM33xx platform, that SPL detected an
unsupported boot-device. But since this message is a debug message
it took a bit of time to really know, where the hangup in SPL
Short version:
* this patch fixes exception handling on i.MX27
which was broken, probably from day one.
* i.MX27-based board Maintainers please test this
patch: make sure your board boots with it and
make sure e.g. a write to address 0 causes U-Boot
to signal a data abort.
* i.MX
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
arch/arm/lib/relocate.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index b4a258c..6ede41c 100644
--- a/arch/arm/lib/relocate.S
+++
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high (0x) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high
On 11/11/2014 05:55 AM, Christian Gmeiner wrote:
Some filesystems have a UUID stored in its superblock. To
allow using root=UUID=... for the kernel command line we
need a way to read-out the filesystem UUID.
Just one more nit below, otherwise,
Acked-by: Stephen Warren swar...@nvidia.com
On Tue, Nov 11, 2014 at 12:44 AM, Stefano Babic sba...@denx.de wrote:
Hi John,
On 10/11/2014 01:23, John Tobias wrote:
Hi Stefano,
On Sun, Nov 9, 2014 at 1:16 PM, Stefano Babic sba...@denx.de wrote:
Hi John,
On 08/11/2014 22:27, John Tobias wrote:
This patch will enable the support for
Dangling PR, sorry it's late ...
The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc:
Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh (2014-11-05
13:11:18
-0500)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git master
for you to
Dangling PR, sorry it's late ...
The following changes since commit 571bdf16a78e9e116a93d46f4809c4f8a3f2adb6:
arm: interrupt_init: set sp in IRQ/FIQ modes (2014-10-29 09:03:28 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch
So the issues of the variables changing were due to me initializing
everything in board_early_init_f(). I moved everything out of it except uart
setup. If I setup the uart in board_init() instead of board_early_init_f()
then the early cpu info stuff is missed. I guess there’s an opportunity for
Add some basic tests to check that the system works as expected.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add a test for automatic binding of generic I2C devices
- Add a new asm/test.h header for tests in sandbox
arch/sandbox/include/asm/test.h | 15 ++
Factor out the common code to make it easier to adjust it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add a suitable commit message
common/cmd_i2c.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/common/cmd_i2c.c
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:
- CONFIG_SYS_I2C_INIT_BOARD
- CONFIG_I2C_MULTI_BUS
- CONFIG_SYS_MAX_I2C_BUS
- CONFIG_SYS_I2C_SPEED
- CONFIG_SYS_I2C
This has
This series adds I2C support to driver model. It has become apparent that
this is a high priority as it is widely used. It follows along to some
extent from the SPI conversion.
Several changes are made from the original I2C implementations.
Firstly it is not necessary to specify the chip
This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/i2c/Makefile | 2 +-
drivers/i2c/sandbox_i2c.c | 148
In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-emul-uclass.c | 14 ++
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sandbox.c | 2 +-
drivers/spi/spi-uclass.c | 11 +--
include/spi.h | 10
Since we scan from left to right looking for the first digit, i2c0 returns
2 instead of 0 for the alias number. Adjust the code to scan from right to
left instead.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to correct handling of aliases with embedded digits
When the device is created from a device tree node, it matches a compatible
string. Allow access to that string and the associated data.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/core/device.c | 5 +
drivers/core/lists.c | 17 -
In some cases we need to manually bind a device to a particular driver.
Add a function to do this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to add a function to bind a device by driver name
drivers/core/lists.c | 21 +
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patches to adjust SPI to use device_bind_driver()
The concept of a 'current bus' is now implemented in the command line
rather than in the uclass. Also the address length does not need to
be specified with each command - really we should consider dropping
this from most commands but it works OK for now.
Signed-off-by: Simon Glass
Add dev_get_parent() as a convenience to obtain the parent of a device.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/core/device.c | 5 +
include/dm/device.h | 8
2 files changed, 13 insertions(+)
diff --git a/drivers/core/device.c
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:
- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions
Enable the options to bring up I2C on sandbox. Also enable all the available
I2C commands for testing purposes.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/configs/sandbox.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/configs/sandbox.h
Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/sandbox/dts/sandbox.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/sandbox/dts/sandbox.dts
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update commit message for EEPROM driver
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/Makefile | 3 ++
drivers/misc/i2c_eeprom_emul.c | 108
On 11/11/14 17:46, Albert ARIBAUD wrote:
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high (0x) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is
We had the problem on an AM33xx platform, that SPL detected an
unsupported boot-device. But since this message is a debug message
it took a bit of time to really know, where the hangup in SPL
resulted from. So let's change this debug message to a printf
and also print the detected boot-device that
Hello trem,
On Tue, 11 Nov 2014 19:02:21 +0100, trem trem...@yahoo.fr wrote:
On 11/11/14 17:46, Albert ARIBAUD wrote:
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high
Short version:
* this patch fixes exception handling on i.MX27
which was broken, probably from day one.
* i.MX27-based board Maintainers please test this
patch: make sure your board boots with it and
make sure e.g. a write to address 0 causes U-Boot
to signal a data abort.
* i.MX
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
Changes in v2: None
arch/arm/lib/relocate.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index b4a258c..6ede41c 100644
--- a/arch/arm/lib/relocate.S
+++
Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x) or
high (0x) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high
On 11 November 2014 23:16, Simon Glass s...@chromium.org wrote:
This code was not updated when the chip select handling was adjusted. Fix
it to call the correct function.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/mtd/spi/sandbox.c | 2 +-
On 11 November 2014 23:16, Simon Glass s...@chromium.org wrote:
In some cases we need to manually bind a device to a particular driver.
Add a function to do this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to add a function to bind a device by driver
On 11 November 2014 23:16, Simon Glass s...@chromium.org wrote:
The SPI function does the same thing, so we may as well just use the new
generic function. The 'cs' parameter was not actually used, so can be
dropped.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new
From: Allen Martin amar...@nvidia.com
Norrin (PM370) is a Tegra124 clamshell board that is very similar to
venice2, but it has a different panel, the sdcard cd and wp sense are
flipped, and it has a different revision of the AS3722 PMIC. This
board is also refered to as nyan in the ChromeOS
bcm11130
bcm11130_nand
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v2:
- split from previous commit
board/broadcom/bcm11130/MAINTAINERS | 6 ++
board/broadcom/bcm11130_nand/MAINTAINERS | 6 ++
configs/bcm11130_defconfig | 3 +++
bcm911360_entphn
bcm911360_entphn-ns
bcm911360k
bcm958300k-ns
bcm958305k
- updates to support Cygnus and NSP board families better
- add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v2:
- split into two commits
This fixes the following two problems:
cppcheck reports:
[arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err
[arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname
Signed-off-by: Simon Glass s...@chromium.org
Reported-by: Wolfgang Denk w...@denx.de
---
arch/sandbox/cpu/os.c
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