[PATCH] D152914: [Draft] Make __builtin_cpu builtins target-independent

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

HI @nemanjai, Did you get a chance to post this as a github PR?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152914/new/

https://reviews.llvm.org/D152914

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D74094: Reapply: [IRGen] Emit lifetime intrinsics around temporary aggregate argument allocas

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

@nickdesaulniers I have verified this patch on top of 
`40ee8abee77a2e8fb0089d4c7f5723b71f27d416` passes our multistage bot 
http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage

Thank-you!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74094/new/

https://reviews.llvm.org/D74094

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D74094: Reapply: [IRGen] Emit lifetime intrinsics around temporary aggregate argument allocas

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

Sorry I missed this.  Will kick off now and let you know the results soon.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74094/new/

https://reviews.llvm.org/D74094

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D155540: [clangd] Remove extra dependancies for clangd

[Lei Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe6f18b75d7ff: [clangd] Remove extra dependancies for clangd 
(authored by saghir, committed by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155540/new/

https://reviews.llvm.org/D155540

Files:
  clang-tools-extra/clangd/tool/CMakeLists.txt


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -26,11 +26,7 @@
   clangBasic
   clangFormat
   clangFrontend
-  clangLex
-  clangSema
   clangTooling
-  clangToolingCore
-  clangToolingRefactoring
   clangToolingSyntax
   )
 
@@ -48,11 +44,8 @@
   PRIVATE
   clangAST
   clangBasic
-  clangFormat
-  clangFrontend
   clangLex
   clangSema
-  clangTooling
   clangToolingCore
   clangToolingRefactoring
   clangToolingSyntax


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -26,11 +26,7 @@
   clangBasic
   clangFormat
   clangFrontend
-  clangLex
-  clangSema
   clangTooling
-  clangToolingCore
-  clangToolingRefactoring
   clangToolingSyntax
   )
 
@@ -48,11 +44,8 @@
   PRIVATE
   clangAST
   clangBasic
-  clangFormat
-  clangFrontend
   clangLex
   clangSema
-  clangTooling
   clangToolingCore
   clangToolingRefactoring
   clangToolingSyntax
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D155540: [clangd] Remove extra dependancies for clangd

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 549374.
lei added a comment.

Rebase to ToT


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155540/new/

https://reviews.llvm.org/D155540

Files:
  clang-tools-extra/clangd/tool/CMakeLists.txt


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -26,11 +26,7 @@
   clangBasic
   clangFormat
   clangFrontend
-  clangLex
-  clangSema
   clangTooling
-  clangToolingCore
-  clangToolingRefactoring
   clangToolingSyntax
   )
 
@@ -48,11 +44,8 @@
   PRIVATE
   clangAST
   clangBasic
-  clangFormat
-  clangFrontend
   clangLex
   clangSema
-  clangTooling
   clangToolingCore
   clangToolingRefactoring
   clangToolingSyntax


Index: clang-tools-extra/clangd/tool/CMakeLists.txt
===
--- clang-tools-extra/clangd/tool/CMakeLists.txt
+++ clang-tools-extra/clangd/tool/CMakeLists.txt
@@ -26,11 +26,7 @@
   clangBasic
   clangFormat
   clangFrontend
-  clangLex
-  clangSema
   clangTooling
-  clangToolingCore
-  clangToolingRefactoring
   clangToolingSyntax
   )
 
@@ -48,11 +44,8 @@
   PRIVATE
   clangAST
   clangBasic
-  clangFormat
-  clangFrontend
   clangLex
   clangSema
-  clangTooling
   clangToolingCore
   clangToolingRefactoring
   clangToolingSyntax
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D155540: [clangd] Remove extra dependancies for clangd

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

I was thinking to commit this patch to minimize the dependencies if there are 
no objections. @MaskRay @nemanjai any preferences?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155540/new/

https://reviews.llvm.org/D155540

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157078: [include-cleaner] Handle files with unnamed buffers

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

This is causing a ld.lld link failure in 
https://lab.llvm.org/buildbot/#/builders/57

  FAILED: 
tools/clang/tools/extra/include-cleaner/unittests/ClangIncludeCleanerTests 
  : && /home/buildbots/clang.15.0.4/bin/clang++ --gcc-toolchain=/usr -fPIC 
-fno-semantic-interposition -fvisibility-inlines-hidden -Werror 
-Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra 
-Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers 
-pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough 
-Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor 
-Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion 
-Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color 
-ffunction-sections -fdata-sections -fno-common -Woverloaded-virtual 
-Wno-nested-anon-types -O3 -DNDEBUG -Wl,--color-diagnostics 
-Wl,--gc-sections 
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/AnalysisTest.cpp.o
 
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/FindHeadersTest.cpp.o
 
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/IncludeSpellerTest.cpp.o
 
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/LocateSymbolTest.cpp.o
 
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/RecordTest.cpp.o
 
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/TypesTest.cpp.o
 
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/WalkASTTest.cpp.o
 -o tools/clang/tools/extra/include-cleaner/unittests/ClangIncludeCleanerTests  
-Wl,-rpath,/home/buildbots/docker-RHEL84-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/lib
  -lpthread  lib/libllvm_gtest_main.so.18git  -lpthread  
lib/libclangIncludeCleaner.so.18git  lib/libclangTesting.so.18git  
lib/libLLVMTestingAnnotations.so.18git  lib/libLLVMTestingSupport.so.18git  
lib/libclangFormat.so.18git  lib/libclangToolingInclusionsStdlib.so.18git  
lib/libllvm_gtest.so.18git  lib/libclangFrontend.so.18git  
lib/libclangAST.so.18git  lib/libclangLex.so.18git  lib/libclangBasic.so.18git  
lib/libLLVMSupport.so.18git  
-Wl,-rpath-link,/home/buildbots/docker-RHEL84-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/lib
 && :
  ld.lld: error: undefined symbol: 
clang::PCHContainerOperations::PCHContainerOperations()
  >>> referenced by RecordTest.cpp
  >>>   
tools/clang/tools/extra/include-cleaner/unittests/CMakeFiles/ClangIncludeCleanerTests.dir/RecordTest.cpp.o:(clang::include_cleaner::(anonymous
 namespace)::PragmaIncludeTest_ExportInUnnamedBuffer_Test::TestBody())
  clang-15: error: linker command failed with exit code 1 (use -v to see 
invocation)

Maybe a lib is needed?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157078/new/

https://reviews.llvm.org/D157078

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D144611: [PowerPC] Adding test coverage for vector compatibility warning

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

thx for the added coverage.
LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144611/new/

https://reviews.llvm.org/D144611

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D145506: [PowerPC] Emit warn_deprecated_lax_vec_conv_all warning only for PPC

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM
Thx


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145506/new/

https://reviews.llvm.org/D145506

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D131622: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c

[Lei Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7d8ae9f755d7: [NFC][PowerPC] Add missing NOCOMPAT checks for 
builtins-ppc-xlcompat.c (authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131622/new/

https://reviews.llvm.org/D131622

Files:
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c


Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
 void test() {
 // CHECK-LABEL: @test(
 // CHECK-NEXT:  entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT:  entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT:  entry:
 
   res_vf = vec_ctf(vsll, 4);
 // CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
 // CHECK-NEXT:[[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x 
i64> [[TMP0]])
 // CHECK-NEXT:fmul <4 x float> [[TMP1]], 
+// NOCOMPAT:  [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]], 
 
   res_vf = vec_ctf(vull, 4);
 // CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
 // CHECK-NEXT:[[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x 
i64> [[TMP2]])
 // CHECK-NEXT:fmul <4 x float> [[TMP3]], 
+// NOCOMPAT:  [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]], 
 
   res_vsll = vec_cts(vd, 4);
 // CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP4]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT:  [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]], 
 
   res_vull = vec_ctu(vd, 4);
 // CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP8]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT:  [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]], 
 
   res_vd = vec_round(vd);
 // CHECK: call double @llvm.ppc.readflm()


Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
 void test() {
 // CHECK-LABEL: @test(
 // CHECK-NEXT:  entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT:  entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT:  entry:
 
   res_vf = vec_ctf(vsll, 4);
 // CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
 // CHECK-NEXT:[[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> [[TMP0]])
 // CHECK-NEXT:fmul <4 x float> [[TMP1]], 
+// NOCOMPAT:  [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]], 
 
   res_vf = vec_ctf(vull, 4);
 // CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
 // CHECK-NEXT:[[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]])
 // CHECK-NEXT:fmul <4 x float> [[TMP3]], 
+// NOCOMPAT:  [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]], 
 
   res_vsll = vec_cts(vd, 4);
 // CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP4]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT:  [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]], 
 
   res_vull = vec_ctu(vd, 4);
 // CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP8]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT:  [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]], 
 
   res_vd = vec_round(vd);
 // CHECK: call double @llvm.ppc.readflm()
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D131622: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c

[Lei Huang via Phabricator via cfe-commits]

lei created this revision.
lei added reviewers: nemanjai, amyk, power-llvm-team.
Herald added a subscriber: shchenz.
Herald added a project: All.
lei requested review of this revision.
Herald added a project: clang.

Followup patch to address request from https://reviews.llvm.org/D124093


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131622

Files:
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c


Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
 void test() {
 // CHECK-LABEL: @test(
 // CHECK-NEXT:  entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT:  entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT:  entry:
 
   res_vf = vec_ctf(vsll, 4);
 // CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
 // CHECK-NEXT:[[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x 
i64> [[TMP0]])
 // CHECK-NEXT:fmul <4 x float> [[TMP1]], 
+// NOCOMPAT:  [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]], 
 
   res_vf = vec_ctf(vull, 4);
 // CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
 // CHECK-NEXT:[[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x 
i64> [[TMP2]])
 // CHECK-NEXT:fmul <4 x float> [[TMP3]], 
+// NOCOMPAT:  [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]], 
 
   res_vsll = vec_cts(vd, 4);
 // CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP4]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT:  [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]], 
 
   res_vull = vec_ctu(vd, 4);
 // CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP8]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT:  [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]], 
 
   res_vd = vec_round(vd);
 // CHECK: call double @llvm.ppc.readflm()


Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
 void test() {
 // CHECK-LABEL: @test(
 // CHECK-NEXT:  entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT:  entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT:  entry:
 
   res_vf = vec_ctf(vsll, 4);
 // CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
 // CHECK-NEXT:[[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> [[TMP0]])
 // CHECK-NEXT:fmul <4 x float> [[TMP1]], 
+// NOCOMPAT:  [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]], 
 
   res_vf = vec_ctf(vull, 4);
 // CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
 // CHECK-NEXT:[[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]])
 // CHECK-NEXT:fmul <4 x float> [[TMP3]], 
+// NOCOMPAT:  [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]], 
 
   res_vsll = vec_cts(vd, 4);
 // CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP4]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT:  [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]], 
 
   res_vull = vec_ctu(vd, 4);
 // CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
 // CHECK-NEXT:fmul <2 x double> [[TMP8]], 
 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT:  [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]], 
 
   res_vd = vec_round(vd);
 // CHECK: call double @llvm.ppc.readflm()
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/list

[PATCH] D129016: [PowerPC] implemented @llvm.ppc.kill.canary to corrupt stack guard

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/kill-canary-intrinsic.ll:4
+; RUN:   --ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux \
+; RUN:   --ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=LINUX

missing LE run test line?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129016/new/

https://reviews.llvm.org/D129016

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128288: [PowerPC] Fix signatures for vec_replace_unaligned builtin

[Lei Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcaf7243a6b53: [PowerPC] Fix signatures for 
vec_replace_unaligned builtin (authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128288/new/

https://reviews.llvm.org/D128288

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
@@ -49,12 +49,12 @@
 }
 
 #elif defined(__TEST_UNALIGNED_UI)
-vector unsigned int test_vec_replace_unaligned_ui(void) {
+vector unsigned char test_vec_replace_unaligned_ui(void) {
   return vec_replace_unaligned(vuia, uia, 16); // expected-error {{byte number 16 is outside of the valid range [0, 12]}}
 }
 
 #else
-vector unsigned long long test_vec_replace_unaligned_ull(void) {
+vector unsigned char test_vec_replace_unaligned_ull(void) {
   return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{byte number 12 is outside of the valid range [0, 8]}}
 }
 #endif
Index: clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
@@ -1183,8 +1183,7 @@
 // CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
 // CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-BE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
 //
 // CHECK-LE-LABEL: @test_vec_replace_unaligned_si(
 // CHECK-LE-NEXT:  entry:
@@ -1194,10 +1193,9 @@
 // CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
 // CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-LE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
 //
-vector signed int test_vec_replace_unaligned_si(void) {
+vector unsigned char test_vec_replace_unaligned_si(void) {
   return vec_replace_unaligned(vsia, sia, 6);
 }
 
@@ -1209,8 +1207,7 @@
 // CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
 // CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-BE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
 //
 // CHECK-LE-LABEL: @test_vec_replace_unaligned_ui(
 // CHECK-LE-NEXT:  entry:
@@ -1220,10 +1217,9 @@
 // CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
 // CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-LE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
 //
-vector unsigned int test_vec_replace_unaligned_ui(void) {
+vector unsigned char test_vec_replace_unaligned_ui(void) {
   return vec_replace_unaligned(vuia, uia, 8);
 }
 
@@ -1236,8 +1232,7 @@
 // CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
 // CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-BE-NEXT:ret <4 x float> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
 //
 // CHECK-LE-LABEL: @test_vec_replace_unaligned_f(
 // CHECK-LE-NEXT:  entry:
@@ -1248,10 +1243,9 @@
 // CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
 // CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-LE-NEXT:ret <4 x float> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
 //
-vector float test_vec_replace_unaligned_f(void) {
+vector unsigned char test_vec_

[PATCH] D128288: [PowerPC] Fix signatures for vec_replace_unaligned builtin

[Lei Huang via Phabricator via cfe-commits]

lei created this revision.
lei added reviewers: amyk, quinnp, power-llvm-team.
Herald added subscribers: shchenz, nemanjai.
Herald added a project: All.
lei requested review of this revision.
Herald added a project: clang.

``vec_replace_unaligned`` is meant to return vuc to emphasize that elements
are being inserted on unnatural boundaries.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128288

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
@@ -49,12 +49,12 @@
 }
 
 #elif defined(__TEST_UNALIGNED_UI)
-vector unsigned int test_vec_replace_unaligned_ui(void) {
+vector unsigned char test_vec_replace_unaligned_ui(void) {
   return vec_replace_unaligned(vuia, uia, 16); // expected-error {{byte number 16 is outside of the valid range [0, 12]}}
 }
 
 #else
-vector unsigned long long test_vec_replace_unaligned_ull(void) {
+vector unsigned char test_vec_replace_unaligned_ull(void) {
   return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{byte number 12 is outside of the valid range [0, 8]}}
 }
 #endif
Index: clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
@@ -1183,8 +1183,7 @@
 // CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
 // CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-BE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
 //
 // CHECK-LE-LABEL: @test_vec_replace_unaligned_si(
 // CHECK-LE-NEXT:  entry:
@@ -1194,10 +1193,9 @@
 // CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
 // CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-LE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
 //
-vector signed int test_vec_replace_unaligned_si(void) {
+vector unsigned char test_vec_replace_unaligned_si(void) {
   return vec_replace_unaligned(vsia, sia, 6);
 }
 
@@ -1209,8 +1207,7 @@
 // CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
 // CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-BE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
 //
 // CHECK-LE-LABEL: @test_vec_replace_unaligned_ui(
 // CHECK-LE-NEXT:  entry:
@@ -1220,10 +1217,9 @@
 // CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
 // CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-LE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
 //
-vector unsigned int test_vec_replace_unaligned_ui(void) {
+vector unsigned char test_vec_replace_unaligned_ui(void) {
   return vec_replace_unaligned(vuia, uia, 8);
 }
 
@@ -1236,8 +1232,7 @@
 // CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
 // CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-BE-NEXT:ret <4 x float> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
 //
 // CHECK-LE-LABEL: @test_vec_replace_unaligned_f(
 // CHECK-LE-NEXT:  entry:
@@ -1248,10 +1243,9 @@
 // CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
 // CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
 // CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-LE-NEXT:ret <4 x float> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[T

[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

[Lei Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG711a71d1ab10: PowerPC] Emit warning for incompatible vector 
types that are currently… (authored by maryammo, committed by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126540/new/

https://reviews.llvm.org/D126540

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/test/Parser/cxx-altivec.cpp

Index: clang/test/Parser/cxx-altivec.cpp
===
--- clang/test/Parser/cxx-altivec.cpp
+++ clang/test/Parser/cxx-altivec.cpp
@@ -1,10 +1,10 @@
-// RUN: %clang_cc1 -triple=powerpc-apple-darwin8 -target-feature +altivec -fsyntax-only -verify=expected,novsx -std=c++11 %s
-// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify=expected,nonaix -std=c++11 %s
-// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify=expected,novsx -std=c++11 %s
-// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +vsx -target-cpu pwr7 -fsyntax-only -verify=expected,nonaix -std=c++11 %s
-// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature -vsx -target-cpu pwr7 -fsyntax-only -verify=expected,novsx -std=c++11 %s
-// RUN: %clang_cc1 -triple=powerpc-ibm-aix -target-feature +altivec -fsyntax-only -verify=expected,aix -std=c++11 %s
-// RUN: %clang_cc1 -triple=powerpc64-ibm-aix -target-feature +altivec -fsyntax-only -verify=expected,aix -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc-apple-darwin8 -Wno-deprecate-lax-vec-conv-all -target-feature +altivec -fsyntax-only -verify=expected,novsx -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -Wno-deprecate-lax-vec-conv-all -target-feature +altivec -target-feature +vsx -fsyntax-only -verify=expected,nonaix -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -Wno-deprecate-lax-vec-conv-all -target-feature +altivec -fsyntax-only -verify=expected,novsx -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -Wno-deprecate-lax-vec-conv-all -target-feature +vsx -target-cpu pwr7 -fsyntax-only -verify=expected,nonaix -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -Wno-deprecate-lax-vec-conv-all -target-feature -vsx -target-cpu pwr7 -fsyntax-only -verify=expected,novsx -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc-ibm-aix -Wno-deprecate-lax-vec-conv-all -target-feature +altivec -fsyntax-only -verify=expected,aix -std=c++11 %s
+// RUN: %clang_cc1 -triple=powerpc64-ibm-aix -Wno-deprecate-lax-vec-conv-all -target-feature +altivec -fsyntax-only -verify=expected,aix -std=c++11 %s
 #include 
 
 __vector char vv_c;
Index: clang/lib/Sema/SemaOverload.cpp
===
--- clang/lib/Sema/SemaOverload.cpp
+++ clang/lib/Sema/SemaOverload.cpp
@@ -1617,8 +1617,9 @@
 ///
 /// \param ICK Will be set to the vector conversion kind, if this is a vector
 /// conversion.
-static bool IsVectorConversion(Sema &S, QualType FromType,
-   QualType ToType, ImplicitConversionKind &ICK) {
+static bool IsVectorConversion(Sema &S, QualType FromType, QualType ToType,
+   ImplicitConversionKind &ICK, Expr *From,
+   bool InOverloadResolution) {
   // We need at least one of these types to be a vector type to have a vector
   // conversion.
   if (!ToType->isVectorType() && !FromType->isVectorType())
@@ -1660,6 +1661,13 @@
 if (S.Context.areCompatibleVectorTypes(FromType, ToType) ||
 (S.isLaxVectorConversion(FromType, ToType) &&
  !ToType->hasAttr(attr::ArmMveStrictPolymorphism))) {
+  if (S.isLaxVectorConversion(FromType, ToType) &&
+  S.anyAltivecTypes(FromType, ToType) &&
+  !S.areSameVectorElemTypes(FromType, ToType) &&
+  !InOverloadResolution) {
+S.Diag(From->getBeginLoc(), diag::warn_deprecated_lax_vec_conv_all)
+<< FromType << ToType;
+  }
   ICK = ICK_Vector_Conversion;
   return true;
 }
@@ -1908,7 +1916,8 @@
  InOverloadResolution, FromType)) {
 // Pointer to member conversions (4.11).
 SCS.Second = ICK_Pointer_Member;
-  } else if (IsVectorConversion(S, FromType, ToType, SecondICK)) {
+  } else if (IsVectorConversion(S, FromType, ToType, SecondICK, From,
+InOverloadResolution)) {
 SCS.Second = SecondICK;
 FromType = ToType.getUnqualifiedType();
   } else if (!S.getLangOpts().CPlusPlus &&
Index: clang/lib/Sema/SemaExpr.cpp
===
--- clang/lib/Sema/SemaExpr.cpp
+

[PATCH] D124093: [PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions

[Lei Huang via Phabricator via cfe-commits]

lei marked an inline comment as not done.
lei added inline comments.



Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c:8
 // RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck %s
-// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec 
-target-feature +vsx \
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers 
-target-feature +altivec -target-feature +vsx \
 // RUN:   -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \

nemanjai wrote:
> I don't know why only one of the functions below has checks for this run 
> line, but that needs to be fixed. Please add the `NOCOMPAT` checks on the 
> other functions.
Can we address this on a followup patch? Since it's not related to the work 
here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124093/new/

https://reviews.llvm.org/D124093

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Sema/SemaExpr.cpp:7738
+// This returns true if both vectors have the same element type.
+bool Sema::areVectorTypesSameElmType(QualType SrcTy, QualType DestTy) {
+  assert((DestTy->isVectorType() || SrcTy->isVectorType()) &&

lei wrote:
> rename suggestion: haveSameVectorElemTypes()
> rename suggestion: haveSameVectorElemTypes()

actually maybe this:  areSameVectorElemTypes()


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126540/new/

https://reviews.llvm.org/D126540

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Sema/SemaExpr.cpp:7716
+// This returns true if at least one of the types is an altivec vector.
+bool Sema::areAnyVectorTypesAltivec(QualType SrcTy, QualType DestTy) {
+  assert((DestTy->isVectorType() || SrcTy->isVectorType()) &&

maybe rename to `anyAltivecTypes()`?



Comment at: clang/lib/Sema/SemaExpr.cpp:7738
+// This returns true if both vectors have the same element type.
+bool Sema::areVectorTypesSameElmType(QualType SrcTy, QualType DestTy) {
+  assert((DestTy->isVectorType() || SrcTy->isVectorType()) &&

rename suggestion: haveSameVectorElemTypes()


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126540/new/

https://reviews.llvm.org/D126540

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

LGTM, just a few nit that can be addressed on commit.




Comment at: clang/lib/Sema/SemaExpr.cpp:7723
+
+  if (SrcTy->isVectorType()) {
+VectorType::VectorKind SrcVecKind =

do we really need this check since we have an assert above?



Comment at: clang/lib/Sema/SemaExpr.cpp:7726
+SrcTy->castAs()->getVectorKind();
+isSrcTyAltivec = (SrcVecKind == VectorType::AltiVecVector);
+  }

I don't think the initialization above is needed.  Can just inline it here.
```
  bool  isSrcTyAltivec = (SrcVecKind == VectorType::AltiVecVector);
```



Comment at: clang/lib/Sema/SemaExpr.cpp:7728
+  }
+  if (DestTy->isVectorType()) {
+VectorType::VectorKind DestVecKind =

same.



Comment at: clang/lib/Sema/SemaExpr.cpp:7731
+DestTy->castAs()->getVectorKind();
+isDestTyAltivec = (DestVecKind == VectorType::AltiVecVector);
+  }

same.



Comment at: clang/lib/Sema/SemaExpr.cpp:7715
 
+bool Sema::areAnyVectorTypesAltivec(QualType SrcTy, QualType DestTy) {
+  assert(DestTy->isVectorType() || SrcTy->isVectorType());

maryammo wrote:
> lei wrote:
> > maryammo wrote:
> > > amyk wrote:
> > > > Can we add some brief documentation for this function, like what is 
> > > > done for other functions in this file?
> > > sure
> > feels like this should be written to just take either 1 param or multiple 
> > params via vararg.. since the 2 arg are not really related in any way.
> I am not sure what you mean, can you please elaborate on that?
actually ignore that comment. I see why you need this now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126540/new/

https://reviews.llvm.org/D126540

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

Please document all new functions added.




Comment at: clang/lib/Sema/SemaExpr.cpp:7715
 
+bool Sema::areAnyVectorTypesAltivec(QualType SrcTy, QualType DestTy) {
+  assert(DestTy->isVectorType() || SrcTy->isVectorType());

amyk wrote:
> Can we add some brief documentation for this function, like what is done for 
> other functions in this file?
feels like this should be written to just take either 1 param or multiple 
params via vararg.. since the 2 arg are not really related in any way.



Comment at: clang/lib/Sema/SemaExpr.cpp:9567
+  if (areAnyVectorTypesAltivec(RHSType, LHSType) &&
+ !areVectorTypesSameElmType(RHSType, LHSType))
+Diag(RHS.get()->getExprLoc(), 
diag::warn_deprecated_lax_vec_conv_all)

clang-format



Comment at: clang/lib/Sema/SemaExpr.cpp:10519
+  if (areAnyVectorTypesAltivec(RHSType, LHSType) &&
+ !areVectorTypesSameElmType(RHSType, LHSType))
+Diag(Loc, diag::warn_deprecated_lax_vec_conv_all) << RHSType << 
LHSType;

clang-format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126540/new/

https://reviews.llvm.org/D126540

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125506: [PowerPC] Implement XL compat __fnabs and __fnabss builtins.

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:46
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+declare double @llvm.ppc.fnabs(double)

nit: same as before no need to test all combination for both pwr7 and pwr8.  
Just a mix of the 2 like in the clang test. What happens if we do pwr6 with 
`+vsx`?  Is this a possible combination?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125506/new/

https://reviews.llvm.org/D125506

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125506: [PowerPC] Implement XL compat __fnabs and __fnabss builtins.

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.
This revision is now accepted and ready to land.

LGTM with minor updates before commit.




Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c:25
+// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
+

Since we emit `xsnabsdp` for pwr7 and above I don't think it's necessary to 
have all combination tested on both pwr7 and pwr8.




Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:24
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX

I think the default pwr level is lower then pwr6 which means it's no vsx by 
default.  Maybe add `pwr[7|8]` to these test lines to test the `-vsx` attr?



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:45
+; CHECK-PWR6-NEXT:fnabs 1, 1
+; CHECK-PWR6-NEXT:blr
+;

probably don't need both NOVSX and PWR6 checks since they are the same.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125506/new/

https://reviews.llvm.org/D125506

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D120907: [docs] Add PowerPC release notes for LLVM 14

[Lei Huang via Phabricator via cfe-commits]

lei closed this revision.
lei added a comment.

Commited to release/14.x


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120907/new/

https://reviews.llvm.org/D120907

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D120907: [docs] Add PowerPC release notes for LLVM 14

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

In D120907#3357433 , @ldionne wrote:

> LGTM for libc++. I assume this is targeting `release/14.x` only.

yes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120907/new/

https://reviews.llvm.org/D120907

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D120907: [docs] Add PowerPC release notes for LLVM 14

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 412710.
lei added a comment.

remove unintented change


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120907/new/

https://reviews.llvm.org/D120907

Files:
  clang/docs/ReleaseNotes.rst
  libcxx/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst

Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -105,7 +105,31 @@
 Changes to the PowerPC Target
 -
 
-During this release ...
+Linux improvements:
+* Provided a number of builtins for compatibility with the XL compiler.
+* Allow MMA builtin types in pre-P10 compilation units.
+* Add support for Return Oriented Programming (ROP) protection for 32 bit.
+* Refactored code to use more inclusive language.
+* Switched to LLD as the default linker for pre-built Linux binaries.
+* Enabled IEEE quad long double on Linux via ``PPC_LINUX_DEFAULT_IEEELONGDOUBLE``
+  in cmake config.
+  * Added ``__ibm128`` type to represent IBM double-double format, also available
+as ``__attribute__((mode(IF)))``.
+  * ``-mfloat128`` can now be used in Linux subtargets with VSX enabled.
+* Added quadword atomic load/store support in codegen; not enabled by default.
+* Codegen improvements for splat load, byval parameter, stack lowering, etc.
+* Implemented P10 instruction scheduling model.
+* Implemented P10 instruction fusion pairs.
+* Improved handling of ``#pragma clang loop unroll_and_jam``.
+* Various bug fixes.
+
+AIX Support/improvements:
+* variadic (ellipsis) functions with C complex types are now supported.
+* Added toc-data support for AIX 64-bit.
+* Added toc-data support for read-only globals.
+* Updated default target on AIX from pwr4 to pwr7.
+* AIX 64-bit now use fast-isel for O0.
+* Added DWARF support for 32-bit XCOFF.
 
 Changes to the X86 Target
 -
@@ -224,6 +248,13 @@
 * llvm-readobj now supports several dump styles (``--needed-libs, --relocs, --syms``) for XCOFF.
 * llvm-symbolizer now supports `--debuginfod `.
   (`D113717 `_)
+* ``llvm-cov`` now accepts "allowlist" spelling for ``-name-allowlist``.
+* ``llvm-nm`` now supports XCOFF object files.
+* Added ``--needed-libs``, aux header, and symbols support in ``llvm-readobj``.
+* Added ``--symbolize-operands`` support in ``llvm-objdump``.
+* Tools that read archive files now support reading AIX big format archive files.
+* Added dump section support in ``obj2yaml``.
+* Added ``yaml2obj`` support for 64-bit XCOFF.
 
 Changes to LLDB
 -
Index: libcxx/docs/ReleaseNotes.rst
===
--- libcxx/docs/ReleaseNotes.rst
+++ libcxx/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@
 - More C++2b features have been implemented. :doc:`Status/Cxx2b` has the full
   overview of libc++'s C++2b implementation status.
 
+- 16-bit ``wchar_t`` handling added for ``codecvt_utf8``, ``codecvt_utf16`` and
+  ``codecvt_utf8_utf16``.
+
 API Changes
 ---
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -51,7 +51,19 @@
   For more details refer to :ref:`the SPIR-V support section `.
 - Completed support of OpenCL C 3.0 and C++ for OpenCL 2021 at experimental
   state.
--  ...
+
+- Prebuilt AIX7.2 TL5 SP3+ binary available with following notes and
+  limitations:
+  - C++ driver modes use the system libc++ headers. These headers are included
+in the optional ``libc++.adt.include`` fileset on AIX.
+  - LTO, although not disabled, is not recommended.
+  - Shared libraries builds (``-shared``) must use explicit symbol export
+options and/or export lists (e.g., with ``-bE:``) on the link step. Clang
+currently will not automatically generate symbol export lists as implicit
+linker inputs.
+
+- ``float.h`` now exposes (in hosted mode) extensions made available from the
+  AIX system header.
 
 Improvements to Clang's diagnostics
 ^^^
@@ -79,6 +91,9 @@
 - The ``-E -P`` preprocessor output now always omits blank lines, matching
   gcc behaviour. Previously, up to 8 consecutive blank lines could appear
   in the output.
+- AIX platform-related predefined macros added:
+  ``_ARCH_PPC64``, ``__HOS_AIX__``, ``__PPC``, ``__THW_BIG_ENDIAN__``,
+  ``__THW_PPC__``, and ``__powerpc``
 
 New Compiler Flags
 --
@@ -103,6 +118,8 @@
   for `ccache `_ and
   `sccache `_ are under review.
 
+- Clang now accepts "allowlist" spelling for ``-objcmt-allowlist-dir-path``.
+
 Deprecated Compiler Flags
 -
 
@@ -169,6 +186,8 @@
   attributes, but will no

[PATCH] D120907: [docs] Add PowerPC release notes for LLVM 14

[Lei Huang via Phabricator via cfe-commits]

lei created this revision.
lei added reviewers: hubert.reinterpretcast, nemanjai, jsji.
Herald added a subscriber: shchenz.
Herald added a project: All.
lei requested review of this revision.
Herald added projects: clang, libc++, LLVM.
Herald added subscribers: llvm-commits, libcxx-commits, cfe-commits.
Herald added a reviewer: libc++.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120907

Files:
  clang/docs/ReleaseNotes.rst
  libcxx/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst

Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -100,12 +100,36 @@
 Changes to the Hexagon Target
 -
 
-* ...
+During this release ...
 
 Changes to the PowerPC Target
 -
 
-During this release ...
+Linux improvements:
+* Provided a number of builtins for compatibility with the XL compiler.
+* Allow MMA builtin types in pre-P10 compilation units.
+* Add support for Return Oriented Programming (ROP) protection for 32 bit.
+* Refactored code to use more inclusive language.
+* Switched to LLD as the default linker for pre-built Linux binaries.
+* Enabled IEEE quad long double on Linux via ``PPC_LINUX_DEFAULT_IEEELONGDOUBLE``
+  in cmake config.
+  * Added ``__ibm128`` type to represent IBM double-double format, also available
+as ``__attribute__((mode(IF)))``.
+  * ``-mfloat128`` can now be used in Linux subtargets with VSX enabled.
+* Added quadword atomic load/store support in codegen; not enabled by default.
+* Codegen improvements for splat load, byval parameter, stack lowering, etc.
+* Implemented P10 instruction scheduling model.
+* Implemented P10 instruction fusion pairs.
+* Improved handling of ``#pragma clang loop unroll_and_jam``.
+* Various bug fixes.
+
+AIX Support/improvements:
+* variadic (ellipsis) functions with C complex types are now supported.
+* Added toc-data support for AIX 64-bit.
+* Added toc-data support for read-only globals.
+* Updated default target on AIX from pwr4 to pwr7.
+* AIX 64-bit now use fast-isel for O0.
+* Added DWARF support for 32-bit XCOFF.
 
 Changes to the X86 Target
 -
@@ -224,6 +248,13 @@
 * llvm-readobj now supports several dump styles (``--needed-libs, --relocs, --syms``) for XCOFF.
 * llvm-symbolizer now supports `--debuginfod `.
   (`D113717 `_)
+* ``llvm-cov`` now accepts "allowlist" spelling for ``-name-allowlist``.
+* ``llvm-nm`` now supports XCOFF object files.
+* Added ``--needed-libs``, aux header, and symbols support in ``llvm-readobj``.
+* Added ``--symbolize-operands`` support in ``llvm-objdump``.
+* Tools that read archive files now support reading AIX big format archive files.
+* Added dump section support in ``obj2yaml``.
+* Added ``yaml2obj`` support for 64-bit XCOFF.
 
 Changes to LLDB
 -
Index: libcxx/docs/ReleaseNotes.rst
===
--- libcxx/docs/ReleaseNotes.rst
+++ libcxx/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@
 - More C++2b features have been implemented. :doc:`Status/Cxx2b` has the full
   overview of libc++'s C++2b implementation status.
 
+- 16-bit ``wchar_t`` handling added for ``codecvt_utf8``, ``codecvt_utf16`` and
+  ``codecvt_utf8_utf16``.
+
 API Changes
 ---
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -51,7 +51,19 @@
   For more details refer to :ref:`the SPIR-V support section `.
 - Completed support of OpenCL C 3.0 and C++ for OpenCL 2021 at experimental
   state.
--  ...
+
+- Prebuilt AIX7.2 TL5 SP3+ binary available with following notes and
+  limitations:
+  - C++ driver modes use the system libc++ headers. These headers are included
+in the optional ``libc++.adt.include`` fileset on AIX.
+  - LTO, although not disabled, is not recommended.
+  - Shared libraries builds (``-shared``) must use explicit symbol export
+options and/or export lists (e.g., with ``-bE:``) on the link step. Clang
+currently will not automatically generate symbol export lists as implicit
+linker inputs.
+
+- ``float.h`` now exposes (in hosted mode) extensions made available from the
+  AIX system header.
 
 Improvements to Clang's diagnostics
 ^^^
@@ -79,6 +91,9 @@
 - The ``-E -P`` preprocessor output now always omits blank lines, matching
   gcc behaviour. Previously, up to 8 consecutive blank lines could appear
   in the output.
+- AIX platform-related predefined macros added:
+  ``_ARCH_PPC64``, ``__HOS_AIX__``, ``__PPC``, ``__THW_BIG_ENDIAN__``,
+  ``__THW_PPC__``, and ``__powerpc``
 
 New Compiler Flags
 --
@@ -103,6 +118,8 @@
   for `ccache 

[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.

LGTM
I think you went a bit overkill with the tests for this patch 🙂.  Please cut 
down the number of run lines before committing.




Comment at: clang/test/Driver/ppc-p10-features-support-check.c:4
+// RUN:   --check-prefix=HASPAIRED
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mpaired-vector-memops %s -o - | FileCheck %s \

I think you can just use `pwr10` and `power10` in diff run lines if you need, 
but no need to test for both in this case.



Comment at: clang/test/Driver/ppc-p10-features-support-check.c:11
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED

might be an overkill to also test for pwr7/8.  I think pwr9/10 test is enough.



Comment at: clang/test/Driver/ppc-p10-features-support-check.c:19
+// RUN:   --check-prefix=NOPAIRED
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \

same comment for the set of runlines below.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109652/new/

https://reviews.llvm.org/D109652

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

[Lei Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8b3d944a97cc: [PowerPC] Disable vector types when not 
supported by subtarget features (authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109178/new/

https://reviews.llvm.org/D109178

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Headers/altivec.h
  clang/lib/Sema/DeclSpec.cpp
  clang/test/CodeGen/builtins-ppc-int128.c
  clang/test/CodeGen/builtins-ppc-vsx.c
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/altivec.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/cxx-altivec.cpp
  clang/test/Sema/altivec-generic-overload.c
  clang/test/Sema/builtins-ppc.c

Index: clang/test/Sema/builtins-ppc.c
===
--- clang/test/Sema/builtins-ppc.c
+++ clang/test/Sema/builtins-ppc.c
@@ -6,6 +6,9 @@
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto\
 // RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only  \
 // RUN: -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto \
+// RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only \
+// RUN: -target-feature +vsx -verify %s
 
 #ifdef TEST_HTM
 void test_htm() {
@@ -37,6 +40,7 @@
   return __builtin_crypto_vshasigmaw(a, 1, 15);
 }
 
+#ifdef __VSX__
 vector unsigned long long test_vshasigmad_or(void)
 {
   vector unsigned long long a = D_INIT
@@ -46,6 +50,7 @@
   vector unsigned long long e = __builtin_crypto_vshasigmad(a, 1, -15); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   return __builtin_crypto_vshasigmad(a, 0, 15);
 }
+#endif
 
 #endif
 
Index: clang/test/Sema/altivec-generic-overload.c
===
--- clang/test/Sema/altivec-generic-overload.c
+++ clang/test/Sema/altivec-generic-overload.c
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only \
+// RUN:  -target-cpu pwr8
 
 typedef signed char __v16sc __attribute__((__vector_size__(16)));
 typedef unsigned char __v16uc __attribute__((__vector_size__(16)));
@@ -20,9 +24,6 @@
 __v4si *__attribute__((__overloadable__)) convert1(vector signed int);
 __v4ui *__attribute__((__overloadable__)) convert1(vector unsigned int);
 __v2sll *__attribute__((__overloadable__)) convert1(vector signed long long);
-__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
-__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
-__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
 __v4f *__attribute__((__overloadable__)) convert1(vector float);
 __v2d *__attribute__((__overloadable__)) convert1(vector double);
 void __attribute__((__overloadable__)) convert1(vector bool int);
@@ -36,11 +37,17 @@
 vector unsigned int *__attribute__((__overloadable__)) convert2(__v4ui);
 vector signed long long *__attribute__((__overloadable__)) convert2(__v2sll);
 vector unsigned long long *__attribute__((__overloadable__)) convert2(__v2ull);
-vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
-vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
 vector float *__attribute__((__overloadable__)) convert2(__v4f);
 vector double *__attribute__((__overloadable__)) convert2(__v2d);
 
+#ifdef __POWER8_VECTOR__
+__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
+__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
+__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
+vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
+vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
+#endif
+
 void test() {
   __v16sc gv1;
   __v16uc gv2;
@@ -49,11 +56,14 @@
   __v4si gv5;
   __v4ui gv6;
   __v2sll gv7;
+  __v4f gv11;
+  __v2d gv12;
+
+#ifdef __POWER8_VECTOR__
   __v2ull gv8;
   __v1slll gv9;
   __v1ulll gv10;
-  __v4f gv11;
-  __v2d gv12;
+#endif
 
   vector signed char av1;
   vector unsigned char av2;
@@ -63,8 +73,10 @@
   vector unsigned int av6;
   vector signed long long av7;
   vector unsigned long long av8;
+#ifdef __POWER8_VECTOR__
   vector signed __int128 av9;
   vector unsigned __int128 av10;
+#endif
   vector float av11;
   vect

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 376969.
lei added a comment.

address line comment and update tc to reflect new behaviour.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109178/new/

https://reviews.llvm.org/D109178

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Headers/altivec.h
  clang/lib/Sema/DeclSpec.cpp
  clang/test/CodeGen/builtins-ppc-int128.c
  clang/test/CodeGen/builtins-ppc-vsx.c
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/altivec.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/cxx-altivec.cpp
  clang/test/Sema/altivec-generic-overload.c
  clang/test/Sema/builtins-ppc.c

Index: clang/test/Sema/builtins-ppc.c
===
--- clang/test/Sema/builtins-ppc.c
+++ clang/test/Sema/builtins-ppc.c
@@ -6,6 +6,9 @@
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto\
 // RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only  \
 // RUN: -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto \
+// RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only \
+// RUN: -target-feature +vsx -verify %s
 
 #ifdef TEST_HTM
 void test_htm() {
@@ -37,6 +40,7 @@
   return __builtin_crypto_vshasigmaw(a, 1, 15);
 }
 
+#ifdef __VSX__
 vector unsigned long long test_vshasigmad_or(void)
 {
   vector unsigned long long a = D_INIT
@@ -46,6 +50,7 @@
   vector unsigned long long e = __builtin_crypto_vshasigmad(a, 1, -15); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   return __builtin_crypto_vshasigmad(a, 0, 15);
 }
+#endif
 
 #endif
 
Index: clang/test/Sema/altivec-generic-overload.c
===
--- clang/test/Sema/altivec-generic-overload.c
+++ clang/test/Sema/altivec-generic-overload.c
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only \
+// RUN:  -target-cpu pwr8
 
 typedef signed char __v16sc __attribute__((__vector_size__(16)));
 typedef unsigned char __v16uc __attribute__((__vector_size__(16)));
@@ -20,9 +24,6 @@
 __v4si *__attribute__((__overloadable__)) convert1(vector signed int);
 __v4ui *__attribute__((__overloadable__)) convert1(vector unsigned int);
 __v2sll *__attribute__((__overloadable__)) convert1(vector signed long long);
-__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
-__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
-__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
 __v4f *__attribute__((__overloadable__)) convert1(vector float);
 __v2d *__attribute__((__overloadable__)) convert1(vector double);
 void __attribute__((__overloadable__)) convert1(vector bool int);
@@ -36,11 +37,17 @@
 vector unsigned int *__attribute__((__overloadable__)) convert2(__v4ui);
 vector signed long long *__attribute__((__overloadable__)) convert2(__v2sll);
 vector unsigned long long *__attribute__((__overloadable__)) convert2(__v2ull);
-vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
-vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
 vector float *__attribute__((__overloadable__)) convert2(__v4f);
 vector double *__attribute__((__overloadable__)) convert2(__v2d);
 
+#ifdef __POWER8_VECTOR__
+__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
+__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
+__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
+vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
+vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
+#endif
+
 void test() {
   __v16sc gv1;
   __v16uc gv2;
@@ -49,11 +56,14 @@
   __v4si gv5;
   __v4ui gv6;
   __v2sll gv7;
+  __v4f gv11;
+  __v2d gv12;
+
+#ifdef __POWER8_VECTOR__
   __v2ull gv8;
   __v1slll gv9;
   __v1ulll gv10;
-  __v4f gv11;
-  __v2d gv12;
+#endif
 
   vector signed char av1;
   vector unsigned char av2;
@@ -63,8 +73,10 @@
   vector unsigned int av6;
   vector signed long long av7;
   vector unsigned long long av8;
+#ifdef __POWER8_VECTOR__
   vector signed __int128 av9;
   vector unsigned __int128 av10;
+#endif
   vector float av11;
   vector double av12;
   vector bool int av13;
@@ -77,9 +89,11 @@
   __v4si *gv5_p = convert1(gv5);
   __v4ui *gv6_p = convert1(gv6);
 

[PATCH] D107899: [PowerPC] Implement builtin for vbpermd

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: clang/lib/Headers/altivec.h:17337
 static __inline__ vector long long __ATTRS_o_ai
 vec_vbpermq(vector unsigned char __a, vector unsigned char __b) {
   return __builtin_altivec_vbpermq(__a, __b);

bmahjour wrote:
> This should be guarded under P8. It would also be good to add a 
> `vec_vbpermd(vector unsigned long long ...)` counter part under 
> `__POWER9_VECTOR__` for consistency.
I think this is actually guarded under ` __POWER8_VECTOR__`.  See line 17237.
As far as I can see, there is no LLVM intrinsic corresponding to vbpermd.



Comment at: clang/lib/Headers/altivec.h:17352
+}
+#endif
+#ifdef __POWER9_VECTOR__

nit: It would be more clear if we had a comment here what this endif if for.  I 
assume it's `/* __POWER8_VECTOR__ */`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107899/new/

https://reviews.llvm.org/D107899

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 375360.
lei added a comment.

Address review comments and add handling for vector long types without vsx.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109178/new/

https://reviews.llvm.org/D109178

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Headers/altivec.h
  clang/lib/Sema/DeclSpec.cpp
  clang/test/CodeGen/builtins-ppc-int128.c
  clang/test/CodeGen/builtins-ppc-vsx.c
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/altivec.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/cxx-altivec.cpp
  clang/test/Sema/altivec-generic-overload.c
  clang/test/Sema/builtins-ppc.c

Index: clang/test/Sema/builtins-ppc.c
===
--- clang/test/Sema/builtins-ppc.c
+++ clang/test/Sema/builtins-ppc.c
@@ -6,6 +6,9 @@
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto\
 // RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only  \
 // RUN: -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto \
+// RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only \
+// RUN: -target-feature +vsx -verify %s
 
 #ifdef TEST_HTM
 void test_htm() {
@@ -37,6 +40,7 @@
   return __builtin_crypto_vshasigmaw(a, 1, 15);
 }
 
+#ifdef __VSX__
 vector unsigned long long test_vshasigmad_or(void)
 {
   vector unsigned long long a = D_INIT
@@ -46,6 +50,7 @@
   vector unsigned long long e = __builtin_crypto_vshasigmad(a, 1, -15); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   return __builtin_crypto_vshasigmad(a, 0, 15);
 }
+#endif
 
 #endif
 
Index: clang/test/Sema/altivec-generic-overload.c
===
--- clang/test/Sema/altivec-generic-overload.c
+++ clang/test/Sema/altivec-generic-overload.c
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only \
+// RUN:  -target-cpu pwr8
 
 typedef signed char __v16sc __attribute__((__vector_size__(16)));
 typedef unsigned char __v16uc __attribute__((__vector_size__(16)));
@@ -20,9 +24,6 @@
 __v4si *__attribute__((__overloadable__)) convert1(vector signed int);
 __v4ui *__attribute__((__overloadable__)) convert1(vector unsigned int);
 __v2sll *__attribute__((__overloadable__)) convert1(vector signed long long);
-__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
-__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
-__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
 __v4f *__attribute__((__overloadable__)) convert1(vector float);
 __v2d *__attribute__((__overloadable__)) convert1(vector double);
 void __attribute__((__overloadable__)) convert1(vector bool int);
@@ -36,11 +37,17 @@
 vector unsigned int *__attribute__((__overloadable__)) convert2(__v4ui);
 vector signed long long *__attribute__((__overloadable__)) convert2(__v2sll);
 vector unsigned long long *__attribute__((__overloadable__)) convert2(__v2ull);
-vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
-vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
 vector float *__attribute__((__overloadable__)) convert2(__v4f);
 vector double *__attribute__((__overloadable__)) convert2(__v2d);
 
+#ifdef __POWER8_VECTOR__
+__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
+__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
+__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
+vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
+vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
+#endif
+
 void test() {
   __v16sc gv1;
   __v16uc gv2;
@@ -49,11 +56,14 @@
   __v4si gv5;
   __v4ui gv6;
   __v2sll gv7;
+  __v4f gv11;
+  __v2d gv12;
+
+#ifdef __POWER8_VECTOR__
   __v2ull gv8;
   __v1slll gv9;
   __v1ulll gv10;
-  __v4f gv11;
-  __v2d gv12;
+#endif
 
   vector signed char av1;
   vector unsigned char av2;
@@ -63,8 +73,10 @@
   vector unsigned int av6;
   vector signed long long av7;
   vector unsigned long long av8;
+#ifdef __POWER8_VECTOR__
   vector signed __int128 av9;
   vector unsigned __int128 av10;
+#endif
   vector float av11;
   vector double av12;
   vector bool int av13;
@@ -77,9 +89,11 @@
   __v4si *gv5_p = convert1(gv5);
   __v4ui *gv6_p = c

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.

LGTM
Pleases address nit on commit.




Comment at: clang/lib/Sema/SemaChecking.cpp:3495-3496
+ArgType != QualType(Context.DoubleTy)) {
+  Diag(TheCall->getBeginLoc(), diag::err_ppc_invalid_test_data_class_type);
+  return true;
+}

nit: I think these 2 stmts can just be merged into `return Diag();` and 
brace removed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Lei Huang via Phabricator via cfe-commits]

lei requested changes to this revision.
lei added inline comments.
This revision now requires changes to proceed.



Comment at: clang/include/clang/Sema/Sema.h:12680
   bool CheckPPCMMAType(QualType Type, SourceLocation TypeLoc);
+  bool CheckPPCTestDataClassType(CallExpr *TheCall);
 

need to remove.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:16039-16040
+  case PPC::BI__builtin_ppc_test_data_class:
+Value *ArgValue = EmitScalarExpr(E->getArg(0));
+llvm::Type *ArgType = ArgValue->getType();
+unsigned Int;

`ArgValue` is only used one so not needed. 
```
llvm::Type *ArgType = EmitScalarExpr(E->getArg(0))->getType();
```




Comment at: clang/lib/CodeGen/CGBuiltin.cpp:16041
+llvm::Type *ArgType = ArgValue->getType();
+unsigned Int;
+if (ArgType->isDoubleTy()) {

variables should be discriptive of what they represent.  This is no diff then a 
single char variable 🙂
```
unsigned IntrinsicID;
```



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:16042
+unsigned Int;
+if (ArgType->isDoubleTy()) {
+  Int = Intrinsic::ppc_test_data_class_d;

braces here are redundant.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:16050
+Function *F = CGM.getIntrinsic(Int);
+return Builder.CreateCall(F, Ops, "test_data_class");
   }

Try to refrain from def one-time use variables.
```
return Builder.CreateCall(CGM.getIntrinsic(Int), Ops, "test_data_class");
```



Comment at: clang/lib/Sema/SemaChecking.cpp:3492
+  Diag(TheCall->getBeginLoc(), diag::err_ppc_invalid_test_data_class_type);
+  ArgTypeIsInvalid = true;
+}

I'm not sure this is needed... can't we just `return true` here since this is a 
`S` error?



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10382-10383
+switch (IntrinsicID) {
+default:
+  llvm_unreachable("Unknown Intrinsic");
+case Intrinsic::ppc_compare_exp_lt:

I dont' think this is needed since you will only be here if he IntrinsicID 
matches the lines listed prior to this block.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10397-10398
+}
+SDValue Op1 = Op.getOperand(1);
+SDValue Op2 = Op.getOperand(2);
+SDValue Ops[]{

one time used variables can be removed.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10408-10417
+switch (IntrinsicID) {
+default:
+  llvm_unreachable("Unknown Intrinsic");
+case Intrinsic::ppc_test_data_class_d:
+  CmprOpc = PPC::XSTSTDCDP;
+  break;
+case Intrinsic::ppc_test_data_class_f:

this can just be an if/else since you won't be in this block unless the 
IntrisicID are `ppc_test_data_class_[d|f]`
```
unsigned CmprOpc = PPC::XSTSTDCDP;
if (IntrinsicID == Intrinsic::ppc_test_data_class_f)
  CmprOpc = PPC::XSTSTDCSP;
```



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10419
+SDValue Op1 = Op.getOperand(2);
+SDValue Op2 = Op.getOperand(1);
+SDValue Ops[]{

one-time use variable.  Can be merged into the call below.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM
Please add comment to tc upon commit.




Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:1417
 
+vector signed int test_vec_vec_splati_ins_range(void) {
+  // CHECK-BE: [[T0:%.+]] = and i32 %{{.+}}, 1

nit: pleases add a comment here explaining behaviour for when param 2 is out of 
expected value range.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.
This revision is now accepted and ready to land.

LGTM once the code is simplified as Nemanja suggested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM.
Pleases address the test issue on commit.




Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c:13
+int testdarn_32(void) {
+  return __darn_32();
+}

Isn't this valid for both 32 and 64bit?
Maybe change one of the run lines above to a 64bit test.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110282/new/

https://reviews.llvm.org/D110282

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D110084: [PowerPC] Support for vector bool int128 on vector comparison builtins

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM
thx


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110084/new/

https://reviews.llvm.org/D110084

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:1414
   // CHECK-LE: ret <4 x float>
   return vec_splati_ins(vfa, 0, 1.0f);
 }

Need to add a testcase where param `b` to `vec_splati_ins(a,b,c)` is not 0 or 1.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109710/new/

https://reviews.llvm.org/D109710

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3518
+// valid. The argument must be either a 'float' or a 'double'.
+bool Sema::CheckPPCTestDataClassType(CallExpr *TheCall) {
+  QualType ArgType = TheCall->getArg(0)->getType();

I don't think this need to be function in the Sema class.  It can just be a 
static function.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10390
+  case Intrinsic::ppc_test_data_class_d:
+  case Intrinsic::ppc_test_data_class_f: {
+unsigned CmprOpc = PPC::XSCMPEXPDP;

I think it'll be more clear if you move `ppc_test_data-*` handling out of this 
case stmt and move them into their own since they don't use the same `CmprOpc` 
or `Op[1|2]` as the other instrinsics.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108823: [PowerPC] Mark splat immediate instructions as rematerializable

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM
Thx.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108823/new/

https://reviews.llvm.org/D108823

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.

LGTM.
Thx!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109780/new/

https://reviews.llvm.org/D109780

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.

LTGM
Thx!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109996/new/

https://reviews.llvm.org/D109996

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:566-569
+  if (llvm::find(FeaturesVec, "+pcrel") != FeaturesVec.end()) {
+Diags.Report(diag::err_opt_not_valid_without_opt) << "-mpcrel"
+  << "-mprefixed";
+  }

I think this need more thought:
```
$ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
error: option '-mprefixed' cannot be specified without '-mcpu=pwr10'

$ clang -mcpu=pwr9 -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
```

For this, the first err makes not sense since both `-mprefixed` and `-mpcrel` 
is specified:
```
$ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
error: option '-mprefixed' cannot be specified without '-mcpu=pwr10'
```
Shouldn't it just give:
```
$ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
```


For this:
```
$ clang -mcpu=pwr9 -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
```
I think it's better if it says:
```
$ clang -mcpu=pwr9 -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109652/new/

https://reviews.llvm.org/D109652

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.
This revision is now accepted and ready to land.

LGTM
Thx!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108302/new/

https://reviews.llvm.org/D108302

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-int128.c:4
+// RUN:   -triple powerpc64-unknown-unknown -target-cpu pwr8 \
+// RUN:  -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \

NeHuang wrote:
> nit: indentation 
thx. Will fix before comit.



Comment at: clang/test/Parser/altivec.c:92
 // These should have errors.
+#ifndef __VSX__
 __vector double vv_d1;   // expected-error {{use of 'double' with 
'__vector' requires VSX support to be enabled (available on POWER7 or later)}}

NeHuang wrote:
> Will this patch also impact `vector double`?   If not, can we move `#ifndef 
> __VSX__` down below `vector double v_d2;`?  
This patch doesn't, but this is needed here since I added RUN line to test 
behavior for when VSX is enabled.  Note the test lines was not changed for 
`vector double`.



Comment at: clang/test/Parser/cxx-altivec.cpp:91
 
-// These should have errors.
+#ifndef __VSX__
+// These should have errors for non pwr7 vsx builds.

NeHuang wrote:
> same as above.
needed due to new RUN line added.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109178/new/

https://reviews.llvm.org/D109178

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 370349.
lei added a comment.

fix spelling in commit message.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109178/new/

https://reviews.llvm.org/D109178

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Headers/altivec.h
  clang/lib/Sema/DeclSpec.cpp
  clang/test/CodeGen/builtins-ppc-int128.c
  clang/test/CodeGen/builtins-ppc-vsx.c
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/altivec.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/cxx-altivec.cpp
  clang/test/Sema/altivec-generic-overload.c
  clang/test/Sema/builtins-ppc.c

Index: clang/test/Sema/builtins-ppc.c
===
--- clang/test/Sema/builtins-ppc.c
+++ clang/test/Sema/builtins-ppc.c
@@ -6,6 +6,9 @@
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto\
 // RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only  \
 // RUN: -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto \
+// RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only \
+// RUN: -target-feature +vsx -verify %s
 
 #ifdef TEST_HTM
 void test_htm() {
@@ -37,6 +40,7 @@
   return __builtin_crypto_vshasigmaw(a, 1, 15);
 }
 
+#ifdef __VSX__
 vector unsigned long long test_vshasigmad_or(void)
 {
   vector unsigned long long a = D_INIT
@@ -46,6 +50,7 @@
   vector unsigned long long e = __builtin_crypto_vshasigmad(a, 1, -15); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   return __builtin_crypto_vshasigmad(a, 0, 15);
 }
+#endif
 
 #endif
 
Index: clang/test/Sema/altivec-generic-overload.c
===
--- clang/test/Sema/altivec-generic-overload.c
+++ clang/test/Sema/altivec-generic-overload.c
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only \
+// RUN:  -target-cpu pwr8
 
 typedef signed char __v16sc __attribute__((__vector_size__(16)));
 typedef unsigned char __v16uc __attribute__((__vector_size__(16)));
@@ -20,9 +24,6 @@
 __v4si *__attribute__((__overloadable__)) convert1(vector signed int);
 __v4ui *__attribute__((__overloadable__)) convert1(vector unsigned int);
 __v2sll *__attribute__((__overloadable__)) convert1(vector signed long long);
-__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
-__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
-__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
 __v4f *__attribute__((__overloadable__)) convert1(vector float);
 __v2d *__attribute__((__overloadable__)) convert1(vector double);
 void __attribute__((__overloadable__)) convert1(vector bool int);
@@ -36,11 +37,17 @@
 vector unsigned int *__attribute__((__overloadable__)) convert2(__v4ui);
 vector signed long long *__attribute__((__overloadable__)) convert2(__v2sll);
 vector unsigned long long *__attribute__((__overloadable__)) convert2(__v2ull);
-vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
-vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
 vector float *__attribute__((__overloadable__)) convert2(__v4f);
 vector double *__attribute__((__overloadable__)) convert2(__v2d);
 
+#ifdef __POWER8_VECTOR__
+__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
+__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
+__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
+vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
+vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
+#endif
+
 void test() {
   __v16sc gv1;
   __v16uc gv2;
@@ -49,11 +56,14 @@
   __v4si gv5;
   __v4ui gv6;
   __v2sll gv7;
+  __v4f gv11;
+  __v2d gv12;
+
+#ifdef __POWER8_VECTOR__
   __v2ull gv8;
   __v1slll gv9;
   __v1ulll gv10;
-  __v4f gv11;
-  __v2d gv12;
+#endif
 
   vector signed char av1;
   vector unsigned char av2;
@@ -63,8 +73,10 @@
   vector unsigned int av6;
   vector signed long long av7;
   vector unsigned long long av8;
+#ifdef __POWER8_VECTOR__
   vector signed __int128 av9;
   vector unsigned __int128 av10;
+#endif
   vector float av11;
   vector double av12;
   vector bool int av13;
@@ -77,9 +89,11 @@
   __v4si *gv5_p = convert1(gv5);
   __v4ui *gv6_p = convert1(gv6);
   __v2sll *gv7_p = convert1(g

[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

[Lei Huang via Phabricator via cfe-commits]

lei created this revision.
lei added reviewers: hubert.reinterpretcast, nemanjai, power-llvm-team.
Herald added a subscriber: shchenz.
lei requested review of this revision.
Herald added a project: clang.

Update clang to treat vector unsigned long long and friends as invalid
for AlttiVec without VSX.

Reported in: https://bugs.llvm.org/show_bug.cgi?id=47782


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109178

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Headers/altivec.h
  clang/lib/Sema/DeclSpec.cpp
  clang/test/CodeGen/builtins-ppc-int128.c
  clang/test/CodeGen/builtins-ppc-vsx.c
  clang/test/Parser/altivec-bool-128.c
  clang/test/Parser/altivec.c
  clang/test/Parser/cxx-altivec-bool-128.cpp
  clang/test/Parser/cxx-altivec.cpp
  clang/test/Sema/altivec-generic-overload.c
  clang/test/Sema/builtins-ppc.c

Index: clang/test/Sema/builtins-ppc.c
===
--- clang/test/Sema/builtins-ppc.c
+++ clang/test/Sema/builtins-ppc.c
@@ -6,6 +6,9 @@
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto\
 // RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only  \
 // RUN: -verify %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +crypto \
+// RUN: -triple powerpc64le-unknown-unknown -DTEST_CRYPTO -fsyntax-only \
+// RUN: -target-feature +vsx -verify %s
 
 #ifdef TEST_HTM
 void test_htm() {
@@ -37,6 +40,7 @@
   return __builtin_crypto_vshasigmaw(a, 1, 15);
 }
 
+#ifdef __VSX__
 vector unsigned long long test_vshasigmad_or(void)
 {
   vector unsigned long long a = D_INIT
@@ -46,6 +50,7 @@
   vector unsigned long long e = __builtin_crypto_vshasigmad(a, 1, -15); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   return __builtin_crypto_vshasigmad(a, 0, 15);
 }
+#endif
 
 #endif
 
Index: clang/test/Sema/altivec-generic-overload.c
===
--- clang/test/Sema/altivec-generic-overload.c
+++ clang/test/Sema/altivec-generic-overload.c
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only
+// RUN: %clang_cc1 %s -triple=powerpc64le-unknown-linux -target-feature +altivec \
+// RUN:  -target-feature +vsx -verify -verify-ignore-unexpected=note -pedantic -fsyntax-only \
+// RUN:  -target-cpu pwr8
 
 typedef signed char __v16sc __attribute__((__vector_size__(16)));
 typedef unsigned char __v16uc __attribute__((__vector_size__(16)));
@@ -20,9 +24,6 @@
 __v4si *__attribute__((__overloadable__)) convert1(vector signed int);
 __v4ui *__attribute__((__overloadable__)) convert1(vector unsigned int);
 __v2sll *__attribute__((__overloadable__)) convert1(vector signed long long);
-__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
-__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
-__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
 __v4f *__attribute__((__overloadable__)) convert1(vector float);
 __v2d *__attribute__((__overloadable__)) convert1(vector double);
 void __attribute__((__overloadable__)) convert1(vector bool int);
@@ -36,11 +37,17 @@
 vector unsigned int *__attribute__((__overloadable__)) convert2(__v4ui);
 vector signed long long *__attribute__((__overloadable__)) convert2(__v2sll);
 vector unsigned long long *__attribute__((__overloadable__)) convert2(__v2ull);
-vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
-vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
 vector float *__attribute__((__overloadable__)) convert2(__v4f);
 vector double *__attribute__((__overloadable__)) convert2(__v2d);
 
+#ifdef __POWER8_VECTOR__
+__v1slll *__attribute__((__overloadable__)) convert1(vector signed __int128);
+__v1ulll *__attribute__((__overloadable__)) convert1(vector unsigned __int128);
+__v2ull *__attribute__((__overloadable__)) convert1(vector unsigned long long);
+vector signed __int128 *__attribute__((__overloadable__)) convert2(__v1slll);
+vector unsigned __int128 *__attribute__((__overloadable__)) convert2(__v1ulll);
+#endif
+
 void test() {
   __v16sc gv1;
   __v16uc gv2;
@@ -49,11 +56,14 @@
   __v4si gv5;
   __v4ui gv6;
   __v2sll gv7;
+  __v4f gv11;
+  __v2d gv12;
+
+#ifdef __POWER8_VECTOR__
   __v2ull gv8;
   __v1slll gv9;
   __v1ulll gv10;
-  __v4f gv11;
-  __v2d gv12;
+#endif
 
   vector signed char av1;
   vector unsigned char av2;
@@ -63,8 +73,10 @@
   vector unsigned int av6;
   vector signed long long av7;
   vector unsigned long long av8;
+#ifdef __POWER8_VECTOR__
   vector signed __int128 av9;
   vector unsigned __int128 av1

[PATCH] D109126: [PowerPC] [NFC] Add Big-Endian checks for existing MMA tests

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

Is it really necessary to add the BE checks in this patch if they are the same 
as LE checks?  Why not just add it later when there is a diff seen?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109126/new/

https://reviews.llvm.org/D109126

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15833
+  // without the need for the programmer to swap operands.
+  if (IsLE) {
+SmallVector RevOps;

doesn't look like we need the interm var `IsLE`. Just use the call directly 
within the if stmt.
```
if (getTarget().isLittleEndian()) {
```



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15835-15837
+unsigned NumVecs = 2;
+if (BuiltinID == PPC::BI__builtin_mma_build_acc)
+  NumVecs = 4;

```
unsigned NumVecs = (BuiltinID == PPC::BI__builtin_mma_build_acc) ? 4 : 2;



Comment at: clang/test/CodeGen/builtins-ppc-pair-mma.c:2
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future 
-emit-llvm %s -o - | FileCheck %s
 

future -> pwr10
We need to add BE tests.



Comment at: clang/test/Sema/ppc-pair-mma-types.c:2
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
 // RUN:   -target-cpu future %s -verify
 

this should be `-target-cpu pwer10` now.



Comment at: clang/test/Sema/ppc-pair-mma-types.c:2
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
 // RUN:   -target-cpu future %s -verify
 

lei wrote:
> this should be `-target-cpu pwer10` now.
Please add BE testing.



Comment at: clang/test/Sema/ppc-pair-mma-types.c:265
+  __builtin_mma_xvf64ger(&vq, vp3, vc);
+  *vpp = vp3;
+}

This looks like a dup of `testVPLocal()`.  Why not just add the new call line 
to that function right below the call to the deprecated function?




Comment at: clang/test/SemaCXX/ppc-pair-mma-types.cpp:2
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
 // RUN:   -fcxx-exceptions -target-cpu future %s -verify
 

please update to pwr10


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108702: [PowerPC][NFC] Rename P10 builtins vec_clrl, vec_clrr to vec_clr_first and vec_clr_last

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108702/new/

https://reviews.llvm.org/D108702

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[Lei Huang via Phabricator via cfe-commits]

lei requested changes to this revision.
lei added a comment.
This revision now requires changes to proceed.

I think there is something wrong with this diff cause there is no context 
available for `PPCInstrInfo.cpp`.




Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1548
+return false;
+  }
+

nit: no need for braces 



Comment at: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 
-verify-machineinstrs | FileCheck %s
+target datalayout = 
"E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"

I believe this affects AIX as well.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108302/new/

https://reviews.llvm.org/D108302

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG8930af45c35b: [PowerPC] Implement XL compatibility builtin 
__addex (authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,14 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will result in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will result in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
 
 void test_builtin_ppc_cmprb() {
   int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, 

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 366094.
lei added a comment.

Fix name of new warning message to be more accuratly represent the diagnostic.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,14 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will result in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will result in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
 
 void test_builtin_ppc_cmprb() {
   int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, -1); // expected-error {{argume

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 366062.
lei added a comment.

Update diag id


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,14 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will result in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will result in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
 
 void test_builtin_ppc_cmprb() {
   int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, -1); // expected-error {{argument value -1 is outside the valid range [0, 3]}}
+}
+
+#endif
Ind

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 365816.
lei added a comment.

Add -W flag to new warning message


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,14 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will result in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will result in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
 
 void test_builtin_ppc_cmprb() {
   int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, -1); // expected-error {{argument value -1 is outside the valid range [0, 3

[PATCH] D107647: [PowerPC] MMA - Remove deprecated built-ins and add new built-ins

[Lei Huang via Phabricator via cfe-commits]

lei requested changes to this revision.
lei added a comment.
This revision now requires changes to proceed.

Actually we should not be removing the deprecated bultins.  Just need to add 
the new ones.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107647: [PowerPC] MMA - Remove deprecated built-ins and add new built-ins

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

LGTM
Can we update the title and description to be more specific though?

  [PowerPC] MMA - Rename deprecated builtins mma_assemble_acc, vsx_assemble_pair
  
  Rename deprecated builtins :
   __builtin_mma_assemble_acc
   __builtin_vsx_assemble_pair
  
  To:
   __builtin_mma_build_acc
   __builtin_vsx_build_pair


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c:4
+// RUN:   -verify %s
+
+extern unsigned long long ull;

NeHuang wrote:
> can we also add the run lines for 64 bit LE Linux, 64 bit AIX and 32 bit AIX? 
>  Will also need `#ifdef __PPC64__` for the test case. 
AFAIK there is no difference between LE and BE for sema checking and it'll be 
overkill to add the `ifdef` since the only run line in here is for 64bit 
compilation.  I think that can be added later if there are needs for 32bit 
testcases later?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 365480.
lei marked 2 inline comments as done.
lei added a comment.

update sema check condition and remove duplicate tc


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,14 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will result in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will result in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
 
 void test_builtin_ppc_cmprb() {
   int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, -1); // expected-err

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/lib/Target/PowerPC/P9InstrResources.td:1434
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }

nemanjai wrote:
> You have added the 64-bit version of this, but it seems this is only 
> available for 64-bit operands in 64-bit mode. Under which conditions do we 
> need the plain `ADDEX`?
Correct, the builtin `__addex()` is only available for 64bit. 
Unless I am reading the ISA wrong, the instruction `addex` is valid for both 
32bit and 64bit:
```
ForCY=0,OVis set to 1 if there is a carry out of bit 0 of the sum in 64-bit 
mode or there is a carry out of bit 32 of the sum in 32-bit mode, and set to 0 
otherwise. OV32 is set to 1 if there is a carry out of bit 32 bit of the sum.
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 362734.
lei added a comment.

put back unintentional space change


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,24 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
 // RUN:   -fsyntax-only -Wall -Werror -verify %s
 
 extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
 
 void test_builtin_ppc_cmprb() {
   int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
 }
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_ad

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 362536.
lei added a comment.

remove extra space


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,24 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
@@ -1821,6 +1828,7 @@
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def CP_COPY8   : X_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;
 def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
+
 }
 
 // SLB Invalidate Entry Global
@@ -1828,7 +1836,6 @@
   "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
-
 } // IsISA3_0
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 362535.
lei added a comment.

fix minor wording and spelling mistakes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107002/new/

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,25 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
@@ -1821,6 +1828,7 @@
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def CP_COPY8   : X_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;
 def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
+
 }
 
 // SLB Invalidate Entry Global
@@ -1828,7 +1836,6 @@
   "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
-
 } // IsISA3_0
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-err

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

[Lei Huang via Phabricator via cfe-commits]

lei created this revision.
lei added reviewers: stefanp, nemanjai, NeHuang, power-llvm-team.
Herald added subscribers: shchenz, hiraditya.
lei requested review of this revision.
Herald added projects: clang, LLVM.

Add builtin and intrinsic for `__addex`.

This patch is part of a series of patches to provide builtins for
compatibility with the XL compiler.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107002

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,25 @@
   ret double %0
 }
 declare double @llvm.ppc.insert.exp(double, i64)
+
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+  ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
  "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
 }
 
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+  (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+  "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+  [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
 //===--===//
 // Instruction Patterns
 //
@@ -1828,7 +1835,6 @@
   "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
-
 } // IsISA3_0
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
   DCBI,
   DCCCI,
   ICCCI,
-  ADDEX
+  ADDEX,
+  ADDEX8
 )> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
   def int_ppc_fres
   : GCCBuiltin<"__builtin_ppc_fres">,
 Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-  
+  def int_ppc_addex
+  : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+  [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
   def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
   llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN:   -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+  long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+  unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/Cod

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.

thx for the update!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106757/new/

https://reviews.llvm.org/D106757

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15133
+bool IsLE = getTarget().isLittleEndian();
+auto StoreSubVec = [&](unsigned Width, unsigned Offset, unsigned EltNo) {
+  switch (Width) {

I find the nested switch to be a bit confusing at first.  Maybe it can be done 
a bit diff?
```
auto StoreSubVec ...
   if (Width==16) {
   }
   switch (Width) {
  default:  ...
  case :
  //set the ConvTy, NumElts for non-16byte widths
   }
// code to handle non-16 byte stores
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106757/new/

https://reviews.llvm.org/D106757

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:116
 BUILTIN(__builtin_ppc_fres, "ff", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*i", "")
 

maybe move this up to where `__builtin_ppc_stdcx` is defined.  To match what 
you did in `PPC.cpp`



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c:31
+  return __builtin_ppc_stbcx(c_addr, c);
+}

Why not just add this tc to 
`clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c`?
The other related store functions are tested there.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106484/new/

https://reviews.llvm.org/D106484

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

please rebase to ToT


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103986/new/

https://reviews.llvm.org/D103986

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll:3
+; NOTE: Had to manually modify the last test case (mtmsr) to allow the
+; NOTE: common check of mtmsr instead of 4 different check prefixes
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \

No need to add this `NOTE`.  Just remove the atuo generate line above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106130/new/

https://reviews.llvm.org/D106130

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105957: [PowerPC] Implement intrinsics for mtfsf[i]

[Lei Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG35a18a981f6b: [PowerPC] Implement intrinsics for mtfsf[i] 
(authored by nemanjai, committed by lei).

Changed prior to commit:
  https://reviews.llvm.org/D105957?vs=358491&id=359451#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105957/new/

https://reviews.llvm.org/D105957

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-math.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll

Index: llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-AIX64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-AIX32
+
+define dso_local void @mtfsb0() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb0 10
+; CHECK-PWR7-NEXT:blr
+; CHECK-LABEL: mtfsb0:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mtfsb0 10
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: mtfsb0:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:mtfsb0 10
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: mtfsb0:
+; CHECK-AIX32:   # %bb.0: # %entry
+; CHECK-AIX32-NEXT:mtfsb0 10
+; CHECK-AIX32-NEXT:blr
+entry:
+  tail call void @llvm.ppc.mtfsb0(i32 10)
+  ret void
+}
+
+define dso_local void @mtfsb1() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb1:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb1 0
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb1:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb1 0
+; CHECK-PWR7-NEXT:blr
+; CHECK-LABEL: mtfsb1:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mtfsb1 0
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: mtfsb1:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:mtfsb1 0
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: mtfsb1:
+; CHECK-AIX32:   # %bb.0: # %entry
+; CHECK-AIX32-NEXT:mtfsb1 0
+; CHECK-AIX32-NEXT:blr
+entry:
+  tail call void @llvm.ppc.mtfsb1(i32 0)
+  ret void
+}
+
+define dso_local void @callmtfsf(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsf:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mtfprwz 0, 3
+; CHECK-NEXT:xscvuxddp 0, 0
+; CHECK-NEXT:mtfsf 7, 0
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: callmtfsf:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:addi 4, 1, -4
+; CHECK-AIX64-NEXT:stw 3, -4(1)
+; CHECK-AIX64-NEXT:lfiwzx 0, 0, 4
+; CHECK-AIX64-NEXT:xscvuxddp 0, 0
+; CHECK-AIX64-NEXT:mtfsf 7, 0
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: callmtfsf:
+; CHECK-AIX32:   # %bb.0: # %entry
+; CHECK-AIX32-NEXT:addi 4, 1, -4
+; CHECK-AIX32-NEXT:stw 3, -4(1)
+; CHECK-AIX32-NEXT:lfiwzx 0, 0, 4
+; CHECK-AIX32-NEXT:xscvuxddp 0, 0
+; CHECK-AIX32-NEXT:mtfsf 7, 0
+; CHECK-AIX32-NEXT:blr
+entry:
+  %0 = uitofp i32 %a to double
+  tail call void @llvm.ppc.mtfsf(i32 7, double %0)
+  ret void
+}
+
+define dso_local void @callmtfsfi(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsfi:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mtfsfi 1, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: callmtfsfi:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:mtfsfi 1, 3
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: callmtfsfi:
+; CHECK-AIX32:   # %bb.0: # %entry
+; CHECK-AIX32-NEXT:mtfsfi 1, 3
+; CHECK-AIX32-NEXT:blr
+entry:
+  tail call void @llvm.ppc.mtfsfi(i32 1, i32 3)
+  ret void
+}
+
+declare void @llvm.ppc.mtfsb0(i32)
+declare void @llvm.ppc.mtfsb1(i32)
+declare void @llvm.ppc.mtfsfi(i32, i32)
+declare void @llvm.ppc.mtfsf(i32, double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -10,50 +10,6 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
 ; RUN:   FileCheck %s --che

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+  // CHECK-LABEL: @test_lwarx
   // CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i32* %a)
   return __lwarx(a);

where is the check for `CHECK-NON-PWR8-ERR:`?



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:36
   // CHECK: %0 = bitcast i32* %a to i8*
   // CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val)
   return __stwcx(a, val);

`CHECK-NON-PWR8-ERR:` check?



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \

why are we only testing this for pwr9 vs pwr7/8 similar to other tests added?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc8937b6cb975: [PowerPC] Implement XL compact math builtins 
(authored by lei).

Changed prior to commit:
  https://reviews.llvm.org/D105930?vs=359070&id=359397#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105930/new/

https://reviews.llvm.org/D105930

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+  ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+  ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+  ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: mtfsb0:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:mtfsb

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3087
 // RM should be set.
+let hasSideEffects = 1 in {
 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),

nemanjai wrote:
> nemanjai wrote:
> > I think we should conservatively set RM as an implicit def here. @ZhangKang 
> > you modified this code most recently, please provide your opinion here.
> This was not addressed. Will this be added in a follow-up patch?
Yes, sorry I will address this in a subsequent patch since adding RM will cause 
unrelated LIT failures.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105930/new/

https://reviews.llvm.org/D105930

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569
 }
-

nit: un-related line deletion



Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:5449
+  def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A),
+  (STHCX (EXTSH gprc:$A), xoaddr:$dst)>;
+}

`EXTSH` should not be needed and we should not be using `xoaddr`



Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll:7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \

this is confusing... maybe this shouldjust be `CHECK-32BIT`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 359070.
lei added a comment.

rebase to ToT


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105930/new/

https://reviews.llvm.org/D105930

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+  ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+  ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+  ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: mtfsb0:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:mtfsb0 10
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb0 10
+; CHECK-PWR7-NEXT:blr
+entry:
+  tail call void @llvm.ppc.mtfsb0(i32 10)
+  ret void
+}
+
+d

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3650
+// XL Compat intrinsics.
+def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>;
+def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>;

nemanjai wrote:
> Please review the order of operands carefully here. I believe the order is 
> wrong either for this one or for the VSX version. Double-check all of the 
> others as well please.
I double checked and both seem correct to me.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105930/new/

https://reviews.llvm.org/D105930

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 359050.
lei marked 3 inline comments as done.
lei added a comment.

Address review comments to add/upate:

- builtin encoding for params that need to be folded into constant expr
- llvm intrinsic property for immediates
- test line for `-mattr=-vsx`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105930/new/

https://reviews.llvm.org/D105930

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+  ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+  ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+  ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: mtfsb0:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:mtfsb0 10
+; CHECK-NOVSX-NEXT:   

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3371
+return SemaFeatureCheck(*this, TheCall, "extdiv",
+diag::err_ppc_builtin_only_on_arch, "8");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \

need tests for these.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569
+  def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], 
[IntrWriteMem]>;
+  def int_ppc_lharx : GCCBuiltin<"__builtin_ppc_lharx">,
+  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;

do these loads not need `IntrReadMem`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

please add sema checking for pwr8 builtins.




Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll:80
+declare i32 @llvm.ppc.lharx(i8*)
+define dso_local signext i16 @test_lharx(i16* %a) local_unnamed_addr #0 {
+; CHECK-64-LABEL: test_lharx:

remove all reference to attributes, `local_unnamed_addr #[0..9]` since it's not 
in the IR.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 358665.
lei added a comment.

cleanup tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105930/new/

https://reviews.llvm.org/D105930

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+  ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+  ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+  ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,179 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb0 10
+; CHECK-PWR7-NEXT:blr
+entry:
+  tail call void @llvm.ppc.mtfsb0(i32 10)
+  ret void
+}
+
+declare void @llvm.ppc.mtfsb0(i32)
+
+define dso_local void @mtfsb1() {
+; CHECK-PWR8-LABEL: mtfsb1:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb1 0
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb1:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK

[PATCH] D104386: [PowerPC][Builtins] Added a number of builtins for compatibility with XL.

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:48
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_alignx, "viCvC*", "nc")
+BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiCUWi", "nc")

I think you need sema checking for parm 1.
```
alignment
Must be a constant integer with a value greater than zero and of a power of two.
```



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:49
+BUILTIN(__builtin_ppc_alignx, "viCvC*", "nc")
+BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiCUWi", "nc")
 

sema checking?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104386/new/

https://reviews.llvm.org/D104386

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 358409.
lei added a comment.

update tc to only check for pwr7 and up


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105930/new/

https://reviews.llvm.org/D105930

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) local_unnamed_addr {
+; CHECK-LABEL: extract_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+  ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) local_unnamed_addr {
+; CHECK-LABEL: extract_sig:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+  ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) local_unnamed_addr {
+; CHECK-LABEL: insert_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+  ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,199 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+
+; Function Attrs: nounwind uwtable
+define dso_local void @mtfsb0() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb0 10
+; CHECK-PWR7-NEXT:blr
+entry:
+  tail call void @llvm.ppc.mtfsb0(i32 10)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.ppc.mtfsb0(i32)
+
+; Function Attrs: nounwind uwtable
+define dso_local void @mtfsb1() loc

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

[Lei Huang via Phabricator via cfe-commits]

lei created this revision.
lei added reviewers: stefanp, nemanjai, power-llvm-team.
Herald added subscribers: shchenz, hiraditya.
lei requested review of this revision.
Herald added projects: clang, LLVM.

Implement a subset of builtins required for compatiblilty with AIX XL compiler.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105930

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-math.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) local_unnamed_addr {
+; CHECK-LABEL: extract_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+  ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) local_unnamed_addr {
+; CHECK-LABEL: extract_sig:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+  ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) local_unnamed_addr {
+; CHECK-LABEL: insert_exp:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+  ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,199 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+
+; Function Attrs: nounwind uwtable
+define dso_local void @mtfsb0() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb0 10
+; CHECK-PWR7-NEXT:blr
+entry:
+  tail call void @llvm.ppc.mtfsb0(i32 10)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm

[PATCH] D105501: [PowerPC] Power ISA features for Semachecking

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3278
+ StringRef DiagArg = "") {
+  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck)) {
+if (!DiagArg.empty()) {

may I suggest early exit instead?

```
if (S.Context.getTargetInfo().hasFeature(FeatureToCheck))
  return false;

if (DiagArg.empty()) 
  S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
else
  S.Diag(TheCall->getBeginLoc(), DiagID) << DiagArg << 
TheCall->getSourceRange();

return true;
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105501/new/

https://reviews.llvm.org/D105501

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D104664: [PowerPC][NFC] Clean up builtin sema checks

[Lei Huang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb259740801d3: [PowerPC][NFC] Clean up builtin sema checks 
(authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104664/new/

https://reviews.llvm.org/D104664

Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3255,34 +3255,33 @@
   }
 }
 
+static bool isPPC_64Builtin(unsigned BuiltinID) {
+  // These builtins only work on PPC 64bit targets.
+  switch (BuiltinID) {
+  case PPC::BI__builtin_divde:
+  case PPC::BI__builtin_divdeu:
+  case PPC::BI__builtin_bpermd:
+return true;
+  }
+  return false;
+}
+
+static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
+ StringRef FeatureToCheck, unsigned DiagID) {
+  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
+return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
+  return false;
+}
+
 bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned 
BuiltinID,
CallExpr *TheCall) {
   unsigned i = 0, l = 0, u = 0;
-  bool Is64BitBltin = BuiltinID == PPC::BI__builtin_divde ||
-  BuiltinID == PPC::BI__builtin_divdeu ||
-  BuiltinID == PPC::BI__builtin_bpermd;
   bool IsTarget64Bit = TI.getTypeWidth(TI.getIntPtrType()) == 64;
-  bool IsBltinExtDiv = BuiltinID == PPC::BI__builtin_divwe ||
-   BuiltinID == PPC::BI__builtin_divweu ||
-   BuiltinID == PPC::BI__builtin_divde ||
-   BuiltinID == PPC::BI__builtin_divdeu;
 
-  if (Is64BitBltin && !IsTarget64Bit)
+  if (isPPC_64Builtin(BuiltinID) && !IsTarget64Bit)
 return Diag(TheCall->getBeginLoc(), diag::err_64_bit_builtin_32_bit_tgt)
<< TheCall->getSourceRange();
 
-  if ((IsBltinExtDiv && !TI.hasFeature("extdiv")) ||
-  (BuiltinID == PPC::BI__builtin_bpermd && !TI.hasFeature("bpermd")))
-return Diag(TheCall->getBeginLoc(), diag::err_ppc_builtin_only_on_pwr7)
-   << TheCall->getSourceRange();
-
-  auto SemaVSXCheck = [&](CallExpr *TheCall) -> bool {
-if (!TI.hasFeature("vsx"))
-  return Diag(TheCall->getBeginLoc(), diag::err_ppc_builtin_only_on_pwr7)
- << TheCall->getSourceRange();
-return false;
-  };
-
   switch (BuiltinID) {
   default: return false;
   case PPC::BI__builtin_altivec_crypto_vshasigmaw:
@@ -3308,11 +3307,22 @@
   case PPC::BI__builtin_vsx_xxpermdi:
   case PPC::BI__builtin_vsx_xxsldwi:
 return SemaBuiltinVSX(TheCall);
+  case PPC::BI__builtin_divwe:
+  case PPC::BI__builtin_divweu:
+  case PPC::BI__builtin_divde:
+  case PPC::BI__builtin_divdeu:
+return SemaFeatureCheck(*this, TheCall, "extdiv",
+diag::err_ppc_builtin_only_on_pwr7);
+  case PPC::BI__builtin_bpermd:
+return SemaFeatureCheck(*this, TheCall, "bpermd",
+diag::err_ppc_builtin_only_on_pwr7);
   case PPC::BI__builtin_unpack_vector_int128:
-return SemaVSXCheck(TheCall) ||
+return SemaFeatureCheck(*this, TheCall, "vsx",
+diag::err_ppc_builtin_only_on_pwr7) ||
SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_pack_vector_int128:
-return SemaVSXCheck(TheCall);
+return SemaFeatureCheck(*this, TheCall, "vsx",
+diag::err_ppc_builtin_only_on_pwr7);
   case PPC::BI__builtin_altivec_vgnb:
  return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
   case PPC::BI__builtin_altivec_vec_replace_elt:


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3255,34 +3255,33 @@
   }
 }
 
+static bool isPPC_64Builtin(unsigned BuiltinID) {
+  // These builtins only work on PPC 64bit targets.
+  switch (BuiltinID) {
+  case PPC::BI__builtin_divde:
+  case PPC::BI__builtin_divdeu:
+  case PPC::BI__builtin_bpermd:
+return true;
+  }
+  return false;
+}
+
+static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
+ StringRef FeatureToCheck, unsigned DiagID) {
+  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
+return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
+  return false;
+}
+
 bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall) {
   unsigned i = 0, l = 0, u = 0;
-  bool Is64BitBltin = BuiltinID == PPC::BI__builtin_divde ||
-  BuiltinID == PPC::BI__builtin_divdeu ||
-  BuiltinID == PPC::BI__builtin_bpermd;
   bool IsTarget64Bit = TI.getTypeWidth(TI.getIntPtrType()) == 64;
-  bool 

[PATCH] D104664: [PowerPC][NFC] Clean up builtin sema checks

[Lei Huang via Phabricator via cfe-commits]

lei updated this revision to Diff 353515.
lei added a comment.

remove extra ";"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104664/new/

https://reviews.llvm.org/D104664

Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3255,34 +3255,33 @@
   }
 }
 
+static bool isPPC_64Builtin(unsigned BuiltinID) {
+  // These builtins only work on PPC 64bit targets.
+  switch (BuiltinID) {
+  case PPC::BI__builtin_divde:
+  case PPC::BI__builtin_divdeu:
+  case PPC::BI__builtin_bpermd:
+return true;
+  }
+  return false;
+}
+
+static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
+ StringRef FeatureToCheck, unsigned DiagID) {
+  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
+return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
+  return false;
+}
+
 bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned 
BuiltinID,
CallExpr *TheCall) {
   unsigned i = 0, l = 0, u = 0;
-  bool Is64BitBltin = BuiltinID == PPC::BI__builtin_divde ||
-  BuiltinID == PPC::BI__builtin_divdeu ||
-  BuiltinID == PPC::BI__builtin_bpermd;
   bool IsTarget64Bit = TI.getTypeWidth(TI.getIntPtrType()) == 64;
-  bool IsBltinExtDiv = BuiltinID == PPC::BI__builtin_divwe ||
-   BuiltinID == PPC::BI__builtin_divweu ||
-   BuiltinID == PPC::BI__builtin_divde ||
-   BuiltinID == PPC::BI__builtin_divdeu;
 
-  if (Is64BitBltin && !IsTarget64Bit)
+  if (isPPC_64Builtin(BuiltinID) && !IsTarget64Bit)
 return Diag(TheCall->getBeginLoc(), diag::err_64_bit_builtin_32_bit_tgt)
<< TheCall->getSourceRange();
 
-  if ((IsBltinExtDiv && !TI.hasFeature("extdiv")) ||
-  (BuiltinID == PPC::BI__builtin_bpermd && !TI.hasFeature("bpermd")))
-return Diag(TheCall->getBeginLoc(), diag::err_ppc_builtin_only_on_pwr7)
-   << TheCall->getSourceRange();
-
-  auto SemaVSXCheck = [&](CallExpr *TheCall) -> bool {
-if (!TI.hasFeature("vsx"))
-  return Diag(TheCall->getBeginLoc(), diag::err_ppc_builtin_only_on_pwr7)
- << TheCall->getSourceRange();
-return false;
-  };
-
   switch (BuiltinID) {
   default: return false;
   case PPC::BI__builtin_altivec_crypto_vshasigmaw:
@@ -3308,11 +3307,22 @@
   case PPC::BI__builtin_vsx_xxpermdi:
   case PPC::BI__builtin_vsx_xxsldwi:
 return SemaBuiltinVSX(TheCall);
+  case PPC::BI__builtin_divwe:
+  case PPC::BI__builtin_divweu:
+  case PPC::BI__builtin_divde:
+  case PPC::BI__builtin_divdeu:
+return SemaFeatureCheck(*this, TheCall, "extdiv",
+diag::err_ppc_builtin_only_on_pwr7);
+  case PPC::BI__builtin_bpermd:
+return SemaFeatureCheck(*this, TheCall, "bpermd",
+diag::err_ppc_builtin_only_on_pwr7);
   case PPC::BI__builtin_unpack_vector_int128:
-return SemaVSXCheck(TheCall) ||
+return SemaFeatureCheck(*this, TheCall, "vsx",
+diag::err_ppc_builtin_only_on_pwr7) ||
SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_pack_vector_int128:
-return SemaVSXCheck(TheCall);
+return SemaFeatureCheck(*this, TheCall, "vsx",
+diag::err_ppc_builtin_only_on_pwr7);
   case PPC::BI__builtin_altivec_vgnb:
  return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
   case PPC::BI__builtin_altivec_vec_replace_elt:


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3255,34 +3255,33 @@
   }
 }
 
+static bool isPPC_64Builtin(unsigned BuiltinID) {
+  // These builtins only work on PPC 64bit targets.
+  switch (BuiltinID) {
+  case PPC::BI__builtin_divde:
+  case PPC::BI__builtin_divdeu:
+  case PPC::BI__builtin_bpermd:
+return true;
+  }
+  return false;
+}
+
+static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
+ StringRef FeatureToCheck, unsigned DiagID) {
+  if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
+return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
+  return false;
+}
+
 bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
CallExpr *TheCall) {
   unsigned i = 0, l = 0, u = 0;
-  bool Is64BitBltin = BuiltinID == PPC::BI__builtin_divde ||
-  BuiltinID == PPC::BI__builtin_divdeu ||
-  BuiltinID == PPC::BI__builtin_bpermd;
   bool IsTarget64Bit = TI.getTypeWidth(TI.getIntPtrType()) == 64;
-  bool IsBltinExtDiv = BuiltinID == PPC::BI__builtin_divwe ||
-   BuiltinID 

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c:8
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 2>&1 | FileCheck %s 
-check-prefix=CHECK-32
+

`-check-prefix=CHECK-32` => `--check-prefix=CHECK-32`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c:6
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s 
--check-prefix=CHECK-64
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix \

why not just use default for 64BIT behaviour?  No need for 
`--check-prefix=CHECK-64`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D102875: [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.h:354
 
-  void defineXLCompatMacros(MacroBuilder &Builder) const {
-Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");

Can you pleases rebase your patch again?  The removal of this function was part 
of D104125.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-compare-64bit-only.c:2
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s 
--check-prefix=CHECK-64
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \

Are these pwr9 specific as well?  If not please targe pwr7 for big endian and 
pwr8 for little endian



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c:2
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s 
--check-prefix=CHECK-64
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \

same comment as above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102875/new/

https://reviews.llvm.org/D102875

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D104125: [PowerPC] Moving defineXLCompatMacros() definition

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.
This revision is now accepted and ready to land.

LGTM
Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104125/new/

https://reviews.llvm.org/D104125

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D102191: [PowerPC] Add clang option -m[no-]prefixed

[Lei Huang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9469ff15b779: [PowerPC] Add clang option -m[no-]prefixed 
(authored by lei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102191/new/

https://reviews.llvm.org/D102191

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-prefixed.cpp


Index: clang/test/Driver/ppc-prefixed.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-prefixed.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 
-mprefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PREFIXED %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 
-mno-prefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPREFIXED %s
+// CHECK-NOPREFIXED: "-target-feature" "-prefixed"
+// CHECK-PREFIXED: "-target-feature" "+prefixed"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S 
%s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mprefixed 
-emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-prefixed 
-emit-llvm -S %s -o - | grep "attributes.*\-prefix-instrs"
+
+int main(int argc, char *argv[]) {
+  return 0;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -73,6 +73,7 @@
   bool PairedVectorMemops = false;
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
+  bool HasPrefixInstrs = false;
 
 protected:
   std::string ABI;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -56,6 +56,8 @@
   HasP10Vector = true;
 } else if (Feature == "+pcrelative-memops") {
   HasPCRelativeMemops = true;
+} else if (Feature == "+prefix-instrs") {
+  HasPrefixInstrs = true;
 } else if (Feature == "+spe" || Feature == "+efpu2") {
   HasSPE = true;
   LongDoubleWidth = LongDoubleAlign = 64;
@@ -394,6 +396,7 @@
   Features["mma"] = true;
   Features["power10-vector"] = true;
   Features["pcrelative-memops"] = true;
+  Features["prefix-instrs"] = true;
   return;
 }
 
@@ -419,6 +422,7 @@
   .Case("paired-vector-memops", PairedVectorMemops)
   .Case("power10-vector", HasP10Vector)
   .Case("pcrelative-memops", HasPCRelativeMemops)
+  .Case("prefix-instrs", HasPrefixInstrs)
   .Case("spe", HasSPE)
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
@@ -451,6 +455,8 @@
   Features["power8-vector"] = Features["power9-vector"] = true;
 if (Name == "pcrel")
   Features["pcrelative-memops"] = true;
+else if (Name == "prefixed")
+  Features["prefix-instrs"] = true;
 else
   Features[Name] = true;
   } else {
@@ -471,6 +477,8 @@
   Features["power10-vector"] = false;
 if (Name == "pcrel")
   Features["pcrelative-memops"] = false;
+else if (Name == "prefixed")
+  Features["prefix-instrs"] = false;
 else
   Features[Name] = false;
   }
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3254,6 +3254,8 @@
 def mno_altivec : Flag<["-"], "mno-altivec">, Group;
 def mpcrel: Flag<["-"], "mpcrel">, Group;
 def mno_pcrel: Flag<["-"], "mno-pcrel">, Group;
+def mprefixed: Flag<["-"], "mprefixed">, Group;
+def mno_prefixed: Flag<["-"], "mno-prefixed">, Group;
 def mspe : Flag<["-"], "mspe">, Group;
 def mno_spe : Flag<["-"], "mno-spe">, Group;
 def mefpu2 : Flag<["-"], "mefpu2">, Group;


Index: clang/test/Driver/ppc-prefixed.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-prefixed.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mprefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PREFIXED %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mno-prefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPREFIXED %s
+// CHECK-NOPREFIXED: "-target-feature" "-prefixed"
+// CHECK-PREFIXED: "-target-feature" "+prefixed"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mprefixed -emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-prefixed -emit-llvm -S %s -o - | grep

[PATCH] D102191: [PowerPC] Add clang option -m[no-]prefixed

[Lei Huang via Phabricator via cfe-commits]

lei created this revision.
lei added reviewers: stefanp, nemanjai, power-llvm-team.
Herald added subscribers: dang, shchenz.
lei requested review of this revision.
Herald added a project: clang.

Add user-facing front end option to turn off power10 prefixed instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102191

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-prefixed.cpp


Index: clang/test/Driver/ppc-prefixed.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-prefixed.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 
-mprefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PREFIXED %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 
-mno-prefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPREFIXED %s
+// CHECK-NOPREFIXED: "-target-feature" "-prefixed"
+// CHECK-PREFIXED: "-target-feature" "+prefixed"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S 
%s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mprefixed 
-emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-prefixed 
-emit-llvm -S %s -o - | grep "attributes.*\-prefix-instrs"
+
+int main(int argc, char *argv[]) {
+  return 0;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -73,6 +73,7 @@
   bool PairedVectorMemops = false;
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
+  bool HasPrefixInstrs = false;
 
 protected:
   std::string ABI;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -56,6 +56,8 @@
   HasP10Vector = true;
 } else if (Feature == "+pcrelative-memops") {
   HasPCRelativeMemops = true;
+} else if (Feature == "+prefix-instrs") {
+  HasPrefixInstrs = true;
 } else if (Feature == "+spe" || Feature == "+efpu2") {
   HasSPE = true;
   LongDoubleWidth = LongDoubleAlign = 64;
@@ -394,6 +396,7 @@
   Features["mma"] = true;
   Features["power10-vector"] = true;
   Features["pcrelative-memops"] = true;
+  Features["prefix-instrs"] = true;
   return;
 }
 
@@ -419,6 +422,7 @@
   .Case("paired-vector-memops", PairedVectorMemops)
   .Case("power10-vector", HasP10Vector)
   .Case("pcrelative-memops", HasPCRelativeMemops)
+  .Case("prefix-instrs", HasPrefixInstrs)
   .Case("spe", HasSPE)
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
@@ -451,6 +455,8 @@
   Features["power8-vector"] = Features["power9-vector"] = true;
 if (Name == "pcrel")
   Features["pcrelative-memops"] = true;
+else if (Name == "prefixed")
+  Features["prefix-instrs"] = true;
 else
   Features[Name] = true;
   } else {
@@ -471,6 +477,8 @@
   Features["power10-vector"] = false;
 if (Name == "pcrel")
   Features["pcrelative-memops"] = false;
+else if (Name == "prefixed")
+  Features["prefix-instrs"] = false;
 else
   Features[Name] = false;
   }
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3254,6 +3254,8 @@
 def mno_altivec : Flag<["-"], "mno-altivec">, Group;
 def mpcrel: Flag<["-"], "mpcrel">, Group;
 def mno_pcrel: Flag<["-"], "mno-pcrel">, Group;
+def mprefixed: Flag<["-"], "mprefixed">, Group;
+def mno_prefixed: Flag<["-"], "mno-prefixed">, Group;
 def mspe : Flag<["-"], "mspe">, Group;
 def mno_spe : Flag<["-"], "mno-spe">, Group;
 def mefpu2 : Flag<["-"], "mefpu2">, Group;


Index: clang/test/Driver/ppc-prefixed.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-prefixed.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mprefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PREFIXED %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mno-prefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPREFIXED %s
+// CHECK-NOPREFIXED: "-target-feature" "-prefixed"
+// CHECK-PREFIXED: "-target-feature" "+prefixed"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mprefixed -emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-prefixed -emit-llvm -S %s -o - | grep "attributes.*\-pref

[PATCH] D99193: [PowerPC] Add mprivileged option

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99193/new/

https://reviews.llvm.org/D99193

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D99185: [PowerPC] Change option to mrop-protect

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99185/new/

https://reviews.llvm.org/D99185

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D89986: [AIX] do not emit visibility attribute into IR when there is -mignore-xcoff-visibility

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

Instead of waiting a day or two, can you please directly ping reviewers who had 
concerns related to the round-trip-args behaviour to get feedback?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89986/new/

https://reviews.llvm.org/D89986

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95634: [PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95634/new/

https://reviews.llvm.org/D95634

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:2658
+  return false;
+}
+

There's alot of nested `if`s, would it be possible to refactor to have some 
early exits instead?




Comment at: llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll:2
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 < %s | FileCheck %s
+

BE test?
Can we add `-ppc-asm-full-reg-names` and update the checks to also ensure the 
reg info is accurate?



Comment at: llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll:4
+
+target datalayout = "e-m:e-i64:64-p:64:64-n32:64-v256:256:256-v512:512:512"
+

is this needed since we have the triple on the run line?



Comment at: llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll:3
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -disable-lsr \
+; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 < %s | FileCheck %s
+

BE test?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90799/new/

https://reviews.llvm.org/D90799

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D87804: [PowerPC][Power10] Implement Vector signed/unsigned __int128 overloads for the comparison builtins

[Lei Huang via Phabricator via cfe-commits]

lei added a comment.

please fix the clang format issues.




Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:365
+  def int_ppc_altivec_vcmpequq : GCCBuiltin<"__builtin_altivec_vcmpequq">,
+   Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty],
+ [IntrNoMem]>;

nit: indentation



Comment at: llvm/test/CodeGen/PowerPC/vec_cmpq.ll:14
+; CHECK-LABEL: v1si128_cmp:
+; CHECK: vcmpequq 2, 2, 3
+}

please add the check for end of function.. eg `// CHECK: ret <1 x i128>`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87804/new/

https://reviews.llvm.org/D87804

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision.
lei added a comment.
This revision is now accepted and ready to land.

Just some minor comments. Please address them prior to commit.




Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10519
+  // 2 or 4 vsx registers.
+  if (VT == MVT::v256i1 || VT == MVT::v512i1) {
+assert((VT != MVT::v512i1 || Subtarget.hasMMA()) &&

Maybe we can do an early exit instead of this if stmt here
```
if (VT != MVT::v256i1 && VT != MVT::v512i1)
  return Op;

assert(Subtarget.pairedVectorMemops()) &&
"Type unsupported without paired vector support");
```




Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10522
+   "Type unsupported without MMA");
+assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) &&
+   "Type unsupported without paired vector support");

I believe the ck for v256i1 here is redundant cause MMA should also set 
pairedVectorMemops 



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10566
+  // underlying registers individually.
+  if (StoreVT == MVT::v256i1 || StoreVT == MVT::v512i1) {
+assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) &&

same comment as above... early exit.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84968/new/

https://reviews.llvm.org/D84968

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits