[PATCH] D155081: Specify the developer policy around links to external resources

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/docs/DeveloperPolicy.rst:349
 
-* If the patch has been reviewed, add a link to its review page, as shown
-  `here `_.

aaron.ballman wrote:
> reames wrote:
> > aaron.ballman wrote:
> > > aaron.ballman wrote:
> > > > reames wrote:
> > > > > Removing this item seems very off topic for the change description, 
> > > > > and certainly hasn't been discussed in the linked thread.  Please add 
> > > > > this back in a separate commit.
> > > > > 
> > > > > (To be clear, no objections to the overall change, just the removal 
> > > > > of the phab link text.)
> > > > Hmm, I thought this was obsoleted by the new text (it is covered by 
> > > > "other kinds of metadata"). That said, losing that link is definitely a 
> > > > regression, so thank you for pointing this out! I'll find a way to add 
> > > > it back in (either as a stand-alone bullet point or incorporated into 
> > > > the new text).
> > > I restored the link in 
> > > https://github.com/llvm/llvm-project/commit/a1562bbc63b49a70b39ba075d9a3332f50cea11d
> > >  as part of the new bullet; please let me know if you have additional 
> > > concerns.
> > That 90% covers it.  What's left is some minor framing.  I'd suggest 
> > separating that point into two.  The first should be recommended metadata 
> > (phab, issues link), and the second can be the additional metadata point.  
> > Something like:
> > 
> > ```
> > If the patch has been reviewed, add a link to its review page, as shown
> >   `here `_. 
> > If the patch fixes a bug in GitHub Issues, we encourage adding a reference 
> > to the issue being closed, as described `here 
> > `_.
> > 
> > It is also acceptable to add other metadata to the commit message to 
> > automate processes, including for downstream consumers. and including links 
> > to resources that are not available to the entire community. However, such 
> > links and/or metadata should not be used in place of making the commit 
> > message self-explanatory.  
> > 
> > ```
> > All of the above is just reorganizing what you had written with some very 
> > minor copy editing.  I'd separately suggest adding the following sentence 
> > at the end of the second bullet.
> > 
> > Note that such non-public links are *only* allowed in commit messages, and 
> > should not be included in the submitted code.  
> I did some minor rewording for clarity, so how about:
> ```
> * If the patch has been reviewed, add a link to its review page, as shown
>   `here `__.
>   If the patch fixes a bug in GitHub Issues, we encourage adding a reference 
> to
>   the issue being closed, as described
>   `here `__.
> 
> * It is also acceptable to add other metadata to the commit message to 
> automate
>   processes, including for downstream consumers. This metadata can include
>   links to resources that are not available to the entire community. However,
>   such links and/or metadata should not be used in place of making the commit
>   message self-explanatory.
> ```
> 
> > All of the above is just reorganizing what you had written with some very 
> > minor copy editing. I'd separately suggest adding the following sentence at 
> > the end of the second bullet.
> > 
> > Note that such non-public links are *only* allowed in commit messages, and 
> > should not be included in the submitted code.
> 
> I think this might need more wordsmithing, which is why I left out of the 
> simple reorganization. The non-public links aren't limited to commit messages 
> -- for example, they're fine to use in a phabricator review or github issue 
> comment, etc. So I don't want to be too restrictive with the wording, though 
> I agree with the intent. How about something along the lines of:
> 
> Note that such non-public links should not be included in the submitted code.
LGTM to both parts.  Wording is hard, and good catch on the second.  :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155081/new/

https://reviews.llvm.org/D155081

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D155081: Specify the developer policy around links to external resources

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/docs/DeveloperPolicy.rst:349
 
-* If the patch has been reviewed, add a link to its review page, as shown
-  `here `_.

aaron.ballman wrote:
> aaron.ballman wrote:
> > reames wrote:
> > > Removing this item seems very off topic for the change description, and 
> > > certainly hasn't been discussed in the linked thread.  Please add this 
> > > back in a separate commit.
> > > 
> > > (To be clear, no objections to the overall change, just the removal of 
> > > the phab link text.)
> > Hmm, I thought this was obsoleted by the new text (it is covered by "other 
> > kinds of metadata"). That said, losing that link is definitely a 
> > regression, so thank you for pointing this out! I'll find a way to add it 
> > back in (either as a stand-alone bullet point or incorporated into the new 
> > text).
> I restored the link in 
> https://github.com/llvm/llvm-project/commit/a1562bbc63b49a70b39ba075d9a3332f50cea11d
>  as part of the new bullet; please let me know if you have additional 
> concerns.
That 90% covers it.  What's left is some minor framing.  I'd suggest separating 
that point into two.  The first should be recommended metadata (phab, issues 
link), and the second can be the additional metadata point.  Something like:

```
If the patch has been reviewed, add a link to its review page, as shown
  `here `_. If 
the patch fixes a bug in GitHub Issues, we encourage adding a reference to the 
issue being closed, as described `here 
`_.

It is also acceptable to add other metadata to the commit message to automate 
processes, including for downstream consumers. and including links to resources 
that are not available to the entire community. However, such links and/or 
metadata should not be used in place of making the commit message 
self-explanatory.  

```
All of the above is just reorganizing what you had written with some very minor 
copy editing.  I'd separately suggest adding the following sentence at the end 
of the second bullet.

Note that such non-public links are *only* allowed in commit messages, and 
should not be included in the submitted code.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155081/new/

https://reviews.llvm.org/D155081

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D155081: Specify the developer policy around links to external resources

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/docs/DeveloperPolicy.rst:349
 
-* If the patch has been reviewed, add a link to its review page, as shown
-  `here `_.

Removing this item seems very off topic for the change description, and 
certainly hasn't been discussed in the linked thread.  Please add this back in 
a separate commit.

(To be clear, no objections to the overall change, just the removal of the phab 
link text.)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155081/new/

https://reviews.llvm.org/D155081

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157362: [RISCV] Add MC layer support for Zicfilp.

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/docs/RISCVUsage.rst:120
  ``Zicboz``   Assembly Support
+ ``Zicfilp``  Assembly Support
  ``Zicntr``   (`See Note <#riscv-i2p1-note>`__)

This in the wrong place; this is not a ratified extension.  

You need to link to the right spec version as well.  This is particularly 
important here as this spec has gone through a ton of churn, and may still do 
so.  



Comment at: llvm/test/MC/RISCV/zicfilp-valid.s:17
+
+# CHECK-ASM-AND-OBJ: auipc zero, 22
+# CHECK-ASM: encoding: [0x17,0x60,0x01,0x00]

If the proper extension is provided to llvm-objdump, we really shouldn't be 
disassembling this as the auipc name, it should be the landing pad mnemonic.  

I think this is just the use of -m no-aliases above.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157362/new/

https://reviews.llvm.org/D157362

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151730: [RISCV] Support target attribute for function

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D151730#4491786 , @craig.topper 
wrote:

> In D151730#4491773 , @jrtc27 wrote:
>
>> Isn't multiversioning a separate thing that builds on top of per-function 
>> target attributes?
>
> That's what I thought. The supportsMultiVersioning call was in an earlier 
> version of the patch that I asked about.

Yeah, looks like I got confused.

I hadn't expected that target("default") would automatically be considered 
multi-versioning, even when there was one definition of the function.  As such, 
my test case was accidentally testing multi-versioning even when I hadn't meant 
to.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151730: [RISCV] Support target attribute for function

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

FYI, this change appears to be a partial diff.  Locally, I need to add RISCV to 
supportsMultiVersioning() to get this to work at all.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151730: [RISCV] Support target attribute for function

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Can you separate the change to RISCVAsmPrinter.cpp into it's own review?  This 
looks useful for any case where we have functions in the same model with 
different function attributes.  The __attribute__((target...) syntax is one way 
to have that, but there are also others.  LTO will see this, and so may other 
frontends.

This will also help with review as the set of people who can review RISCV 
backend changes and clang frontend changes is fairly non-overlapping.




Comment at: llvm/test/CodeGen/RISCV/riscv-func-attr-target.ll:5
+; CHECK-NEXT: .optionarch,   +c, +v, +zifencei, +zve32f, +zve32x, 
+zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
+define void @test1() #0 {
+; CHECK-LABEL: test1

This test would be a lot easier to follow if you pruned all the spurious 
attributes, and uses the inline attribute syntax rather than the #0 reference 
syntax.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151730/new/

https://reviews.llvm.org/D151730

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:3338
+unsigned Rs2 = Inst.getOperand(2).getReg();
+if (Rd % 2 == 1) {
+  SMLoc Loc = Operands[1]->getStartLoc();

Very minor, but != 0 would read more naturally for me here.  Checking for odd, 
and then an error message about even requires one extra second of thought.

Same with the one below.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149248/new/

https://reviews.llvm.org/D149248

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D149495#4373796 , @michaelmaitland 
wrote:

> In D149495#4373768 , @reames wrote:
>
>> Let's go ahead and land this as is, we can rework the stylistic pieces once 
>> the linked patches land.
>
> This has landed in 
> https://reviews.llvm.org/rG1a855819a87f426bdbd83c815fa47ca01fdf928f. I raised 
> my question regarding examples in my previous comment on this post because I 
> am starting to rework the stylistic concerns raised by @pcwang-thead. 
> However, I will wait until Wang's patches land before making any 
> modifications to style.

My apologies, I read right past the commit in the history.  Oops.  Sorry for 
the noise!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Let's go ahead and land this as is, we can rework the stylistic pieces once the 
linked patches land.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.

LGTM


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147612/new/

https://reviews.llvm.org/D147612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.

LGTM


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147611/new/

https://reviews.llvm.org/D147611

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147610/new/

https://reviews.llvm.org/D147610

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D149495: [RISCV] Add support for V extension in SiFive7

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM, thought please wait for other review feedback to settle.

I am very very happy to have this upstream, thank you!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

Mechanically, this looks fine.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149710/new/

https://reviews.llvm.org/D149710

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D149314#4302300 , @aaron.ballman 
wrote:

> In D149314#4302266 , @asb wrote:
>
>> In D149314#4302203 , 
>> @aaron.ballman wrote:
>>
>>> Is this a potentially breaking change that we need to call out for users to 
>>> be aware of?
>>
>> We should mention this in the Clang release notes I think.
>
> Beyond that, we've got a process for what to do when considering potentially 
> breaking changes, we should be following that: 
> https://llvm.org/docs/DeveloperPolicy.html#making-potentially-breaking-changes
>  Also, if we're all agreed this is potentially breaking, it really should 
> have more review time and buy-in from the code owner.

I don't think this change should count as "potentially breaking" in the sense 
of that document.  We're talking about an experimental feature for an 
experimental ISA extension which never got to ratification.  There's no 
hardware in the wild which implements this (to my knowledge).  Given the churn 
on the RISCV extension side, we've adopted a policy for experimental extensions 
(https://llvm.org/docs/RISCVUsage.html#experimental-extensions) which offers 
much less in the way of support.  I think we should release note it just to be 
friendly, but the process described in your link is significant overkill.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149314/new/

https://reviews.llvm.org/D149314

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D148066#4294924 , @kito-cheng 
wrote:

>> My concern would be that as we don't gate CSR names on enabling the relevant 
>> extension, people could start using CSR names and encodings that could 
>> change, without opting in via -menable-experimental-extensions, perhaps not 
>> realising that they're using the unratified version. OTOH, you could argue 
>> it was user error from the start by not trying to specify all the needed 
>> extensions in the ISA naming string.
>
> We decide don't gate CSR before, but I am wondering maybe we should gate 
> those CSR if they are defined by a unratified/experimental ext., and remove 
> the checking once it ratified, since it might change the name or CSR number 
> before ratified.

I think I agree with Kito here.  Requiring gating for experimental extensions 
even if we don't gate ratified ones seems like a good way to address the issue 
of name collision risk in experimental extensions.

I'm less concerned about number reassignment.  I'm most concerned that the same 
name might be reused across two extensions in a mutually incompatible way.  
This would clearly get fixed before both were ratified, but well, the entire 
point of experimental is that they not yet ratified.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148066/new/

https://reviews.llvm.org/D148066

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

I generally think this is a good idea.  I'd ask you add this to RISCVUsage 
under "The current known variances from the specification are", and mention it 
at the next sync up call, but otherwise, I think we should proceed with this.

LGTM once the above are done.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149246/new/

https://reviews.llvm.org/D149246

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

I would be fine landing this as experimental before ratification.  I see no 
real downside to doing that, and would essentially leave it the judgement of 
the patch author as to whether just waiting until ratification or doing the 
extra work for staging as experimental is worthwhile.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148066/new/

https://reviews.llvm.org/D148066

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

FYI, zvkb was discussed at the Architectural Review Committee this week and 
they've asked for some significant changes and expansions.  See the notes 
shared here: https://lists.riscv.org/g/tech-unprivileged/message/450

I actively do not think we need to wait on landing this patch until those 
expansions have been finalized.  I think is fine to land this in experimental 
state, and then transform zvkb into the requested form.   Having a generic 
vector bitmanip extension pulled out seems to make a lot of sense to me, and I 
like (most of) the proposed additions as they close holes we've encountered in 
codegen.

I've skimmed the review and didn't spot anything glaring, but want to leave 
approval to @craig.topper since he's already done one pass and is generally 
more familiar with the MC layer than I am.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D146146: [Clang] Stop demoting ElementCount/TypeSize conversion errors to warnings.

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

This makes perfect sense to me.  LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146146/new/

https://reviews.llvm.org/D146146

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144914/new/

https://reviews.llvm.org/D144914

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D144914: [Clang][Driver] Add -mcpu=help to clang

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Code and description appear out of sync.  (help != list)  Personally, I like 
the help naming a lot better.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144914/new/

https://reviews.llvm.org/D144914

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D144288: [RISCV] Add missing plumbing and tests for zfa

[Philip Reames via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG495b65348023: [RISCV] Add missing plumbing and tests for zfa 
(authored by reames).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144288/new/

https://reviews.llvm.org/D144288

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -199,3 +199,6 @@
 
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute  5, "rv32i2p0_zifencei2p0"
+
+.attribute arch, "rv32izfa0p1"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zfa0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -48,6 +48,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZCF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZICSR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZIFENCEI %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZFA %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck 
--check-prefixes=CHECK,RV64M %s
@@ -103,6 +104,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZCD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZICSR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZIFENCEI %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZFA %s
 
 ; CHECK: .attribute 4, 16
 
@@ -153,6 +155,7 @@
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
+; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -207,6 +210,7 @@
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
+; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -126,6 +126,7 @@
 {"zcb", RISCVExtensionVersion{1, 0}},
 {"zcd", RISCVExtensionVersion{1, 0}},
 {"zcf", RISCVExtensionVersion{1, 0}},
+{"zfa", RISCVExtensionVersion{0, 1}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
 {"zawrs", RISCVExtensionVersion{1, 0}},
 {"ztso", RISCVExtensionVersion{0, 1}},
@@ -836,6 +837,7 @@
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsZcb[] = {"zca"};
+static const char *ImpliedExtsZfa[] = {"f"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -854,6 +856,7 @@
 {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
 {{"zcb"}, {ImpliedExtsZcb}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
+{{"zfa"}, {ImpliedExtsZfa}},
 {{"zfh"}, {ImpliedExtsZfh}},
 {{"zfhmin"}, {ImpliedExtsZfhmin}},
 {{"zhinx"}, {ImpliedExtsZhinx}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -506,3 +506,11 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64izifencei2p0 -x c 
-E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZIFENCEI-EXT %s
 // CHECK-ZIFENCEI-EXT: __riscv_zifencei 200{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv32izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv64izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// CHECK-ZFA-EXT: __riscv_zfa 1000{{$}}


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -199,3 +199,6 @@
 
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute  5, "rv32i2p0_zifencei2p0"
+
+.attribute arch, "rv32izfa0p1"
+# CHECK

[PATCH] D144288: [RISCV] Add missing plumbing and tests for zfa

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 498512.
reames added a comment.

Address review comment


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144288/new/

https://reviews.llvm.org/D144288

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -199,3 +199,6 @@
 
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute  5, "rv32i2p0_zifencei2p0"
+
+.attribute arch, "rv32izfa0p1"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zfa0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -48,6 +48,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZCF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZICSR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZIFENCEI %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZFA %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck 
--check-prefixes=CHECK,RV64M %s
@@ -103,6 +104,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZCD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZICSR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZIFENCEI %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZFA %s
 
 ; CHECK: .attribute 4, 16
 
@@ -153,6 +155,7 @@
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
+; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -207,6 +210,7 @@
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
+; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -126,6 +126,7 @@
 {"zcb", RISCVExtensionVersion{1, 0}},
 {"zcd", RISCVExtensionVersion{1, 0}},
 {"zcf", RISCVExtensionVersion{1, 0}},
+{"zfa", RISCVExtensionVersion{0, 1}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
 {"zawrs", RISCVExtensionVersion{1, 0}},
 {"ztso", RISCVExtensionVersion{0, 1}},
@@ -836,6 +837,7 @@
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsZcb[] = {"zca"};
+static const char *ImpliedExtsZfa[] = {"f"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -854,6 +856,7 @@
 {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
 {{"zcb"}, {ImpliedExtsZcb}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
+{{"zfa"}, {ImpliedExtsZfa}},
 {{"zfh"}, {ImpliedExtsZfh}},
 {{"zfhmin"}, {ImpliedExtsZfhmin}},
 {{"zhinx"}, {ImpliedExtsZhinx}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -506,3 +506,11 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64izifencei2p0 -x c 
-E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZIFENCEI-EXT %s
 // CHECK-ZIFENCEI-EXT: __riscv_zifencei 200{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv32izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv64izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// CHECK-ZFA-EXT: __riscv_zfa 1000{{$}}


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -199,3 +199,6 @@
 
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute  5, "rv32i2p0_zifencei2p0"
+
+.attribute arch, "rv32izfa0p1"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zfa0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
==

[PATCH] D144288: [RISCV] Add missing plumbing and tests for zfa

[Philip Reames via Phabricator via cfe-commits]

reames created this revision.
reames added reviewers: craig.topper, asb, Joshua-401, kito-cheng, lbenes, 
jrtc27.
Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, jdoerfert, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, shiva0217, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, 
hiraditya, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Experimental support for the zfa extension was recently added in 
https://reviews.llvm.org/D141984.  A couple of the normal test changes and 
clang plumbing got missed in that change.  This commit updates the usual 
suspects.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144288

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -199,3 +199,6 @@
 
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute  5, "rv32i2p0_zifencei2p0"
+
+.attribute arch, "rv32izfa0p1"
+# CHECK: attribute  5, "rv32i2p0_zfa0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -48,6 +48,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZCF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZICSR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZIFENCEI %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck 
--check-prefixes=CHECK,RV32ZFA %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck 
--check-prefixes=CHECK,RV64M %s
@@ -103,6 +104,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZCD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZICSR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZIFENCEI %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck 
--check-prefixes=CHECK,RV64ZFA %s
 
 ; CHECK: .attribute 4, 16
 
@@ -153,6 +155,7 @@
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
+; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -207,6 +210,7 @@
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
+; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -126,6 +126,7 @@
 {"zcb", RISCVExtensionVersion{1, 0}},
 {"zcd", RISCVExtensionVersion{1, 0}},
 {"zcf", RISCVExtensionVersion{1, 0}},
+{"zfa", RISCVExtensionVersion{0, 1}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
 {"zawrs", RISCVExtensionVersion{1, 0}},
 {"ztso", RISCVExtensionVersion{0, 1}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -506,3 +506,11 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64izifencei2p0 -x c 
-E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZIFENCEI-EXT %s
 // CHECK-ZIFENCEI-EXT: __riscv_zifencei 200{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv32izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv64izfa0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
+// CHECK-ZFA-EXT: __riscv_zfa 1000{{$}}


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -199,3 +199,6 @@
 
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute  5, "rv32i2p0_zifencei2p

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG22e199e6afb1: [RISCV] Accept zicsr and zifencei command line 
options (authored by reames).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143953/new/

https://reviews.llvm.org/D143953

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -193,3 +193,9 @@
 
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
+
+.attribute arch, "rv32izicsr2p0"
+# CHECK: attribute  5, "rv32i2p0_zicsr2p0"
+
+.attribute arch, "rv32izifencei2p0"
+# CHECK: attribute  5, "rv32i2p0_zifencei2p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -46,6 +46,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
+; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -99,6 +101,8 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
+; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
 
 ; CHECK: .attribute 4, 16
 
@@ -147,6 +151,8 @@
 ; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
+; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
+; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -199,6 +205,8 @@
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
+; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
+; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -71,6 +71,20 @@
 AssemblerPredicate<(all_of FeatureStdExtZihintntl),
 "'Zihintntl' (Non-Temporal Locality Hints)">;
 
+def FeatureStdExtZicsr
+: SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+   "'zicsr' (CSRs)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+AssemblerPredicate<(all_of FeatureStdExtZicsr),
+"'Zicsr' (CSRs)">;
+
+def FeatureStdExtZifencei
+: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
+   "'zifencei' (fence.i)">;
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+   AssemblerPredicate<(all_of FeatureStdExtZifencei),
+   "'Zifencei' (fence.i)">;
+
 def FeatureStdExtZfhmin
 : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -103,6 +103,8 @@
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
+{"zicsr", RISCVExtensionVersion{2, 0}},
+{"zifencei", RISCVExtensionVersion{2, 0}},
 
 {"svnapot", RISCVExtensionVersion{1, 0}},
 {"svpbmt", RISCVExtensionVersion{1, 0}},
Index: l

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

This was discussed at today's RISCV sync-up call.  We have a large conversion 
pending on the topic of isa compatibility checking, but there was a consensus 
that this was reasonable and could move forward.  I'm going to be landing this 
change in the near future.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143953/new/

https://reviews.llvm.org/D143953

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

We seem to have rough consensus here, but I'm going to wait roughly 24 hours 
before landing to give others time to comment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143953/new/

https://reviews.llvm.org/D143953

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 497336.
reames added a comment.

Address @jrtc27's comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143953/new/

https://reviews.llvm.org/D143953

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -193,3 +193,9 @@
 
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
+
+.attribute arch, "rv32izicsr2p0"
+# CHECK: attribute  5, "rv32i2p0_zicsr2p0"
+
+.attribute arch, "rv32izifencei2p0"
+# CHECK: attribute  5, "rv32i2p0_zifencei2p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -45,6 +45,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
+; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -97,6 +99,8 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
+; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
 
 ; CHECK: .attribute 4, 16
 
@@ -144,6 +148,8 @@
 ; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
+; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
+; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -195,6 +201,8 @@
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
+; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
+; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -71,6 +71,20 @@
 AssemblerPredicate<(all_of FeatureStdExtZihintntl),
 "'Zihintntl' (Non-Temporal Locality Hints)">;
 
+def FeatureStdExtZicsr
+: SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+   "'zicsr' (CSRs)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+AssemblerPredicate<(all_of FeatureStdExtZicsr),
+"'Zicsr' (CSRs)">;
+
+def FeatureStdExtZifencei
+: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
+   "'zifencei' (fence.i)">;
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+   AssemblerPredicate<(all_of FeatureStdExtZifencei),
+   "'Zifencei' (fence.i)">;
+
 def FeatureStdExtZfhmin
 : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -103,6 +103,8 @@
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
+{"zicsr", RISCVExtensionVersion{2, 0}},
+{"zifencei", RISCVExtensionVersion{2, 0}},
 
 {"svnapot", RISCVExtensionVersion{1, 0}},
 {"svpbmt", RISCVExtensionVersion{1, 0}},
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -130,7 +130,7 @@
 .. _riscv-i

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 497328.
reames edited the summary of this revision.
reames added a comment.

Add docs, and rework description.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143953/new/

https://reviews.llvm.org/D143953

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -193,3 +193,9 @@
 
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
+
+.attribute arch, "rv32izicsr2p0"
+# CHECK: attribute  5, "rv32i2p0_zicsr2p0"
+
+.attribute arch, "rv32izifencei2p0"
+# CHECK: attribute  5, "rv32i2p0_zifencei2p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -45,6 +45,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
+; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -97,6 +99,9 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
+; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
+
 
 ; CHECK: .attribute 4, 16
 
@@ -144,6 +149,9 @@
 ; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
+; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
+; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
+
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -195,6 +203,8 @@
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
+; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
+; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -71,6 +71,20 @@
 AssemblerPredicate<(all_of FeatureStdExtZihintntl),
 "'Zihintntl' (Non-Temporal Locality Hints)">;
 
+def FeatureStdExtZicsr
+: SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+   "'zicsr' (CSRs)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+AssemblerPredicate<(all_of FeatureStdExtZicsr),
+"'Zicsr' (CSRs)">;
+
+def FeatureStdExtZifencei
+: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
+   "'zifencei' (ifence)">;
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+   AssemblerPredicate<(all_of FeatureStdExtZifencei),
+   "'Zifencei' (ifence)">;
+
 def FeatureStdExtZfhmin
 : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -103,6 +103,8 @@
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
+{"zicsr", RISCVExtensionVersion{2, 0}},
+{"zifencei", RISCVExtensionVersion{2, 0}},
 
 {"svnapot", RISCVExtensionVersion{1, 0}},
 {"svpbmt", RISCVExtensionVersion{1, 0}},
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D143953#4124649 , @jrtc27 wrote:

> In D143953#4124636 , @reames wrote:
>
>> @jrtc27 Not sure if this changes your take, but I realized the variant being 
>> introduced is maybe much less interesting than I'd first thought.  We 
>> generally make no effort to make sure an extension was defined in the spec 
>> version corresponding to our base revision.  Given that, we have a bunch of 
>> cases where we allow I2.0 + some random extension.  Given that, this one 
>> stops looking all that interesting.  It doesn't actually set much precedent 
>> - because we already did that, a long time ago.
>>
>> If you agree with that framing, I'll rework the description.
>
> Hm, do we allow M + Zmmul? If so then I guess I can get behind that view.



  $ ~/llvm-dev/build/bin/clang -target riscv64 -march=rv64g_zmmul 
vector_add_i32.c -S
  $ cat vector_add_i32.s 
.text
.attribute  4, 16
.attribute  5, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"

vector_add_i32.c is a random C file; contents are uninteresting.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143953/new/

https://reviews.llvm.org/D143953

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

@jrtc27 Not sure if this changes your take, but I realized the variant being 
introduced is maybe much less interesting than I'd first thought.  We generally 
make no effort to make sure an extension was defined in the spec version 
corresponding to our base revision.  Given that, we have a bunch of cases where 
we allow I2.0 + some random extension.  Given that, this one stops looking all 
that interesting.  It doesn't actually set much precedent - because we already 
did that, a long time ago.

If you agree with that framing, I'll rework the description.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143953/new/

https://reviews.llvm.org/D143953

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

reames created this revision.
reames added reviewers: asb, frasercrmck, kito-cheng, jrtc27, craig.topper.
Herald added subscribers: luke, VincentWu, vkmr, jdoerfert, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, 
shiva0217, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, hiraditya, 
kristof.beyls, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

This change adds the definition of the two extensions, but does not either a) 
make any instruction conditional on them or b) enabled the extensions by 
default.  (The *instructions* do remain enabled by default per ISA version 2.0 
which is our current default.)

This is meant to be a building block towards something like 
https://reviews.llvm.org/D141666, and in the meantime, address one of the most 
surprising of the current user experience warts.  The current behavior of 
rejecting the extensions at the command line despite emitting code which 
appears to use them is surprising to anyone not deeply versed in the details of 
this situation.

Between versions 2.0 and 2.1 of the base I specification, a backwards 
incompatible change was made to remove selected instructions and CSRs from the 
base ISA. These instructions were grouped into a set of new extensions (these), 
but were no longer required by the base ISA. This change is described in 
“Preface to Document Version 20190608-Base-Ratified” from the specification 
document.

As LLVM currently implements only version 2.0 of the base specification, 
accepting these extensions at the command line introduces a configuration which 
doesn't actually match any spec version.  It's a pretty harmless variant since 
the 2.0 extension definitions, to my knowledge, exactly match the text from the 
2.0 I text before they were moved into standalone extensions in 2.1 of I.  (The 
version numbering in that sentence is a tad confusing to say the least.  
Hopefully I got it right.)

If we decide we don't want to accept this variant, the other obvious near term 
option would be to detect and error with a more helpful error message.

Worth noting is that we're setting precedent here.  There's at least one other 
case I know of which is analogous (counters), and others may come up in the 
future.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143953

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -193,3 +193,9 @@
 
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
+
+.attribute arch, "rv32izicsr2p0"
+# CHECK: attribute  5, "rv32i2p0_zicsr2p0"
+
+.attribute arch, "rv32izifencei2p0"
+# CHECK: attribute  5, "rv32i2p0_zifencei2p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -45,6 +45,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
+; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -97,6 +99,9 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
+; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
+
 
 ; CHECK: .attribute 4, 16
 
@@ -144,6 +149,9 @@
 ; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
+; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
+; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
+
 
 ; RV64M: .attribute 5, "rv64i2

[PATCH] D141666: [RISCV] Proper support of extensions Zicsr and Zifencei

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

JFYI, I have a change out which just documents current status while we wait for 
a resolution.  https://reviews.llvm.org/D143924


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141666/new/

https://reviews.llvm.org/D141666

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143507: [RISCV][MC] Mark Zawrs extension as non-experimental

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143507/new/

https://reviews.llvm.org/D143507

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

This was brought up in today's RISCV sync call; I want to summarize the major 
points of discussion.

This patch is now behind the current most recent revision on the vector-crypto 
spec.  
(https://github.com/riscv/riscv-crypto/releases/download/v20230125/riscv-crypto-spec-vector.pdf)
  The assumption is that the patch needs to be updated to match most recent.  
If there's a reason why this assumption is wrong, please explicitly describe 
the argument.

There was confusion around the versioning scheme used in the vector-crypto 
spec.  It looks like newer version have moved to an internally consistent (and 
less than 1.0) version scheme, so I think this item is resolved.

There was a mention of another change being made to the spec in the near future 
and a desire to wait until that had happened.  This isn't required by our 
experimental extension policy.  However, in generally trying to minimize churn 
by delaying a couple days is not unreasonable.  I'd welcome comment from 
someone following spec changes as to whether we should delay here or not, and 
why.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Generally supportive of having such an option, but going to defer to others on 
the review.  I don't work enough on clang to have an opinion on code here.




Comment at: clang/docs/ReleaseNotes.rst:844
   take architecture extensions from ``-march`` if both are given.
+- Added -rvv-vector-bits= option to give an upper bound on vector length. Valid
+  values are powers of 2 between 64 and 65536. We also accept "zvl" to use

MaskRay wrote:
> 
Correct me if I'm wrong, but doesn't this set both an upper and lower bound?  
If so, the wording in the note here needs changed.  If not, the naming should 
probably be something like rvv-vector-bits-max.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142144/new/

https://reviews.llvm.org/D142144

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136817: [RISCV] Add H extension

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136817/new/

https://reviews.llvm.org/D136817

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Some very high level comments for the moment.

Until the spec is frozen, these need to be moved into the experimental 
namespace.  You should also add a mention of them under the experimental list 
in docs/RISCVUsage.  A link to the current spec version - along with an exact 
version you're implementing - in both the docs, and commit comment is also 
needed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG780c53984449: [RISCV] Implement assembler support for 
XVentanaCondOps (authored by reames).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -190,6 +191,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -0,0 +1,29 @@
+//===-- RISCVInstrInfoXVentana.td --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by Ventana Micro Systems.
+//
+//===--===//
+
+//===--===//
+// XVentanaCondOps
+//===--===//
+
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana" in
+class VTMaskedMove funct3, string opcodestr>
+: RVInstR<0b

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 474782.
reames added a comment.

Address comments from @craig.topper


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -189,6 +190,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -0,0 +1,29 @@
+//===-- RISCVInstrInfoXVentana.td --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by Ventana Micro Systems.
+//
+//===--===//
+
+//===--===//
+// XVentanaCondOps
+//===--===//
+
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana" in
+class VTMaskedMove funct3, string opcodestr>
+: RVInstR<0b000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
+  (ins GPR:$rs1, GPR:$rs2), opcodestr,
+  "$rd, $rs1, $rs2"> {
+}
+
+def VT_MASKC : VTMaskedMove<0b110, "v

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 474620.
reames added a comment.

Address Kito's review comments


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -189,6 +190,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -0,0 +1,32 @@
+//===-- RISCVInstrInfoXVentana.td --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by Ventana Micro Systems.
+//
+//===--===//
+
+//===--===//
+// -XVentanaCondOps
+//===--===//
+
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana"
+  in {
+
+class VTMaskedMove funct3, string opcodestr>
+: RVInstR<0b000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
+  (ins GPR:$rs1, GPR:$rs2), opcodestr,
+  "$rd, $rs1, $rs2">{
+}
+
+def VT_MASKC : VTMaskedMove<0b110, 

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 473285.
reames added a comment.

Rebase


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -189,6 +190,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1780,3 +1780,25 @@
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
+
+//===--===//
+// Vendor extensions
+//===--===//
+
+// -XVentanaCondOps
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana"
+  in {
+
+class VTMaskedMove funct3, string opcodestr>
+: RVInstR<0b000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
+  (ins GPR:$rs1, GPR:$rs2), opcodestr,
+  "$rd, $rs1, $rs2">{
+}
+
+def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
+   Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+
+def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
+   Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+}
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,21 @@
AssemblerPredicate<(all_of FeatureStdExtZawrs),

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 473272.
reames added a comment.

Add a decoder namespace.

I did one per vendor - i.e. used a Ventana table rather than a VentanaCondOps 
one.  In theory, we could have a vendor who ships incompatible extensions (in 
two different pieces of hardware), but if we hit that case, we can adjust 
later.  Or at least, I think we can?  This is new to me.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -189,6 +190,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1780,3 +1780,25 @@
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
+
+//===--===//
+// Vendor extensions
+//===--===//
+
+// -XVentanaCondOps
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana"
+  in {
+
+class VTMaskedMove funct3, string opcodestr>
+: RVInstR<0b000, funct3, OPC_CUSTOM3, (outs GPR:$rd),
+  (ins GPR:$rs1, GPR:$rs2), opcodestr,
+  "$rd, $rs1, $rs2">{
+}
+
+def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
+   Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+
+def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
+  

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 473022.
reames added a comment.

Address review comments from @craig.topper


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -189,6 +190,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1780,3 +1780,24 @@
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
+
+//===--===//
+// Vendor extensions
+//===--===//
+
+// -XVentanaCondOps
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in {
+
+class VTMaskedMove funct3, string opcodestr>
+: RVInstR<0b000, funct3, OPC_CUSTOM3, (outs GPR:$rd),
+  (ins GPR:$rs1, GPR:$rs2), opcodestr,
+  "$rd, $rs1, $rs2">{
+}
+
+def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
+   Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+
+def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
+   Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+}
Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td
===
--- llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -145,6 +145,7 @@
 def OPC_JALR  : RISCVOpcode<"JALR",  0b1100111>;
 def OPC_JAL   : RISCVOpcod

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D137350#3906126 , @craig.topper 
wrote:

> Do these need their own DecoderNameSpace?

What is a decoder namespace?  Some quick grepping and googling isn't very 
informative.




Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:148
 def OPC_SYSTEM: RISCVOpcode<"SYSTEM",0b1110011>;
+def OPC_CUSTOM3   : RISCVOpcode<"CUSTOM3",   0b011>;
 

craig.topper wrote:
> Since the string here is used for .insn parsing, I think it should be 
> CUSTOM_3. I'm not sure why we don't already have all 4 added.
https://reviews.llvm.org/D137355


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 473001.
reames added a comment.

Fix silly typo


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -189,6 +190,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondOps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1780,3 +1780,24 @@
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
+
+//===--===//
+// Vendor extensions
+//===--===//
+
+// -XVentanaCondOps
+let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in {
+
+class VTMaskedMove funct3, string opcodestr>
+: RVInstR<0b000, funct3, OPC_CUSTOM3, (outs GPR:$rd),
+  (ins GPR:$rs1, GPR:$rs2), opcodestr,
+  "$rd, $rs1, $rs2">{
+}
+
+def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
+   Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+
+def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
+   Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+}
Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td
===
--- llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -145,6 +145,7 @@
 def OPC_JALR  : RISCVOpcode<"JALR",  0b1100111>;
 def OPC_JAL   : RISCVOpcode<"JAL",   0b110>;
 

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:437
+
+// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s

Naming wise, is xventanacondops what we want this called?  The toolchain docs 
linked are a bit ambiguous on this point.  They seem to be saying that the 
extension should maybe be xvtcondops.  But that's not what the spec uses, not 
what we tend to use in discussion, and not what is being discussed for 
binutils.



Comment at: clang/test/Preprocessor/riscv-target-features.c:439
+// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
+// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 100{{$}}

This patch only includes positive tests for riscv64.  Per the current 
specification, no rv32 chips have shipped with this feature.  I chose not to 
actually reject the flags or elf settings for riscv32, but to not enable the 
assembler either.

What do we think is the right answer here?  Should we accept the riscv32 forms? 
 This would essentially be an LLVM extension.  Should we explicitly error on 
the riscv32 form?  Something else?



Comment at: llvm/docs/RISCVUsage.rst:161
+``XVentanaCondOps``
+  LLVM implements `version 1.0.0 of the VTx-family custom instructions 
specification 
`_
 by Ventana Micro Systems.  All instructions are prefixed with `vt.` as 
described in the specification, and the riscv-toolchai-convention document 
linked above.  These instructions are only available for riscv64 at this time.
+

Anything else we want in the documentation?  Remember, we're setting precedent 
here.  



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1785
+//===--===//
+// Vendor extensions
+//===--===//

How do we want to manage td files for vendor extensions?

I put them inline - which is probably not the right answer.  I'm leaning 
towards a vendor specific td file with extensions split out if complexity 
justifies it.  So, this patch would add a RISCVInstInfoXVentana.td.  

Is that the precedent we want here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames created this revision.
reames added reviewers: craig.topper, asb, frasercrmck, kito-cheng, jrtc27.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, jdoerfert, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, shiva0217, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, 
hiraditya, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

This change provides an implementation of the XVentanaCondOps vendor extension. 
 This extension is defined in version 1.0.0 of the VTx-family custom 
instructions specification 
(https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)
 by Ventana Micro Systems.

This change is intended to be a test case for our vendor extension policy.  I 
believe this to be a case we clearly should accept, but it gives us an 
opportunity to discuss and set precedent on various policy and naming 
questions.  (I will comment on the review to highlight questions I think are 
worth discussion.)

I intent to bring this up at the next RISCV sync call, and ensure we have 
consensus.  Once this lands, I plan to use this extension to prototype 
selection lowering to conditional moves.  There's an RVI proposal in flight, 
and the expectation is that lowering to these and the new RVI instructions is 
likely to be substantially similar.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

Index: llvm/test/MC/RISCV/XVentanaCondOps-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/XVentanaCondOps-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN: | llvm-objdump --mattr=+xventanacondops -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x60,0x00,0x00]
+vt.maskc x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskcn zero, zero, zero
+# CHECK-ASM: encoding: [0x7b,0x70,0x00,0x00]
+vt.maskcn x0, x0, x0
+
+# CHECK-ASM-AND-OBJ: vt.maskc ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x60,0x31,0x00]
+vt.maskc x1, x2, x3
+
+# CHECK-ASM-AND-OBJ: vt.maskcn ra, sp, gp
+# CHECK-ASM: encoding: [0xfb,0x70,0x31,0x00]
+vt.maskcn x1, x2, x3
+
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -76,6 +76,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
@@ -157,6 +158,7 @@
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -90,6 +90,7 @@
   bool HasStdExtZmmul = false;
   bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
+  bool HasVendorXVentanaCondOps = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -189,6 +190,7 @@
   bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
+  bool hasVendorXVentanaCondPps() const { return HasVendorXVentanaCondOps; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return 

[PATCH] D137280: [RISCV] Prevent autovectorization using vscale with Zvl32b.

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM

I'm fine with this, but I thought we didn't support zve32f during compilation 
at all right now?  Is this the only issue which needs fixed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137280/new/

https://reviews.llvm.org/D137280

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137266: [RISCV] Move RVVBitsPerBlock to TargetParser.h so we can use it in clang. NFC

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137266/new/

https://reviews.llvm.org/D137266

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136817: [RISCV] Add H extension

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/docs/RISCVUsage.rst:54
  ``F``Supported
+ ``H``Supported
  ``M``Supported

If I'm reading the code right here, we only have assembly support here.  Given 
that, shouldn't this be Assembly Support?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136817/new/

https://reviews.llvm.org/D136817

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136571: [RISCV] add svinval extension

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136571: [RISCV] add svinval extension

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/docs/RISCVUsage.rst:56
  ``V``Supported
+ ``Svinval``  Assembly Support
  ``Zba``  Supported

This table is sorted alphabetically, please move above V.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136511: [RISCV][clang] Support RISC-V vectors in UninitializedValues.

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136511/new/

https://reviews.llvm.org/D136511

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136571: [RISCV] add svinval extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Please update https://llvm.org/docs/RISCVUsage.html#extensions

It seems like we'd previously accept these instruction without the extension 
being explicitly named?  If so, this is probably worth a release note to 
document the change in user behavior.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136571/new/

https://reviews.llvm.org/D136571

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136570: [RISCV] Add Svnapot extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

https://llvm.org/docs/RISCVUsage.html#extensions needs to updated after this 
change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136570/new/

https://reviews.llvm.org/D136570

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Just want to note that I have no strong opinion on this patch.  It doesn't seem 
unreasonable, and I'm comfortable with this being an empirically driven 
decision.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116735/new/

https://reviews.llvm.org/D116735

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136106: [clang][RISCV] Set vscale_range attribute based on VLEN

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D136106#3863202 , @reames wrote:

> In D136106#3863147 , @craig.topper 
> wrote:
>
>>> In the original review, I'd mentioned that MinVLEN was sometimes zero. 
>>> That's still true, but apparently only happens if you specify multiple 
>>> extensions in the -target_feature string. So, we can at least test "v" and 
>>> "zve64x" on their own before I go figure out exactly what's going wrong 
>>> regarding e.g. parsing "+v,+zvl512b".
>>
>> I think you need to use `-target-feature "v" -target-feature "zvl512b".
>
> So, this was part right.  The other issue is I'd been using Zvl512b, and 
> apparently this bit of parsing code is case sensitive.  I'm going to look 
> into improving the error reporting here.

Replying back to myself here as I'm not quite sure where to put this...

So, it turns out target-feature is currently quite weird.  At the *clang* 
level, we require individual target-feature options for each extensions.  Using 
a compound "+v,+zvl512b" is not recognized by the clang code (i.e, the bit this 
patch was modifying).  However, this raw string gets joined with the valid 
attributes, and set into the IR as "target-features"="+64bit,+v,+zvl512b" on 
the function.  This string is then parsed by later consumers, and thus the 
extensions listed in the compound list *are* picked up during e.g. codegen.  
So, it turns out we both do, and don't, parse these compound target-feature 
strings.

I'm leaning in the direction of having clang just support the compound 
target-feature strings, but I haven't found the right place for that just yet.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136106/new/

https://reviews.llvm.org/D136106

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136106: [clang][RISCV] Set vscale_range attribute based on VLEN

[Philip Reames via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9a8f3b113d05: [clang][RISCV] Set vscale_range attribute 
based on VLEN (authored by reames).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136106/new/

https://reviews.llvm.org/D136106

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/riscv-vector-bits-vscale-range.c
  llvm/include/llvm/Support/RISCVISAInfo.h


Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -60,6 +60,7 @@
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
   unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxVLen() const { return 65536; }
   unsigned getMaxELen() const { return MaxELen; }
   unsigned getMaxELenFp() const { return MaxELenFp; }
 
Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- clang/test/CodeGen/riscv-vector-bits-vscale-range.c
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -9,11 +9,17 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 
--check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 
--check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-UNBOUNDED
-// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-V
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-target-feature +zvl512b -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-ZVL
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64x -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ZVE64
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64f 
-target-feature +f -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-ZVE64
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d 
-target-feature +f -target-feature +d -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-ZVE64
 
 // CHECK-LABEL: @func() #0
 // CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
 // CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
 // CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
-// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-V: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-ZVL: attributes #0 = { {{.*}} vscale_range(8,1024) {{.*}} }
+// CHECK-ZVE64: attributes #0 = { {{.*}} vscale_range(1,1024) {{.*}} }
 void func(void) {}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -252,9 +252,11 @@
 return std::pair(
 LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
 
-  if (hasFeature("v"))
-// Minimum VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
-return std::pair(2, 1024);
+  if (unsigned MinVLen = ISAInfo->getMinVLen()) {
+unsigned MaxVLen = ISAInfo->getMaxVLen();
+// RISCV::RVVBitsPerBlock is 64.
+return std::pair(MinVLen/64, MaxVLen/64);
+  }
 
   return None;
 }


Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -60,6 +60,7 @@
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
   unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxVLen() const { return 65536; }
   unsigned getMaxELen() const { return MaxELen; }
   unsigned getMaxELenFp() const { return MaxELenFp; }
 
Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- clang/test/CodeGen/riscv-vector-bits-vscale-range.c
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -9,11 +9,17 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 --check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 --ch

[PATCH] D136106: [clang][RISCV] Set vscale_range attribute based on VLEN

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 468344.
reames edited the summary of this revision.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136106/new/

https://reviews.llvm.org/D136106

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/riscv-vector-bits-vscale-range.c
  llvm/include/llvm/Support/RISCVISAInfo.h


Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -60,6 +60,7 @@
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
   unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxVLen() const { return 65536; }
   unsigned getMaxELen() const { return MaxELen; }
   unsigned getMaxELenFp() const { return MaxELenFp; }
 
Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- clang/test/CodeGen/riscv-vector-bits-vscale-range.c
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -9,11 +9,17 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 
--check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 
--check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-UNBOUNDED
-// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-V
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-target-feature +zvl512b -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-ZVL
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64x -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ZVE64
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64f 
-target-feature +f -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-ZVE64
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d 
-target-feature +f -target-feature +d -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-ZVE64
 
 // CHECK-LABEL: @func() #0
 // CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
 // CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
 // CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
-// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-V: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-ZVL: attributes #0 = { {{.*}} vscale_range(8,1024) {{.*}} }
+// CHECK-ZVE64: attributes #0 = { {{.*}} vscale_range(1,1024) {{.*}} }
 void func(void) {}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -252,9 +252,11 @@
 return std::pair(
 LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
 
-  if (hasFeature("v"))
-// Minimum VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
-return std::pair(2, 1024);
+  if (unsigned MinVLen = ISAInfo->getMinVLen()) {
+unsigned MaxVLen = ISAInfo->getMaxVLen();
+// RISCV::RVVBitsPerBlock is 64.
+return std::pair(MinVLen/64, MaxVLen/64);
+  }
 
   return None;
 }


Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -60,6 +60,7 @@
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
   unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxVLen() const { return 65536; }
   unsigned getMaxELen() const { return MaxELen; }
   unsigned getMaxELenFp() const { return MaxELenFp; }
 
Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- clang/test/CodeGen/riscv-vector-bits-vscale-range.c
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -9,11 +9,17 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 --check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 --check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-UNBOUNDED
-

[PATCH] D136106: [clang][RISCV] Set vscale_range attribute based on VLEN

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D136106#3863147 , @craig.topper 
wrote:

>> In the original review, I'd mentioned that MinVLEN was sometimes zero. 
>> That's still true, but apparently only happens if you specify multiple 
>> extensions in the -target_feature string. So, we can at least test "v" and 
>> "zve64x" on their own before I go figure out exactly what's going wrong 
>> regarding e.g. parsing "+v,+zvl512b".
>
> I think you need to use `-target-feature "v" -target-feature "zvl512b".

So, this was part right.  The other issue is I'd been using Zvl512b, and 
apparently this bit of parsing code is case sensitive.  I'm going to look into 
improving the error reporting here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136106/new/

https://reviews.llvm.org/D136106

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136106: [clang][RISCV] Set vscale_range attribute based on VLEN

[Philip Reames via Phabricator via cfe-commits]

reames created this revision.
reames added a reviewer: craig.topper.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, bollu, simoncook, 
johnrusso, rbar, asb, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Follow up on D135894 , restructure code to 
work in terms of minimum and maximum VLEN coming from RISCVISAInfo.cpp.

In the original review, I'd mentioned that MinVLEN was sometimes zero.  That's 
still true, but apparently only happens if you specify multiple extensions in 
the -target_feature string.  So, we can at least test "v" and "zve64x" on their 
own before I go figure out exactly what's going wrong regarding e.g. parsing 
"+v,+zvl512b".


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136106

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/riscv-vector-bits-vscale-range.c
  llvm/include/llvm/Support/RISCVISAInfo.h


Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -60,6 +60,7 @@
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
   unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxVLen() const { return 65536; }
   unsigned getMaxELen() const { return MaxELen; }
   unsigned getMaxELenFp() const { return MaxELenFp; }
 
Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- clang/test/CodeGen/riscv-vector-bits-vscale-range.c
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -9,11 +9,13 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 
--check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 
--check-prefix=CHECK-NOMAX
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-UNBOUNDED
-// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-V
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64x -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ZVE64
 
 // CHECK-LABEL: @func() #0
 // CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
 // CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
 // CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
-// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-V: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+// CHECK-ZVE64: attributes #0 = { {{.*}} vscale_range(1,1024) {{.*}} }
 void func(void) {}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -252,9 +252,11 @@
 return std::pair(
 LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
 
-  if (hasFeature("v"))
-// Minimum VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
-return std::pair(2, 1024);
+  if (unsigned MinVLen = ISAInfo->getMinVLen()) {
+unsigned MaxVLen = ISAInfo->getMaxVLen();
+// RISCV::RVVBitsPerBlock is 64.
+return std::pair(MinVLen/64, MaxVLen/64);
+  }
 
   return None;
 }


Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -60,6 +60,7 @@
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
   unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxVLen() const { return 65536; }
   unsigned getMaxELen() const { return MaxELen; }
   unsigned getMaxELenFp() const { return MaxELenFp; }
 
Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- clang/test/CodeGen/riscv-vector-bits-vscale-range.c
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -9,11 +9,13 @@
 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=8 -S -emi

[PATCH] D135894: [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

[Philip Reames via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4467c781d7bb: [clang][RISCV] Set vscale_range attribute 
based on presence of "v" extension (authored by reames).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135894/new/

https://reviews.llvm.org/D135894

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/riscv-vector-bits-vscale-range.c


Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- /dev/null
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=2 -mvscale-max=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=4 -mvscale-max=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -mvscale-max=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -mvscale-max=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-UNBOUNDED
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+
+// CHECK-LABEL: @func() #0
+// CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
+// CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
+// CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
+// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+void func(void) {}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -90,6 +90,9 @@
  StringRef CPU,
  const std::vector &FeaturesVec) const override;
 
+  Optional>
+  getVScaleRange(const LangOptions &LangOpts) const override;
+
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector &Features,
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -246,6 +246,19 @@
   return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
+Optional>
+RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+  if (LangOpts.VScaleMin || LangOpts.VScaleMax)
+return std::pair(
+LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
+
+  if (hasFeature("v"))
+// Minimum VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
+return std::pair(2, 1024);
+
+  return None;
+}
+
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;


Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- /dev/null
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=1 -mvscale-max=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=2 -mvscale-max=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=4 -mvscale-max=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feat

[PATCH] D135894: [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 468239.
reames added a comment.

fix typo


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135894/new/

https://reviews.llvm.org/D135894

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/riscv-vector-bits-vscale-range.c


Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- /dev/null
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=2 -mvscale-max=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=4 -mvscale-max=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -mvscale-max=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -mvscale-max=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-UNBOUNDED
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+
+// CHECK-LABEL: @func() #0
+// CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
+// CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
+// CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
+// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+void func(void) {}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -90,6 +90,9 @@
  StringRef CPU,
  const std::vector &FeaturesVec) const override;
 
+  Optional>
+  getVScaleRange(const LangOptions &LangOpts) const override;
+
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector &Features,
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -246,6 +246,19 @@
   return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
+Optional>
+RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+  if (LangOpts.VScaleMin || LangOpts.VScaleMax)
+return std::pair(
+LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
+
+  if (hasFeature("v"))
+// Minimum VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
+return std::pair(2, 1024);
+
+  return None;
+}
+
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;


Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- /dev/null
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=1 -mvscale-max=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=2 -mvscale-max=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=4 -mvscale-max=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-min=8 -mvscale-max=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -mvscale-mi

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.
Herald added subscribers: sunshaoce, StephenFan, arichardson.
Herald added a project: All.

Not knowing about this patch, I posted D135894 
 which addresses a small sub-set of this.  If 
that goes in, I plan to iterative split off some other parts of this into stand 
alone changes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107290/new/

https://reviews.llvm.org/D107290

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D135894: [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D135894#3856229 , @craig.topper 
wrote:

> There's also this patch from @frasercrmck https://reviews.llvm.org/D107290

So there is; had not seen that.  Looking at it, that patch seems to roll 
several items together.  I'd strongly prefer if we worked incrementally here.  
I think we do need to merge the frontend and backend handling here, but we can 
we work one step at a time?

Steps as I currently see them:
Step 1 - get basic support for "v", to unblock practical codegen 
Step 2 - expose the necessary constants for frontend use, and rephrase in terms 
of VLEN
Step 3 - figure out why getMinVLen on RISCVISAInfo is currently always 
returning 0, fix that
Step 4 - revisit question if whether the result replaces TTI callback (I don't 
think it does, but don't want to speculate too much now.)

I'm willing to commit my time through at least step 3, and possibly beyond.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135894/new/

https://reviews.llvm.org/D135894

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D135894: [clang][RISCV] Set vscale_range attribute based on presence of "v" extension

[Philip Reames via Phabricator via cfe-commits]

reames created this revision.
reames added reviewers: asb, frasercrmck, craig.topper.
Herald added subscribers: sunshaoce, VincentWu, ctetreau, StephenFan, vkmr, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
javed.absar, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, bollu, 
simoncook, johnrusso, rbar, kristof.beyls, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

This follows the path that AArch64 SVE has taken.  Doing this via a function 
attribute set in the frontend is basically a workaround for the fact that 
several analyzes which need the information (i.e. known bits, lvi, scev) can't 
easily use TTI without significant amounts of plumbing changes.

This patch hard codes "v" numbers, and directly follows the SVE precedent as a 
result.  In a follow up, I hope to drive this from RISCVISAInfo.h/cpp instead, 
but the MinVLen number being returned from that interface seemed to always be 0 
(which is wrong), and I haven't figured out what's going wrong there.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D135894

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/riscv-vector-bits-vscale-range.c


Index: clang/test/CodeGen/riscv-vector-bits-vscale-range.c
===
--- /dev/null
+++ clang/test/CodeGen/riscv-vector-bits-vscale-range.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=2 -mvscale-max=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=4 -mvscale-max=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -mvscale-max=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -mvscale-max=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=2 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=4 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=4 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=8 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=8 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=16 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=16 
--check-prefix=CHECK-NOMAX
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v 
-mvscale-min=1 -mvscale-max=0 -S -emit-llvm -o - %s | FileCheck %s 
--check-prefix=CHECK-UNBOUNDED
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +v -S 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+
+// CHECK-LABEL: @func() #0
+// CHECK: attributes #0 = { {{.*}} vscale_range([[#VBITS]],[[#VBITS]]) {{.*}} }
+// CHECK-NOMAX: attributes #0 = { {{.*}} vscale_range([[#VBITS]],0) {{.*}} }
+// CHECK-UNBOUNDED: attributes #0 = { {{.*}} vscale_range(1,0) {{.*}} }
+// CHECK-NONE: attributes #0 = { {{.*}} vscale_range(2,1024) {{.*}} }
+void func(void) {}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -90,6 +90,9 @@
  StringRef CPU,
  const std::vector &FeaturesVec) const override;
 
+  Optional>
+  getVScaleRange(const LangOptions &LangOpts) const override;
+
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector &Features,
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -246,6 +246,19 @@
   return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
+Optional>
+RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+  if (LangOpts.VScaleMin || LangOpts.VScaleMax)
+return std::pair(
+LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
+
+  if (hasFeature("v"))
+// Minium VLEN=128, Maximum VLEN=64k, and RISCV::RVVBitsPerBlock is 64.
+return std::

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Please add to the review description a link to the appropriate specification.  
Please update docs/RISCVUsage.rst to add Zcmt, and link to the specification.  
It's impossible to review e.g. encoding without knowing what you're 
implementing.




Comment at: llvm/lib/Target/RISCV/RISCV.td:367
+   [FeatureExtZca]>; // TODO: add Zicsr as another 
dependence
+def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt() && 
!Subtarget->hasStdExtC()">,
+   AssemblerPredicate<(all_of FeatureExtZcmt, (not 
FeatureStdExtC)),

Wait, Zcmt can't be enabled if C is?  That seems odd...



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td:1
+//===-- RISCVInstrInfoZc.td - RISC-V 'Zc' instructions -*- tablegen 
-*-===//
+//

We have Zca in RISCVInstrInfoC.td.  Not sure it makes sense to have Zcmt in one 
place, and Zca in another. 

Also, did Zca change between 0.7 and 0.7.5?  If so, any plans to update that 
extension?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td:10
+/// This file describes the RISC-V instructions from the 'Zc' Code-size 
+/// reduction extension, version 0.70.5.
+/// This version is still experimental as the 'Zc' extension hasn't been

It's not just one extension.  It is several sub-extensions.

Please reword as "from the Zc* family of code size reduction extensions, 
version ...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133863/new/

https://reviews.llvm.org/D133863

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D133834: [RISCV] Remove support for the unratified Zbt extension.

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.

LGTM as well.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133834/new/

https://reviews.llvm.org/D133834

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D133443#3801899 , @asb wrote:

> It looks like they're still missing in this updated version of the patch?

I have no idea what's going wrong here.  I had been very careful to make sure 
the patch contained the new test file, but you're right, the revision in phab 
didn't.

Since we now had two LGTMs, and the tests had been in the original patch 
upload, I went ahead and landed.  The tests are in the committed patch; if you 
want any changes, let me know.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rGeda2af575fdf: [RISCV][MC] Add support for experimental Zawrs 
extension (authored by reames).

Changed prior to commit:
  https://reviews.llvm.org/D133443?vs=461345&id=461608#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/Zawrs-valid.s
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -197,5 +197,8 @@
 .attribute arch, "rv32izca0p70"
 # CHECK: attribute  5, "rv32i2p0_zca0p70"
 
+.attribute arch, "rv32izawrs1p0"
+# CHECK: attribute  5, "rv32i2p0_zawrs1p0"
+
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
Index: llvm/test/MC/RISCV/Zawrs-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/Zawrs-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zawrs -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zawrs -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zawrs < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zawrs -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zawrs < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zawrs -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: wrs.nto
+# CHECK-ASM: encoding: [0x73,0x00,0xd0,0x00]
+wrs.nto
+
+# CHECK-ASM-AND-OBJ: wrs.sto
+# CHECK-ASM: encoding: [0x73,0x00,0xd0,0x01]
+wrs.sto
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -84,6 +84,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
@@ -170,6 +171,7 @@
 ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
+; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -92,6 +92,7 @@
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
   bool HasStdExtZmmul = false;
+  bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
@@ -192,6 +193,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
   bool is64Bit() const { return HasRV64; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -705,6 +705,23 @@
   let rd = 0;
   let imm12 = 0b1100;
 }
+
+let Predicates = [HasStdExtZawrs] in {
+def WRS_NTO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.nto", "">,
+  Sched<[]> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b1101;
+}
+
+def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
+  Sched<[]> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 461345.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -197,5 +197,8 @@
 .attribute arch, "rv32izca0p70"
 # CHECK: attribute  5, "rv32i2p0_zca0p70"
 
+.attribute arch, "rv32izawrs1p0"
+# CHECK: attribute  5, "rv32i2p0_zawrs1p0"
+
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -84,6 +84,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
@@ -170,6 +171,7 @@
 ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
+; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -92,6 +92,7 @@
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
   bool HasStdExtZmmul = false;
+  bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
@@ -192,6 +193,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
   bool is64Bit() const { return HasRV64; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -705,6 +705,23 @@
   let rd = 0;
   let imm12 = 0b1100;
 }
+
+let Predicates = [HasStdExtZawrs] in {
+def WRS_NTO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.nto", "">,
+  Sched<[]> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b1101;
+}
+
+def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
+  Sched<[]> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b00011101;
+}
+} // Predicates = [HasStdExtZawrs]
+
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
 def CSRRW : CSR_ir<0b001, "csrrw">;
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -461,6 +461,13 @@
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
 
+def FeatureStdExtZawrs
+: SubtargetFeature<"experimental-zawrs", "HasStdExtZawrs", "true",
+   "'Zawrs' (Wait on Reservation Set)">;
+def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
+   AssemblerPredicate<(all_of FeatureStdExtZawrs),
+   "'Zawrs' (Wait on Reservation Set)">;
+
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -114,6 +114,7 @@
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zca", RISCVExtensionVersion{0, 70}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+{"zawrs", RISCVExtensionVersion{1, 0}},
 {"ztso", RISCVExtensionVersion{0, 1}},
 };
 
Index: llvm/docs/RISCVUsage.rst
=

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D133443#3795603 , @asb wrote:

> Everything that's in this patch looks good to me - it's just missing some 
> simple round-trip tests in the style of rv32zicboz-valid.s (and perhaps an 
> -invalid.s that shows a sensible error message being produced when the 
> instructions have an argument).

You had me very confused at first as I'd written the valid tests - until I 
realized they'd been lost in the rebase.  Updated patch forthcoming.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 460447.
reames added a comment.

Add docs.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -197,5 +197,8 @@
 .attribute arch, "rv32izca0p70"
 # CHECK: attribute  5, "rv32i2p0_zca0p70"
 
+.attribute arch, "rv32izawrs1p0"
+# CHECK: attribute  5, "rv32i2p0_zawrs1p0"
+
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -84,6 +84,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
@@ -170,6 +171,7 @@
 ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
+; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -92,6 +92,7 @@
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
   bool HasStdExtZmmul = false;
+  bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
@@ -192,6 +193,7 @@
   bool hasStdExtZicbom() const { return HasStdExtZicbom; }
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+  bool hasStdExtZawrs() const { return HasStdExtZawrs; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
   bool hasStdExtZtso() const { return HasStdExtZtso; }
   bool is64Bit() const { return HasRV64; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -705,6 +705,23 @@
   let rd = 0;
   let imm12 = 0b1100;
 }
+
+let Predicates = [HasStdExtZawrs] in {
+def WRS_NTO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.nto", "">,
+  Sched<[]> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b1101;
+}
+
+def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
+  Sched<[]> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b00011101;
+}
+} // Predicates = [HasStdExtZawrs]
+
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
 def CSRRW : CSR_ir<0b001, "csrrw">;
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -461,6 +461,13 @@
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
 
+def FeatureStdExtZawrs
+: SubtargetFeature<"experimental-zawrs", "HasStdExtZawrs", "true",
+   "'Zawrs' (Wait on Reservation Set)">;
+def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
+   AssemblerPredicate<(all_of FeatureStdExtZawrs),
+   "'Zawrs' (Wait on Reservation Set)">;
+
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -114,6 +114,7 @@
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zca", RISCVExtensionVersion{0, 70}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+{"zawrs", RISCVExtensionVersion{1, 0}},
 {"ztso", RISCVExtensionVersion{0, 1}},
 };
 
Index: llvm/docs/RISCVUsage.rst
=

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D133443#3792627 , @asb wrote:

> I think the summary of our discussion on this was:
>
> - The versioning confusion is unfortunate - ideally there would be discussion 
> elsewhere at RVI on improving the situation (either ELF attributes to 
> indicate extensions are experimental, or making that unnecessary via never 
> using 1.0 until something is ratified)
> - But the above isn't a blocker to merging. As the extension is gated by the 
> experimental flag, even if there are last minute changes the impact on users 
> should be minimal / non-existent.

Matches my takeaway.  I'm going to rebase this and add in a doc change which 
clearly notes the release candidate bit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D133443#3790420 , @asb wrote:

> The change in set of instructions without changing the version number is 
> concerning - do you know anyone involved in that group? It would be good to 
> feedback the difficulties this can cause for us. It's also not clear if there 
> might be changes again during ratification without changing the version 
> number, which wouldn't be ideal (though probably just about livable given 
> it's marked as experimental).

I agree that the incompatible change is highly sub-optimal.  I've asked around 
a bit on the status here, but nothing I would consider "official" or would want 
to quote someone on.  My overall take is that we probably should take this as 
experimental, but only with the understanding that it may change in 
incompatible ways.

> Let's discuss briefly in the meeting tomorrow. Implementation-wise it all 
> seems straightforward.

Definitely.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:709
+
+let Predicates = [HasStdExtZawrs] in {
+def WRS_NTO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.nto", "">,

jrtc27 wrote:
> This doesn't really belong here, but a separate RISCVInstrInfoZawrs.td also 
> seems a little overkill... hmm
I had the same thoughts.  I'm happy to defer to reviewers' preference.  



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:95
   bool HasStdExtZmmul = false;
+  bool HasStdExtZawrs = false;
   bool HasStdExtZtso = false;

jrtc27 wrote:
> I would say keep these sorted but this seems to be a bit of a mess...
I'm happy to sort in a separate change if you'd like.  Preferably after this 
lands.  :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133443/new/

https://reviews.llvm.org/D133443

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Philip Reames via Phabricator via cfe-commits]

reames created this revision.
reames added reviewers: palmer-dabbelt, sunshaoce, craig.topper, kito-cheng, 
jrtc27, frasercrmck, asb, luismarques.
Herald added subscribers: VincentWu, luke957, StephenFan, vkmr, jdoerfert, 
evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, 
niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, hiraditya, arichardson, 
mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

This implements the Zawrs specification as specified here: 
https://github.com/riscv/riscv-zawrs/releases/download/V1.0-rc3/Zawrs.pdf.  
Despite the 1.0 version name, this does not appear to have been ratified, so 
putting it under experimental for the moment.  I have been told that the 
current version is near final, and unlikely to change (again), but have nothing 
to cite on that.

This change adds assembly support, but does not include C language or IR 
intrinsics.  We can decide if we want them, and handle that in a separate patch.

There were two prior attempts at implementing this.

D128235  by @palmer-dabbelt implements a 
prior version of this extension.  Very annoyingly, the specification appears to 
have changed *without* a change in version number.  This patch also didn't make 
the extension experimental.

D129462  by @sunshaoce implements the current 
version, but was abandoned due to confusion with the prior.  Additionally, it's 
missing a few tests.  I took the .td file change and the valid assembly test 
from that change.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D133443

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/Zawrs-valid.s
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -197,5 +197,8 @@
 .attribute arch, "rv32izca0p70"
 # CHECK: attribute  5, "rv32i2p0_zca0p70"
 
+.attribute arch, "rv32izawrs1p0"
+# CHECK: attribute  5, "rv32i2p0_zawrs1p0"
+
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute  5, "rv32i2p0_ztso0p1"
Index: llvm/test/MC/RISCV/Zawrs-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/Zawrs-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zawrs -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zawrs -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zawrs < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zawrs -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zawrs < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zawrs -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: wrs.nto
+# CHECK-ASM: encoding: [0x73,0x00,0xd0,0x00]
+wrs.nto
+
+# CHECK-ASM-AND-OBJ: wrs.sto
+# CHECK-ASM: encoding: [0x73,0x00,0xd0,0x01]
+wrs.sto
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -84,6 +84,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
@@ -170,6 +171,7 @@
 ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
+; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSub

[PATCH] D133239: [RISCV][MC] Add minimal support for Ztso extension

[Philip Reames via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa4a29438f451: [RISCV][MC] Add minimal support for Ztso 
extension (authored by reames).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133239/new/

https://reviews.llvm.org/D133239

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/elf-flags.s

Index: llvm/test/MC/RISCV/elf-flags.s
===
--- llvm/test/MC/RISCV/elf-flags.s
+++ llvm/test/MC/RISCV/elf-flags.s
@@ -5,6 +5,8 @@
 # RUN: llvm-mc -triple=riscv32 -mattr=+e -filetype=obj < %s \
 # RUN:   | llvm-readobj --file-headers - \
 # RUN:   | FileCheck -check-prefix=CHECK-RVE %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
 
 # CHECK-RVI:   Flags [ (0x0)
 # CHECK-RVI-NEXT:  ]
@@ -17,4 +19,8 @@
 # CHECK-RVE-NEXT: EF_RISCV_RVE (0x8)
 # CHECK-RVE-NEXT:   ]
 
+# CHECK-TSO:Flags [ (0x10)
+# CHECK-NEXT-TSO  EF_RISCV_TSO (0x10)
+# CHECK-NEXT-TSO]
+
 nop
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -196,3 +196,6 @@
 
 .attribute arch, "rv32izca0p70"
 # CHECK: attribute  5, "rv32i2p0_zca0p70"
+
+.attribute arch, "rv32iztso0p1"
+# CHECK: attribute  5, "rv32i2p0_ztso0p1"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -84,6 +84,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -170,6 +171,7 @@
 ; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
 ; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -92,6 +92,7 @@
   bool HasStdExtZicboz = false;
   bool HasStdExtZicbop = false;
   bool HasStdExtZmmul = false;
+  bool HasStdExtZtso = false;
   bool HasRV32 = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
@@ -192,6 +193,7 @@
   bool hasStdExtZicboz() const { return HasStdExtZicboz; }
   bool hasStdExtZicbop() const { return HasStdExtZicbop; }
   bool hasStdExtZmmul() const { return HasStdExtZmmul; }
+  bool hasStdExtZtso() const { return HasStdExtZtso; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -454,6 +454,13 @@
 AssemblerPredicate<(all_of FeatureStdExtZicbop),
 "'Zicbop' (Cache-Block Prefetch Instructions)">;
 
+def FeatureStdExtZtso
+: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
+   "'Ztso' (Memory Model - Total Store Order)">;
+def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
+   AssemblerPredicate<(all_of FeatureStdExtZtso),
+   "'Ztso' (Memory Model - Total Store Order)">;
+
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -157,6 +157,8 @@
 
   if (Features[RISCV::FeatureStdExtC])
 EFlags |= ELF::EF_RISCV_RVC;
+  if 

[PATCH] D132197: [RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/ optional comment.




Comment at: clang/lib/Driver/ToolChains/Linux.cpp:741
  getTriple().getArch() == llvm::Triple::thumbeb;
-  const bool IsRISCV64 = getTriple().getArch() == llvm::Triple::riscv64;
+  const bool IsRISCV64 = getTriple().isRISCV64();
   const bool IsSystemZ = getTriple().getArch() == llvm::Triple::systemz;

I would leave this one unchanged for consistency with surrounding code.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132197/new/

https://reviews.llvm.org/D132197

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: clang/docs/ReleaseNotes.rst:197
+
+- ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for `-mcpu`.
+

Can you given any guidance on what to use instead?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131708/new/

https://reviews.llvm.org/D131708

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:286
+  // StrictFP support for vectors is incomplete.
+  if (ISAInfo->hasExtension("zve32x"))
+HasStrictFP = false;

craig.topper wrote:
> reames wrote:
> > craig.topper wrote:
> > > reames wrote:
> > > > asb wrote:
> > > > > There's also code in RISCVISAInfo.cpp that does `HasVector = 
> > > > > Exts.count("zve32x") != 0`. It's probably worth adding a helper 
> > > > > (`hasVInstructions`?) that encapsulates this, and use it from both 
> > > > > places.
> > > > It's not clear to me why this condition is specific to embedded vector 
> > > > variants.  Do we have strict FP with +V?  Either you need to fix a 
> > > > comment here, or the condition.  One or the other.  
> > > V implies Zve64d implies Zve64f implies Zve32f and Zve64x. Zve32f implies 
> > > Zve32x. Zve32x is the root of the vector inheritance tree.
> > So, I went digging.  I agree that our *implementation* treats V as implying 
> > Zve64d, but I can find anything in the *specification* to that effect.  The 
> > feature set seems like it might be identical between the two, but I don't 
> > see anything in the spec which requires a +V implementation to claim 
> > support for Zve64d.  Do you have particular wording in mind I'm missing?  
> > 
> > (Regardless, the fact we assume this elsewhere means this is a non-blocking 
> > comment for this review.  At the very least, this isn't introducing a new 
> > problem.)
> We removed the implication for a brief period but Krste and Andrew disagreed. 
> I believe this is now covered by the note at the end of 
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#183-v-vector-extension-for-application-processors
> 
> "As is the case with other RISC-V extensions, it is valid to include 
> overlapping extensions in the same ISA string. For example, RV64GCV and 
> RV64GCV_Zve64f are both valid and equivalent ISA strings, as is 
> RV64GCV_Zve64f_Zve32x_Zvl128b."
Er, yuck that's subtle.  Not quite sure I'd read it the way you do, but your 
read is at least easily defensible.  We can wait until someone has a concrete 
case where they aren't implied before figuring out if that case is disallowed 
per the spec.  :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130311/new/

https://reviews.llvm.org/D130311

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D130311#3691146 , @craig.topper 
wrote:

> In D130311#3691029 , @reames wrote:
>
>> I'm not fluent on strict FP, so let me summarize my understanding.  This is 
>> mostly so you can easily correct me if one my assumptions is wrong.
>>
>> - Under strict FP, clang will emit constrained fp intrinsics instead of 
>> normal floating point ops.
>> - To my knowledge, clang will never emit an explicit vector constrained 
>> intrinsic.
>
> operator +, -, *, / etc. on __attribute__((__vector_size__)) types will 
> generate vector constrained intrinsics.

And probably also explicit intrinsic calls now that I'm thinking about it.

However, that doesn't really resolve my user interface concern.  If I have 
purely scalar code, just adding +v to the extension list at the command line 
doesn't change whether strict FP is supported or not.  This change would cause 
us to start reporting warnings which seems less than actionable to the user.  
It really seems like we need to be reporting warnings *when the explicit vector 
constructs are used*.

Worse than the warning bit, having strict FP scalar code stop being strict FP 
if you add +v seems... error prone.

(In case it's not clear, I can probably be convinced this is an imperfect step 
in the right general direction.  I just want to make sure I fully understand 
the implications before giving an LGTM.)




Comment at: clang/lib/Basic/Targets/RISCV.cpp:286
+  // StrictFP support for vectors is incomplete.
+  if (ISAInfo->hasExtension("zve32x"))
+HasStrictFP = false;

craig.topper wrote:
> reames wrote:
> > asb wrote:
> > > There's also code in RISCVISAInfo.cpp that does `HasVector = 
> > > Exts.count("zve32x") != 0`. It's probably worth adding a helper 
> > > (`hasVInstructions`?) that encapsulates this, and use it from both places.
> > It's not clear to me why this condition is specific to embedded vector 
> > variants.  Do we have strict FP with +V?  Either you need to fix a comment 
> > here, or the condition.  One or the other.  
> V implies Zve64d implies Zve64f implies Zve32f and Zve64x. Zve32f implies 
> Zve32x. Zve32x is the root of the vector inheritance tree.
So, I went digging.  I agree that our *implementation* treats V as implying 
Zve64d, but I can find anything in the *specification* to that effect.  The 
feature set seems like it might be identical between the two, but I don't see 
anything in the spec which requires a +V implementation to claim support for 
Zve64d.  Do you have particular wording in mind I'm missing?  

(Regardless, the fact we assume this elsewhere means this is a non-blocking 
comment for this review.  At the very least, this isn't introducing a new 
problem.)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130311/new/

https://reviews.llvm.org/D130311

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

I'm not fluent on strict FP, so let me summarize my understanding.  This is 
mostly so you can easily correct me if one my assumptions is wrong.

- Under strict FP, clang will emit constrained fp intrinsics instead of normal 
floating point ops.
- To my knowledge, clang will never emit an explicit vector constrained 
intrinsic.
- The vectorizers (LV, SLP) don't appear to have any handling for constrained 
FP intrinsics.  If it did, I'd expect it to have to ask about legality of the 
widened operation - the same way it does for e.g. a scatter/gather.

So, my question is: why don't we support StrictFP when targeting a vector 
enabled platform?  Don't we trivially support them by simply never using the 
vector forms?




Comment at: clang/lib/Basic/Targets/RISCV.cpp:286
+  // StrictFP support for vectors is incomplete.
+  if (ISAInfo->hasExtension("zve32x"))
+HasStrictFP = false;

asb wrote:
> There's also code in RISCVISAInfo.cpp that does `HasVector = 
> Exts.count("zve32x") != 0`. It's probably worth adding a helper 
> (`hasVInstructions`?) that encapsulates this, and use it from both places.
It's not clear to me why this condition is specific to embedded vector 
variants.  Do we have strict FP with +V?  Either you need to fix a comment 
here, or the condition.  One or the other.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130311/new/

https://reviews.llvm.org/D130311

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

This was very briefly discussed at today's sync up call.  We were running short 
on time, so we didn't get a chance to talk through it, but there did seem to be 
a consensus that discussion on the interface implications was needed.  This 
should hopefully be on the agenda when we talk again in two weeks.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129824/new/

https://reviews.llvm.org/D129824

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff new_vl output pointer isn't null

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Ok, with the revised description, let me start anew in my response.

I don't have any particular problem with this change.  I do think it would be 
good to explicitly update the docs to indicate whether the param can be null or 
not, but given a) gcc has allowed it, and b) the performance impact should be 
minimal, I would see no concerns with just documenting the current gcc state 
and implementing it in clang.  That seems like the path of least resistance 
here and is a reasonable outcome.

I'm not worried about perf impact from the null check as idiomatic usage is 
likely to involve taking the address of a local variable which will be 
trivially non-null.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126461/new/

https://reviews.llvm.org/D126461

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff new_vl output pointer isn't null

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

@craig.topper Much clearer, thank you.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126461/new/

https://reviews.llvm.org/D126461

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D126461#3597862 , @craig.topper 
wrote:

> `dst` in the patch description is not the pointer being loaded, it's the 
> pointer of where to store the new_vl. That is only thing being checked for 
> null in this patch.

I agree this is a possible interpretation, but it's also inconsistent with some 
of the other review discussion above.

@pcwang-thead Please consider clarifying the patch description a blocking item 
for future review or potential approval.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126461/new/

https://reviews.llvm.org/D126461

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

[Philip Reames via Phabricator via cfe-commits]

reames requested changes to this revision.
reames added a comment.
This revision now requires changes to proceed.

Despite the comments above, the purpose of this patch remains unclear.

Per the draft spec, the relevant wording is:
"These instructions execute as a regular load except that they will only take a 
trap caused by a synchronous exception
on element 0. If element 0 raises an exception, vl is not modied, and the trap 
is taken. If an element > 0 raises an
exception, the corresponding trap is not taken, and the vector length vl is 
reduced to the index of the element that would
have raised an exception."

Working through the scenario in this patch with the destination being null, the 
expected result is for a trap to be generated (provided null is unmapped of 
course), and VL not to be modified.  In order for this change to make any 
difference in runtime behavior, the value passed must be null (or otherwise 
guaranteed to fault).  It seems very odd to me that we are modifying code which 
only runs after an instruction which is guaranteed to fault.  Is there an 
assumed runtime here which is e.g. restarting execution?

Presumably, the actual IR instruction returns the unmodified VL in the faulting 
first access case.  (If it doesn't, that's a bug we should fix.)

The last point, and it's a critical one, is that the outparam for new_vl does 
not have to be null if dest is.  Given that, I think the entire prior 
discussion on motivation here is off base.  Unless you can point to something 
in the intrinsic docs which says *explicitly* that the new_vl param to the 
intrinsic can be null when the dest is known to fault, I think we should 
strongly reject this patch.  Even if you can, I think we should first ask if 
that's a bug in the intrinsic spec.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126461/new/

https://reviews.llvm.org/D126461

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

[Philip Reames via Phabricator via cfe-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125893/new/

https://reviews.llvm.org/D125893

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Coming into this late, but I'd have preferred to see this separated into at 
least two pieces.  One for each "non-obvious" adjustment, and one final one 
which just did the replace on the renaming sites.  This differs from feedback 
from other reviewers above, so don't feel bound by this in any way.  Just 
expressing the general preference.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125557/new/

https://reviews.llvm.org/D125557

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117091: [Clang] Add attributes alloc_size and alloc_align to mm_malloc

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

In D117091#3265986 , @xbolva00 wrote:

> Ping @reames

Not qualified to review clang/c++ library semantic changes.

Also, did we implement allocalign in LLVM?  Last I knew it was a clang only 
attribute.   If we did, it's missing from LangRef.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117091/new/

https://reviews.llvm.org/D117091

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D115003: [funcattrs] Infer writeonly argument attribute [part 2]

[Philip Reames via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0b09313cd533: [funcattrs] Infer writeonly argument attribute 
[part 2] (authored by reames).

Changed prior to commit:
  https://reviews.llvm.org/D115003?vs=397124&id=397319#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115003/new/

https://reviews.llvm.org/D115003

Files:
  clang/test/CodeGen/arm-vfp16-arguments.c
  clang/test/CodeGenCXX/wasm-args-returns.cpp
  clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
  llvm/lib/Transforms/IPO/FunctionAttrs.cpp
  llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
  llvm/test/Other/cgscc-devirt-iteration.ll
  llvm/test/Transforms/FunctionAttrs/norecurse.ll
  llvm/test/Transforms/FunctionAttrs/writeonly.ll

Index: llvm/test/Transforms/FunctionAttrs/writeonly.ll
===
--- llvm/test/Transforms/FunctionAttrs/writeonly.ll
+++ llvm/test/Transforms/FunctionAttrs/writeonly.ll
@@ -78,15 +78,23 @@
 
 declare void @direct2_callee(i8* %p) writeonly
 
+; writeonly w/o nocapture is not enough
 ; CHECK: define void @direct2(i8* %p)
 define void @direct2(i8* %p) {
   call void @direct2_callee(i8* %p)
+  ; read back from global, read through pointer...
   ret void
 }
 
-declare void @direct3_callee(i8* writeonly %p)
+; CHECK: define void @direct2b(i8* nocapture writeonly %p)
+define void @direct2b(i8* %p) {
+  call void @direct2_callee(i8* nocapture %p)
+  ret void
+}
+
+declare void @direct3_callee(i8* nocapture writeonly %p)
 
-; CHECK: define void @direct3(i8* %p)
+; CHECK: define void @direct3(i8* nocapture writeonly %p)
 define void @direct3(i8* %p) {
   call void @direct3_callee(i8* %p)
   ret void
@@ -98,15 +106,15 @@
   ret void
 }
 
-; CHECK: define void @fptr_test2(i8* %p, void (i8*)* nocapture readonly %f)
+; CHECK: define void @fptr_test2(i8* nocapture writeonly %p, void (i8*)* nocapture readonly %f)
 define void @fptr_test2(i8* %p, void (i8*)* %f) {
-  call void %f(i8* writeonly %p)
+  call void %f(i8* nocapture writeonly %p)
   ret void
 }
 
-; CHECK: define void @fptr_test3(i8* %p, void (i8*)* nocapture readonly %f)
+; CHECK: define void @fptr_test3(i8* nocapture writeonly %p, void (i8*)* nocapture readonly %f)
 define void @fptr_test3(i8* %p, void (i8*)* %f) {
-  call void %f(i8* %p) writeonly
+  call void %f(i8* nocapture %p) writeonly
   ret void
 }
 
Index: llvm/test/Transforms/FunctionAttrs/norecurse.ll
===
--- llvm/test/Transforms/FunctionAttrs/norecurse.ll
+++ llvm/test/Transforms/FunctionAttrs/norecurse.ll
@@ -50,7 +50,7 @@
 ; CHECK: Function Attrs
 ; CHECK-SAME: nounwind
 ; CHECK-NOT: norecurse
-; CHECK-NEXT: define void @intrinsic(i8* nocapture %dest, i8* nocapture readonly %src, i32 %len)
+; CHECK-NEXT: define void @intrinsic(i8* nocapture writeonly %dest, i8* nocapture readonly %src, i32 %len)
 define void @intrinsic(i8* %dest, i8* %src, i32 %len) {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 %len, i1 false)
   ret void
Index: llvm/test/Other/cgscc-devirt-iteration.ll
===
--- llvm/test/Other/cgscc-devirt-iteration.ll
+++ llvm/test/Other/cgscc-devirt-iteration.ll
@@ -112,7 +112,7 @@
 ; CHECK-NOT: read
 ; CHECK-SAME: noinline
 ; BEFORE-LABEL: define void @test3(i8* %src, i8* %dest, i64 %size)
-; AFTER-LABEL: define void @test3(i8* nocapture readonly %src, i8* nocapture %dest, i64 %size)
+; AFTER-LABEL: define void @test3(i8* nocapture readonly %src, i8* nocapture writeonly %dest, i64 %size)
   %fptr = alloca i8* (i8*, i8*, i64)*
   store i8* (i8*, i8*, i64)* @memcpy, i8* (i8*, i8*, i64)** %fptr
   %f = load i8* (i8*, i8*, i64)*, i8* (i8*, i8*, i64)** %fptr
Index: llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
===
--- llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
+++ llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
@@ -49,7 +49,7 @@
   ret void
 }
 
-; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture readonly %q, i64 %n) #5 {
+; CHECK: define void @test2_no(i8* nocapture writeonly %p, i8* nocapture readonly %q, i64 %n) #5 {
 define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i1 false), !tbaa !2
   ret void
Index: llvm/lib/Transforms/IPO/FunctionAttrs.cpp
===
--- llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -720,10 +720,16 @@
 
   // The accessors used on call site here do the right thing for calls and
   // invokes with operand bundles.
-  if (!CB.onlyReadsMemory() && !CB.onlyReadsMemory(UseIndex))
-return Attribute::None;
-  if (!CB

[PATCH] D115003: [funcattrs] Infer writeonly argument attribute [part 2]

[Philip Reames via Phabricator via cfe-commits]

reames added inline comments.



Comment at: llvm/lib/Transforms/IPO/FunctionAttrs.cpp:728
+  } else if (CB.hasFnAttr(Attribute::WriteOnly) ||
+ CB.dataOperandHasImpliedAttr(UseIndex, Attribute::WriteOnly)) 
{
+IsWrite = true;

nikic wrote:
> This could be written as `CB.doesNotReadMemory() || 
> CB.doesNotReadMemory(UseIndex)` for symmetry with the other cases. Though 
> personally I find the naming of these methods really unfortunate (they should 
> probably be called `onlyWritesMemory()`) so maybe the explicit form is better.
I'm leaving this as is, but I agree we could use some naming cleanup here.  (I 
may even do it since this is the second time I've hit this.)

Though to highlight "does not read memory" and "WriteOnly" are not quite the 
same.  The former allows readnone which is correct, but surprising here.  
Personally, I hate subtle semantic surprises and am increasing of the view that 
we should check the attributes we mean.  (At least in inference code.)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115003/new/

https://reviews.llvm.org/D115003

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D115003: [funcattrs] Infer writeonly argument attribute [part 2]

[Philip Reames via Phabricator via cfe-commits]

reames updated this revision to Diff 397124.
reames edited the summary of this revision.
reames added a comment.

Rework account for only being to infer on nocapture arguments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115003/new/

https://reviews.llvm.org/D115003

Files:
  llvm/lib/Transforms/IPO/FunctionAttrs.cpp
  llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
  llvm/test/Other/cgscc-devirt-iteration.ll
  llvm/test/Transforms/FunctionAttrs/norecurse.ll
  llvm/test/Transforms/FunctionAttrs/writeonly.ll

Index: llvm/test/Transforms/FunctionAttrs/writeonly.ll
===
--- llvm/test/Transforms/FunctionAttrs/writeonly.ll
+++ llvm/test/Transforms/FunctionAttrs/writeonly.ll
@@ -78,15 +78,23 @@
 
 declare void @direct2_callee(i8* %p) writeonly
 
+; writeonly w/o nocapture is not enough
 ; CHECK: define void @direct2(i8* %p)
 define void @direct2(i8* %p) {
   call void @direct2_callee(i8* %p)
+  ; read back from global, read through pointer...
   ret void
 }
 
-declare void @direct3_callee(i8* writeonly %p)
+; CHECK: define void @direct2b(i8* nocapture writeonly %p)
+define void @direct2b(i8* %p) {
+  call void @direct2_callee(i8* nocapture %p)
+  ret void
+}
+
+declare void @direct3_callee(i8* nocapture writeonly %p)
 
-; CHECK: define void @direct3(i8* %p)
+; CHECK: define void @direct3(i8* nocapture writeonly %p)
 define void @direct3(i8* %p) {
   call void @direct3_callee(i8* %p)
   ret void
@@ -98,15 +106,15 @@
   ret void
 }
 
-; CHECK: define void @fptr_test2(i8* %p, void (i8*)* nocapture readonly %f)
+; CHECK: define void @fptr_test2(i8* nocapture writeonly %p, void (i8*)* nocapture readonly %f)
 define void @fptr_test2(i8* %p, void (i8*)* %f) {
-  call void %f(i8* writeonly %p)
+  call void %f(i8* nocapture writeonly %p)
   ret void
 }
 
-; CHECK: define void @fptr_test3(i8* %p, void (i8*)* nocapture readonly %f)
+; CHECK: define void @fptr_test3(i8* nocapture writeonly %p, void (i8*)* nocapture readonly %f)
 define void @fptr_test3(i8* %p, void (i8*)* %f) {
-  call void %f(i8* %p) writeonly
+  call void %f(i8* nocapture %p) writeonly
   ret void
 }
 
Index: llvm/test/Transforms/FunctionAttrs/norecurse.ll
===
--- llvm/test/Transforms/FunctionAttrs/norecurse.ll
+++ llvm/test/Transforms/FunctionAttrs/norecurse.ll
@@ -50,7 +50,7 @@
 ; CHECK: Function Attrs
 ; CHECK-SAME: nounwind
 ; CHECK-NOT: norecurse
-; CHECK-NEXT: define void @intrinsic(i8* nocapture %dest, i8* nocapture readonly %src, i32 %len)
+; CHECK-NEXT: define void @intrinsic(i8* nocapture writeonly %dest, i8* nocapture readonly %src, i32 %len)
 define void @intrinsic(i8* %dest, i8* %src, i32 %len) {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 %len, i1 false)
   ret void
Index: llvm/test/Other/cgscc-devirt-iteration.ll
===
--- llvm/test/Other/cgscc-devirt-iteration.ll
+++ llvm/test/Other/cgscc-devirt-iteration.ll
@@ -112,7 +112,7 @@
 ; CHECK-NOT: read
 ; CHECK-SAME: noinline
 ; BEFORE-LABEL: define void @test3(i8* %src, i8* %dest, i64 %size)
-; AFTER-LABEL: define void @test3(i8* nocapture readonly %src, i8* nocapture %dest, i64 %size)
+; AFTER-LABEL: define void @test3(i8* nocapture readonly %src, i8* nocapture writeonly %dest, i64 %size)
   %fptr = alloca i8* (i8*, i8*, i64)*
   store i8* (i8*, i8*, i64)* @memcpy, i8* (i8*, i8*, i64)** %fptr
   %f = load i8* (i8*, i8*, i64)*, i8* (i8*, i8*, i64)** %fptr
Index: llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
===
--- llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
+++ llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
@@ -49,7 +49,7 @@
   ret void
 }
 
-; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture readonly %q, i64 %n) #5 {
+; CHECK: define void @test2_no(i8* nocapture writeonly %p, i8* nocapture readonly %q, i64 %n) #5 {
 define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i1 false), !tbaa !2
   ret void
Index: llvm/lib/Transforms/IPO/FunctionAttrs.cpp
===
--- llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -720,10 +720,16 @@
 
   // The accessors used on call site here do the right thing for calls and
   // invokes with operand bundles.
-  if (!CB.onlyReadsMemory() && !CB.onlyReadsMemory(UseIndex))
-return Attribute::None;
-  if (!CB.doesNotAccessMemory(UseIndex))
+  if (CB.doesNotAccessMemory(UseIndex)) {
+/* nop */
+  } else if (CB.onlyReadsMemory() || CB.onlyReadsMemory(UseIndex)) {
 IsRead = true;
+  } else if (CB.hasFnAttr(Attribute::WriteOnly) ||
+ CB.dataOperandHasImpliedAttr(UseIndex, Attribute::WriteOnly)) 

[PATCH] D115021: [funcatts] Rewrite callsite operand handling in memory access inference

[Philip Reames via Phabricator via cfe-commits]

reames abandoned this revision.
reames added a comment.

This has been replaced by a series of smaller patches implementing individual 
parts.

The last of which - parameter attributes on indirect calls - is out for review 
as D116118 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115021/new/

https://reviews.llvm.org/D115021

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D115021: [funcatts] Rewrite callsite operand handling in memory access inference

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

D115961  and D115964 
 were the next two pieces of this, both have 
now landed.

The last bit is honoring call site parameter attributes on indirect calls 
outside the SCC.  I'll post that separately and then close this review because 
everything will have been covered.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115021/new/

https://reviews.llvm.org/D115021

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D115916: [funcattrs] Consistently treat calling a function pointer as a non-capturing read

[Philip Reames via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG33cbaab1416b: [funcattrs] Consistently treat calling a 
function pointer as a non-capturing… (authored by reames).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D115916?vs=395035&id=395148#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115916/new/

https://reviews.llvm.org/D115916

Files:
  clang/test/CodeGen/arm-cmse-attr.c
  llvm/lib/Transforms/IPO/FunctionAttrs.cpp
  llvm/test/Transforms/FunctionAttrs/nocapture.ll
  llvm/test/Transforms/FunctionAttrs/writeonly.ll

Index: llvm/test/Transforms/FunctionAttrs/writeonly.ll
===
--- llvm/test/Transforms/FunctionAttrs/writeonly.ll
+++ llvm/test/Transforms/FunctionAttrs/writeonly.ll
@@ -92,19 +92,19 @@
   ret void
 }
 
-; CHECK: define void @fptr_test1(i8* %p, void (i8*)* nocapture %f)
+; CHECK: define void @fptr_test1(i8* %p, void (i8*)* nocapture readonly %f)
 define void @fptr_test1(i8* %p, void (i8*)* %f) {
   call void %f(i8* %p)
   ret void
 }
 
-; CHECK: define void @fptr_test2(i8* %p, void (i8*)* nocapture %f)
+; CHECK: define void @fptr_test2(i8* %p, void (i8*)* nocapture readonly %f)
 define void @fptr_test2(i8* %p, void (i8*)* %f) {
   call void %f(i8* writeonly %p)
   ret void
 }
 
-; CHECK: define void @fptr_test3(i8* %p, void (i8*)* nocapture %f)
+; CHECK: define void @fptr_test3(i8* %p, void (i8*)* nocapture readonly %f)
 define void @fptr_test3(i8* %p, void (i8*)* %f) {
   call void %f(i8* %p) writeonly
   ret void
Index: llvm/test/Transforms/FunctionAttrs/nocapture.ll
===
--- llvm/test/Transforms/FunctionAttrs/nocapture.ll
+++ llvm/test/Transforms/FunctionAttrs/nocapture.ll
@@ -128,7 +128,7 @@
 }
 
 
-; FNATTR: define void @nc3(void ()* nocapture %p)
+; FNATTR: define void @nc3(void ()* nocapture readonly %p)
 define void @nc3(void ()* %p) {
 	call void %p()
 	ret void
@@ -141,7 +141,7 @@
 	ret void
 }
 
-; FNATTR: define void @nc5(void (i8*)* nocapture %f, i8* nocapture %p)
+; FNATTR: define void @nc5(void (i8*)* nocapture readonly %f, i8* nocapture %p)
 define void @nc5(void (i8*)* %f, i8* %p) {
 	call void %f(i8* %p) readonly nounwind
 	call void %f(i8* nocapture %p)
@@ -319,21 +319,21 @@
 
 declare void @capture(i8*)
 
-; FNATTR: define void @nocapture_fptr(i8* (i8*)* nocapture %f, i8* %p)
+; FNATTR: define void @nocapture_fptr(i8* (i8*)* nocapture readonly %f, i8* %p)
 define void @nocapture_fptr(i8* (i8*)* %f, i8* %p) {
   %res = call i8* %f(i8* %p)
   call void @capture(i8* %res)
   ret void
 }
 
-; FNATTR: define void @recurse_fptr(i8* (i8*)* nocapture %f, i8* %p)
+; FNATTR: define void @recurse_fptr(i8* (i8*)* nocapture readonly %f, i8* %p)
 define void @recurse_fptr(i8* (i8*)* %f, i8* %p) {
   %res = call i8* %f(i8* %p)
   store i8 0, i8* %res
   ret void
 }
 
-; FNATTR: define void @readnone_indirec(void (i8*)* nocapture readnone %f, i8* readnone %p)
+; FNATTR: define void @readnone_indirec(void (i8*)* nocapture readonly %f, i8* readnone %p)
 define void @readnone_indirec(void (i8*)* %f, i8* %p) {
   call void %f(i8* %p) readnone
   ret void
Index: llvm/lib/Transforms/IPO/FunctionAttrs.cpp
===
--- llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -702,6 +702,11 @@
   };
 
   CallBase &CB = cast(*I);
+  if (CB.isCallee(U)) {
+IsRead = true;
+Captures = false; // See comment in CaptureTracking for context
+continue;
+  }
   if (CB.doesNotAccessMemory()) {
 AddUsersToWorklistIfCapturing();
 continue;
Index: clang/test/CodeGen/arm-cmse-attr.c
===
--- clang/test/CodeGen/arm-cmse-attr.c
+++ clang/test/CodeGen/arm-cmse-attr.c
@@ -29,9 +29,9 @@
 {
 }
 
-// CHECK: define{{.*}} void @f1(void ()* nocapture %fptr) {{[^#]*}}#0 {
+// CHECK: define{{.*}} void @f1(void ()* nocapture readonly %fptr) {{[^#]*}}#0 {
 // CHECK: call void %fptr() #2
-// CHECK: define{{.*}} void @f2(void ()* nocapture %fptr) {{[^#]*}}#0 {
+// CHECK: define{{.*}} void @f2(void ()* nocapture readonly %fptr) {{[^#]*}}#0 {
 // CHECK: call void %fptr() #2
 // CHECK: define{{.*}} void @f3() {{[^#]*}}#1 {
 // CHECK: define{{.*}} void @f4() {{[^#]*}}#1 {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits