Re: [edk2-devel] [Patch V2 3/3] UefiCpuPkg: Add Pei/DxeCpuExceptionHandlerLibUnitTest in dsc

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Friday, October 14, 2022 9:54 AM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar, 
> Rahul R 
> Subject: [Patch V2 3/3] UefiCpuPkg: Add Pei/DxeCpuExceptionHandlerLibUnitTest 
> in dsc
> 
> Add Pei/DxeCpuExceptionHandlerLibUnitTest module in UefiCpuPkg.dsc
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> ---
>  UefiCpuPkg/UefiCpuPkg.dsc | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
> index f694b3a77c..31145dbe7e 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dsc
> +++ b/UefiCpuPkg/UefiCpuPkg.dsc
> @@ -63,6 +63,9 @@
>MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
>
> SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
>CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
> +  UnitTestLib|UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.inf
> +  
> UnitTestPersistenceLib|UnitTestFrameworkPkg/Library/UnitTestPersistenceLibNull/UnitTestPersistenceLibNull.inf
> +  
> UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibDebugLib.inf
> 
>  [LibraryClasses.common.SEC]
>PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf
> @@ -177,6 +180,10 @@
>UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
>UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
>UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
> +  
> UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerLibUnitTest.inf
> +
> +[Components.X64]
> +  
> UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerLibUnitTest.inf
> 
>  [BuildOptions]
>*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V2 2/3] UefiCpuPkg: Add Unit tests for PeiCpuExceptionHandlerLib

[Ni, Ray]

The commit message is the same as the last patch, right?

Maybe you could say:

The previous change adds unit test for DxeCpuExeptionHandlerLib in 64bit mode.
This change adds unit test for PeiCpuExceptionHandlerLib based on previous 
change.
It can run in both 32bit and 64bit modes.

> +extern GENERAL_REGISTER_IA32  mIa32ExpectedContextInHandler;
> +extern GENERAL_REGISTER_IA32  mIa32ActualContextAfterException;
Can you use the same variable name for IA32?
The variable name is the same but the structure definitions are different.


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Re: [edk2-devel] [Patch V2 1/3] UefiCpuPkg: Add Unit tests for DxeCpuExceptionHandlerLib

[Ni, Ray]

the patch looks good!
5 minor comments in below.

> since [StackBase, StackBase + SIZE_4KB] is guarded in page
1. can you say specifically "... is marked as not present in page table" 
instead of "guarded"?

> +#pragma pack (1)
> +
> +typedef union {
> +  struct {
> +UINT32LimitLow: 16;
> +UINT32BaseLow : 16;
> +UINT32BaseMid : 8;
> +UINT32Type: 4;
> +UINT32System  : 1;
> +UINT32Dpl : 2;
> +UINT32Present : 1;
> +UINT32LimitHigh   : 4;
> +UINT32Software: 1;
> +UINT32Reserved: 1;
> +UINT32DefaultSize : 1;
> +UINT32Granularity : 1;
> +UINT32BaseHigh: 8;
> +  } Bits;
> +  UINT64Uint64;
> +} IA32_GDT;

2. can you reuse IA32_SEGMENT_DESCRIPTOR definition from BaseLib.h?

> +
> +typedef struct {
> +  UINT32InitialApicId;
> +  UINT32ApicId;
> +  UINT32Health;
> +  UINT64ApTopOfStack;
> +} CPU_INFO_IN_HOB;

3. This is an internal data structure used by MpInitLib. Do you still need it?

> +typedef struct {
> +  UINT64Rdi;
> +  UINT64Rsi;
> +  UINT64Rbx;
> +  UINT64Rdx;
> +  UINT64Rcx;
> +  UINT64Rax;
> +  UINT64R8Register;
> +  UINT64R9Register;
> +  UINT64R10Register;
> +  UINT64R11Register;
> +  UINT64R12Register;
> +  UINT64R13Register;
> +  UINT64R14Register;
> +  UINT64R15Register;

4. Can we just use "R8/R9" as the register name? If needed, you can change the 
ECC exception file to fix the ECC failure.



> +
> +  Cr0.UintN = AsmReadCr0 ();
> +  if (Cr0.Bits.PG == 0) {
> +return;
5. FoundPFAddress is not set to FALSE when returning.
How about let the function return a Boolean flag so the caller code can be 
as below?
if (FindPFAddressInPageTable ()) {
   ...
}



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[edk2-devel] [edk2-platforms][PATCH V3 15/16] Platform/Loongson: Add QemuFlashFvbServicesRuntimeDxe driver.

[xianglai]

This library provides flash read and write functionality
and supports writing variables to flash.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../QemuFlashFvbServicesRuntimeDxe/FvbInfo.c  |  115 ++
 .../FvbServicesRuntimeDxe.inf |   73 ++
 .../FwBlockService.c  | 1158 +
 .../FwBlockService.h  |  178 +++
 .../FwBlockServiceDxe.c   |  152 +++
 .../QemuFlash.c   |  251 
 .../QemuFlash.h   |   86 ++
 .../QemuFlashDxe.c|   21 +
 .../Loongson/LoongArchQemuPkg/Loongson.dsc|4 +-
 9 files changed, 2036 insertions(+), 2 deletions(-)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FwBlockService.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FwBlockService.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
new file mode 100644
index 00..df772f72be
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
@@ -0,0 +1,115 @@
+/** @file
+  Defines data structure that is the volume header found.These data is intent
+  to decouple FVB driver with FV header.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The protocols, PPI and GUID definitions for this module
+//
+#include 
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+
+typedef struct {
+  UINT64FvLength;
+  EFI_FIRMWARE_VOLUME_HEADERFvbInfo;
+  //
+  // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+  //
+  EFI_FV_BLOCK_MAP_ENTRYEnd[1];
+} EFI_FVB_MEDIA_INFO;
+
+EFI_FVB_MEDIA_INFO  mPlatformFvbMediaInfo[] = {
+  //
+  // System NvStorage FVB
+  //
+  {
+FixedPcdGet32 (PcdAllVarSize),
+{
+  {
+0,
+  },  // ZeroVector[16]
+  EFI_SYSTEM_NV_DATA_FV_GUID,
+  FixedPcdGet32 (PcdAllVarSize),
+  EFI_FVH_SIGNATURE,
+  EFI_FVB2_MEMORY_MAPPED |
+  EFI_FVB2_READ_ENABLED_CAP |
+  EFI_FVB2_READ_STATUS |
+  EFI_FVB2_WRITE_ENABLED_CAP |
+  EFI_FVB2_WRITE_STATUS |
+  EFI_FVB2_ERASE_POLARITY |
+  EFI_FVB2_ALIGNMENT_16,
+  sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+  0,  // CheckSum
+  0,  // ExtHeaderOffset
+  {
+0,
+  },  // Reserved[1]
+  2,  // Revision
+  {
+{
+  (FixedPcdGet32 (PcdAllVarSize))/
+  FixedPcdGet32 (PcdFlashBlockSize),
+  FixedPcdGet32 (PcdFlashBlockSize),
+}
+  } // BlockMap[1]
+},
+{
+  {
+0,
+0
+  }
+}  // End[1]
+  }
+};
+
+EFI_STATUS
+GetFvbInfo (
+  IN  UINT64  FvLength,
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **FvbInfo
+  )
+{
+  STATIC BOOLEAN  Checksummed = FALSE;
+  UINTN   Index;
+
+  if (!Checksummed) {
+for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1)
+{
+  UINT16  Checksum;
+  mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = 0;
+  Checksum  = CalculateCheckSum16 (
+(UINT16 
*)[Index].FvbInfo,
+
mPlatformFvbMediaInfo[Index].FvbInfo.HeaderLength
+);
+  mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = Checksum;
+}
+Checksummed = TRUE;
+  }
+
+  for (Index = 0;
+   Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+   Index += 1)
+  {
+if (mPlatformFvbMediaInfo[Index].FvLength == FvLength) {
+  *FvbInfo = [Index].FvbInfo;
+  return EFI_SUCCESS;
+}
+  }
+
+  return EFI_NOT_FOUND;
+}
diff --git 

[edk2-devel] [edk2-platforms][PATCH V3 14/16] Platform/Loongson: Support Dxe

[xianglai]

Support Dxe for LoogArch.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Loongson/LoongArchQemuPkg/Loongson.dec|  14 +-
 .../Loongson/LoongArchQemuPkg/Loongson.dsc| 420 +-
 .../Loongson/LoongArchQemuPkg/Loongson.fdf| 243 ++
 .../LoongArchQemuPkg/Loongson.fdf.inc |  42 ++
 .../LoongArchQemuPkg/VarStore.fdf.inc |  64 +++
 5 files changed, 778 insertions(+), 5 deletions(-)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/VarStore.fdf.inc

diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
index 6a423f3ed6..5065f99042 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -18,7 +18,8 @@
 #   Comments are used for Keywords and Module Types.
 #
 # Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER
+#  DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
 #
 

 [Includes.common]
@@ -26,12 +27,20 @@
 
 [Guids]
   gLoongArchQemuPkgTokenSpaceGuid  = { 0x0e0383ce, 0x0151, 0x4d01, { 0x80, 
0x0e, 0x3f, 0xef, 0x8b, 0x27, 0x6d, 0x52 } }
+  gEfiLoongsonBootparamsTableGuid  = { 0x4660f721, 0x2ec5, 0x416a, { 0x89, 
0x9a, 0x43, 0x18, 0x02, 0x50, 0xa0, 0xc9 } }
+
+[Protocols]
 
 [PcdsFixedAtBuild, PcdsDynamic]
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvOffset|0x0|UINT64|0x0007
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|0x0|UINT64|0x0008
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvSize|0x0|UINT32|0x0009
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecModuleBase|0x0|UINT64|0x000a
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecModuleSize|0x0|UINT32|0x000b
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashEventLogBase|0x0|UINT64|0x000c
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashEventLogSize|0x0|UINT32|0x000d
   gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreeBase|0x0|UINT64|0x0018
   gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreePadding|256|UINT32|0x0019
 
@@ -45,6 +54,8 @@
 [PcdsFixedAtBuild.LOONGARCH64]
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32|UINT8|0x0010
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0|UINT8|0x0011
+   
gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceSpaceStartAddress|0x1000|UINT32|0x0012
+   
gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceSpaceLength|0x8000|UINT32|0x0013
 
 [PcdsDynamic]
   gLoongArchQemuPkgTokenSpaceGuid.PcdRamSize|0x4000|UINT64|0x0041
@@ -56,3 +67,4 @@
   gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPmd|0x0|UINT64|0x0047
   gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPte|0x0|UINT64|0x0048
 
+[PcdsFeatureFlag]
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
index 1ca8cc09f7..74c83720b7 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -24,6 +24,25 @@
   FLASH_DEFINITION   = 
Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
   TTY_TERMINAL   = FALSE
 
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  DEFINE TTY_TERMINAL= FALSE
+  DEFINE SECURE_BOOT_ENABLE  = FALSE
+  DEFINE TPM2_ENABLE = FALSE
+  DEFINE TPM2_CONFIG_ENABLE  = FALSE
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_IP6_ENABLE  = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE= FALSE
+  DEFINE NETWORK_SNP_ENABLE  = FALSE
+  DEFINE NETWORK_TLS_ENABLE  = FALSE
+  DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS  = TRUE
+  DEFINE NETWORK_ISCSI_ENABLE= FALSE
+
+!include NetworkPkg/NetworkDefines.dsc.inc
 
 #
 # Defines for default states.  These can be changed on the command line.
@@ -37,16 +56,25 @@
   #
   GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
 
+!include NetworkPkg/NetworkBuildOptions.dsc.inc
 
 [BuildOptions.LOONGARCH64.EDKII.SEC]
   *_*_*_CC_FLAGS =
 
-#[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
-#  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   

[edk2-devel] [edk2-platforms][PATCH V3 16/16] Platform/Loongson: Support for saving variables to flash.

[xianglai]

Added the function of saving non-volatile variables.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 Platform/Loongson/LoongArchQemuPkg/Loongson.dec|  6 ++
 Platform/Loongson/LoongArchQemuPkg/Loongson.dsc|  2 +-
 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf| 14 ++
 .../Loongson/LoongArchQemuPkg/Loongson.fdf.inc | 11 +++
 .../Loongson/LoongArchQemuPkg/VarStore.fdf.inc | 10 +-
 5 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
index 5065f99042..2fd80e7ea2 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -32,6 +32,8 @@
 [Protocols]
 
 [PcdsFixedAtBuild, PcdsDynamic]
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashFdBase|0x0|UINT64|0
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashBlockSize|0x0|UINT32|2
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvOffset|0x0|UINT64|0x0007
@@ -48,6 +50,10 @@
   gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d
   gLoongArchQemuPkgTokenSpaceGuid.PcdUefiRamTop|0x0|UINT64|0x001e
   gLoongArchQemuPkgTokenSpaceGuid.PcdRamRegionsBottom|0x0|UINT64|0x0022
+  
gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT64|0x0024
+  gLoongArchQemuPkgTokenSpaceGuid.PcdAllVarSize|0x0|UINT32|0x0025
+  
gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT64|0x0026
+  
gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT64|0x0027
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029
 
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
index 59beafb34f..46b326f0a5 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -444,7 +444,7 @@
   #
   # Variable
   #
-#  
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+  
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
   OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.inf {
 
   PlatformFvbLib|OvmfPkg/Library/EmuVariableFvbLib/EmuVariableFvbLib.inf
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
index ba2942e455..12920a0833 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
@@ -31,6 +31,19 @@ 
gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|gLoongArchQemuPkgTokenSpaceGui
 FV = FVMAIN_COMPACT
 
 !include VarStore.fdf.inc
+
+#
+[FD.QEMU_EFI_VARS]
+BaseAddress   = $(VARIABLE_BASE_ADDRESS)
+Size  = $(VAR_ALL_SIZE)
+ErasePolarity = 1
+BlockSize = $(BLOCK_SIZE)
+NumBlocks = $(VAR_ALL_BLOCKS)
+
+DEFINE VARIABLE_OFFSET = 0
+!include VarStore.fdf.inc
+DEFINE VARIABLE_OFFSET = 0x003a
+
 
#
 [FV.SECFV]
 FvNameGuid = 587d4265-5e71-41da-9c35-4258551f1e22
@@ -87,6 +100,7 @@ INF  MdeModulePkg/Core/Pei/PeiMain.inf
 INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
 INF  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 INF  Platform/Loongson/LoongArchQemuPkg/PlatformPei/PlatformPei.inf
+
 
#
 [FV.DXEFV]
 FvNameGuid = 5d19a5b3-130f-459b-a292-9270a9e6bc62
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
index 964d69ed44..4b926a85ff 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
@@ -34,6 +34,7 @@ DEFINE VAR_ALL_SIZE   = 0x6
 
 
 #Set Var Flash layout
+DEFINE VARIABLE_BASE_ADDRESS  = 0x1c3a
 DEFINE VARIABLE_SIZE  = 0x0001
 DEFINE VAR_ALL_BLOCKS = 0x60
 
@@ -53,11 +54,21 @@ DEFINE EVENT_LOG_OFFSET   = $(FWTWORKING_OFFSET) + 
$(FWTWORKING_SIZE)
 DEFINE EVENT_LOG_SIZE = 0x8000
 
 # Set Variable
+SET gLoongArchQemuPkgTokenSpaceGuid.PcdFlashFdBase = $(FD_BASE_ADDRESS)
+
+SET gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase = 
$(FD_BASE_ADDRESS) + $(VARIABLE_OFFSET)
+SET gLoongArchQemuPkgTokenSpaceGuid.PcdAllVarSize = $(VAR_ALL_SIZE)
+
+SET 

[edk2-devel] [edk2-platforms][PATCH V3 13/16] Platform/Loongson: Add Reset System Lib.

[xianglai]

This library provides interfaces related to restart and shutdown.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../BaseResetSystemAcpiGed.c  | 155 ++
 .../BaseResetSystemAcpiGedLib.inf |  42 +++
 .../DxeResetSystemAcpiGed.c   | 270 ++
 .../DxeResetSystemAcpiGedLib.inf  |  47 +++
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.c   | 128 +
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.h   |  20 ++
 6 files changed, 662 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGedLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGed.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGedLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.h

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
new file mode 100644
index 00..a50672410b
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
@@ -0,0 +1,155 @@
+/** @file
+  Base ResetSystem library implementation.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include "ResetSystemAcpiGed.h"
+#include 
+
+/**
+  Get configuration item data by the firmware configuration file name.
+
+  @param[in]  Name - Name of file to look up.
+
+  @returnVOID*   The Pointer of Value of Firmware Configuration item 
read.
+
+**/
+VOID *
+GetFwCfgData(
+CONST CHAR8   *Name
+)
+{
+  FIRMWARE_CONFIG_ITEM FwCfgItem;
+  EFI_STATUS   Status;
+  UINTNFwCfgSize;
+  VOID *Data;
+
+  Status = QemuFwCfgFindFile (Name, , );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read  %s error Status %d \n", __func__, 
__LINE__, Name, Status));
+return NULL;
+  }
+
+  Data = AllocatePool (FwCfgSize);
+  if (Data == NULL) {
+return NULL;
+  }
+
+  QemuFwCfgSelectItem (FwCfgItem);
+  QemuFwCfgReadBytes (FwCfgSize, Data);
+
+  return Data;
+}
+
+/**
+  Find the power manager related info from ACPI table
+
+
+  @retval RETURN_SUCCESS Successfully find out all the required 
information.
+  @retval RETURN_NOT_FOUND   Failed to find the required info.
+
+**/
+STATIC EFI_STATUS
+GetPowerManagerByParseAcpiInfo (VOID)
+{
+  EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE*Fadt = NULL;
+  EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER  *Xsdt = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER  *Rsdt = NULL;
+  VOID *AcpiTables = NULL;
+  UINT32   *Entry32 = NULL;
+  UINTN Entry32Num;
+  UINT32   *Signature = NULL;
+  UINTN Idx;
+
+  Rsdp = GetFwCfgData ("etc/acpi/rsdp");
+  if (Rsdp == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/rsdp error \n", __func__, 
__LINE__));
+return RETURN_NOT_FOUND;
+  }
+
+  AcpiTables = GetFwCfgData ("etc/acpi/tables");
+  if (AcpiTables == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/tables error \n", __func__, 
__LINE__));
+FreePool (Rsdp);
+return RETURN_NOT_FOUND;
+  }
+
+  Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->RsdtAddress);
+  Entry32= (UINT32 *)(Rsdt + 1);
+  Entry32Num = (Rsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+  Fadt = (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+  DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
+  goto Done;
+}
+  }
+
+
+  Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->XsdtAddress);
+  Entry32= (UINT32 *)(Xsdt + 1);
+  Entry32Num = (Xsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+  Fadt = (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+  DEBUG ((DEBUG_INFO, "Found Fadt in Xsdt\n"));
+  goto Done;

[edk2-devel] [edk2-platforms][PATCH V3 11/16] Platform/Loongson: Add RealTime Clock lib.

[xianglai]

This library provides interfaces such as
real-time clock initialization
to get time and setting time.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LsRealTimeClockLib/LsRealTimeClock.h  |  41 +++
 .../LsRealTimeClockLib/LsRealTimeClockLib.c   | 343 ++
 .../LsRealTimeClockLib/LsRealTimeClockLib.inf |  41 +++
 3 files changed, 425 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
new file mode 100644
index 00..c98881e5d0
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
@@ -0,0 +1,41 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef LS_REAL_TIME_CLOCK_H_
+#define LS_REAL_TIME_CLOCK_H_
+
+#define TOY_WRITE0_REG0x24
+#define TOY_WRITE1_REG0x28
+#define TOY_READ0_REG 0x2c
+#define TOY_READ1_REG 0x30
+#define RTC_CTRL_REG  0x40
+
+/* TOY Enable bits */
+#define RTC_ENABLE_BIT(1UL << 13)
+#define TOY_ENABLE_BIT(1UL << 11)
+#define OSC_ENABLE_BIT(1UL << 8)
+
+/*
+ * shift bits and filed mask
+ */
+#define TOY_MON_MASK  0x3f
+#define TOY_DAY_MASK  0x1f
+#define TOY_HOUR_MASK 0x1f
+#define TOY_MIN_MASK  0x3f
+#define TOY_SEC_MASK  0x3f
+#define TOY_MSEC_MASK 0xf
+
+#define TOY_MON_SHIFT 26
+#define TOY_DAY_SHIFT 21
+#define TOY_HOUR_SHIFT16
+#define TOY_MIN_SHIFT 10
+#define TOY_SEC_SHIFT 4
+
+#endif //__LS_REAL_TIME_CLOCK_H__
diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
new file mode 100644
index 00..78420ddfab
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
@@ -0,0 +1,343 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "LsRealTimeClock.h"
+
+STATIC BOOLEANmInitialized = FALSE;
+STATIC EFI_EVENT  mRtcVirtualAddrChangeEvent;
+STATIC UINTN  mRtcBase = 0X100d0100;
+/*
+  Enable Real-time clock.
+
+  @param VOID
+
+  @retval  VOID
+ */
+VOID
+InitRtc (
+  VOID
+  )
+{
+ UINTN  Val;
+
+  if (!mInitialized) {
+/* enable rtc */
+Val  = MmioRead32 (mRtcBase + RTC_CTRL_REG);
+Val |= TOY_ENABLE_BIT | OSC_ENABLE_BIT;
+MmioWrite32 (mRtcBase + RTC_CTRL_REG, Val);
+mInitialized = TRUE;
+  }
+}
+
+/**
+  Returns the current time and date information, and the time-keeping 
capabilities
+  of the hardware platform.
+
+  @param  Time   A pointer to storage to receive a snapshot of 
the current time.
+  @param  Capabilities   An optional pointer to a buffer to receive 
the real time clock
+ device's capabilities.
+
+  @retval EFI_SUCCESSThe operation completed successfully.
+  @retval EFI_INVALID_PARAMETER  Time is NULL.
+  @retval EFI_DEVICE_ERROR   The time could not be retrieved due to 
hardware error.
+  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an 
authentication failure.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME*Time,
+  OUT EFI_TIME_CAPABILITIES   *Capabilities
+  )
+{
+  UINT32  Val;
+
+  // Ensure Time is a valid pointer
+  if (Time == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  InitRtc ();
+  Val = MmioRead32 (mRtcBase + TOY_READ1_REG);
+  Time->Year = Val + 1900;
+
+  Val = MmioRead32 (mRtcBase + TOY_READ0_REG);
+  Time->Month =  (Val >> TOY_MON_SHIFT) & TOY_MON_MASK;
+  Time->Day   =  (Val >> TOY_DAY_SHIFT) & TOY_DAY_MASK;
+  Time->Hour  =  (Val >> TOY_HOUR_SHIFT) & TOY_HOUR_MASK;
+  Time->Minute = (Val >> TOY_MIN_SHIFT) & TOY_MIN_MASK;
+  Time->Second = (Val >> TOY_SEC_SHIFT) & TOY_SEC_MASK;
+  Time->Nanosecond  = 0;
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time  A pointer to the current time.
+
+  @retval EFI_SUCCESS   The 

[edk2-devel] [edk2-platforms][PATCH V3 10/16] Platform/Loongson: Add timer Dxe driver.

[xianglai]

This driver produces Timer Architectural Protocol,
Registers a timer interrupt and initializes the timer.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Drivers/StableTimerDxe/Timer.c| 405 ++
 .../Drivers/StableTimerDxe/Timer.h| 165 +++
 .../Drivers/StableTimerDxe/TimerDxe.inf   |  40 ++
 3 files changed, 610 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/TimerDxe.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
new file mode 100644
index 00..68742551ec
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
@@ -0,0 +1,405 @@
+/** @file
+  Timer Architectural Protocol as defined in the DXE CIS
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include "Library/Cpu.h"
+#include 
+#include 
+#include "Timer.h"
+#include 
+#include 
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLEmTimerHandle = NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL   mTimer = {
+  TimerDriverRegisterHandler,
+  TimerDriverSetTimerPeriod,
+  TimerDriverGetTimerPeriod,
+  TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+volatile UINT64   mTimerPeriod = 0;
+volatile UINT64   mTimerTicks = 0;
+
+//
+// Const frequence in Hz
+//
+extern UINT32 StableTimerFreq;
+
+/**
+  Sets the counter value for timer.
+
+  @param CountThe 16-bit counter value to program into stable timer.
+
+  @retval VOID
+**/
+VOID
+SetPitCount (
+  IN UINT64  Count
+  )
+{
+  if (Count <= 4) {
+return;
+  }
+
+  Count &= LOONGARCH_CSR_TMCFG_TIMEVAL;
+  Count |= LOONGARCH_CSR_TMCFG_EN | LOONGARCH_CSR_TMCFG_PERIOD;
+  LOONGARCH_CSR_WRITEQ (Count, LOONGARCH_CSR_TMCFG);
+}
+
+/**
+  Timer Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occurred
+  @param SystemContextA pointer to the system context when the interrupt 
occurred
+
+  @retval VOID
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+  IN EFI_EXCEPTION_TYPE   InterruptType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  EFI_TPL OriginalTPL;
+
+  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+  //
+  // Clear interrupt.
+  //
+  LOONGARCH_CSR_WRITEQ (0x1, LOONGARCH_CSR_TINTCLR);
+
+  if (mTimerNotifyFunction != NULL) {
+//
+// @bug : This does not handle missed timer interrupts
+//
+mTimerNotifyFunction (mTimerPeriod);
+  }
+
+  gBS->RestoreTPL (OriginalTPL);
+}
+
+/**
+
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a 
handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+  is returned.
+
+
+  @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param NotifyFunction   The function to call when a timer interrupt fires.  
This
+  function executes at TPL_HIGH_LEVEL.  The DXE Core 
will
+  register a handler for the timer interrupt, so it 
can know
+  how much time has passed.  This information is used 
to
+  signal timer based events.  NULL will unregister the 
handler.
+
+  @retvalEFI_SUCCESSThe timer handler was registered.
+  @retvalEFI_UNSUPPORTEDThe platform does not support timer 
interrupts.
+  @retvalEFI_ALREADY_STARTEDNotifyFunction is not NULL, and a 
handler is already
+registered.
+  @retval  

[edk2-devel] [edk2-platforms][PATCH V3 12/16] Platform/Loongson: Add Platform Boot Manager Lib.

[xianglai]

The Library provides Boot Manager interfaces.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../PlatformBootManagerLib/PlatformBm.c   | 760 ++
 .../PlatformBootManagerLib/PlatformBm.h   | 112 +++
 .../PlatformBootManagerLib.inf|  78 ++
 .../PlatformBootManagerLib/QemuKernel.c   |  81 ++
 4 files changed, 1031 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/QemuKernel.c

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
new file mode 100644
index 00..f58c43fa89
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -0,0 +1,760 @@
+/** @file
+  Implementation for PlatformBootManagerLib library class interfaces.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "PlatformBm.h"
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+//
+// VENDOR_DEVICE_PATH SerialDxe
+//
+{
+{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) 
},
+SERIAL_DXE_FILE_GUID
+},
+
+//
+// UART_DEVICE_PATH Uart
+//
+{
+{ MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+0,  // Reserved
+FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+FixedPcdGet8 (PcdUartDefaultDataBits),  // DataBits
+FixedPcdGet8 (PcdUartDefaultParity),// Parity
+FixedPcdGet8 (PcdUartDefaultStopBits)   // StopBits
+  },
+
+  //
+  // VENDOR_DEFINED_DEVICE_PATH TermType
+  //
+  {
+{
+  MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+  DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+}
+//
+// Guid to be filled in dynamically
+//
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+  //
+  // USB_CLASS_DEVICE_PATH Keyboard
+  //
+  {
+{
+  MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,
+  DP_NODE_LEN (USB_CLASS_DEVICE_PATH)
+},
+0x, // VendorId: any
+0x, // ProductId: any
+3,  // DeviceClass: HID
+1,  // DeviceSubClass: boot
+1   // DeviceProtocol: keyboard
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+/**
+  Locate all handles that carry the specified protocol, filter them with a
+  callback function, and pass each handle that passes the filter to another
+  callback.
+
+  @param[in] ProtocolGuid  The protocol to look for.
+
+  @param[in] FilterThe filter function to pass each handle to. If this
+   parameter is NULL, then all handles are processed.
+
+  @param[in] Process   The callback function to pass each handle to that
+   clears the filter.
+**/
+VOID
+FilterAndProcess (
+  IN EFI_GUID  *ProtocolGuid,
+  IN FILTER_FUNCTION   Filter OPTIONAL,
+  IN CALLBACK_FUNCTION Process
+  )
+{
+  EFI_STATUS Status;
+  EFI_HANDLE *Handles;
+  UINTN  NoHandles;
+  UINTN  Idx;
+
+  Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
+  NULL /* SearchKey */, , );
+  if (EFI_ERROR (Status)) {
+//
+// This is not an error, just an informative condition.
+//
+DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
+  Status));
+return;
+  }
+
+  ASSERT (NoHandles > 0);
+  for (Idx = 0; Idx < NoHandles; ++Idx) {
+CHAR16*DevicePathText;
+STATIC CHAR16 Fallback[] = L"";
+
+//
+// The ConvertDevicePathToText () function handles NULL input 
transparently.
+//
+DevicePathText = ConvertDevicePathToText (
+   DevicePathFromHandle (Handles[Idx]),
+   FALSE, // DisplayOnly
+   FALSE  // AllowShortcuts
+   );
+if (DevicePathText == NULL) {
+  DevicePathText = Fallback;
+}
+
+if ((Filter == NULL)
+  || (Filter (Handles[Idx], DevicePathText)))
+{
+  Process (Handles[Idx], DevicePathText);
+}
+
+if (DevicePathText != 

[edk2-devel] [edk2-platforms][PATCH V3 09/16] Platform/Loongson: Add PciCpuIoDxe driver.

[xianglai]

Add PCI CpuIo protocol.there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c   | 548 ++
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h   | 219 +++
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf |  40 ++
 3 files changed, 807 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 00..f5154eea7a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,548 @@
+/** @file
+  Produces the CPU I/O 2 Protocol.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "PciCpuIo2Dxe.h"
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE  mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  0, // EfiCpuIoWidthFifoUint8
+  0, // EfiCpuIoWidthFifoUint16
+  0, // EfiCpuIoWidthFifoUint32
+  0, // EfiCpuIoWidthFifoUint64
+  1, // EfiCpuIoWidthFillUint8
+  2, // EfiCpuIoWidthFillUint16
+  4, // EfiCpuIoWidthFillUint32
+  8  // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  1, // EfiCpuIoWidthFifoUint8
+  2, // EfiCpuIoWidthFifoUint16
+  4, // EfiCpuIoWidthFifoUint32
+  8, // EfiCpuIoWidthFifoUint64
+  0, // EfiCpuIoWidthFillUint8
+  0, // EfiCpuIoWidthFillUint16
+  0, // EfiCpuIoWidthFillUint32
+  0  // EfiCpuIoWidthFillUint64
+};
+
+/**
+  Check parameters to a CPU I/O 2 Protocol service request.
+
+  The I/O operations are carried out exactly as requested. The caller is 
responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port 
operation.
+  @param[in] Width  Signifies the width of the I/O or Memory operation.
+  @param[in] AddressThe base address of the I/O operation.
+  @param[in] Count  The number of I/O operations to perform. The 
number of
+bytes moved is Width size * Count, starting at 
Address.
+  @param[in] Buffer For read operations, the destination buffer to 
store the results.
+For write operations, the source buffer from which 
to write data.
+
+  @retval EFI_SUCCESSThe parameters for this request pass the 
checks.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+CpuIoCheckParameter (
+  IN BOOLEANMmioOperation,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64 Address,
+  IN UINTN  Count,
+  IN VOID   *Buffer
+  )
+{
+  UINT64  MaxCount;
+  UINT64  Limit;
+
+  //
+  // Check to see if Buffer is NULL
+  //
+  if (Buffer == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Width is in the valid range
+  //
+  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // For FIFO type, the target address won't increase during the access,
+  // so treat Count as 1
+  //
+  if ((Width >= EfiCpuIoWidthFifoUint8)
+&& (Width <= EfiCpuIoWidthFifoUint64))
+  {
+Count = 1;
+  }
+
+  //
+  // Check to see if Width is in the valid range for I/O Port operations
+  //
+  Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  if ((!MmioOperation)
+&& (Width == EfiCpuIoWidthUint64))
+  {
+return EFI_INVALID_PARAMETER;
+  }
+
+  

[edk2-devel] [edk2-platforms][PATCH V3 08/16] Platform/Loongson: Add CPU DXE driver.

[xianglai]

The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c  | 382 ++
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h  | 151 +++
 .../Drivers/CpuDxe/CpuDxe.inf |  56 +++
 .../Drivers/CpuDxe/LoongArch64/Exception.c| 338 
 .../Drivers/CpuDxe/LoongArch64/Fpu.S  |  67 +++
 .../Drivers/CpuDxe/LoongArch64/LoongArch.S| 292 +
 6 files changed, 1286 insertions(+)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Exception.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Fpu.S
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/LoongArch.S

diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
new file mode 100644
index 00..bff2bd0c0a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
@@ -0,0 +1,382 @@
+/** @file
+  CPU DXE Module to produce CPU ARCH Protocol
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "CpuDxe.h"
+
+BOOLEAN mInterruptState   = FALSE;
+
+/*
+  This function flushes the range of addresses from Start to Start+Length
+  from the processor's data cache. If Start is not aligned to a cache line
+  boundary, then the bytes before Start to the preceding cache line boundary
+  are also flushed. If Start+Length is not aligned to a cache line boundary,
+  then the bytes past Start+Length to the end of the next cache line boundary
+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+  supported. If the data cache is fully coherent with all DMA operations, then
+  this function can just return EFI_SUCCESS. If the processor does not support
+  flushing a range of the data cache, then the entire data cache can be 
flushed.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+  @param  StartThe beginning physical address to flush from the 
processor's data
+   cache.
+  @param  Length   The number of bytes to flush from the processor's 
data cache. This
+   function may flush more bytes than Length specifies 
depending upon
+   the granularity of the flush operation that the 
processor supports.
+  @param  FlushTypeSpecifies the type of flush operation to perform.
+
+  @retval EFI_SUCCESS   The address range from Start to Start+Length 
was flushed from
+the processor's data cache.
+  @retval EFI_UNSUPPORTEDT  The processor does not support the cache flush 
type specified
+by FlushType.
+  @retval EFI_DEVICE_ERROR  The address range from Start to Start+Length 
could not be flushed
+from the processor's data cache.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+  IN EFI_CPU_ARCH_PROTOCOL   *This,
+  IN EFI_PHYSICAL_ADDRESSStart,
+  IN UINT64  Length,
+  IN EFI_CPU_FLUSH_TYPE  FlushType
+  )
+{
+
+  switch (FlushType) {
+case EfiCpuFlushTypeWriteBack:
+  WriteBackDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+  break;
+case EfiCpuFlushTypeInvalidate:
+  InvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+  break;
+case EfiCpuFlushTypeWriteBackInvalidate:
+  WriteBackInvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+  break;
+default:
+  return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function enables interrupt processing by the processor.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+
+  @retval EFI_SUCCESS   Interrupts are enabled on the processor.
+  @retval EFI_DEVICE_ERROR  Interrupts could not be enabled on the 
processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+  IN EFI_CPU_ARCH_PROTOCOL  *This
+  )
+{
+  EnableInterrupts ();
+
+  mInterruptState  = TRUE;
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function disables interrupt processing by the processor.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+
+  @retval EFI_SUCCESS   Interrupts are disabled on the processor.
+  @retval EFI_DEVICE_ERROR  Interrupts could not be disabled on 

[edk2-devel] [edk2-platforms][PATCH V3 07/16] Platform/Loongson: Support PEI phase.

[xianglai]

Platform PEI module for LoongArch platform initialization.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Loongson/LoongArchQemuPkg/Loongson.dec|  22 ++
 .../Loongson/LoongArchQemuPkg/Loongson.dsc|  65 -
 .../Loongson/LoongArchQemuPkg/Loongson.fdf|  51 
 .../LoongArchQemuPkg/PlatformPei/Fv.c |  61 
 .../LoongArchQemuPkg/PlatformPei/MemDetect.c  | 108 +++
 .../LoongArchQemuPkg/PlatformPei/Platform.c   | 264 ++
 .../LoongArchQemuPkg/PlatformPei/Platform.h   |  87 ++
 .../PlatformPei/PlatformPei.inf   |  71 +
 8 files changed, 728 insertions(+), 1 deletion(-)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Fv.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/MemDetect.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Platform.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Platform.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/PlatformPei/PlatformPei.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
index 8cfa63ee8a..6a423f3ed6 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -30,7 +30,29 @@
 [PcdsFixedAtBuild, PcdsDynamic]
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|0x0|UINT64|0x0008
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvSize|0x0|UINT32|0x0009
+  gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreeBase|0x0|UINT64|0x0018
+  gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreePadding|256|UINT32|0x0019
+
   gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT64|0x001c
   gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d
+  gLoongArchQemuPkgTokenSpaceGuid.PcdUefiRamTop|0x0|UINT64|0x001e
+  gLoongArchQemuPkgTokenSpaceGuid.PcdRamRegionsBottom|0x0|UINT64|0x0022
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029
+
+[PcdsFixedAtBuild.LOONGARCH64]
+   gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32|UINT8|0x0010
+   gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0|UINT8|0x0011
+
+[PcdsDynamic]
+  gLoongArchQemuPkgTokenSpaceGuid.PcdRamSize|0x4000|UINT64|0x0041
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x0042
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x0043
+  gLoongArchQemuPkgTokenSpaceGuid.PcdSwapPageDir|0x0|UINT64|0x0044
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPgd|0x0|UINT64|0x0045
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPud|0x0|UINT64|0x0046
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPmd|0x0|UINT64|0x0047
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPte|0x0|UINT64|0x0048
+
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
index 52ab11de9a..1ca8cc09f7 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -57,22 +57,58 @@
 
 [LibraryClasses.common]
   PcdLib   | 
MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  TimerLib | 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.inf
   PrintLib | 
MdePkg/Library/BasePrintLib/BasePrintLib.inf
   BaseMemoryLib| 
MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
 
 
   BaseLib  | MdePkg/Library/BaseLib/BaseLib.inf
+  PerformanceLib   | 
MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
   PeCoffLib| 
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  CacheMaintenanceLib  | 
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  UefiDecompressLib| 
MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
   PeCoffGetEntryPointLib   | 
MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
   IoLib| 
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
   SerialPortLib| 
Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.inf
   DebugPrintErrorLevelLib  | 
MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+  FdtLib   | EmbeddedPkg/Library/FdtLib/FdtLib.inf
   PeCoffExtraActionLib | 
MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
   DebugAgentLib| 
MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
 
   DebugLib | 

[edk2-devel] [edk2-platforms][PATCH V3 05/16] Platform/Loongson: Add MmuLib.

[xianglai]

Read the memory map information through the QemuFwCfg interface,
then build the page table through the memory map information,
and finally enable Mmu.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LoongArchQemuPkg/Include/Library/MmuLib.h |  85 ++
 .../LoongArchQemuPkg/Library/MmuLib/Mmu.S |  35 +
 .../Library/MmuLib/MmuBaseLib.inf |  35 +
 .../Library/MmuLib/MmuBaseLibPei.inf  |  42 +
 .../Library/MmuLib/MmuLibCore.c   | 908 ++
 .../Library/MmuLib/MmuLibCore.h   |  39 +
 .../Library/MmuLib/MmuLibCorePei.c| 236 +
 .../LoongArchQemuPkg/Library/MmuLib/mmu.h | 104 ++
 .../LoongArchQemuPkg/Library/MmuLib/page.h| 267 +
 .../LoongArchQemuPkg/Library/MmuLib/pte.h |  57 ++
 10 files changed, 1808 insertions(+)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuBaseLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuBaseLibPei.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCore.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCore.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCorePei.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/mmu.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/page.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/pte.h

diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h
new file mode 100644
index 00..6c501eca07
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h
@@ -0,0 +1,85 @@
+/** @file
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- EXC - execute
+**/
+#ifndef MMU_LIB_H_
+#define MMU_LIB_H_
+/**
+  write operation is performed Count times from the first element of Buffer.
+Convert EFI Attributes to Loongarch Attributes.
+  @param[in]  EfiAttributes Efi Attributes.
+
+  @retval  LoongArch Attributes.
+**/
+UINTN
+EfiAttributeToLoongArchAttribute (
+  IN UINTN  EfiAttributes
+  );
+
+/**
+  Finds the length and memory properties of the memory region corresponding to 
the specified base address.
+
+  @param[in]  BaseAddressTo find the base address of the memory region.
+  @param[in]  EndAddress To find the end address of the memory region.
+  @param[out]  RegionLengthThe length of the memory region found.
+  @param[out]  RegionAttributesProperties of the memory region found.
+
+  @retval  EFI_SUCCESSThe corresponding memory area was successfully found
+   EFI_NOT_FOUNDNo memory area found
+**/
+EFI_STATUS
+GetLoongArchMemoryRegion (
+  IN UINTN  BaseAddress,
+  IN UINTN  EndAddress,
+  OUTUINTN  *RegionLength,
+  OUTUINTN  *RegionAttributes
+  );
+
+/**
+  Sets the Attributes  of the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to set the 
Attributes.
+  @param[in]  Length   The length of the memory region to set the 
Attributes.
+  @param[in]  Attributes   The Attributes to be set.
+
+  @retval  EFI_SUCCESSThe Attributes was set successfully
+
+**/
+EFI_STATUS
+LoongArchSetMemoryAttributes (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINTN Length,
+  IN UINTN Attributes
+  );
+
+/**
+  Sets the non-executable Attributes for the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to set the 
Attributes.
+  @param[in]  Length   The length of the memory region to set the 
Attributes.
+
+  @retval  EFI_SUCCESSThe Attributes was set successfully
+**/
+EFI_STATUS
+LoongArchSetMemoryRegionNoExec (
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN  UINTNLength
+  );
+/**
+  Create a page table and initialize the MMU.
+
+  @param[] VOID
+
+  @retval  VOID
+**/
+VOID
+EFIAPI
+ConfigureMmu (
+  VOID
+  );
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S 
b/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S
new file mode 100644
index 00..a697b54e65
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S
@@ -0,0 +1,35 @@
+#--
+#
+# LoongArch for LoongArch
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#-
+
+#ifndef _KERNEL
+#define _KERNEL
+#endif
+

[edk2-devel] [edk2-platforms][PATCH V3 06/16] Platform/Loongson: Add StableTimerLib.

[xianglai]

This library provides a delay interface and a timing interface.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Include/Library/StableTimer.h |  43 
 .../Library/StableTimerLib/Count.S|  35 +++
 .../Library/StableTimerLib/TimerLib.c | 242 ++
 .../Library/StableTimerLib/TimerLib.inf   |  28 ++
 4 files changed, 348 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
new file mode 100644
index 00..09a2d07404
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
@@ -0,0 +1,43 @@
+/** @file
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- Csr- Cpu Status Register
+- Calc   - Calculation
+- Freq   - frequency
+**/
+
+#ifndef STABLE_TIMER_H_
+#define STABLE_TIMER_H_
+#include "Library/Cpu.h"
+
+/**
+  Gets the timer count value.
+
+  @param[] VOID
+
+  @retval  timer count value.
+**/
+extern
+UINTN
+EFIAPI
+LoongArchReadTime (
+  VOID
+  );
+
+/**
+  Calculate the timer frequency.
+
+  @param[] VOID
+
+  @retval  Timer frequency.
+**/
+UINT32
+EFIAPI
+CalcConstFreq (
+  VOID
+  );
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S 
b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
new file mode 100644
index 00..f22635712c
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
@@ -0,0 +1,35 @@
+#--
+#
+# Count for LoongArch
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+#ifndef __ASSEMBLY__
+#define  __ASSEMBLY__
+#endif
+
+#include "Library/Cpu.h"
+#include "LoongArchAsmMacro.h"
+#
+# Set cpu interrupts
+# @param A0 The interrupt number
+#
+ASM_FUNC(CpuSetIP)
+csrrd   T0, LOONGARCH_CSR_ECFG
+or  T0, T0, A0
+csrwr   T0, LOONGARCH_CSR_ECFG
+jirlZERO, RA,0
+
+#
+#Gets the timer count value.
+#
+#@param[] VOID
+#
+#@retval  timer count value.
+ASM_FUNC(LoongArchReadTime)
+rdtime.d   A0, ZERO
+jirlZERO, RA,0
diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c 
b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
new file mode 100644
index 00..660a5d8b0b
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
@@ -0,0 +1,242 @@
+/** @file
+  Generic LoongArch implementation of TimerLib.h
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- Freq - Frequency
+- Csr  - Cpu Status Register
+- calc - calculate
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include "Library/StableTimer.h"
+#include "Library/Cpu.h"
+
+UINT32 StableTimerFreq = 0;
+
+/**
+  Calculate the timer frequency.
+
+  @param[] VOID
+
+  @retval  Timer frequency.
+**/
+UINT32
+EFIAPI
+CalcConstFreq (
+  VOID
+  )
+{
+  UINT32 Result;
+  UINT32 BaseFreq;
+  UINT32 ClockMultiplier;
+  UINT32 ClockDivide;
+
+  LOONGARCH_GET_CPUCFG (BaseFreq, LOONGARCH_CPUCFG4);
+  LOONGARCH_GET_CPUCFG (Result, LOONGARCH_CPUCFG5);
+  ClockMultiplier = Result & 0x;
+  ClockDivide = (Result >> 16) & 0x;
+
+  if ((!BaseFreq)
+|| (!ClockMultiplier)
+|| (!ClockDivide))
+  {
+return 0;
+  }
+  else {
+return (BaseFreq * ClockMultiplier / ClockDivide);
+  }
+}
+/**
+  Get the timer frequency.
+
+  @param[] VOID
+
+  @retval  Timer frequency.
+**/
+UINT32
+EFIAPI
+GetFreq (
+  VOID
+  )
+{
+  if (StableTimerFreq) {
+  } else {
+StableTimerFreq = CalcConstFreq ();
+  }
+
+  return StableTimerFreq;
+}
+
+/**
+  Stalls the CPU for at least the given number of microseconds.
+
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+  @param  MicroSeconds  The minimum number of microseconds to delay.
+
+  @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+  IN  UINTN MicroSeconds
+  )
+{
+
+  UINTN Count;
+  UINTN Ticks;
+  UINTN Start;
+  UINTN End;
+
+  Count = GetFreq ();
+  Count = (Count * MicroSeconds) / 100;
+  Start = LoongArchReadTime ();
+  End = Start + Count;
+
+  do {
+Ticks = LoongArchReadTime 

[edk2-devel] [edk2-platforms][PATCH V3 01/16] Platform/Loongson: Add Serial Port library

[xianglai]

Serial Port library for LoongarchQemuPkg

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LoongArchQemuPkg/Include/Library/Cpu.h| 387 +++
 .../Include/LoongArchQemuPlatform.h   |  97 +++
 .../Library/SerialPortLib/SerialPortLib.c | 612 ++
 .../Library/SerialPortLib/SerialPortLib.inf   |  36 ++
 4 files changed, 1132 insertions(+)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/LoongArchQemuPlatform.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h
new file mode 100644
index 00..8c3c21bd96
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h
@@ -0,0 +1,387 @@
+/** @file
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- EXC - Exception
+- INT - Interrupt
+- FPU - Floating Point Unit
+- CSR - CPU Status Register
+- READQ   - Read Quad Word
+**/
+#ifndef LOONGARCH_CPU_H_
+#define LOONGARCH_CPU_H_
+
+/* Exception types decoded by machdep exception decoder */
+#define EXC_INT 0   /* HW interrupt */
+#define EXC_TLBL1   /* TLB miss on a load */
+#define EXC_TLBS2   /* TLB miss on a store */
+#define EXC_TLBI3   /* TLB miss on a ifetch */
+#define EXC_TLBM4   /* TLB modified fault */
+#define EXC_TLBRI   5   /* TLB Read-Inhibit exception */
+#define EXC_TLBXI   6   /* TLB Execution-Inhibit exception 
*/
+#define EXC_TLBPE   7   /* TLB Privilege Error */
+#define EXC_ADE 8   /* Address Error */
+#define EXC_ALE 9   /* Unalign Access */
+#define EXC_OOB 10  /* Out of bounds */
+#define EXC_SYS 11  /* System call */
+#define EXC_BP  12  /* Breakpoint */
+#define EXC_INE 13  /* Inst. Not Exist */
+#define EXC_IPE 14  /* Inst. Privileged Error */
+#define EXC_FPDIS   15  /* FPU Disabled */
+#define EXC_LSXDIS  16  /* LSX Disabled */
+#define EXC_LASXDIS 17  /* LASX Disabled */
+#define EXC_FPE 18  /* Floating Point Exception */
+#define EXC_WATCH   19  /* Watch address reference */
+#define EXC_BAD 255 /* Undecodeable */
+
+#define COPY_SIGCODE// copy sigcode above user stack in exec
+#define ZERO$r0 /* wired zero */
+#define RA  $r1 /* return address */
+#define GP  $r2 /* global pointer - caller saved for 
PIC */
+#define SP  $r3 /* stack pointer */
+#define V0  $r4 /* return value - caller saved */
+#define V1  $r5
+#define A0  $r4 /* argument registers */
+#define A1  $r5
+#define A2  $r6
+#define A3  $r7
+#define A4  $r8 /* arg reg 64 bit; caller saved in 32 
bit */
+#define A5  $r9
+#define A6  $r10
+#define A7  $r11
+#define T0  $r12 /* caller saved */
+#define T1  $r13
+#define T2  $r14
+#define T3  $r15
+#define T4  $r16 /* callee saved */
+#define T5  $r17
+#define T6  $r18
+#define T7  $r19
+#define T8  $r20 /* caller saved */
+#define TP  $r21 /* TLS */
+#define FP  $r22 /* frame pointer */
+#define S0  $r23 /* callee saved */
+#define S1  $r24
+#define S2  $r25
+#define S3  $r26
+#define S4  $r27
+#define S5  $r28
+#define S6  $r29
+#define S7  $r30
+#define S8  $r31 /* callee saved */
+
+#define FCSR0   $r0
+
+//
+// Location of the saved registers relative to ZERO.
+// Usage is p->p_regs[XX].
+//
+#define RA_NUM  1
+#define GP_NUM  2
+#define SP_NUM   

[edk2-devel] [edk2-platforms][PATCH V3 04/16] Platform/Loongson: Add QemuFwCfgLib.

[xianglai]

QemuFwCfgLib for PEI phase.
This library obtains the QemuFWCfg base address by
directly parsing the fdt, and reads and writes the data
in the QemuFWCfg by operating on the QemuFWCfg base address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Include/IndustryStandard/QemuFwCfg.h  |  95 
 .../Include/Library/QemuFwCfgLib.h| 193 +++
 .../QemuFwCfgLib/QemuFwCfgLibInternal.h   |  64 +++
 .../Library/QemuFwCfgLib/QemuFwCfgPei.c   | 119 +
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.c| 477 ++
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf  |  44 ++
 6 files changed, 992 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
new file mode 100644
index 00..a028ca1124
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
@@ -0,0 +1,95 @@
+/** @file
+  Macro and type definitions corresponding to the QEMU fw_cfg interface.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- FW - FireWare
+- CFG- Configure
+- FNAME- File Name
+- CTL- Contorl
+**/
+
+#ifndef QEMU_FW_CFG_H_
+#define QEMU_FW_CFG_H_
+
+#include 
+
+//
+// The size, in bytes, of names of firmware configuration files, including at
+// least one terminating NUL byte.
+//
+#define QEMU_FW_CFG_FNAME_SIZE  56
+
+//
+// If the following bit is set in the UINT32 fw_cfg revision / feature bitmap
+// -- read from key 0x0001 with the basic IO Port or MMIO method --, then the
+// DMA interface is available.
+//
+#define FW_CFG_F_DMA BIT1
+
+//
+// Macros for the FW_CFG_DMA_ACCESS.Control bitmap (in native encoding).
+//
+#define FW_CFG_DMA_CTL_ERROR BIT0
+#define FW_CFG_DMA_CTL_READ  BIT1
+#define FW_CFG_DMA_CTL_SKIP  BIT2
+#define FW_CFG_DMA_CTL_SELECTBIT3
+#define FW_CFG_DMA_CTL_WRITE BIT4
+
+//
+// The fw_cfg registers can be found at these IO Ports, on the IO-mapped
+// platforms (Ia32 and X64).
+//
+#define FW_CFG_IO_SELECTOR  0x510
+#define FW_CFG_IO_DATA  0x511
+#define FW_CFG_IO_DMA_ADDRESS   0x514
+
+//
+// Numerically defined keys.
+//
+typedef enum {
+  QemuFwCfgItemSignature= 0x,
+  QemuFwCfgItemInterfaceVersion = 0x0001,
+  QemuFwCfgItemSystemUuid   = 0x0002,
+  QemuFwCfgItemRamSize  = 0x0003,
+  QemuFwCfgItemGraphicsEnabled  = 0x0004,
+  QemuFwCfgItemSmpCpuCount  = 0x0005,
+  QemuFwCfgItemMachineId= 0x0006,
+  QemuFwCfgItemKernelAddress= 0x0007,
+  QemuFwCfgItemKernelSize   = 0x0008,
+  QemuFwCfgItemKernelCommandLine= 0x0009,
+  QemuFwCfgItemInitrdAddress= 0x000a,
+  QemuFwCfgItemInitrdSize   = 0x000b,
+  QemuFwCfgItemBootDevice   = 0x000c,
+  QemuFwCfgItemNumaData = 0x000d,
+  QemuFwCfgItemBootMenu = 0x000e,
+  QemuFwCfgItemMaximumCpuCount  = 0x000f,
+  QemuFwCfgItemKernelEntry  = 0x0010,
+  QemuFwCfgItemKernelData   = 0x0011,
+  QemuFwCfgItemInitrdData   = 0x0012,
+  QemuFwCfgItemCommandLineAddress   = 0x0013,
+  QemuFwCfgItemCommandLineSize  = 0x0014,
+  QemuFwCfgItemCommandLineData  = 0x0015,
+  QemuFwCfgItemKernelSetupAddress   = 0x0016,
+  QemuFwCfgItemKernelSetupSize  = 0x0017,
+  QemuFwCfgItemKernelSetupData  = 0x0018,
+  QemuFwCfgItemFileDir  = 0x0019,
+
+} FIRMWARE_CONFIG_ITEM;
+
+//
+// Communication structure for the DMA access method. All fields are encoded in
+// big endian.
+//
+#pragma pack (1)
+typedef struct {
+  UINT32 Control;
+  UINT32 Length;
+  UINT64 Address;
+} FW_CFG_DMA_ACCESS;
+#pragma pack ()
+
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
new file mode 100644
index 00..6b42cf3073
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
@@ -0,0 +1,193 @@
+/** @file
+  QEMU/KVM Firmware Configuration access
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- FW or Fw 

[edk2-devel] [edk2-platforms][PATCH V3 00/16] Platform: Add Loongson support.

[xianglai]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

The uploaded code generates firmware to support Linux launching on the 
LoongArch platform under qemu,
So it will run in a virtual machine.

LoongArch is the general processor architecture of Loongson.
You can get the latest LoongArch documents or LoongArch tools at 
https://github.com/loongson/.

You can also view the code through the Loongson community.
The edk2 code in Loongson community:
https://github.com/loongson/edk2/tree/LoongArch
The edk2-platform code in Loonson community:
https://github.com/loongson/edk2-platforms
The qemu code in Loongson community:
https://gitlab.com/qemu-project/qemu.git
The LoongArch Documentation in Loongson community:
https://github.com/loongson/LoongArch-Documentation/tree/main/docs
The all patches at:
https://github.com/loongson/edk2-platforms/tree/devel-LoongArch-patch

v2 changes:
 - Remove the inline assembly from StableTimerLib.
 - troubleshoot TAB strings, convert TAB characters to spaces.
 - remove smm related code, loongarch has no smm mode.

v3 changes:
 - delete ExtractHandler related code.
 - Boot UEFI with low 256M memory.
 - Modify common interrupt handling.

xianglai li (16):
  Platform/Loongson: Add Serial Port library
  Platform/Loongson: Support SEC And Add Readme.md
  Platform/Loongson: Add PeiServicesTablePointerLib.
  Platform/Loongson: Add QemuFwCfgLib.
  Platform/Loongson: Add MmuLib.
  Platform/Loongson: Add StableTimerLib.
  Platform/Loongson: Support PEI phase.
  Platform/Loongson: Add CPU DXE driver.
  Platform/Loongson: Add PciCpuIoDxe driver.
  Platform/Loongson:  Add timer Dxe driver.
  Platform/Loongson: Add RealTime Clock lib.
  Platform/Loongson: Add Platform Boot Manager Lib.
  Platform/Loongson: Add Reset System Lib.
  Platform/Loongson: Support Dxe
  Platform/Loongson: Add QemuFlashFvbServicesRuntimeDxe driver.
  Platform/Loongson: Support for saving variables to flash.

 Maintainers.txt   |4 +
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c  |  382 ++
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h  |  151 +++
 .../Drivers/CpuDxe/CpuDxe.inf |   56 +
 .../Drivers/CpuDxe/LoongArch64/Exception.c|  338 +
 .../Drivers/CpuDxe/LoongArch64/Fpu.S  |   67 +
 .../Drivers/CpuDxe/LoongArch64/LoongArch.S|  292 +
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c   |  548 
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h   |  219 
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf |   40 +
 .../QemuFlashFvbServicesRuntimeDxe/FvbInfo.c  |  115 ++
 .../FvbServicesRuntimeDxe.inf |   73 ++
 .../FwBlockService.c  | 1158 +
 .../FwBlockService.h  |  178 +++
 .../FwBlockServiceDxe.c   |  152 +++
 .../QemuFlash.c   |  251 
 .../QemuFlash.h   |   86 ++
 .../QemuFlashDxe.c|   21 +
 .../Drivers/StableTimerDxe/Timer.c|  405 ++
 .../Drivers/StableTimerDxe/Timer.h|  165 +++
 .../Drivers/StableTimerDxe/TimerDxe.inf   |   40 +
 .../Include/IndustryStandard/QemuFwCfg.h  |   95 ++
 .../LoongArchQemuPkg/Include/Library/Cpu.h|  387 ++
 .../LoongArchQemuPkg/Include/Library/MmuLib.h |   85 ++
 .../Include/Library/QemuFwCfgLib.h|  193 +++
 .../Include/Library/StableTimer.h |   43 +
 .../Include/LoongArchAsmMacro.h   |   23 +
 .../Include/LoongArchQemuPlatform.h   |   97 ++
 .../LsRealTimeClockLib/LsRealTimeClock.h  |   41 +
 .../LsRealTimeClockLib/LsRealTimeClockLib.c   |  343 +
 .../LsRealTimeClockLib/LsRealTimeClockLib.inf |   41 +
 .../LoongArchQemuPkg/Library/MmuLib/Mmu.S |   35 +
 .../Library/MmuLib/MmuBaseLib.inf |   35 +
 .../Library/MmuLib/MmuBaseLibPei.inf  |   42 +
 .../Library/MmuLib/MmuLibCore.c   |  908 +
 .../Library/MmuLib/MmuLibCore.h   |   39 +
 .../Library/MmuLib/MmuLibCorePei.c|  236 
 .../LoongArchQemuPkg/Library/MmuLib/mmu.h |  104 ++
 .../LoongArchQemuPkg/Library/MmuLib/page.h|  267 
 .../LoongArchQemuPkg/Library/MmuLib/pte.h |   57 +
 .../PeiServicesTablePointer.c |   78 ++
 .../PeiServicesTablePointerLib.inf|   32 +
 .../PlatformBootManagerLib/PlatformBm.c   |  760 +++
 .../PlatformBootManagerLib/PlatformBm.h   |  112 ++
 .../PlatformBootManagerLib.inf|   78 ++
 .../PlatformBootManagerLib/QemuKernel.c   |   81 ++
 .../QemuFwCfgLib/QemuFwCfgLibInternal.h   |   64 +
 .../Library/QemuFwCfgLib/QemuFwCfgPei.c   |  119 ++
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.c|  477 +++
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf  |   44 +
 .../BaseResetSystemAcpiGed.c  |  155 +++
 .../BaseResetSystemAcpiGedLib.inf |   42 +
 .../DxeResetSystemAcpiGed.c   

[edk2-devel] [edk2-platforms][PATCH V3 02/16] Platform/Loongson: Support SEC And Add Readme.md

[xianglai]

Add SEC Code And Readme.md for LoongArchQemu

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li  
---
 Maintainers.txt   |   4 +
 .../Include/LoongArchAsmMacro.h   |  23 +
 .../Loongson/LoongArchQemuPkg/Loongson.dec|  36 ++
 .../Loongson/LoongArchQemuPkg/Loongson.dsc| 131 +
 .../Loongson/LoongArchQemuPkg/Loongson.fdf|  53 ++
 .../LoongArchQemuPkg/Loongson.fdf.inc |  21 +
 Platform/Loongson/LoongArchQemuPkg/Readme.md  |  59 ++
 .../LoongArchQemuPkg/Sec/LoongArch64/Start.S  |  76 +++
 .../Loongson/LoongArchQemuPkg/Sec/SecMain.c   | 510 ++
 .../Loongson/LoongArchQemuPkg/Sec/SecMain.inf |  47 ++
 Readme.md |   9 +
 11 files changed, 969 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.dec
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Readme.md
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/LoongArch64/Start.S
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/SecMain.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/SecMain.inf

diff --git a/Maintainers.txt b/Maintainers.txt
index 700ca0af60..8921d6b4e1 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -329,6 +329,10 @@ M: Bob Feng 
 M: Liming Gao 
 R: Yuwei Chen 
 
+Loongson platforms
+F: Platform/Loongson/
+M: xianglai li 
+
 Marvell platforms and silicon
 F: Platform/Marvell/
 F: Platform/SolidRun/Armada80x0McBin/
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
new file mode 100644
index 00..366d4308e8
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
@@ -0,0 +1,23 @@
+/** @file
+   LoongArch ASM macro definition.
+
+   Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+
+#ifndef LOONGARCH_ASM_MACRO_H_
+#define LOONGARCH_ASM_MACRO_H_
+
+#include 
+
+#define _ASM_FUNC(Name, Section)\
+  .global   Name  ; \
+  .section  #Section, "ax"; \
+  .type Name, %function   ; \
+  Name:
+
+#define ASM_FUNC(Name)_ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#endif // __LOONGARCH_ASM_MACRO_H__
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
new file mode 100644
index 00..8cfa63ee8a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -0,0 +1,36 @@
+## @file
+#
+#  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = LoongArchQemuPkg
+  PACKAGE_GUID   = b51d765a-41da-45fc-a537-de3ee785c0f6
+  PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
+
+[Guids]
+  gLoongArchQemuPkgTokenSpaceGuid  = { 0x0e0383ce, 0x0151, 0x4d01, { 0x80, 
0x0e, 0x3f, 0xef, 0x8b, 0x27, 0x6d, 0x52 } }
+
+[PcdsFixedAtBuild, PcdsDynamic]
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+  gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT64|0x001c
+  gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
new file mode 100644
index 00..52ab11de9a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -0,0 +1,131 @@
+## @file
+#
+#  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that will be processed to create a 

[edk2-devel] [edk2-platforms][PATCH V3 03/16] Platform/Loongson: Add PeiServicesTablePointerLib.

[xianglai]

Use a register to save PeiServicesTable pointer,
This lib Provides PeiServicesTable pointer saving
and retrieval services.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../PeiServicesTablePointer.c | 78 +++
 .../PeiServicesTablePointerLib.inf| 32 
 2 files changed, 110 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
new file mode 100644
index 00..068960d4ce
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
@@ -0,0 +1,78 @@
+/** @file
+  PEI Services Table Pointer Library.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include "Library/Cpu.h"
+
+/**
+  Caches a pointer PEI Services Table.
+
+  Caches the pointer to the PEI Services Table specified by 
PeiServicesTablePointer
+  in a platform specific manner.
+
+  If PeiServicesTablePointer is NULL, then ASSERT ().
+
+  @paramPeiServicesTablePointer   The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+  IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+  )
+{
+  LOONGARCH_CSR_WRITEQ ((UINTN)PeiServicesTablePointer, LOONGARCH_CSR_KS0);
+}
+
+/**
+  Retrieves the cached value of the PEI Services Table pointer.
+
+  Returns the cached value of the PEI Services Table pointer in a CPU specific 
manner
+  as specified in the CPU binding section of the Platform Initialization 
Pre-EFI
+  Initialization Core Interface Specification.
+
+  If the cached PEI Services Table pointer is NULL, then ASSERT ().
+
+  @return  The pointer to PeiServices.
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+  VOID
+  )
+{
+  UINTN  val;
+
+  LOONGARCH_CSR_READQ (val, LOONGARCH_CSR_KS0);
+  return (CONST EFI_PEI_SERVICES **)val;
+}
+
+/**
+Perform CPU specific actions required to migrate the PEI Services Table
+pointer from temporary RAM to permanent RAM.
+
+For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+a dedicated CPU register.  This means that there is no memory storage
+associated with storing the PEI Services Table pointer, so no additional
+migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+VOID
+)
+{
+  return;
+}
diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
new file mode 100644
index 00..6fe76d1351
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
@@ -0,0 +1,32 @@
+## @file
+#  PEI Services Table Pointer Library.
+#
+#  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PeiServicesTablePointerLib
+  FILE_GUID  = C3C9C4ED-EB8A-4548-BE1B-ABB0B6F35B1E
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PeiServicesTablePointerLib|PEIM PEI_CORE SEC
+
+#
+#  VALID_ARCHITECTURES   = LOONGARCH64
+#
+
+[Sources]
+  PeiServicesTablePointer.c
+
+[Packages]
+  Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  DebugLib
+
+[Pcd]
+
-- 
2.31.1



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Re: [edk2-devel] [PATCH v2 2/2] Fix bug on SRIOV ReservedBusNum when ARI enable.

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Foster Nong
> Sent: Wednesday, October 12, 2022 10:37 AM
> To: devel@edk2.groups.io
> Cc: Nong, Foster 
> Subject: [edk2-devel] [PATCH v2 2/2] Fix bug on SRIOV ReservedBusNum when ARI 
> enable.
> 
> If a device which support both features SR-IOV/ARI  has multi
> functions, which maybe support 8-255. After enable ARI forwarding in
> the root port and ARI Capable Hierarchy in the SR-IOV PF0.
> The device will support and expose multi functions(0-255) with ARI ID routing.
> In next device loop in below for() code, actually it still be in the
> same SR-IOV device, and just some PF which is over 8 or higher
> one(n*8), PciAllocateBusNumber() will allocate bus
> number(ReservedBusNum - TempReservedBusNum)) for this PF. if reset
> TempReservedBusNum as 0 in this case,it will allocate wrong bus number
> for this PF because TempReservedBusNum should be total previous PF's
> reserved bus numbers.
> 
> code:
>   for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
> TempReservedBusNum = 0;
> for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
> //
> // Check to see whether a pci device is present
> //
> Status = PciDevicePresent (
>  PciRootBridgeIo,
>  ,
>  StartBusNumber,
>  Device,
>  Func
>  );
> ...
> Status = PciAllocateBusNumber (PciDevice, *SubBusNumber,
> (UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);
> 
> The solution is add a new flag IsAriEnabled to help handle this case.
> if ARI is enabled, then TempReservedBusNum will not be reset again
> during all functions(1-255) scan with checking flag IsAriEnabled.
> 
> Signed-off-by: Foster Nong 
> ---
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c |  1 +
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c   | 19 
> ++-
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  1 +
>  3 files changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> index bc20da1f38..8eca859695 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> @@ -2286,6 +2286,7 @@ CreatePciIoDevice (
>   
> 
>   );
> 
>if ((Data32 & 
> EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {
> 
> +PciIoDevice->IsAriEnabled = TRUE;
> 
>  //
> 
>  // ARI forward support in bridge, so enable it.
> 
>  //
> 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c 
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
> index d5e3ef4d3f..3a57c05755 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
> @@ -1106,6 +1106,7 @@ PciScanBus (
>EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL*PciRootBridgeIo;
> 
>BOOLEANBusPadding;
> 
>UINT32 TempReservedBusNum;
> 
> +  BOOLEANIsAriEnabled;
> 
> 
> 
>PciRootBridgeIo = Bridge->PciRootBridgeIo;
> 
>SecondBus   = 0;
> 
> @@ -1116,9 +1117,12 @@ PciScanBus (
>BusPadding  = FALSE;
> 
>PciDevice   = NULL;
> 
>PciAddress  = 0;
> 
> +  IsAriEnabled= FALSE;
> 
> 
> 
>for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
> 
> -TempReservedBusNum = 0;
> 
> +if (!IsAriEnabled) {
> 
> +  TempReservedBusNum = 0;
> 
> +}
> 
>  for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
> 
>//
> 
>// Check to see whether a pci device is present
> 
> @@ -1157,6 +1161,19 @@ PciScanBus (
>if (EFI_ERROR (Status)) {
> 
>  continue;
> 
>}
> 
> +  //
> 
> +  // Per Pcie spec ARI Extended Capability
> 
> +  // This capability must be implemented by each function in an ARI 
> device.
> 
> +  // It is not applicable to a Root Port, a Switch Downstream Port, an 
> RCiEP, or a Root Complex Event Collector
> 
> +  //
> 
> +  if (((Device == 0) && (Func == 0)) && (PciDevice->IsAriEnabled)) {
> 
> +IsAriEnabled = TRUE;
> 
> +  }
> 
> +  if (PciDevice->IsAriEnabled != IsAriEnabled) {
> 
> +DEBUG ((DEBUG_ERROR, "ERROR: %02x:%02x:%02x device ARI Feature(%x) 
> is not consistent with others Function\n",
> 
> +StartBusNumber, Device, Func, PciDevice->IsAriEnabled));
> 
> +return EFI_DEVICE_ERROR;
> 
> +  }
> 
> 
> 
>PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);
> 
> 
> 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> index 4b58c3ea9b..ca5c06204d 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> @@ -262,6 +262,7 

Re: [edk2-devel] [PATCH v2 1/2] MdeModulePkg: Fixed extra 1 SR-IOV reserved bus

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Foster Nong
> Sent: Wednesday, October 12, 2022 10:37 AM
> To: devel@edk2.groups.io
> Cc: Nong, Foster 
> Subject: [edk2-devel] [PATCH v2 1/2] MdeModulePkg: Fixed extra 1 SR-IOV 
> reserved bus
> 
> Below code will calculate the reserved bus number for the each PF.
> 
> Based on the VF routing ID algorithm, PFRid and LastVF in below code
> already sure that "All VFs and PFs must have distinct Routing IDs".
> PF will be assigned Routing ID based on secBusNumber, ReservedBusNum
> will add into SubBusNumber directly. So the SR-IOV device will be
> assigned bus range as SecBusNumber ~ (SubBusNumber=(SecBusNumber +
> ReservedBusNum)).
> Thus "+1" in below code will cause extra 1 bus, and introduce a bus hole.
> 
>  PFRid  = EFI_PCI_RID (Bus, Device, Func);
>  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
>  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) -
>  Bus + 1);
> 
> In SR-IOV spec, there is a note in section 2.1.2:
> Note: Bus Numbers are a constrained resource. Devices are strongly
> encouraged to avoid leaving “holes” in their Bus Number usage to avoid
> wasting Bus Numbers
> 
> So the issue can be fixed with below code change.
>   PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) -
>   Bus);
> 
> https://bugzilla.tianocore.org/show_bug.cgi?id=4069
> 
> Signed-off-by: Foster Nong 
> ---
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> index eb250f6f7b..bc20da1f38 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> @@ -2425,7 +2425,7 @@ CreatePciIoDevice (
>  //
> 
>  // Calculate ReservedBusNum for this PF
> 
>  //
> 
> -PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - 
> Bus + 1);
> 
> +PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - 
> Bus);
> 
>}
> 
> 
> 
>DEBUG ((
> 
> --
> 2.37.1.windows.1
> 
> 
> 
> 
> 



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Re: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] [PATCH] MdeModulePkg VariablePei: Add Variable state check when find variable in IndexTable.

[Jiading Zhang]

Hi Liming:
My case is special, the HOB is created in a special memory, neither cache nor 
normal memory,  and it is non-volatile for a warm reboot, so the change works 
in my code. Maybe I should try to  create the hob in a volatile cache or 
memory, so I needn't change the open source code.

Thanks very much.
Jiading

On Fri, Oct 14, 2022 at 09:57 AM, gaoliming wrote:

> 
> 
> 
> Jiading:
> 
> 
> 
> HOB is created in volatile memory (cache or physical memory). And, HOB is
> re-created for every boot (normal boot, S3 boot). When the first call
> GetVariable, gEfiVariableIndexTableGuid guid hob should not exist. If this
> guid hob exits, it should be created by other module. Please check.
> 
> 
> 
> 
> 
> 
> 
> Thanks
> 
> 
> 
> Liming
> 
> 
> 
> *发件人 :* Jiading Zhang 
> *发送时间 :* 2022 年 10 月 10 日 16:36
> *收件人 :* gaoliming ; devel@edk2.groups.io
> *主题 :* Re: [edk2-devel] 回复 : [edk2-devel] 回复 : [edk2-devel] [PATCH]
> MdeModulePkg VariablePei: Add Variable state check when find variable in
> IndexTable.
> 
> 
> 
> 
> 
> 
> 
> 
> Hi liming:
> I checked the code, and found the root cause of the issue.
> As the following code in edk2,   in my code,  after the  first time to
> read the variable in PEI phase,  it cached the variable store info 
> IndexTable into  a Hob in a special non-volatile memory,  but after the
> code running in dxe phase, the variable was changed.  And after a warm
> reboot, maybe call s3 sleep is more exactly, when read the variable, it 
> first get the IndexTable from the Hob but not build the IndexTable again,
> so it read the deleted variable if hasn't the condition check.  This is
> really a special case.
> 
> 
> 
> GuidHob = GetFirstGuidHob ();
> 
> 
> 
> 
> if (GuidHob != NULL) {
> 
> 
> 
> 
> StoreInfo->IndexTable = GET_GUID_HOB_DATA (GuidHob);
> 
> 
> 
> 
> } else {
> 
> 
> 
> 
> //
> 
> 
> 
> 
> // If it's the first time to access variable region in flash, create a
> guid hob to record
> 
> 
> 
> 
> // VAR_ADDED type variable info.
> 
> 
> 
> 
> // Note that as the resource of PEI phase is limited, only store the
> limited number of
> 
> 
> 
> 
> // VAR_ADDED type variables to reduce access time.
> 
> 
> 
> 
> //
> 
> 
> 
> 
> StoreInfo->IndexTable = (VARIABLE_INDEX_TABLE *) BuildGuidHob
> (, sizeof (VARIABLE_INDEX_TABLE));
> 
> 
> 
> 
> StoreInfo->IndexTable->Length      = 0;
> 
> 
> 
> 
> StoreInfo->IndexTable->StartPtr    = GetStartPointer
> (VariableStoreHeader);
> 
> 
> 
> 
> StoreInfo->IndexTable->EndPtr      = GetEndPointer  
> (VariableStoreHeader);
> 
> 
> 
> 
> StoreInfo->IndexTable->GoneThrough = 0;
> 
> 
> 
> 
> }
> 
> 
> 
> 
> 
> 
> 
> 
> On Mon, Oct 10, 2022 at 09:39 AM, gaoliming wrote:
> 
> 
>> 
>> 
>> Jiading:
>> 
>> 
>> 
>> Please check why NV variable data is required to be changed in PEI phase.
>> This will be helpful for this issue.
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> Thanks
>> 
>> 
>> 
>> Liming
>> 
>> 
>> 
>> *发件人 :* Jiading Zhang < jdzh...@kunluntech.com.cn >
>> *发送时间 :* 2022 年 10 月 10 日 8:35
>> *收件人 :* gaoliming < gaolim...@byosoft.com.cn >; devel@edk2.groups.io
>> *主题 :* Re: [edk2-devel] 回复 : [edk2-devel] [PATCH] MdeModulePkg VariablePei:
>> Add Variable state check when find variable in IndexTable.
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> Hi liming:
>> Yes, NV Variable Data is not changed in PEI phase in normal case. This
>> issue was found when we did a special coding, and when found variable in
>> the IndexTable, it found the variable before the last changed if  didn't
>> add the following condition:
>> "if ((VariableHeader->State == VAR_ADDED) || (VariableHeader->State ==
>> (VAR_IN_DELETED_TRANSITION & VAR_ADDED)))"
>> 
>> Maybe our specail coding had some defect ， and caused this issue.
>> 
>> On Fri, Sep 30, 2022 at 10:46 AM, gaoliming wrote:
>> 
>> 
>>> 
>>> 
>>> Jiading:
>>> 
>>> 
>>> 
>>> Hob Variable Store Info IndexTable is NULL. So, this logic doesn ’ t work
>>> for HOB variable store. NV Variable Store Info has IndexTable. When its
>>> IndexTable is initialized, its IndexTable will only record the variable
>>> with VAR_ADDED attribute. Because NV Variable Data is not changed in PEI
>>> phase, this check is not required by NV variable.
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> Thanks
>>> 
>>> 
>>> 
>>> Liming
>>> 
>>> 
>>> 
>>> *发件人 :* devel@edk2.groups.io < devel@edk2.groups.io > *代表* Jiading Zhang
>>> *发送时间 :* 2022 年 9 月 28 日 11:05
>>> *收件人 :* devel@edk2.groups.io
>>> *主题 :* [edk2-devel] [PATCH] MdeModulePkg VariablePei: Add Variable state
>>> check when find variable in IndexTable.
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> When read a variable in PEI, it will find it first in the HOB, then find
>>> in variable store. When find in variable store, it will check the variable
>>> state, but find in HOB, it doesn't check the state, so if the variable was
>>> changed, it will find the obsolete variable in the HOB.
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> Signed-off-by: jdzhang < jdzh...@kunluntech.com.cn >
>>> 
>>> 
>>> 
>>> 
>>> ---
>>> 
>>> 
>>> 

[edk2-devel] [PATCH] Pkg-Module: Remove Non-ASCII Characters

[SteveX Li]

It would cause compiler error.

Signed-off-by: SteveX Li 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Abner Chang 
Cc: Daniel Schaefer 
---
 EmbeddedPkg/GdbStub/GdbStubInternal.h| 32 
 EmbeddedPkg/Include/Protocol/UsbDevice.h |  2 +-
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/EmbeddedPkg/GdbStub/GdbStubInternal.h 
b/EmbeddedPkg/GdbStub/GdbStubInternal.h
index 9c3929c812..5eaff61d83 100644
--- a/EmbeddedPkg/GdbStub/GdbStubInternal.h
+++ b/EmbeddedPkg/GdbStub/GdbStubInternal.h
@@ -322,7 +322,7 @@ SendNotSupported (
   VOID
   );
 
-/** ‘p n’
+/** 'p n'
  Reads the n-th register's value into an output buffer and sends it as a packet
  @param SystemContext   Register content at time of the exception
  @param InBufferThis is the input buffer received from gdb 
server
@@ -333,7 +333,7 @@ ReadNthRegister (
   INCHAR8   *InBuffer
   );
 
-/** ‘g’
+/** 'g'
  Reads the general registers into an output buffer  and sends it as a packet
  @param SystemContext   Register content at time of the exception
  **/
@@ -343,7 +343,7 @@ ReadGeneralRegisters (
   INEFI_SYSTEM_CONTEXT  SystemContext
   );
 
-/** ‘P n...=r...’
+/** 'P n...=r...'
  Writes the new value of n-th register received into the input buffer to the 
n-th register
  @param SystemContext   Register content at time of the exception
  @param InBufferThis is the input buffer received from gdb 
server
@@ -355,7 +355,7 @@ WriteNthRegister (
   INCHAR8   *InBuffer
   );
 
-/** ‘G XX...’
+/** 'G XX...'
  Writes the new values received into the input buffer to the general registers
  @param SystemContext   Register content at time of the 
exception
  @param InBufferPointer to the input buffer received 
from gdb server
@@ -368,7 +368,7 @@ WriteGeneralRegisters (
   INCHAR8   *InBuffer
   );
 
-/** ‘m addr,length ’
+/** 'm addr,length '
  Find the Length of the area to read and the start address. Finally, pass them 
to
  another function, TransferFromMemToOutBufAndSend, that will read from that 
memory space and
  send it as a packet.
@@ -381,7 +381,7 @@ ReadFromMemory (
   IN  CHAR8  *PacketData
   );
 
-/** ‘M addr,length :XX...’
+/** 'M addr,length :XX...'
  Find the Length of the area in bytes to write and the start address. Finally, 
pass them to
  another function, TransferFromInBufToMem, that will write to that memory 
space the info in
  the input buffer.
@@ -394,7 +394,7 @@ WriteToMemory (
   IN CHAR8  *PacketData
   );
 
-/** ‘c [addr ]’
+/** 'c [addr ]'
  Continue. addr is Address to resume. If addr is omitted, resume at current
  Address.
 
@@ -409,7 +409,7 @@ ContinueAtAddress (
   IN  CHAR8   *PacketData
   );
 
-/** ‘s [addr ]’
+/** 's [addr ]'
  Single step. addr is the Address at which to resume. If addr is omitted, 
resume
  at same Address.
 
@@ -444,10 +444,10 @@ RemoveSingleStep (
   );
 
 /**
-  ‘Z1, [addr], [length]’
-  ‘Z2, [addr], [length]’
-  ‘Z3, [addr], [length]’
-  ‘Z4, [addr], [length]’
+  'Z1, [addr], [length]'
+  'Z2, [addr], [length]'
+  'Z3, [addr], [length]'
+  'Z4, [addr], [length]'
 
   Insert hardware breakpoint/watchpoint at address addr of size length
 
@@ -463,10 +463,10 @@ InsertBreakPoint (
   );
 
 /**
-  ‘z1, [addr], [length]’
-  ‘z2, [addr], [length]’
-  ‘z3, [addr], [length]’
-  ‘z4, [addr], [length]’
+  'z1, [addr], [length]'
+  'z2, [addr], [length]'
+  'z3, [addr], [length]'
+  'z4, [addr], [length]'
 
   Remove hardware breakpoint/watchpoint at address addr of size length
 
diff --git a/EmbeddedPkg/Include/Protocol/UsbDevice.h 
b/EmbeddedPkg/Include/Protocol/UsbDevice.h
index b299ee10a7..b07f459afa 100644
--- a/EmbeddedPkg/Include/Protocol/UsbDevice.h
+++ b/EmbeddedPkg/Include/Protocol/UsbDevice.h
@@ -83,7 +83,7 @@ EFI_STATUS
 first interface descriptor. If there are
 additional interfaces, their interface
 descriptor and endpoint descriptors follow the
-first interface’s endpoint descriptors".
+first interface's endpoint descriptors".
 
 The size of each buffer is the TotalLength
 member of the Configuration Descriptor.
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V2 3/3] UefiCpuPkg: Add Pei/DxeCpuExceptionHandlerLibUnitTest in dsc

[duntan]

Add Pei/DxeCpuExceptionHandlerLibUnitTest module in UefiCpuPkg.dsc

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
---
 UefiCpuPkg/UefiCpuPkg.dsc | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index f694b3a77c..31145dbe7e 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -63,6 +63,9 @@
   MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
   
SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
   CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
+  UnitTestLib|UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.inf
+  
UnitTestPersistenceLib|UnitTestFrameworkPkg/Library/UnitTestPersistenceLibNull/UnitTestPersistenceLibNull.inf
+  
UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibDebugLib.inf
 
 [LibraryClasses.common.SEC]
   PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf
@@ -177,6 +180,10 @@
   UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
   UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
   UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
+  UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerLibUnitTest.inf
+
+[Components.X64]
+  UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerLibUnitTest.inf
 
 [BuildOptions]
   *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V2 2/3] UefiCpuPkg: Add Unit tests for PeiCpuExceptionHandlerLib

[duntan]

Add target based unit tests for the PeiCpuExceptionHandlerLib.
A PEIM is created to test PeiCpuExceptionHandlerLib.
Four of test cases are created in this module:
a.Test if exception handler can be registered/unregistered
for no error code exception.In the test case, only no error
code exception is triggered and tested by INTn instruction.

b.Test if exception handler can be registered/unregistered
for GP and PF. In the test case, GP exception is triggered
and tested by setting CR4_RESERVED_BIT to 1. PF exception
is triggered by writting to not-present or RO address.

c.Test if CpuContext is consistent before and after exception.
In this test case:
1.Set Cpu register to mExpectedContextInHandler before
exception. 2.Trigger exception specified by ExceptionType.
3.Store SystemContext in mActualContextInHandler and set
SystemContext to mExpectedContextAfterException in handler.
4.After return from exception, store Cpu registers in
mActualContextAfterException.
The expectation is:
1.Register values in mActualContextInHandler are the same
with register values in mExpectedContextInHandler.
2.Register values in mActualContextAfterException are the
same with register values mActualContextAfterException.

d.Test if stack overflow can be captured by CpuStackGuard
in both Bsp and AP. In this test case, stack overflow is
triggered by a funtion which calls itself continuously.
This test case triggers stack overflow in both BSP and AP.
All AP use same Idt with Bsp. The expectation is:
1. PF exception is triggered (leading to a DF if sepereated
stack is not prepared for PF) when Esp<=StackBase+SIZE_4KB
since [StackBase, StackBase + SIZE_4KB] is guarded in page
table when PcdCpuStackGuard is TRUE.
2. Stack for PF/DF exception handler in both Bsp and AP is
succussfully switched by InitializeSeparateExceptionStacks.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
---
 UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h | 
 21 -
 UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTest.c   | 
135 
+++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTestAsm.nasm | 
208 

 UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerLibUnitTest.inf | 
 61 +
 UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerUnitTest.c  | 
204 

 5 files changed, 624 insertions(+), 5 deletions(-)

diff --git a/UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h 
b/UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h
index 3034257d9c..7d9a07a491 100644
--- a/UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h
+++ b/UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h
@@ -122,11 +122,22 @@ typedef struct {
   UINT64R15Register;
 } GENERAL_REGISTER;
 
-extern UINTN   mFaultInstructionLength;
-extern EFI_EXCEPTION_TYPE  mExceptionType;
-extern UINTN   mRspAddress[];
-extern GENERAL_REGISTERmExpectedContextInHandler;
-extern GENERAL_REGISTERmActualContextAfterException;
+typedef struct {
+  UINT32Edi;
+  UINT32Esi;
+  UINT32Ebx;
+  UINT32Edx;
+  UINT32Ecx;
+  UINT32Eax;
+} GENERAL_REGISTER_IA32;
+
+extern UINTN  mFaultInstructionLength;
+extern EFI_EXCEPTION_TYPE mExceptionType;
+extern UINTN  mRspAddress[];
+extern GENERAL_REGISTER   mExpectedContextInHandler;
+extern GENERAL_REGISTER   mActualContextAfterException;
+extern GENERAL_REGISTER_IA32  mIa32ExpectedContextInHandler;
+extern GENERAL_REGISTER_IA32  mIa32ActualContextAfterException;
 
 /**
   Initialize Bsp Idt with a new Idt table and return the IA32_DESCRIPTOR 
buffer.
diff --git 
a/UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTest.c 
b/UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTest.c
new file mode 100644
index 00..cb83dad215
--- /dev/null
+++ b/UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTest.c
@@ -0,0 +1,135 @@
+/** @file
+  Unit tests of the CpuExceptionHandlerLib.
+
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuExceptionHandlerTest.h"
+
+GENERAL_REGISTER_IA32  mIa32ActualContextInHandler;
+GENERAL_REGISTER_IA32  mIa32ActualContextAfterException;
+
+//
+// In 

[edk2-devel] [Patch V2 1/3] UefiCpuPkg: Add Unit tests for DxeCpuExceptionHandlerLib

[duntan]

Add target based unit tests for the DxeCpuExceptionHandlerLib.
A DXE driver is created to test DxeCpuExceptionHandlerLib.

Four test cases are created in this Unit Test module:
a.Test if exception handler can be registered/unregistered
for no error code exception.In the test case, only no error
code exception is triggered and tested by INTn instruction.

b.Test if exception handler can be registered/unregistered
for GP and PF. In the test case, GP exception is triggered
and tested by setting CR4_RESERVED_BIT to 1. PF exception
is triggered by writting to not-present or RO address.

c.Test if CpuContext is consistent before and after exception.
In this test case:
1.Set Cpu register to mExpectedContextInHandler before
exception. 2.Trigger exception specified by ExceptionType.
3.Store SystemContext in mActualContextInHandler and set
SystemContext to mExpectedContextAfterException in handler.
4.After return from exception, store Cpu registers in
mActualContextAfterException.
The expectation is:
1.Register values in mActualContextInHandler are the same
with register values in mExpectedContextInHandler.
2.Register values in mActualContextAfterException are the
same with register values mActualContextAfterException.

d.Test if stack overflow can be captured by CpuStackGuard
in both Bsp and AP. In this test case, stack overflow is
triggered by a funtion which calls itself continuously.
This test case triggers stack overflow in both BSP and AP.
All AP use same Idt with Bsp. The expectation is:
1. PF exception is triggered (leading to a DF if sepereated
stack is not prepared for PF) when Rsp<=StackBase+SIZE_4KB
since [StackBase, StackBase + SIZE_4KB] is guarded in page
table when PcdCpuStackGuard is TRUE.
2. Stack for PF/DF exception handler in both Bsp and AP is
succussfully switched by InitializeSeparateExceptionStacks.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
---
 UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h | 
367 
+++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTestCommon.c   | 
862 
++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerLibUnitTest.inf | 
 58 ++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerUnitTest.c  | 
196 

 UefiCpuPkg/CpuExceptionHandlerUnitTest/X64/ArchExceptionHandlerTest.c| 
166 
++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/X64/ArchExceptionHandlerTestAsm.nasm  | 
256 

 6 files changed, 1905 insertions(+)

diff --git a/UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h 
b/UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h
new file mode 100644
index 00..3034257d9c
--- /dev/null
+++ b/UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h
@@ -0,0 +1,367 @@
+/** @file
+
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  Four test cases are created in this Unit Test module.
+  a.Test if exception handler can be registered/unregistered for no error code 
exception
+In this test case, only no error code 

[edk2-devel] [Patch V2 0/3] Add Unit tests for Pei/DxeCpuExceptionHandlerLib

[duntan]

Add more comments to explain the unit test case in V2 patch.
Do some code refinement to the unit test case.

Dun Tan (3):
  UefiCpuPkg: Add Unit tests for DxeCpuExceptionHandlerLib
  UefiCpuPkg: Add Unit tests for PeiCpuExceptionHandlerLib
  UefiCpuPkg: Add Pei/DxeCpuExceptionHandlerLibUnitTest in dsc

 UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h | 
378 
++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTestCommon.c   | 
862 
++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerLibUnitTest.inf | 
 58 ++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerUnitTest.c  | 
196 

 UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTest.c   | 
135 
+++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTestAsm.nasm | 
208 

 UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerLibUnitTest.inf | 
 61 +
 UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerUnitTest.c  | 
204 

 UefiCpuPkg/CpuExceptionHandlerUnitTest/X64/ArchExceptionHandlerTest.c| 
166 
++
 UefiCpuPkg/CpuExceptionHandlerUnitTest/X64/ArchExceptionHandlerTestAsm.nasm  | 
256 

 UefiCpuPkg/UefiCpuPkg.dsc| 
  7 +++
 11 files changed, 2531 insertions(+)
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTest.h
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/CpuExceptionHandlerTestCommon.c
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerLibUnitTest.inf
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/DxeCpuExceptionHandlerUnitTest.c
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTest.c
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/Ia32/ArchExceptionHandlerTestAsm.nasm
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerLibUnitTest.inf
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/PeiCpuExceptionHandlerUnitTest.c
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/X64/ArchExceptionHandlerTest.c
 create mode 100644 
UefiCpuPkg/CpuExceptionHandlerUnitTest/X64/ArchExceptionHandlerTestAsm.nasm

-- 
2.31.1.windows.1



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回复: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] [PATCH] MdeModulePkg VariablePei: Add Variable state check when find variable in IndexTable.

[gaoliming via groups.io]

Jiading:

 HOB is created in volatile memory (cache or physical memory). And, HOB is 
re-created for every boot (normal boot, S3 boot). When the first call 
GetVariable, gEfiVariableIndexTableGuid guid hob should not exist. If this guid 
hob exits, it should be created by other module. Please check. 

 

Thanks

Liming

发件人: Jiading Zhang  
发送时间: 2022年10月10日 16:36
收件人: gaoliming ; devel@edk2.groups.io
主题: Re: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] [PATCH] MdeModulePkg 
VariablePei: Add Variable state check when find variable in IndexTable.

 

Hi liming:
I checked the code, and found the root cause of the issue.
As the following code in edk2,   in my code,  after the  first time to read 
the variable in PEI phase,  it cached the variable store info  IndexTable into  
a Hob in a special non-volatile memory,  but after the code running in dxe 
phase, the variable was changed.  And after a warm reboot, maybe call s3 sleep 
is more exactly, when read the variable, it  first get the IndexTable from the 
Hob but not build the IndexTable again, so it read the deleted variable if 
hasn't the condition check.  This is really a special case.

  GuidHob = GetFirstGuidHob ();

if (GuidHob != NULL) {

  StoreInfo->IndexTable = GET_GUID_HOB_DATA (GuidHob);

} else {

  //

  // If it's the first time to access variable region in flash, create 
a guid hob to record

  // VAR_ADDED type variable info.

  // Note that as the resource of PEI phase is limited, only store the 
limited number of

  // VAR_ADDED type variables to reduce access time.

  //

  StoreInfo->IndexTable = (VARIABLE_INDEX_TABLE *) BuildGuidHob 
(, sizeof (VARIABLE_INDEX_TABLE));

  StoreInfo->IndexTable->Length  = 0;

  StoreInfo->IndexTable->StartPtr= GetStartPointer 
(VariableStoreHeader);

  StoreInfo->IndexTable->EndPtr  = GetEndPointer   
(VariableStoreHeader);

  StoreInfo->IndexTable->GoneThrough = 0;

}



 

On Mon, Oct 10, 2022 at 09:39 AM, gaoliming wrote:

Jiading: 

  Please check why NV variable data is required to be changed in PEI phase. 
This will be helpful for this issue.

 

Thanks

Liming

发件人: Jiading Zhang mailto:jdzh...@kunluntech.com.cn> > 
发送时间: 2022年10月10日 8:35
收件人: gaoliming mailto:gaolim...@byosoft.com.cn> >; 
devel@edk2.groups.io  
主题: Re: [edk2-devel] 回复: [edk2-devel] [PATCH] MdeModulePkg VariablePei: Add 
Variable state check when find variable in IndexTable.

 

Hi liming:
   Yes, NV Variable Data is not changed in PEI phase in normal case. This issue 
was found when we did a special coding, and when found variable in the 
IndexTable, it found the variable before the last changed if  didn't add the 
following condition:
  "if ((VariableHeader->State == VAR_ADDED) || (VariableHeader->State == 
(VAR_IN_DELETED_TRANSITION & VAR_ADDED)))"

Maybe our specail coding had some defect，and caused this issue.

On Fri, Sep 30, 2022 at 10:46 AM, gaoliming wrote:

Jiading:

 Hob Variable Store Info IndexTable is NULL. So, this logic doesn’t work for 
HOB variable store. NV Variable Store Info has IndexTable. When its IndexTable 
is initialized, its IndexTable will only record the variable with VAR_ADDED 
attribute. Because NV Variable Data is not changed in PEI phase, this check is 
not required by NV variable. 

 

Thanks

Liming

发件人: devel@edk2.groups.io   mailto:devel@edk2.groups.io> > 代表 Jiading Zhang
发送时间: 2022年9月28日 11:05
收件人: devel@edk2.groups.io  
主题: [edk2-devel] [PATCH] MdeModulePkg VariablePei: Add Variable state check 
when find variable in IndexTable.

 

When read a variable in PEI, it will find it first in the HOB, then find in 
variable store. When find in variable store, it will check the variable state, 
but find in HOB, it doesn't check the state, so if the variable was changed, it 
will find the obsolete variable in the HOB.

 

Signed-off-by: jdzhang mailto:jdzh...@kunluntech.com.cn> >

---

 MdeModulePkg/Universal/Variable/Pei/Variable.c | 12 +++-

 1 file changed, 7 insertions(+), 5 deletions(-)

 

diff --git a/MdeModulePkg/Universal/Variable/Pei/Variable.c 
b/MdeModulePkg/Universal/Variable/Pei/Variable.c

index 26a4c73b45..dffbd8cdb1 100644

--- a/MdeModulePkg/Universal/Variable/Pei/Variable.c

+++ b/MdeModulePkg/Universal/Variable/Pei/Variable.c

@@ -866,11 +866,13 @@ FindVariableEx (

   Offset  += IndexTable->Index[Index];

   MaxIndex = (VARIABLE_HEADER *)((UINT8 *)IndexTable->StartPtr + Offset);

   GetVariableHeader (StoreInfo, MaxIndex, );

-  if (CompareWithValidVariable (StoreInfo, MaxIndex, VariableHeader, 
VariableName, VendorGuid, PtrTrack) == EFI_SUCCESS) {

-if (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & VAR_ADDED)) {

-  InDeletedVariable = PtrTrack->CurrPtr;

-} else {

-  return 

回复: [edk2-devel] 回复: edk2-devel] [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II

[gaoliming via groups.io]

Chao:

 

I create PR https://github.com/tianocore/edk2/pull/3474 to merge this patch 
set. 

 

Thanks

Liming

发件人: devel@edk2.groups.io  代表 Chao Li
发送时间: 2022年10月13日 9:55
收件人: "gaoliming" 
抄送: devel@edk2.groups.io; "Ray_Ni" ; "Michael_D_Kinney" 
; "Guomin_Jiang" ; 
"Wei6_Xu" ; "Maciej_Rabeda" ; 
"Jiaxin_Wu" ; "Jiewen_Yao" ; 
"Jian_J_Wang" ; "Xiaoyu_Lu" ; 
"Zhiguang_Liu" ; "Zhichao_Gao" ; 
"Bob_Feng" ; "Yuwei_Chen" 
主题: Re: [edk2-devel] 回复: edk2-devel] [PATCH v3 00/34] Add a new architecture 
called LoongArch in EDK II

 

Liming,

Thank you. If EDK2 have merged new commit, I will rebase the PR in a few days. 
Please let me know if you have any questions.

 


Thanks,
Chao


On 10月 12 2022, at 8:20 早上, "gaoliming" mailto:gaolim...@byosoft.com.cn> > wrote:

Chao:

 

 I will check this PR, and merge it this week if no other comment.

 

 

 

Thanks

 

Liming

 

发件人: devel@edk2.groups.io   mailto:devel@edk2.groups.io> > 代表 Chao Li

发送时间: 2022年10月11日 11:33

收件人: devel@edk2.groups.io  ; lic...@loongson.cn 
 

抄送: " devel@edk2.groups.io   " 
mailto:devel@edk2.groups.io> >; "Ray_Ni" 
mailto:ray...@intel.com> >; "Liming_Gao" 
mailto:gaolim...@byosoft.com.cn> >; 
"Michael_D_Kinney" mailto:michael.d.kin...@intel.com> >; "Guomin_Jiang" mailto:guomin.ji...@intel.com> >; "Wei6_Xu" mailto:wei6...@intel.com> >; "Maciej_Rabeda" mailto:maciej.rab...@linux.intel.com> >; "Jiaxin_Wu" mailto:jiaxin...@intel.com> >; "Siyuan_Fu" mailto:siyuan...@intel.com> >; "Jiewen_Yao" mailto:jiewen@intel.com> >; "Jian_J_Wang" mailto:jian.j.w...@intel.com> >; "Xiaoyu_Lu" mailto:xiaoyu1...@intel.com> >; "Zhiguang_Liu" mailto:zhiguang@intel.com> >; "Zhichao_Gao" mailto:zhichao@intel.com> >; "Bob_Feng" mailto:bob.c.f...@intel.com> >; "Yuwei_Chen" mailto:yuwei.c...@intel.com> >

主题: Re: [edk2-devel] [PATCH v3 00/34] Add a new architecture called LoongArch 
in EDK II

 

 

Hi All,

I have created a PR in EDK2 repo: https://github.com/tianocore/edk2/pull/3457 

 , and all the EDK2 CI passed, so I think LoongArch port is ready to be 
enabled, I request to merge the LoongArch base code into EDK2 master branch.

 

 

 

Thanks,

Chao



On 10月 8 2022, at 12:18 中午, "Chao Li" https://link.getmailspring.com/link/88a9d77b-7f20-48bc-8dd5-ffe005e0f...@getmailspring.com/1?redirect=mailto%3Alichao%40loongson.cn=ZGV2ZWxAZWRrMi5ncm91cHMuaW8%3D>
 > wrote:

Hi All,

I have updated LoongArch repo, the CI has passed, please check again:

https://dev.azure.com/kilaterlee/LoongArch_edk2/_build/results?buildId=77=results

 

 

 

 

Thanks,

Chao



 

On 10月 1 2022, at 8:54 早上, "Chao Li" https://link.getmailspring.com/link/88a9d77b-7f20-48bc-8dd5-ffe005e0f...@getmailspring.com/3?redirect=mailto%3Alichao%40loongson.cn=ZGV2ZWxAZWRrMi5ncm91cHMuaW8%3D>
 > wrote:

Hi All,

Today, all of LoongArch patches have been approved, a big thank you to all the 
maintainers!

 

 

I have updated the LoongArch code repo to the EDK2 latest commit, applied the 
LoongArch patches based on it, and CI passed.

 

 

LoongArch repo URL: https://github.com/loongson/edk2/tree/LoongArch 

 

CI results: 
https://dev.azure.com/kilaterlee/LoongArch_edk2/_build/results?buildId=75 

 =results

 

 

I think the LoongArch port is ready to merge into the EDK2 master branch, if so 
please help me merge them. Please let me know if something should I do next.

 

 

--

Thanks,

Chao

 

 

> -原始邮件-

> 发件人: "Chao Li"  
>  >

> 发送时间:2022-09-27 19:13:20 (星期二)

> 收件人: devel@edk2.groups.io 
> 
>  

> 抄送: "Ray Ni"  
>  >, "Liming Gao"  

Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions

[Chang, Abner via groups.io]

[AMD Official Use Only - General]



> -Original Message-
> From: Sunil V L 
> Sent: Friday, October 14, 2022 12:29 AM
> To: Chang, Abner 
> Cc: devel@edk2.groups.io; Michael D Kinney ;
> Liming Gao ; Zhiguang Liu
> 
> Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34]
> MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> On Thu, Oct 13, 2022 at 12:40:14PM +, Chang, Abner wrote:
> > [AMD Official Use Only - General]
> >
> >
> >
> > > -Original Message-
> > > From: devel@edk2.groups.io  On Behalf Of Sunil
> > > V L via groups.io
> > > Sent: Thursday, October 13, 2022 5:58 PM
> > > To: devel@edk2.groups.io
> > > Cc: Michael D Kinney ; Liming Gao
> > > ; Zhiguang Liu 
> > > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34]
> MdePkg:
> > > Add RISCV_EFI_BOOT_PROTOCOL related definitions
> > >
> > > Caution: This message originated from an External Source. Use proper
> > > caution when opening attachments, clicking links, or responding.
> > >
> > >
> > > REF:
> > >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.
> > >
> tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Cabne
> r.
> > >
> chang%40amd.com%7C0df18d1274f04083208208daad018bc2%7C3dd8961fe4
> 8
> > >
> 84e608e11a82d994e183d%7C0%7C0%7C638012519406523318%7CUnknown%
> > >
> 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> wiL
> > >
> CJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=%2Bynu9ig0EeeuMDr5V
> 0F
> > > ON3iY1p4nrTdb77O0j8SGkxs%3Dreserved=0
> > >
> > > RISC-V UEFI based platforms need to support
> RISCV_EFI_BOOT_PROTOCOL.
> > > Add this protocol GUID definition and the header file required.
> > >
> > > Cc: Michael D Kinney 
> > > Cc: Liming Gao 
> > > Cc: Zhiguang Liu 
> > > Signed-off-by: Sunil V L 
> > > ---
> > >  MdePkg/MdePkg.dec   |  6 
> > >  MdePkg/Include/Protocol/RiscVBootProtocol.h | 32
> > > +
> > >  2 files changed, 38 insertions(+)
> > >  create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h
> > >
> > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> > > f1ebf9e251c1..8f1bcfdc3e97 100644
> > > --- a/MdePkg/MdePkg.dec
> > > +++ b/MdePkg/MdePkg.dec
> > > @@ -1915,6 +1915,12 @@ [Protocols]
> > >## Include/Protocol/ShellDynamicCommand.h
> > >gEfiShellDynamicCommandProtocolGuid  = { 0x3c7200e9, 0x005f,
> > > 0x4ea4, {0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }}
> > >
> > > +  #
> > > +  # Protocols defined for RISC-V systems  #  ##
> > > + Include/Protocol/RiscVBootProtocol.h
> > > +  gRiscVEfiBootProtocolGuid  = { 0xccd15fec, 0x6f73, 0x4eec, {
> > > + 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
> > > +
> > >  #
> > >  # [Error.gEfiMdePkgTokenSpaceGuid]
> > >  #   0x8001 | Invalid value provided.
> > > diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h
> > > b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> > > new file mode 100644
> > > index ..cb94f61cd46c
> > > --- /dev/null
> > > +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> > > @@ -0,0 +1,32 @@
> > > +/** @file
> > > +  RISC-V Boot Protocol mandatory for RISC-V UEFI platforms.
> > > +
> > > +  Specification available at
> > > +
> > I found here are some whitespaces in the patch. You can check it again.
> > And I can't apply this patch on edk2 master. Is your edk2-staging branch
> rebase to edk2 master?
> 
> Thanks Abner. Please use git am with --quoted-cr=nowarn and --keep-cr
> arguments.
It is failed to applied because line #1915 indicated in the patch is not the 
same as #1915 in MdePkg.dec,  that should be at line #1919. You can rebase your 
staging to the edk2 master. I am thinking that why not just send your patch 
against edk2 repo? 

Thanks
Abner

> 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fww
> w.mail-
> archive.com%2Fdevel%40edk2.groups.io%2Fmsg47612.htmldata=05%
> 7C01%7CAbner.Chang%40amd.com%7C8ca08a585d004b36851908daad3817f4
> %7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63801275368221040
> 4%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzI
> iLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=Ezgh
> Mq6QjvgIX8QBSnNJcqLOTNR51M91ZzqL4Nivh2E%3Dreserved=0
> 
> Thanks
> Sunil


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Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions

[Chang, Abner via groups.io]

[AMD Official Use Only - General]



> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sunil V L via
> groups.io
> Sent: Thursday, October 13, 2022 5:58 PM
> To: devel@edk2.groups.io
> Cc: Michael D Kinney ; Liming Gao
> ; Zhiguang Liu 
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg:
> Add RISCV_EFI_BOOT_PROTOCOL related definitions
> 
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.
> tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Cabner.
> chang%40amd.com%7C0df18d1274f04083208208daad018bc2%7C3dd8961fe48
> 84e608e11a82d994e183d%7C0%7C0%7C638012519406523318%7CUnknown%
> 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=%2Bynu9ig0EeeuMDr5V0F
> ON3iY1p4nrTdb77O0j8SGkxs%3Dreserved=0
> 
> RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
> Add this protocol GUID definition and the header file required.
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Sunil V L 
> ---
>  MdePkg/MdePkg.dec   |  6 
>  MdePkg/Include/Protocol/RiscVBootProtocol.h | 32 +
>  2 files changed, 38 insertions(+)
>  create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h
> 
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> f1ebf9e251c1..8f1bcfdc3e97 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -1915,6 +1915,12 @@ [Protocols]
>## Include/Protocol/ShellDynamicCommand.h
>gEfiShellDynamicCommandProtocolGuid  = { 0x3c7200e9, 0x005f, 0x4ea4,
> {0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }}
> 
> +  #
> +  # Protocols defined for RISC-V systems  #  ##
> + Include/Protocol/RiscVBootProtocol.h
> +  gRiscVEfiBootProtocolGuid  = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83,
> + 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
> +
>  #
>  # [Error.gEfiMdePkgTokenSpaceGuid]
>  #   0x8001 | Invalid value provided.
> diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h
> b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> new file mode 100644
> index ..cb94f61cd46c
> --- /dev/null
> +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> @@ -0,0 +1,32 @@
> +/** @file
> +  RISC-V Boot Protocol mandatory for RISC-V UEFI platforms.
> +

You can have  "@par Revision Reference:" for the reference to spec.

> +  Specification available at
> +
> + https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> + ub.com%2Friscv-non-isa%2Friscv-
> uefidata=05%7C01%7Cabner.chang%40a
> +
> md.com%7C0df18d1274f04083208208daad018bc2%7C3dd8961fe4884e608e11
> a82d99
> +
> 4e183d%7C0%7C0%7C638012519406523318%7CUnknown%7CTWFpbGZsb3d8e
> yJWIjoiMC
> +
> 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C
> %7C%
> +
> 7Csdata=f2SuwtirAU08pL2MlMris2XmdKkf6OH1muIG%2FPhmH5M%3D&
> amp;rese
> + rved=0
> +
> +  Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> + reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef RISCV_BOOT_PROTOCOL_H_
> +#define RISCV_BOOT_PROTOCOL_H_
> +
> +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL;
> +
> +#define RISCV_EFI_BOOT_PROTOCOL_REVISION  0x0001 #define
> +RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \
> +RISCV_EFI_BOOT_PROTOCOL_REVISION
> +
> +typedef EFI_STATUS
"EFI_STATUS " in the new line for the consistent coding style with other files.

After you fix that: Acked-by: Abner Chang 
Abner

> +(EFIAPI *EFI_GET_BOOT_HARTID)(
> +  IN RISCV_EFI_BOOT_PROTOCOL   *This,
> +  OUT UINTN*BootHartId
> +  );
> +
> +typedef struct _RISCV_EFI_BOOT_PROTOCOL {
> +  UINT64 Revision;
> +  EFI_GET_BOOT_HARTIDGetBootHartId;
> +} RISCV_EFI_BOOT_PROTOCOL;
> +
> +#endif
> --
> 2.25.1
> 
> 
> 
> 
> 


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Re: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy device path

[Dionna Glaze via groups.io]

Hi Abdul, I'm not a maintainer, just a contributor. I thought I'd pop
in with an observation though. I'm not seeing any diffs in these
emails. I'm not going to click a suspicious-looking link either.
Likely other folks have the same reservation. Have you read the
contributor guidelines on how to send in patches?

https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process

On Thu, Oct 13, 2022 at 8:12 AM Attar, AbdulLateef (Abdul Lateef) via
groups.io  wrote:
>
> [Public]
>
> Review please
>
> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Attar, 
> AbdulLateef (Abdul Lateef) via groups.io
> Sent: 16 September 2022 12:58
> To: devel@edk2.groups.io; Eric Dong ; Liming Gao 
> 
> Subject: Re: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
> device path
>
> [Public]
>
> Caution: This message originated from an External Source. Use proper caution 
> when opening attachments, clicking links, or responding.
>
>
> [Public]
>
> Hello Maintainers, Reviewers,
> Could you please review the patch?
> Thanks
> AbduL
>
> -Original Message-
> From: Attar, AbdulLateef (Abdul Lateef)
> Sent: 13 July 2022 09:49
> To: 'devel@edk2.groups.io' ; 'Eric Dong' 
> ; 'Liming Gao' 
> Subject: RE: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
> device path
>
> Maintainers, Reviewers,
>  please review the patch.
> Thanks
> AbduL
>
>
> -Original Message-
> From: Attar, AbdulLateef (Abdul Lateef)
> Sent: 25 April 2022 12:45
> To: devel@edk2.groups.io; Eric Dong ; Liming Gao 
> 
> Subject: RE: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
> device path
>
> Hi,
>Please review the patch.
> Thanks
> AbduL
>
> -Original Message-
> From: Attar, AbdulLateef (Abdul Lateef) 
> Sent: 05 April 2022 11:25
> To: devel@edk2.groups.io; Attar, AbdulLateef (Abdul Lateef) 
> ; Eric Dong ; Liming Gao 
> 
> Subject: RE: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
> device path
>
> [Public]
>
> Hi,
>Could you please review the patch?
> Thanks
> AbduL
>
> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Abdul Lateef 
> Attar via groups.io
> Sent: 15 March 2022 10:16
> To: devel@edk2.groups.io
> Cc: Eric Dong ; Liming Gao 
> Subject: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
> device path
>
> [CAUTION: External Email]
>
> (Resending patch with [edk2-platforms] prefix with correct emailid).
> GCC compiler puts the DevicePath PCDs to the read-only section. During boot 
> if try to process the device path after PtrGetPtr it throws a page fault 
> exception.
>
> Hence making a local copy using DuplicateDevicePath() to avoid the page fault 
> exception.
>
> REF : 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fabdattar%2Fedk2-platforms%2Ftree%2FBoardModulePkgdata=05%7C01%7CAbdulLateef.Attar%40amd.com%7C8ed1e10f30a44c51ed8808da97e873c5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637989321879784020%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=GL91Bvyavwj0eK%2F81WXVp7LDVSu2MHJudT%2BdNIa99jU%3Dreserved=0
>
> Cc: Eric Dong 
> Cc: Liming Gao 
>
> Abdul Lateef Attar (1):
>   BoardModulePkg: Copy device path before processing
>
>  Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c | 19 
> ++-
>  1 file changed, 14 insertions(+), 5 deletions(-)
>
> --
> 2.25.1
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> 
>
>


-- 
-Dionna Glaze, PhD (she/her)


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Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 06/34] OvmfPkg/PlatformInitLib: Add support for RISC-V

[Sunil V L]

On Thu, Oct 13, 2022 at 02:58:17PM +, Chang, Abner wrote:
> [AMD Official Use Only - General]
> 
> Hi Sunil,
> This file is originally from RISC-V FdtPeim.c. Please just keep HPE copyright 
> because the difference between this one and the original one is the header 
> file reference for the build and the correction of DEBUG macro. Or you can 
> separate this this commit into two commits, one is the original file another 
> is the changes made by Ventana.
> 
> I have no problem with the code logic by the way. 
> Thanks
> Abner 
Thanks Abner. Again I missed updating it. I will just keep HPE.

Thanks
Sunil


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Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34] MdePkg/BaseLib: RISC-V: Add few more helper functions

[Sunil V L]

On Thu, Oct 13, 2022 at 02:10:49PM +, Chang, Abner wrote:
> [AMD Official Use Only - General]
> 
> 
> 
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of Sunil V L
> > via groups.io
> > Sent: Thursday, October 13, 2022 5:58 PM
> > To: devel@edk2.groups.io
> > Cc: Michael D Kinney ; Liming Gao
> > ; Zhiguang Liu ; Daniel
> > Schaefer 
> > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34]
> > MdePkg/BaseLib: RISC-V: Add few more helper functions
> > 
> > Caution: This message originated from an External Source. Use proper
> > caution when opening attachments, clicking links, or responding.
> > 
> > 
> > REF:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Ca
> > bner.chang%40amd.com%7Cb23d246aae8843c15cd108daad018f1b%7C3dd89
> > 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519458082377%7CUnkn
> > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=Kflz7rvGivG00Ij
> > 6thrbhdf%2Bd1hVU7wBxEi45P6Ti0k%3Dreserved=0
> > 
> > Few of the basic helper functions required for any RISC-V CPU were added in
> > edk2-platforms. To support qemu virt, they need to be added in BaseLib.
> > 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Daniel Schaefer 
> > Signed-off-by: Sunil V L 
> > ---
> >  MdePkg/Library/BaseLib/BaseLib.inf|  2 +
> >  MdePkg/Include/Library/BaseLib.h  | 50 +
> >  MdePkg/Library/BaseLib/RiscV64/CpuScratch.S   | 31 +++
> >  MdePkg/Library/BaseLib/RiscV64/ReadTimer.S| 24 +
> >  .../Library/BaseLib/RiscV64/RiscVInterrupt.S  | 53 +--
> >  5 files changed, 156 insertions(+), 4 deletions(-)  create mode 100644
> > MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> > 
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> > b/MdePkg/Library/BaseLib/BaseLib.inf
> > index 6be5be9428f2..86d7bb080971 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -401,6 +401,8 @@ [Sources.RISCV64]
> >RiscV64/RiscVCpuPause.S   | GCC
> >RiscV64/RiscVInterrupt.S  | GCC
> >RiscV64/FlushCache.S  | GCC
> > +  RiscV64/CpuScratch.S  | GCC
> > +  RiscV64/ReadTimer.S   | GCC
> > 
> >  [Packages]
> >MdePkg/MdePkg.dec
> > diff --git a/MdePkg/Include/Library/BaseLib.h
> > b/MdePkg/Include/Library/BaseLib.h
> > index a6f9a194ef1c..9724b84eef89 100644
> > --- a/MdePkg/Include/Library/BaseLib.h
> > +++ b/MdePkg/Include/Library/BaseLib.h
> > @@ -150,6 +150,56 @@ typedef struct {
> > 
> >  #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
> > 
> > +VOID
> > +  RiscVSetSupervisorScratch (
> > + UINT64
> > + );
> > +
> > +UINT64
> > +RiscVGetSupervisorScratch (
> > +  VOID
> > +  );
> > +
> > +VOID
> > +  RiscVSetSupervisorStvec (
> > +   UINT64
> > +   );
> > +
> > +UINT64
> > +RiscVGetSupervisorStvec (
> > +  VOID
> > +  );
> > +
> > +UINT64
> > +RiscVGetSupervisorTrapCause (
> > +  VOID
> > +  );
> > +
> > +VOID
> > +  RiscVSetSupervisorAddressTranslationRegister (
> > +UINT64
> > +);
> > +
> > +UINT64
> > +RiscVReadTimer (
> > +  VOID
> > +  );
> > +
> > +VOID
> > +RiscVEnableTimerInterrupt (
> > +  VOID
> > +  );
> > +
> > +VOID
> > +RiscVDisableTimerInterrupt (
> > +  VOID
> > +  );
> > +
> > +VOID
> > +RiscVClearPendingTimerInterrupt (
> > +  VOID
> > +  );
> > +
> >  #endif // defined (MDE_CPU_RISCV64)
> > 
> >  //
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
> > b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
> > new file mode 100644
> > index ..dd7adc21eb07
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
> > @@ -0,0 +1,31 @@
> > +//-
> > +-
> > +//
> > +// CPU scratch register related functions for RISC-V // // Copyright
> > +(c) 2020, Hewlett Packard Enterprise Development LP. All rights
> > +reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent //
> > +//-
> > +-
> > +
> > +#include 
> > +
> > +.data
> > +.align 3
> > +.section .text
> > +
> > +//
> > +// Set Supervisor mode scratch.
> > +// @param a0 : Value set to Supervisor mode scratch // ASM_FUNC
> > +(RiscVSetSupervisorScratch)
> > +csrrw a1, CSR_SSCRATCH, a0
> > +ret
> > +
> > +//
> > +// Get Supervisor mode scratch.
> > +// @retval a0 : Value in Supervisor mode scratch // ASM_FUNC
> > +(RiscVGetSupervisorScratch)
> > +csrr a0, CSR_SSCRATCH
> > +ret
> > diff --git 

Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34] MdePkg/Register: Add register definition header files for RISC-V

[Sunil V L]

On Thu, Oct 13, 2022 at 12:59:32PM +, Chang, Abner wrote:
> [AMD Official Use Only - General]
> 
> 
> 
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of Sunil V L
> > via groups.io
> > Sent: Thursday, October 13, 2022 5:58 PM
> > To: devel@edk2.groups.io
> > Cc: Daniel Schaefer ; Michael D Kinney
> > ; Liming Gao ;
> > Zhiguang Liu 
> > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34]
> > MdePkg/Register: Add register definition header files for RISC-V
> > 
> > Caution: This message originated from an External Source. Use proper
> > caution when opening attachments, clicking links, or responding.
> > 
> > 
> > REF:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Ca
> > bner.chang%40amd.com%7C7e426705a0a5494fddb608daad0188ff%7C3dd89
> > 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519360901317%7CUnkn
> > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=brw9id8sl20kW
> > gKGn0ltbrgPxdRwNZvA2nOCX3CAidU%3Dreserved=0
> > 
> > Add register definitions and access routines for RISC-V. These headers are
> > leveraged from opensbi repo.
> > 
> > Cc: Daniel Schaefer 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Signed-off-by: Sunil V L 
> > ---
> >  .../Include/Register/RiscV64/RiscVEncoding.h  | 125 ++
> >  MdePkg/Include/Register/RiscV64/RiscVImpl.h   |  25 
> >  2 files changed, 150 insertions(+)
> >  create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> >  create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > 
> > diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> > b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> > new file mode 100644
> > index ..434436b37fcf
> > --- /dev/null
> > +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> > @@ -0,0 +1,125 @@
> > +/** @file
> > +  RISC-V CSR encodings
> > +
> > +  Copyright (c) 2019, Western Digital Corporation or its affiliates.
> > + All rights reserved.  Copyright (c) 2022, Ventana Micro Systems
> > + Inc. All rights reserved.
> > +  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef RISCV_ENCODING_H_
> > +#define RISCV_ENCODING_H_
> > +
> > +/* clang-format off */
> > +#define MSTATUS_SIE 0x0002UL
> > +#define MSTATUS_MIE 0x0008UL
> > +#define MSTATUS_SPIE_SHIFT  5
> > +#define MSTATUS_SPIE(1UL << MSTATUS_SPIE_SHIFT)
> > +#define MSTATUS_UBE 0x0040UL
> > +#define MSTATUS_MPIE0x0080UL
> > +#define MSTATUS_SPP_SHIFT   8
> > +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
> > +#define MSTATUS_MPP_SHIFT   11
> > +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
> > +
> > +#define SSTATUS_SIE MSTATUS_SIE
> > +#define SSTATUS_SPIE_SHIFT  MSTATUS_SPIE_SHIFT
> > +#define SSTATUS_SPIEMSTATUS_SPIE
> > +#define SSTATUS_SPP_SHIFT   MSTATUS_SPP_SHIFT
> > +#define SSTATUS_SPP MSTATUS_SPP
> > +
> > +#define IRQ_S_SOFT1
> > +#define IRQ_VS_SOFT   2
> > +#define IRQ_M_SOFT3
> > +#define IRQ_S_TIMER   5
> > +#define IRQ_VS_TIMER  6
> > +#define IRQ_M_TIMER   7
> > +#define IRQ_S_EXT 9
> > +#define IRQ_VS_EXT10
> > +#define IRQ_M_EXT 11
> > +#define IRQ_S_GEXT12
> > +#define IRQ_PMU_OVF   13
> > +
> > +#define MIP_SSIP(1UL << IRQ_S_SOFT)
> > +#define MIP_VSSIP   (1UL << IRQ_VS_SOFT)
> > +#define MIP_MSIP(1UL << IRQ_M_SOFT)
> > +#define MIP_STIP(1UL << IRQ_S_TIMER)
> > +#define MIP_VSTIP   (1UL << IRQ_VS_TIMER)
> > +#define MIP_MTIP(1UL << IRQ_M_TIMER)
> > +#define MIP_SEIP(1UL << IRQ_S_EXT)
> > +#define MIP_VSEIP   (1UL << IRQ_VS_EXT)
> > +#define MIP_MEIP(1UL << IRQ_M_EXT)
> > +#define MIP_SGEIP   (1UL << IRQ_S_GEXT)
> > +#define MIP_LCOFIP  (1UL << IRQ_PMU_OVF)
> > +
> > +#define SIP_SSIP  MIP_SSIP
> > +#define SIP_STIP  MIP_STIP
> > +
> > +#define PRV_U  0UL
> > +#define PRV_S  1UL
> > +#define PRV_M  3UL
> > +
> > +#define SATP64_MODE  0xF000ULL #define SATP64_ASID
> > +0x0000ULL
> > +#define SATP64_PPN   0x0FFFULL
> > +
> > +#define SATP_MODE_OFF   0UL
> > +#define SATP_MODE_SV32  1UL
> > +#define SATP_MODE_SV39  8UL
> > +#define SATP_MODE_SV48  9UL
> > +#define SATP_MODE_SV57  10UL
> > +#define SATP_MODE_SV64  11UL
> > +
> > +#define SATP_MODE  SATP64_MODE
> > +
> > +/* = User-level CSRs = */
> Would you like to have the consistent comment style as /* Supervisor 
> Configuration */ in below (without the equal signs)? Thus the comments are in 
> the same style in this file.
> You can fix this in the next version.

Sure. Will update the comments. Thanks!
> 
> Not the reviewer or maintainer, however Acked-by: Abner Chang 
> 
> Thanks
> Abner


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Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions

[Sunil V L]

On Thu, Oct 13, 2022 at 12:40:14PM +, Chang, Abner wrote:
> [AMD Official Use Only - General]
> 
> 
> 
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of Sunil V L via
> > groups.io
> > Sent: Thursday, October 13, 2022 5:58 PM
> > To: devel@edk2.groups.io
> > Cc: Michael D Kinney ; Liming Gao
> > ; Zhiguang Liu 
> > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg:
> > Add RISCV_EFI_BOOT_PROTOCOL related definitions
> > 
> > Caution: This message originated from an External Source. Use proper caution
> > when opening attachments, clicking links, or responding.
> > 
> > 
> > REF:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.
> > tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Cabner.
> > chang%40amd.com%7C0df18d1274f04083208208daad018bc2%7C3dd8961fe48
> > 84e608e11a82d994e183d%7C0%7C0%7C638012519406523318%7CUnknown%
> > 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> > CJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=%2Bynu9ig0EeeuMDr5V0F
> > ON3iY1p4nrTdb77O0j8SGkxs%3Dreserved=0
> > 
> > RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
> > Add this protocol GUID definition and the header file required.
> > 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Signed-off-by: Sunil V L 
> > ---
> >  MdePkg/MdePkg.dec   |  6 
> >  MdePkg/Include/Protocol/RiscVBootProtocol.h | 32 +
> >  2 files changed, 38 insertions(+)
> >  create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h
> > 
> > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> > f1ebf9e251c1..8f1bcfdc3e97 100644
> > --- a/MdePkg/MdePkg.dec
> > +++ b/MdePkg/MdePkg.dec
> > @@ -1915,6 +1915,12 @@ [Protocols]
> >## Include/Protocol/ShellDynamicCommand.h
> >gEfiShellDynamicCommandProtocolGuid  = { 0x3c7200e9, 0x005f, 0x4ea4,
> > {0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }}
> > 
> > +  #
> > +  # Protocols defined for RISC-V systems  #  ##
> > + Include/Protocol/RiscVBootProtocol.h
> > +  gRiscVEfiBootProtocolGuid  = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83,
> > + 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
> > +
> >  #
> >  # [Error.gEfiMdePkgTokenSpaceGuid]
> >  #   0x8001 | Invalid value provided.
> > diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h
> > b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> > new file mode 100644
> > index ..cb94f61cd46c
> > --- /dev/null
> > +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> > @@ -0,0 +1,32 @@
> > +/** @file
> > +  RISC-V Boot Protocol mandatory for RISC-V UEFI platforms.
> > +
> > +  Specification available at
> > +
> I found here are some whitespaces in the patch. You can check it again.
> And I can't apply this patch on edk2 master. Is your edk2-staging branch 
> rebase to edk2 master?

Thanks Abner. Please use git am with --quoted-cr=nowarn and --keep-cr
arguments.

https://www.mail-archive.com/devel@edk2.groups.io/msg47612.html

Thanks
Sunil


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Re: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy device path

[Attar, AbdulLateef (Abdul Lateef) via groups.io]

[Public]

Review please

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Attar, 
AbdulLateef (Abdul Lateef) via groups.io
Sent: 16 September 2022 12:58
To: devel@edk2.groups.io; Eric Dong ; Liming Gao 

Subject: Re: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
device path

[Public]

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


[Public]

Hello Maintainers, Reviewers,
Could you please review the patch?
Thanks
AbduL

-Original Message-
From: Attar, AbdulLateef (Abdul Lateef)
Sent: 13 July 2022 09:49
To: 'devel@edk2.groups.io' ; 'Eric Dong' 
; 'Liming Gao' 
Subject: RE: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
device path

Maintainers, Reviewers,
 please review the patch.
Thanks
AbduL


-Original Message-
From: Attar, AbdulLateef (Abdul Lateef)
Sent: 25 April 2022 12:45
To: devel@edk2.groups.io; Eric Dong ; Liming Gao 

Subject: RE: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
device path

Hi,
   Please review the patch.
Thanks
AbduL

-Original Message-
From: Attar, AbdulLateef (Abdul Lateef) 
Sent: 05 April 2022 11:25
To: devel@edk2.groups.io; Attar, AbdulLateef (Abdul Lateef) 
; Eric Dong ; Liming Gao 

Subject: RE: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy 
device path

[Public]

Hi,
   Could you please review the patch?
Thanks
AbduL

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Abdul Lateef 
Attar via groups.io
Sent: 15 March 2022 10:16
To: devel@edk2.groups.io
Cc: Eric Dong ; Liming Gao 
Subject: [edk2-devel] [edk2-platforms PATCH v1 0/1] BoardModulePkg: Copy device 
path

[CAUTION: External Email]

(Resending patch with [edk2-platforms] prefix with correct emailid).
GCC compiler puts the DevicePath PCDs to the read-only section. During boot if 
try to process the device path after PtrGetPtr it throws a page fault exception.

Hence making a local copy using DuplicateDevicePath() to avoid the page fault 
exception.

REF : 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fabdattar%2Fedk2-platforms%2Ftree%2FBoardModulePkgdata=05%7C01%7CAbdulLateef.Attar%40amd.com%7C8ed1e10f30a44c51ed8808da97e873c5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637989321879784020%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=GL91Bvyavwj0eK%2F81WXVp7LDVSu2MHJudT%2BdNIa99jU%3Dreserved=0

Cc: Eric Dong 
Cc: Liming Gao 

Abdul Lateef Attar (1):
  BoardModulePkg: Copy device path before processing

 Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c | 19 
++-
 1 file changed, 14 insertions(+), 5 deletions(-)

--
2.25.1














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[edk2-devel] [PATCH] Pkg-Module: Remove Non-ASCII Characters

[SteveX Li]

It would cause compiler error.

Signed-off-by: SteveX Li 
---
 EmbeddedPkg/GdbStub/GdbStubInternal.h| 32 
 EmbeddedPkg/Include/Protocol/UsbDevice.h |  2 +-
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/EmbeddedPkg/GdbStub/GdbStubInternal.h 
b/EmbeddedPkg/GdbStub/GdbStubInternal.h
index 9c3929c812..5eaff61d83 100644
--- a/EmbeddedPkg/GdbStub/GdbStubInternal.h
+++ b/EmbeddedPkg/GdbStub/GdbStubInternal.h
@@ -322,7 +322,7 @@ SendNotSupported (
   VOID
   );
 
-/** ‘p n’
+/** 'p n'
  Reads the n-th register's value into an output buffer and sends it as a packet
  @param SystemContext   Register content at time of the exception
  @param InBufferThis is the input buffer received from gdb 
server
@@ -333,7 +333,7 @@ ReadNthRegister (
   INCHAR8   *InBuffer
   );
 
-/** ‘g’
+/** 'g'
  Reads the general registers into an output buffer  and sends it as a packet
  @param SystemContext   Register content at time of the exception
  **/
@@ -343,7 +343,7 @@ ReadGeneralRegisters (
   INEFI_SYSTEM_CONTEXT  SystemContext
   );
 
-/** ‘P n...=r...’
+/** 'P n...=r...'
  Writes the new value of n-th register received into the input buffer to the 
n-th register
  @param SystemContext   Register content at time of the exception
  @param InBufferThis is the input buffer received from gdb 
server
@@ -355,7 +355,7 @@ WriteNthRegister (
   INCHAR8   *InBuffer
   );
 
-/** ‘G XX...’
+/** 'G XX...'
  Writes the new values received into the input buffer to the general registers
  @param SystemContext   Register content at time of the 
exception
  @param InBufferPointer to the input buffer received 
from gdb server
@@ -368,7 +368,7 @@ WriteGeneralRegisters (
   INCHAR8   *InBuffer
   );
 
-/** ‘m addr,length ’
+/** 'm addr,length '
  Find the Length of the area to read and the start address. Finally, pass them 
to
  another function, TransferFromMemToOutBufAndSend, that will read from that 
memory space and
  send it as a packet.
@@ -381,7 +381,7 @@ ReadFromMemory (
   IN  CHAR8  *PacketData
   );
 
-/** ‘M addr,length :XX...’
+/** 'M addr,length :XX...'
  Find the Length of the area in bytes to write and the start address. Finally, 
pass them to
  another function, TransferFromInBufToMem, that will write to that memory 
space the info in
  the input buffer.
@@ -394,7 +394,7 @@ WriteToMemory (
   IN CHAR8  *PacketData
   );
 
-/** ‘c [addr ]’
+/** 'c [addr ]'
  Continue. addr is Address to resume. If addr is omitted, resume at current
  Address.
 
@@ -409,7 +409,7 @@ ContinueAtAddress (
   IN  CHAR8   *PacketData
   );
 
-/** ‘s [addr ]’
+/** 's [addr ]'
  Single step. addr is the Address at which to resume. If addr is omitted, 
resume
  at same Address.
 
@@ -444,10 +444,10 @@ RemoveSingleStep (
   );
 
 /**
-  ‘Z1, [addr], [length]’
-  ‘Z2, [addr], [length]’
-  ‘Z3, [addr], [length]’
-  ‘Z4, [addr], [length]’
+  'Z1, [addr], [length]'
+  'Z2, [addr], [length]'
+  'Z3, [addr], [length]'
+  'Z4, [addr], [length]'
 
   Insert hardware breakpoint/watchpoint at address addr of size length
 
@@ -463,10 +463,10 @@ InsertBreakPoint (
   );
 
 /**
-  ‘z1, [addr], [length]’
-  ‘z2, [addr], [length]’
-  ‘z3, [addr], [length]’
-  ‘z4, [addr], [length]’
+  'z1, [addr], [length]'
+  'z2, [addr], [length]'
+  'z3, [addr], [length]'
+  'z4, [addr], [length]'
 
   Remove hardware breakpoint/watchpoint at address addr of size length
 
diff --git a/EmbeddedPkg/Include/Protocol/UsbDevice.h 
b/EmbeddedPkg/Include/Protocol/UsbDevice.h
index b299ee10a7..b07f459afa 100644
--- a/EmbeddedPkg/Include/Protocol/UsbDevice.h
+++ b/EmbeddedPkg/Include/Protocol/UsbDevice.h
@@ -83,7 +83,7 @@ EFI_STATUS
 first interface descriptor. If there are
 additional interfaces, their interface
 descriptor and endpoint descriptors follow the
-first interface’s endpoint descriptors".
+first interface's endpoint descriptors".
 
 The size of each buffer is the TotalLength
 member of the Configuration Descriptor.
-- 
2.31.1.windows.1



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Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 06/34] OvmfPkg/PlatformInitLib: Add support for RISC-V

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Hi Sunil,
This file is originally from RISC-V FdtPeim.c. Please just keep HPE copyright 
because the difference between this one and the original one is the header file 
reference for the build and the correction of DEBUG macro. Or you can separate 
this this commit into two commits, one is the original file another is the 
changes made by Ventana.

I have no problem with the code logic by the way. 
Thanks
Abner 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sunil V L
> via groups.io
> Sent: Thursday, October 13, 2022 5:58 PM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel ; Jiewen Yao
> ; Jordan Justen ; Gerd
> Hoffmann ; Daniel Schaefer 
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 06/34]
> OvmfPkg/PlatformInitLib: Add support for RISC-V
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Ca
> bner.chang%40amd.com%7C03bbd4f7f5f748c8964a08daad01988b%7C3dd896
> 1fe4884e608e11a82d994e183d%7C0%7C0%7C638012519614946969%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=PXc%2FF92%2F
> N67WFosTnDPCf%2FMGmaGVSnjUw2MXdk4Uq%2F8%3Dreserved=0
> 
> This is copied from
> edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/FdtPeim
> but added as part of library instead of a separate module.
> 
> Cc: Ard Biesheuvel 
> Cc: Jiewen Yao 
> Cc: Jordan Justen 
> Cc: Gerd Hoffmann 
> Cc: Daniel Schaefer 
> Signed-off-by: Sunil V L 
> ---
>  .../PlatformInitLib/PlatformInitLib.inf   |  9 ++-
>  OvmfPkg/Include/Library/PlatformInitLib.h |  6 ++
>  .../PlatformInitLib/RiscV64/PlatformPeiLib.c  | 73 +++
>  3 files changed, 87 insertions(+), 1 deletion(-)  create mode 100644
> OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c
> 
> diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
> b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
> index d4449e40af61..ef8675999583 100644
> --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
> +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
> @@ -19,7 +19,7 @@ [Defines]
>  #
>  # The following information is for reference only and not required by the
> build tools.
>  #
> -#  VALID_ARCHITECTURES   = IA32 X64 EBC
> +#  VALID_ARCHITECTURES   = IA32 X64 EBC RISCV64
>  #
> 
>  [Sources.IA32, Sources.X64]
> @@ -33,6 +33,9 @@ [Sources.IA32]
>  [Sources.X64]
>Ia32_X64/IntelTdx.c
> 
> +[Sources.RISCV64]
> +  RiscV64/PlatformPeiLib.c
> +
>  [Packages]
>EmbeddedPkg/EmbeddedPkg.dec
>MdeModulePkg/MdeModulePkg.dec
> @@ -58,6 +61,10 @@ [LibraryClasses.IA32, LibraryClasses.X64]
> [LibraryClasses.X64]
>TdxLib
> 
> +[LibraryClasses.RISCV64]
> +  RiscVSbiLib
> +  FdtLib
> +
>  [Pcd]
>gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> 
> diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h
> b/OvmfPkg/Include/Library/PlatformInitLib.h
> index c5234bf26d45..1b8d1fad3b49 100644
> --- a/OvmfPkg/Include/Library/PlatformInitLib.h
> +++ b/OvmfPkg/Include/Library/PlatformInitLib.h
> @@ -285,4 +285,10 @@ PlatformInitEmuVariableNvStore (
>IN VOID  *EmuVariableNvStore
>);
> 
> +EFI_STATUS
> +EFIAPI
> +PlatformPeim (
> +  VOID
> +  );
> +
>  #endif // PLATFORM_INIT_LIB_H_
> diff --git a/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c
> b/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c
> new file mode 100644
> index ..c5dbc849
> --- /dev/null
> +++ b/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c
> @@ -0,0 +1,73 @@
> +/** @file
> +The library call to pass the device tree to DXE via HOB.
> +
> +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All
> +rights reserved. Copyright (c) 2022, Ventana Micro Systems Inc. All
> +rights reserved.
> +
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +//
> + The package level header files this module uses  #include
> +
> +
> +#include 
> +#include 
> +#include  #include
> +
> +
> +#include 
> +
> +#include 
> +
> +/**
> +  @retval EFI_SUCCESSThe address of FDT is passed in HOB.
> +  EFI_UNSUPPORTEDCan't locate FDT.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformPeim (
> +  VOID
> +  )
> +{
> +  EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext;
> +  VOID*FdtPointer;
> +  VOID*Base;
> +  VOID*NewBase;
> +  UINTN   FdtSize;
> +  UINTN   FdtPages;
> +  UINT64  *FdtHobData;
> +
> +  FirmwareContext = NULL;
> +  GetFirmwareContextPointer ();
> +
> +  if (FirmwareContext == NULL) {
> +DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n",
> __FUNCTION__));
> +return 

Re: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] [edk2] [PATCH]MdeModulePkg\scsi: Coverity scan flags multiple issues in edk2-stable202205

[Michael D Kinney]

Hi Sivaparvathi ,

Thank you for the contribution.

Can you please send code review using EDK II Dev process?

https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process

I also see some CI checks are failing.  Please address those before sending 
updates.

Thanks,

Mike

From: devel@edk2.groups.io  On Behalf Of sivaparvathi C 
via groups.io
Sent: Thursday, October 13, 2022 6:15 AM
To: Kinney, Michael D ; devel@edk2.groups.io
Subject: Re: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] [edk2] 
[PATCH]MdeModulePkg\scsi: Coverity scan flags multiple issues in 
edk2-stable202205

Hi mikub...@linux.microsoft.com, 
gaolim...@byosoft.com.cn,michael.d.kin...@intel.com

Created Pull Request for edk2_Stable202205 Coverity Changes  for SCSI driver.

https://github.com/tianocore/edk2/pull/3473

Thanks,
Sivaparvathi



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Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 04/34] MdePkg: Add BaseRiscVSbiLib Library for RISC-V

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

I have no problem with these source files. Those are already verified on 
edk2-platform.

Acked-by: Abner Chang 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sunil V L
> via groups.io
> Sent: Thursday, October 13, 2022 5:58 PM
> To: devel@edk2.groups.io
> Cc: Michael D Kinney ; Liming Gao
> ; Zhiguang Liu 
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 04/34]
> MdePkg: Add BaseRiscVSbiLib Library for RISC-V
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Ca
> bner.chang%40amd.com%7Cfd6b6a96550a4e2bb93108daad01a788%7C3dd89
> 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519876960817%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=ZhtBOz4KYaE%
> 2F9YEhZhU0HXGHnlBM5aCBMpv4%2BUtHWOk%3Dreserved=0
> 
> This library is required to make SBI ecalls from the S-mode EDK2.
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Sunil V L 
> ---
>  MdePkg/MdePkg.dec |   4 +
>  MdePkg/MdePkg.dsc |   3 +
>  .../BaseRiscVSbiLib/BaseRiscVSbiLib.inf   |  25 ++
>  MdePkg/Include/Library/BaseRiscVSbiLib.h  | 127 ++
>  .../Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 227 ++
>  5 files changed, 386 insertions(+)
>  create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
>  create mode 100644 MdePkg/Include/Library/BaseRiscVSbiLib.h
>  create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c
> 
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> 8f1bcfdc3e97..1762068ffad7 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -307,6 +307,10 @@ [LibraryClasses.IA32, LibraryClasses.X64]
>##  @libraryclass  Provides function to support TDX processing.
>TdxLib|Include/Library/TdxLib.h
> 
> +[LibraryClasses.RISCV64]
> +  ##  @libraryclass  Provides function to make ecalls to SBI
> +  BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h
> +
>  [Guids]
>#
># GUID defined in UEFI2.1/UEFI2.0/EFI1.1 diff --git a/MdePkg/MdePkg.dsc
> b/MdePkg/MdePkg.dsc index cc1ac196a931..fd08122f441d 100644
> --- a/MdePkg/MdePkg.dsc
> +++ b/MdePkg/MdePkg.dsc
> @@ -188,4 +188,7 @@ [Components.ARM, Components.AARCH64]
>MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
>MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> 
> +[Components.RISCV64]
> +  MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> +
>  [BuildOptions]
> diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> new file mode 100644
> index ..d03132bf01c1
> --- /dev/null
> +++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> @@ -0,0 +1,25 @@
> +## @file
> +# RISC-V Library to call SBI ecalls
> +#
> +#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> +rights reserved. # #  SPDX-License-Identifier: BSD-2-Clause-Patent
> +# ##
> +
> +[Defines]
> +  INF_VERSION = 0x0001001b
> +  BASE_NAME   = BaseRiscVSbiLib
> +  FILE_GUID   = D742CF3D-E600-4009-8FB5-318073008508
> +  MODULE_TYPE = BASE
> +  VERSION_STRING  = 1.0
> +  LIBRARY_CLASS   = RiscVSbiLib
> +
> +[Sources]
> +  BaseRiscVSbiLib.c
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> +  BaseLib
> diff --git a/MdePkg/Include/Library/BaseRiscVSbiLib.h
> b/MdePkg/Include/Library/BaseRiscVSbiLib.h
> new file mode 100644
> index ..e9886187526a
> --- /dev/null
> +++ b/MdePkg/Include/Library/BaseRiscVSbiLib.h
> @@ -0,0 +1,127 @@
> +/** @file
> +  Library to call the RISC-V SBI ecalls
> +
> +  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights
> + reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +  @par Glossary:
> +- Hart - Hardware Thread, similar to a CPU core
> +
> +  Currently, EDK2 needs to call SBI only to set the time and to do system
> reset.
> +
> +**/
> +
> +#ifndef RISCV_SBI_LIB_H_
> +#define RISCV_SBI_LIB_H_
> +
> +#include 
> +
> +/* SBI Extension IDs */
> +#define SBI_EXT_TIME  0x54494D45
> +#define SBI_EXT_SRST  0x53525354
> +
> +/* SBI function IDs for TIME extension*/ #define
> SBI_EXT_TIME_SET_TIMER
> +0x0
> +
> +/* SBI function IDs for SRST extension */ #define SBI_EXT_SRST_RESET
> +0x0
> +
> +#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
> +#define SBI_SRST_RESET_TYPE_COLD_REBOOT  0x1 #define
> +SBI_SRST_RESET_TYPE_WARM_REBOOT  0x2
> +#define SBI_SRST_RESET_TYPE_LAST
> SBI_SRST_RESET_TYPE_WARM_REBOOT
> +
> +#define SBI_SRST_RESET_REASON_NONE 0x0
> +#define SBI_SRST_RESET_REASON_SYSFAIL  0x1
> +
> +/* SBI return error codes */
> +#define 

Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34] MdePkg/BaseLib: RISC-V: Add few more helper functions

[Chang, Abner via groups.io]

[AMD Official Use Only - General]



> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sunil V L
> via groups.io
> Sent: Thursday, October 13, 2022 5:58 PM
> To: devel@edk2.groups.io
> Cc: Michael D Kinney ; Liming Gao
> ; Zhiguang Liu ; Daniel
> Schaefer 
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34]
> MdePkg/BaseLib: RISC-V: Add few more helper functions
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Ca
> bner.chang%40amd.com%7Cb23d246aae8843c15cd108daad018f1b%7C3dd89
> 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519458082377%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=Kflz7rvGivG00Ij
> 6thrbhdf%2Bd1hVU7wBxEi45P6Ti0k%3Dreserved=0
> 
> Few of the basic helper functions required for any RISC-V CPU were added in
> edk2-platforms. To support qemu virt, they need to be added in BaseLib.
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Cc: Daniel Schaefer 
> Signed-off-by: Sunil V L 
> ---
>  MdePkg/Library/BaseLib/BaseLib.inf|  2 +
>  MdePkg/Include/Library/BaseLib.h  | 50 +
>  MdePkg/Library/BaseLib/RiscV64/CpuScratch.S   | 31 +++
>  MdePkg/Library/BaseLib/RiscV64/ReadTimer.S| 24 +
>  .../Library/BaseLib/RiscV64/RiscVInterrupt.S  | 53 +--
>  5 files changed, 156 insertions(+), 4 deletions(-)  create mode 100644
> MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
>  create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> 
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 6be5be9428f2..86d7bb080971 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -401,6 +401,8 @@ [Sources.RISCV64]
>RiscV64/RiscVCpuPause.S   | GCC
>RiscV64/RiscVInterrupt.S  | GCC
>RiscV64/FlushCache.S  | GCC
> +  RiscV64/CpuScratch.S  | GCC
> +  RiscV64/ReadTimer.S   | GCC
> 
>  [Packages]
>MdePkg/MdePkg.dec
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index a6f9a194ef1c..9724b84eef89 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -150,6 +150,56 @@ typedef struct {
> 
>  #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
> 
> +VOID
> +  RiscVSetSupervisorScratch (
> + UINT64
> + );
> +
> +UINT64
> +RiscVGetSupervisorScratch (
> +  VOID
> +  );
> +
> +VOID
> +  RiscVSetSupervisorStvec (
> +   UINT64
> +   );
> +
> +UINT64
> +RiscVGetSupervisorStvec (
> +  VOID
> +  );
> +
> +UINT64
> +RiscVGetSupervisorTrapCause (
> +  VOID
> +  );
> +
> +VOID
> +  RiscVSetSupervisorAddressTranslationRegister (
> +UINT64
> +);
> +
> +UINT64
> +RiscVReadTimer (
> +  VOID
> +  );
> +
> +VOID
> +RiscVEnableTimerInterrupt (
> +  VOID
> +  );
> +
> +VOID
> +RiscVDisableTimerInterrupt (
> +  VOID
> +  );
> +
> +VOID
> +RiscVClearPendingTimerInterrupt (
> +  VOID
> +  );
> +
>  #endif // defined (MDE_CPU_RISCV64)
> 
>  //
> diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
> b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
> new file mode 100644
> index ..dd7adc21eb07
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
> @@ -0,0 +1,31 @@
> +//-
> +-
> +//
> +// CPU scratch register related functions for RISC-V // // Copyright
> +(c) 2020, Hewlett Packard Enterprise Development LP. All rights
> +reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent //
> +//-
> +-
> +
> +#include 
> +
> +.data
> +.align 3
> +.section .text
> +
> +//
> +// Set Supervisor mode scratch.
> +// @param a0 : Value set to Supervisor mode scratch // ASM_FUNC
> +(RiscVSetSupervisorScratch)
> +csrrw a1, CSR_SSCRATCH, a0
> +ret
> +
> +//
> +// Get Supervisor mode scratch.
> +// @retval a0 : Value in Supervisor mode scratch // ASM_FUNC
> +(RiscVGetSupervisorScratch)
> +csrr a0, CSR_SSCRATCH
> +ret
> diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> new file mode 100644
> index ..bdddb67618ab
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
Hi Sunil,
Where is this code comes from? Was it written by HPE? If not then you can 
remove HPE copyright, otherwise please remove Ventana.
Thanks
Abner

> @@ -0,0 +1,24 @@
> 

Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34] MdePkg/Register: Add register definition header files for RISC-V

[Chang, Abner via groups.io]

[AMD Official Use Only - General]



> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sunil V L
> via groups.io
> Sent: Thursday, October 13, 2022 5:58 PM
> To: devel@edk2.groups.io
> Cc: Daniel Schaefer ; Michael D Kinney
> ; Liming Gao ;
> Zhiguang Liu 
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34]
> MdePkg/Register: Add register definition header files for RISC-V
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Ca
> bner.chang%40amd.com%7C7e426705a0a5494fddb608daad0188ff%7C3dd89
> 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519360901317%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=brw9id8sl20kW
> gKGn0ltbrgPxdRwNZvA2nOCX3CAidU%3Dreserved=0
> 
> Add register definitions and access routines for RISC-V. These headers are
> leveraged from opensbi repo.
> 
> Cc: Daniel Schaefer 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Sunil V L 
> ---
>  .../Include/Register/RiscV64/RiscVEncoding.h  | 125 ++
>  MdePkg/Include/Register/RiscV64/RiscVImpl.h   |  25 
>  2 files changed, 150 insertions(+)
>  create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h
>  create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h
> 
> diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> new file mode 100644
> index ..434436b37fcf
> --- /dev/null
> +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> @@ -0,0 +1,125 @@
> +/** @file
> +  RISC-V CSR encodings
> +
> +  Copyright (c) 2019, Western Digital Corporation or its affiliates.
> + All rights reserved.  Copyright (c) 2022, Ventana Micro Systems
> + Inc. All rights reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef RISCV_ENCODING_H_
> +#define RISCV_ENCODING_H_
> +
> +/* clang-format off */
> +#define MSTATUS_SIE 0x0002UL
> +#define MSTATUS_MIE 0x0008UL
> +#define MSTATUS_SPIE_SHIFT  5
> +#define MSTATUS_SPIE(1UL << MSTATUS_SPIE_SHIFT)
> +#define MSTATUS_UBE 0x0040UL
> +#define MSTATUS_MPIE0x0080UL
> +#define MSTATUS_SPP_SHIFT   8
> +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
> +#define MSTATUS_MPP_SHIFT   11
> +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
> +
> +#define SSTATUS_SIE MSTATUS_SIE
> +#define SSTATUS_SPIE_SHIFT  MSTATUS_SPIE_SHIFT
> +#define SSTATUS_SPIEMSTATUS_SPIE
> +#define SSTATUS_SPP_SHIFT   MSTATUS_SPP_SHIFT
> +#define SSTATUS_SPP MSTATUS_SPP
> +
> +#define IRQ_S_SOFT1
> +#define IRQ_VS_SOFT   2
> +#define IRQ_M_SOFT3
> +#define IRQ_S_TIMER   5
> +#define IRQ_VS_TIMER  6
> +#define IRQ_M_TIMER   7
> +#define IRQ_S_EXT 9
> +#define IRQ_VS_EXT10
> +#define IRQ_M_EXT 11
> +#define IRQ_S_GEXT12
> +#define IRQ_PMU_OVF   13
> +
> +#define MIP_SSIP(1UL << IRQ_S_SOFT)
> +#define MIP_VSSIP   (1UL << IRQ_VS_SOFT)
> +#define MIP_MSIP(1UL << IRQ_M_SOFT)
> +#define MIP_STIP(1UL << IRQ_S_TIMER)
> +#define MIP_VSTIP   (1UL << IRQ_VS_TIMER)
> +#define MIP_MTIP(1UL << IRQ_M_TIMER)
> +#define MIP_SEIP(1UL << IRQ_S_EXT)
> +#define MIP_VSEIP   (1UL << IRQ_VS_EXT)
> +#define MIP_MEIP(1UL << IRQ_M_EXT)
> +#define MIP_SGEIP   (1UL << IRQ_S_GEXT)
> +#define MIP_LCOFIP  (1UL << IRQ_PMU_OVF)
> +
> +#define SIP_SSIP  MIP_SSIP
> +#define SIP_STIP  MIP_STIP
> +
> +#define PRV_U  0UL
> +#define PRV_S  1UL
> +#define PRV_M  3UL
> +
> +#define SATP64_MODE  0xF000ULL #define SATP64_ASID
> +0x0000ULL
> +#define SATP64_PPN   0x0FFFULL
> +
> +#define SATP_MODE_OFF   0UL
> +#define SATP_MODE_SV32  1UL
> +#define SATP_MODE_SV39  8UL
> +#define SATP_MODE_SV48  9UL
> +#define SATP_MODE_SV57  10UL
> +#define SATP_MODE_SV64  11UL
> +
> +#define SATP_MODE  SATP64_MODE
> +
> +/* = User-level CSRs = */
Would you like to have the consistent comment style as /* Supervisor 
Configuration */ in below (without the equal signs)? Thus the comments are in 
the same style in this file.
You can fix this in the next version.

Not the reviewer or maintainer, however Acked-by: Abner Chang 

Thanks
Abner

> +
> +/* User Counters/Timers */
> +#define CSR_CYCLE  0xc00
> +#define CSR_TIME   0xc01
> +
> +/* = Supervisor-level CSRs = */
> +
> +/* Supervisor Trap Setup */
> +#define CSR_SSTATUS  0x100
> +#define CSR_SEDELEG  0x102
> +#define CSR_SIDELEG  0x103
> +#define CSR_SIE  0x104
> +#define CSR_STVEC0x105
> +
> +/* Supervisor Configuration */
> +#define CSR_SENVCFG  0x10a
> +
> +/* Supervisor Trap Handling */
> +#define CSR_SSCRATCH  0x140
> +#define CSR_SEPC  0x141
> +#define 

Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions

[Chang, Abner via groups.io]

[AMD Official Use Only - General]



> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sunil V L via
> groups.io
> Sent: Thursday, October 13, 2022 5:58 PM
> To: devel@edk2.groups.io
> Cc: Michael D Kinney ; Liming Gao
> ; Zhiguang Liu 
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg:
> Add RISCV_EFI_BOOT_PROTOCOL related definitions
> 
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.
> tianocore.org%2Fshow_bug.cgi%3Fid%3D4076data=05%7C01%7Cabner.
> chang%40amd.com%7C0df18d1274f04083208208daad018bc2%7C3dd8961fe48
> 84e608e11a82d994e183d%7C0%7C0%7C638012519406523318%7CUnknown%
> 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=%2Bynu9ig0EeeuMDr5V0F
> ON3iY1p4nrTdb77O0j8SGkxs%3Dreserved=0
> 
> RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
> Add this protocol GUID definition and the header file required.
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Sunil V L 
> ---
>  MdePkg/MdePkg.dec   |  6 
>  MdePkg/Include/Protocol/RiscVBootProtocol.h | 32 +
>  2 files changed, 38 insertions(+)
>  create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h
> 
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> f1ebf9e251c1..8f1bcfdc3e97 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -1915,6 +1915,12 @@ [Protocols]
>## Include/Protocol/ShellDynamicCommand.h
>gEfiShellDynamicCommandProtocolGuid  = { 0x3c7200e9, 0x005f, 0x4ea4,
> {0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }}
> 
> +  #
> +  # Protocols defined for RISC-V systems  #  ##
> + Include/Protocol/RiscVBootProtocol.h
> +  gRiscVEfiBootProtocolGuid  = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83,
> + 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
> +
>  #
>  # [Error.gEfiMdePkgTokenSpaceGuid]
>  #   0x8001 | Invalid value provided.
> diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h
> b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> new file mode 100644
> index ..cb94f61cd46c
> --- /dev/null
> +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h
> @@ -0,0 +1,32 @@
> +/** @file
> +  RISC-V Boot Protocol mandatory for RISC-V UEFI platforms.
> +
> +  Specification available at
> +
I found here are some whitespaces in the patch. You can check it again.
And I can't apply this patch on edk2 master. Is your edk2-staging branch rebase 
to edk2 master?

Thanks
Abner

> + https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> + ub.com%2Friscv-non-isa%2Friscv-
> uefidata=05%7C01%7Cabner.chang%40a
> +
> md.com%7C0df18d1274f04083208208daad018bc2%7C3dd8961fe4884e608e11
> a82d99
> +
> 4e183d%7C0%7C0%7C638012519406523318%7CUnknown%7CTWFpbGZsb3d8e
> yJWIjoiMC
> +
> 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C
> %7C%
> +
> 7Csdata=f2SuwtirAU08pL2MlMris2XmdKkf6OH1muIG%2FPhmH5M%3D&
> amp;rese
> + rved=0
> +
> +  Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> + reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef RISCV_BOOT_PROTOCOL_H_
> +#define RISCV_BOOT_PROTOCOL_H_
> +
> +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL;
> +
> +#define RISCV_EFI_BOOT_PROTOCOL_REVISION  0x0001 #define
> +RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \
> +RISCV_EFI_BOOT_PROTOCOL_REVISION
> +
> +typedef EFI_STATUS
> +(EFIAPI *EFI_GET_BOOT_HARTID)(
> +  IN RISCV_EFI_BOOT_PROTOCOL   *This,
> +  OUT UINTN*BootHartId
> +  );
> +
> +typedef struct _RISCV_EFI_BOOT_PROTOCOL {
> +  UINT64 Revision;
> +  EFI_GET_BOOT_HARTIDGetBootHartId;
> +} RISCV_EFI_BOOT_PROTOCOL;
> +
> +#endif
> --
> 2.25.1
> 
> 
> 
> 
> 


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Re: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] [PATCH] [PATCH]MdeModulePkg/Ufs: Coverity scan flags multiple issues in edk2-stable202205 Signed-off-by: sivaparvat...@ami.com

[sivaparvathi C via groups.io]

Hi mikub...@linux.microsoft.com , gaolim...@byosoft.com.cn , 
michael.d.kin...@intel.com

Created PULL request for edk2_stable202205 coverity issue changes for Ufs 
driver.
https://github.com/tianocore/edk2/pull/3472

Thanks,
Sivaparvathi C


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Re: [edk2-devel] 回复: [edk2-devel] 回复: [edk2-devel] [edk2] [PATCH]MdeModulePkg\scsi: Coverity scan flags multiple issues in edk2-stable202205

[sivaparvathi C via groups.io]

Hi mikub...@linux.microsoft.com , gaolim...@byosoft.com.cn , 
michael.d.kin...@intel.com

Created Pull Request for edk2_Stable202205 Coverity Changes  for SCSI driver.

https://github.com/tianocore/edk2/pull/3473

Thanks,
Sivaparvathi


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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 33/34] Maintainers.txt: Add entry for OvmfPkg/RiscVVirt

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RiscVVirt is created to support EDK2 for RISC-V qemu
virt machine platform. Add maintainer entries.

Cc: Andrew Fish 
Cc: Leif Lindholm 
Cc: Michael D Kinney 
Signed-off-by: Sunil V L 
---
 Maintainers.txt | 4 
 1 file changed, 4 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index c641414109ad..ed8891b34606 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -527,6 +527,10 @@ F: OvmfPkg/XenResetVector/
 R: Anthony Perard  [sheep]
 R: Julien Grall  [jgrall]
 
+OvmfPkg: RISC-V Qemu Virt Platform
+F: OvmfPkg/Platforms/RiscVVirt
+R: Sunil V L  [vlsunil]
+
 PcAtChipsetPkg
 F: PcAtChipsetPkg/
 W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 11/34] OvmfPkg/PlatformPei: Refactor to allow other architectures

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Currently, PlatformPei supports only X86 architecture. So,
refactor it to allow other CPU architectures.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 OvmfPkg/PlatformPei/PlatformPei.inf   | 34 +++
 OvmfPkg/PlatformPei/{ => Ia32_X64}/Platform.h |  0
 OvmfPkg/PlatformPei/{ => Ia32_X64}/AmdSev.c   |  0
 .../PlatformPei/{ => Ia32_X64}/ClearCache.c   |  0
 .../{ => Ia32_X64}/FeatureControl.c   |  0
 OvmfPkg/PlatformPei/{ => Ia32_X64}/Fv.c   |  0
 OvmfPkg/PlatformPei/{ => Ia32_X64}/IntelTdx.c |  0
 .../PlatformPei/{ => Ia32_X64}/MemDetect.c|  0
 .../PlatformPei/{ => Ia32_X64}/MemTypeInfo.c  |  0
 OvmfPkg/PlatformPei/{ => Ia32_X64}/Platform.c |  0
 10 files changed, 19 insertions(+), 15 deletions(-)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/Platform.h (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/AmdSev.c (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/ClearCache.c (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/FeatureControl.c (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/Fv.c (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/IntelTdx.c (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/MemDetect.c (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/MemTypeInfo.c (100%)
 rename OvmfPkg/PlatformPei/{ => Ia32_X64}/Platform.c (100%)

diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf 
b/OvmfPkg/PlatformPei/PlatformPei.inf
index 3cd83e6ec3e5..683ebf1a440a 100644
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -22,16 +22,16 @@ [Defines]
 #  VALID_ARCHITECTURES   = IA32 X64 EBC
 #
 
-[Sources]
-  AmdSev.c
-  ClearCache.c
-  FeatureControl.c
-  Fv.c
-  MemDetect.c
-  MemTypeInfo.c
-  Platform.c
-  Platform.h
-  IntelTdx.c
+[Sources.IA32, Sources.X64]
+  Ia32_X64/AmdSev.c
+  Ia32_X64/ClearCache.c
+  Ia32_X64/FeatureControl.c
+  Ia32_X64/Fv.c
+  Ia32_X64/MemDetect.c
+  Ia32_X64/MemTypeInfo.c
+  Ia32_X64/Platform.c
+  Ia32_X64/Platform.h
+  Ia32_X64/IntelTdx.c
 
 [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
@@ -57,14 +57,16 @@ [LibraryClasses]
   PeiServicesLib
   PeiServicesTablePointerLib
   PeimEntryPoint
+  PcdLib
+  PlatformInitLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+  MtrrLib
+  VmgExitLib
   QemuFwCfgLib
   QemuFwCfgS3Lib
   QemuFwCfgSimpleParserLib
-  MtrrLib
   MemEncryptSevLib
-  PcdLib
-  VmgExitLib
-  PlatformInitLib
 
 [Pcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase
@@ -99,7 +101,6 @@ [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
   gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
-  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
   gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable
@@ -116,6 +117,9 @@ [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures
   gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask
 
+[Pcd.IA32, Pcd.X64]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
+
 [FixedPcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize
diff --git a/OvmfPkg/PlatformPei/Platform.h 
b/OvmfPkg/PlatformPei/Ia32_X64/Platform.h
similarity index 100%
rename from OvmfPkg/PlatformPei/Platform.h
rename to OvmfPkg/PlatformPei/Ia32_X64/Platform.h
diff --git a/OvmfPkg/PlatformPei/AmdSev.c 
b/OvmfPkg/PlatformPei/Ia32_X64/AmdSev.c
similarity index 100%
rename from OvmfPkg/PlatformPei/AmdSev.c
rename to OvmfPkg/PlatformPei/Ia32_X64/AmdSev.c
diff --git a/OvmfPkg/PlatformPei/ClearCache.c 
b/OvmfPkg/PlatformPei/Ia32_X64/ClearCache.c
similarity index 100%
rename from OvmfPkg/PlatformPei/ClearCache.c
rename to OvmfPkg/PlatformPei/Ia32_X64/ClearCache.c
diff --git a/OvmfPkg/PlatformPei/FeatureControl.c 
b/OvmfPkg/PlatformPei/Ia32_X64/FeatureControl.c
similarity index 100%
rename from OvmfPkg/PlatformPei/FeatureControl.c
rename to OvmfPkg/PlatformPei/Ia32_X64/FeatureControl.c
diff --git a/OvmfPkg/PlatformPei/Fv.c b/OvmfPkg/PlatformPei/Ia32_X64/Fv.c
similarity index 100%
rename from OvmfPkg/PlatformPei/Fv.c
rename to OvmfPkg/PlatformPei/Ia32_X64/Fv.c
diff --git a/OvmfPkg/PlatformPei/IntelTdx.c 
b/OvmfPkg/PlatformPei/Ia32_X64/IntelTdx.c
similarity index 100%
rename from OvmfPkg/PlatformPei/IntelTdx.c
rename to OvmfPkg/PlatformPei/Ia32_X64/IntelTdx.c
diff --git a/OvmfPkg/PlatformPei/MemDetect.c 
b/OvmfPkg/PlatformPei/Ia32_X64/MemDetect.c
similarity index 100%
rename from OvmfPkg/PlatformPei/MemDetect.c
rename to OvmfPkg/PlatformPei/Ia32_X64/MemDetect.c
diff --git a/OvmfPkg/PlatformPei/MemTypeInfo.c 
b/OvmfPkg/PlatformPei/Ia32_X64/MemTypeInfo.c
similarity index 100%
rename from OvmfPkg/PlatformPei/MemTypeInfo.c
rename to OvmfPkg/PlatformPei/Ia32_X64/MemTypeInfo.c
diff --git a/OvmfPkg/PlatformPei/Platform.c 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 34/34] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V register names do not follow the EDK2 formatting.
So, add it to ignore list for now.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Signed-off-by: Sunil V L 
---
 UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml
index bbdc44a45b34..ae963e94c8e6 100644
--- a/UefiCpuPkg/UefiCpuPkg.ci.yaml
+++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml
@@ -19,6 +19,7 @@
 ],
 ## Both file path and directory path are accepted.
 "IgnoreFiles": [
+  "Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h"
 ]
 },
 "CompilerPlugin": {
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 32/34] OvmfPkg: RiscVVirt: Add Qemu Virt platform support

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add infrastructure files to build edk2 for RISC-V qemu virt machine.

- EDK2 will boot as S-mode payload of opensbi.
- It supports building
  either code and variables in unified flash or in two separate drives
  via build time option UNIFIED_NVVARS.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc | 726 ++
 OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf | 406 ++
 OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf.inc |  66 ++
 OvmfPkg/Platforms/RiscVVirt/VarStore.fdf.inc  |  79 ++
 4 files changed, 1277 insertions(+)
 create mode 100644 OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc
 create mode 100644 OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf
 create mode 100644 OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf.inc
 create mode 100644 OvmfPkg/Platforms/RiscVVirt/VarStore.fdf.inc

diff --git a/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc 
b/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc
new file mode 100644
index ..63d95e91abe2
--- /dev/null
+++ b/OvmfPkg/Platforms/RiscVVirt/RiscVVirt.dsc
@@ -0,0 +1,726 @@
+## @file
+#  RISC-V EFI on RiscVVirt RISC-V platform
+#
+#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = RiscVVirt
+  PLATFORM_GUID  = 39DADB39-1B21-4867-838E-830B6149B9E0
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001c
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= RISCV64
+  BUILD_TARGETS  = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = OvmfPkg/Platforms/RiscVVirt/RiscVVirt.fdf
+
+  #
+  # Enable below options may cause build error or may not work on
+  # the initial version of RISC-V package
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  DEFINE SECURE_BOOT_ENABLE  = FALSE
+  DEFINE DEBUG_ON_SERIAL_PORT= TRUE
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE   = FALSE
+  DEFINE NETWORK_IP6_ENABLE   = FALSE
+  DEFINE NETWORK_TLS_ENABLE   = TRUE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE = TRUE
+  DEFINE NETWORK_ISCSI_ENABLE = FALSE
+  DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
+
+[BuildOptions]
+  GCC:RELEASE_*_*_CC_FLAGS   = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+  GCC:*_*_RISCV64_GENFW_FLAGS= --keepexceptiontable
+!endif
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:  *_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+  MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096
+
+
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+
+[SkuIds]
+  0|DEFAULT
+
+
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+
+
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+  
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 31/34] OvmfPkg/NorFlashDxe: Avoid switching between modes in a tight loop

[Sunil V L]

Currently, when dealing with small updates that can be written out
directly (i.e., if they only involve clearing bits and not setting bits,
as the latter requires a block level erase), we iterate over the data
one word at a time, read the old value, compare it, write the new value,
and repeat, unless we encountered a value that we cannot write (0->1
transition), in which case we fall back to a block level operation.

This is inefficient for two reasons:
- reading and writing a word at a time involves switching between array
  and programming mode for every word of data, which is
  disproportionately costly when running under KVM;
- we end up writing some data twice, as we may not notice that a block
  erase is needed until after some data has been written to flash.

So replace this sequence with a single read of up to twice the buffered
write maximum size, followed by one or two buffered writes if the data
can be written directly. Otherwise, fall back to the existing block
level sequence, but without writing out part of the data twice.

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Signed-off-by: Ard Biesheuvel 
---
 OvmfPkg/Drivers/NorFlashDxe/NorFlash.c | 211 +
 1 file changed, 75 insertions(+), 136 deletions(-)

diff --git a/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c 
b/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c
index cdc6b5da8bfb..649e0789db3c 100644
--- a/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c
+++ b/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c
@@ -582,20 +582,11 @@ NorFlashWriteSingleBlock (
   INUINT8   *Buffer
   )
 {
-  EFI_STATUS  TempStatus;
-  UINT32  Tmp;
-  UINT32  TmpBuf;
-  UINT32  WordToWrite;
-  UINT32  Mask;
-  BOOLEAN DoErase;
-  UINTN   BytesToWrite;
+  EFI_STATUS  Status;
   UINTN   CurOffset;
-  UINTN   WordAddr;
   UINTN   BlockSize;
   UINTN   BlockAddress;
-  UINTN   PrevBlockAddress;
-
-  PrevBlockAddress = 0;
+  UINT8   *OrigData;
 
   DEBUG ((DEBUG_BLKIO, "NorFlashWriteSingleBlock(Parameters: Lba=%ld, 
Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", Lba, Offset, *NumBytes, 
Buffer));
 
@@ -606,6 +597,12 @@ NorFlashWriteSingleBlock (
 return EFI_ACCESS_DENIED;
   }
 
+  // Check we did get some memory. Buffer is BlockSize.
+  if (Instance->ShadowBuffer == NULL) {
+DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
+return EFI_DEVICE_ERROR;
+  }
+
   // Cache the block size to avoid de-referencing pointers all the time
   BlockSize = Instance->Media.BlockSize;
 
@@ -625,149 +622,91 @@ NorFlashWriteSingleBlock (
 return EFI_BAD_BUFFER_SIZE;
   }
 
-  // Pick 128bytes as a good start for word operations as opposed to erasing 
the
-  // block and writing the data regardless if an erase is really needed.
-  // It looks like most individual NV variable writes are smaller than 
128bytes.
-  if (*NumBytes <= 128) {
+  // Pick P30_MAX_BUFFER_SIZE_IN_BYTES (== 128 bytes) as a good start for word
+  // operations as opposed to erasing the block and writing the data regardless
+  // if an erase is really needed.  It looks like most individual NV variable
+  // writes are smaller than 128 bytes.
+  // To avoid pathological cases were a 2 byte write is disregarded because it
+  // occurs right at a 128 byte buffered write alignment boundary, permit up to
+  // twice the max buffer size, and perform two writes if needed.
+  if ((*NumBytes + (Offset & BOUNDARY_OF_32_WORDS)) <= (2 * 
P30_MAX_BUFFER_SIZE_IN_BYTES)) {
 // Check to see if we need to erase before programming the data into NOR.
 // If the destination bits are only changing from 1s to 0s we can just 
write.
 // After a block is erased all bits in the block is set to 1.
 // If any byte requires us to erase we just give up and rewrite all of it.
-DoErase  = FALSE;
-BytesToWrite = *NumBytes;
-CurOffset= Offset;
 
-while (BytesToWrite > 0) {
-  // Read full word from NOR, splice as required. A word is the smallest
-  // unit we can write.
-  TempStatus = NorFlashRead (Instance, Lba, CurOffset & ~(0x3), sizeof 
(Tmp), );
-  if (EFI_ERROR (TempStatus)) {
-return EFI_DEVICE_ERROR;
-  }
-
-  // Physical address of word in NOR to write.
-  WordAddr = (CurOffset & ~(0x3)) + GET_NOR_BLOCK_ADDRESS (
-  Instance->RegionBaseAddress,
-  Lba,
-  BlockSize
-  );
-  // The word of data that is to be written.
-  TmpBuf = *((UINT32 *)(Buffer + (*NumBytes - BytesToWrite)));
-
-  // First do word aligned chunks.
-  if ((CurOffset & 0x3) == 0) {
-if (BytesToWrite >= 4) {
-  // Is the destination still in 'erased' state?
-  if (~Tmp != 0) {
-// Check to see if we are only changing bits to zero.
-if ((Tmp ^ 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 29/34] OvmfPkg: Add Qemu NOR flash DXE driver

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V needs NorFlashDxe driver for qemu virt machine. The
ArmPlatformPkg has this driver but migrating it to generic
package like MdeModulePkg introduces circular dependencies.
So, add NorFlashDxe driver in OvmfPkg which is mostly the
copy of the driver in ArmPlatformPkg except the support
for PcdNorFlashCheckBlockLocked feature. This approach also
allows to optimize the driver for virtual platforms.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.inf   |  67 ++
 .../NorFlashDxe/NorFlashStandaloneMm.inf  |  61 ++
 OvmfPkg/Drivers/NorFlashDxe/NorFlash.h| 422 
 OvmfPkg/Drivers/NorFlashDxe/NorFlash.c| 972 ++
 .../Drivers/NorFlashDxe/NorFlashBlockIoDxe.c  | 123 +++
 OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.c | 506 +
 OvmfPkg/Drivers/NorFlashDxe/NorFlashFvb.c | 777 ++
 .../NorFlashDxe/NorFlashStandaloneMm.c| 383 +++
 8 files changed, 3311 insertions(+)
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlash.h
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlash.c
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.c
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlashFvb.c
 create mode 100644 OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c

diff --git a/OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.inf 
b/OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
new file mode 100644
index ..cc2f48bcb6bf
--- /dev/null
+++ b/OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
@@ -0,0 +1,67 @@
+#/** @file
+#
+#  Component description file for NorFlashDxe module
+#
+#  Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = NorFlashDxe
+  FILE_GUID  = D4F3B3FC-3AEF-4774-AC94-304438ABDA53
+  MODULE_TYPE= DXE_RUNTIME_DRIVER
+  VERSION_STRING = 1.0
+  ENTRY_POINT= NorFlashInitialise
+
+[Sources.common]
+  NorFlash.c
+  NorFlash.h
+  NorFlashDxe.c
+  NorFlashFvb.c
+  NorFlashBlockIoDxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  IoLib
+  BaseLib
+  DebugLib
+  HobLib
+  NorFlashPlatformLib
+  UefiLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  UefiRuntimeLib
+  DxeServicesTableLib
+
+[Guids]
+  gEfiSystemNvDataFvGuid
+  gEfiVariableGuid
+  gEfiAuthenticatedVariableGuid
+  gEfiEventVirtualAddressChangeGuid
+  gEdkiiNvVarStoreFormattedGuid ## PRODUCES ## PROTOCOL
+
+[Protocols]
+  gEfiBlockIoProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiFirmwareVolumeBlockProtocolGuid
+  gEfiDiskIoProtocolGuid
+
+[Pcd.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+[Depex]
+  gEfiCpuArchProtocolGuid
diff --git a/OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf 
b/OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf
new file mode 100644
index ..18294c587d22
--- /dev/null
+++ b/OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf
@@ -0,0 +1,61 @@
+#/** @file
+#
+#  Component description file for NorFlashStandaloneMm module
+#
+#  Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
+#  Copyright (c) 2020, Linaro, Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = NorFlashStandaloneMm
+  FILE_GUID  = 9FFDD489-54D9-44EA-855E-E79FD6DF4E43
+  MODULE_TYPE= MM_STANDALONE
+  VERSION_STRING = 1.0
+  PI_SPECIFICATION_VERSION   = 0x00010032
+  ENTRY_POINT= NorFlashInitialise
+
+[Sources.common]
+  NorFlash.h
+  NorFlash.c
+  NorFlashStandaloneMm.c
+  NorFlashFvb.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  IoLib
+  MemoryAllocationLib
+  MmServicesTableLib
+  NorFlashPlatformLib
+  StandaloneMmDriverEntryPoint
+
+[Guids]
+  gEfiSystemNvDataFvGuid
+  

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 30/34] OvmfPkg/NorFlashDxe: Avoid switching to array mode during writes

[Sunil V L]

Switching to array mode (i.e., ROM memory mode rather than NOR flash
programming mode) is rather costly when running under KVM emulation, as it
involves setting up the read-only memslot in the hypervisor's stage 2
page tables. So let's avoid jumping between modes unnecessarily, and
only switch back to array mode when we are done writing to flash.

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Signed-off-by: Ard Biesheuvel 
---
 OvmfPkg/Drivers/NorFlashDxe/NorFlash.c | 9 +++--
 OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.c  | 3 +++
 OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c | 3 +++
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c 
b/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c
index c2a6aa281578..cdc6b5da8bfb 100644
--- a/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c
+++ b/OvmfPkg/Drivers/NorFlashDxe/NorFlash.c
@@ -205,9 +205,6 @@ NorFlashWriteSingleWord (
 SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, 
P30_CMD_CLEAR_STATUS_REGISTER);
   }
 
-  // Put device back into Read Array mode
-  SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY);
-
   return Status;
 }
 
@@ -338,9 +335,6 @@ NorFlashWriteBuffer (
   }
 
 EXIT:
-  // Put device back into Read Array mode
-  SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY);
-
   return Status;
 }
 
@@ -750,6 +744,9 @@ NorFlashWriteSingleBlock (
   }
 
   TempStatus = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite);
+  // Put device back into Read Array mode
+  SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY);
+
   if (EFI_ERROR (TempStatus)) {
 return EFI_DEVICE_ERROR;
   }
diff --git a/OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.c 
b/OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.c
index f7b92de21a57..862a8e621fd0 100644
--- a/OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.c
+++ b/OvmfPkg/Drivers/NorFlashDxe/NorFlashDxe.c
@@ -316,6 +316,9 @@ NorFlashWriteFullBlock (
   }
 
 EXIT:
+  // Put device back into Read Array mode
+  SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY);
+
   if (!EfiAtRuntime ()) {
 // Interruptions can resume.
 gBS->RestoreTPL (OriginalTPL);
diff --git a/OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c 
b/OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c
index b72ad97b0b55..f6dec84176d4 100644
--- a/OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c
+++ b/OvmfPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.c
@@ -270,6 +270,9 @@ NorFlashWriteFullBlock (
   }
 
 EXIT:
+  // Put device back into Read Array mode
+  SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0, P30_CMD_READ_ARRAY);
+
   if (EFI_ERROR (Status)) {
 DEBUG ((DEBUG_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed at 
address 0x%08x. Exit Status = \"%r\".\n", WordAddress, Status));
   }
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 28/34] OvmfPkg: Add NorFlashQemuLib library

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is mostly copied from ArmVirtPkg since it is required for
other architectures also. It uses OVMF specific PCD variables.

Also add the instance for single flash drive which has
both code and variables. This is copied from SbsaQemu.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 OvmfPkg/OvmfPkg.dec   |   4 +
 .../NorFlashQemuLib/NorFlashQemuLib.inf   |  40 ++
 .../NorFlashQemuUnifiedLib.inf|  30 
 .../Library/NorFlashQemuLib/NorFlashQemuLib.c | 136 ++
 .../NorFlashQemuLib/NorFlashQemuUnifiedLib.c  |  40 ++
 5 files changed, 250 insertions(+)
 create mode 100644 OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf
 create mode 100644 OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuUnifiedLib.inf
 create mode 100644 OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.c
 create mode 100644 OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuUnifiedLib.c

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 7d2acc5ea0e0..1a77b6ff801d 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -405,6 +405,10 @@ [PcdsFixedAtBuild]
   #  check to decide whether to abort dispatch of the driver it is linked into.
   gUefiOvmfPkgTokenSpaceGuid.PcdEntryPointOverrideFwCfgVarName|""|VOID*|0x68
 
+  ## The base address and size of the FVMAIN
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress|0|UINT64|0x71
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvSize|0|UINT32|0x72
+
 [PcdsDynamic, PcdsDynamicEx]
   gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10
diff --git a/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf 
b/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf
new file mode 100644
index ..ecd8059b3508
--- /dev/null
+++ b/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf
@@ -0,0 +1,40 @@
+#/** @file
+#
+#  Component description file for NorFlashQemuLib module
+#
+#  Copyright (c) 2014, Linaro Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = NorFlashQemuLib
+  FILE_GUID  = 42C30D8E-BFAD-4E77-9041-E7DAAE88DF7A
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = NorFlashPlatformLib
+
+[Sources.common]
+  NorFlashQemuLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OvmfPkg/OvmfPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  UefiBootServicesTableLib
+
+[Protocols]
+  gFdtClientProtocolGuid  ## CONSUMES
+
+[Depex]
+  gFdtClientProtocolGuid
+
+[Pcd]
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvBaseAddress
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFvSize
diff --git a/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuUnifiedLib.inf 
b/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuUnifiedLib.inf
new file mode 100644
index ..91d1406fc3e7
--- /dev/null
+++ b/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuUnifiedLib.inf
@@ -0,0 +1,30 @@
+#/** @file
+#
+#  Component description file for NorFlashQemuLib module
+#
+#  Copyright (c) 2014, Linaro Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = NorFlashQemuUnifiedLib
+  FILE_GUID  = 064742F1-E531-4D7D-A154-22315889CC23
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = NorFlashPlatformLib
+
+[Sources.common]
+  NorFlashQemuUnifiedLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OvmfPkg/OvmfPkg.dec
+
+[Pcd]
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
diff --git a/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.c 
b/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.c
new file mode 100644
index ..3632fa9e7a98
--- /dev/null
+++ b/OvmfPkg/Library/NorFlashQemuLib/NorFlashQemuLib.c
@@ -0,0 +1,136 @@
+/** @file
+
+ Copyright (c) 2014-2018, Linaro Ltd. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define QEMU_NOR_BLOCK_SIZE  SIZE_256KB
+
+#define MAX_FLASH_BANKS  4
+
+EFI_STATUS
+NorFlashPlatformInitialization (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+NOR_FLASH_DESCRIPTION  mNorFlashDevices[MAX_FLASH_BANKS];
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+  OUT NOR_FLASH_DESCRIPTION  **NorFlashDescriptions,
+  OUT UINT32 *Count
+  )
+{
+  FDT_CLIENT_PROTOCOL  *FdtClient;
+  INT32Node;
+  EFI_STATUS   Status;
+  EFI_STATUS 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 27/34] ArmVirtPkg: Update the references to NvVarStoreFormattedLib

[Sunil V L]

The NvVarStoreFormattedLib library is moved to MdeModulePkg.
So, updates its users with the new location.

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 ArmVirtPkg/ArmVirtKvmTool.dsc| 2 +-
 ArmVirtPkg/ArmVirtQemu.dsc   | 2 +-
 ArmVirtPkg/ArmVirtQemuKernel.dsc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc
index 3bd3ebd6e0b3..a40bea5b4bb2 100644
--- a/ArmVirtPkg/ArmVirtKvmTool.dsc
+++ b/ArmVirtPkg/ArmVirtKvmTool.dsc
@@ -258,7 +258,7 @@ [Components.common]
   MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
 
   NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
-  
NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
+  
NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
   }
 
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 0e460d21b2f5..96ae26e751be 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -357,7 +357,7 @@ [Components.common]
   MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
 
   NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
-  
NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
+  
NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
   # don't use unaligned CopyMem () on the UEFI varstore NOR flash region
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
   }
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index e3967db53133..bbcd7264572e 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -294,7 +294,7 @@ [Components.common]
   MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
 
   NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
-  
NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
+  
NULL|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
   # don't use unaligned CopyMem () on the UEFI varstore NOR flash region
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
   }
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 26/34] EmbeddedPkg/NvVarStoreFormattedLib: Migrate to MdeModulePkg

[Sunil V L]

This library is required by NorFlashDxe. Since it will be used by
both virtual and real platforms, migrate this library to
MdeModulePkg.

Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Abner Chang 
Cc: Daniel Schaefer 
Cc: Jian J Wang 
Cc: Liming Gao 
Cc: Andrew Fish 
Cc: Michael D Kinney 
Signed-off-by: Sunil V L 
---
 EmbeddedPkg/EmbeddedPkg.dec| 3 ---
 MdeModulePkg/MdeModulePkg.dec  | 3 +++
 MdeModulePkg/MdeModulePkg.dsc  | 2 ++
 .../Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf  | 1 -
 .../Include/Guid/NvVarStoreFormatted.h | 0
 .../Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c| 0
 6 files changed, 5 insertions(+), 4 deletions(-)
 rename {EmbeddedPkg => 
MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf (96%)
 rename {EmbeddedPkg => MdeModulePkg}/Include/Guid/NvVarStoreFormatted.h (100%)
 rename {EmbeddedPkg => 
MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c (100%)

diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec
index 341ef5e6a679..b1f5654835f6 100644
--- a/EmbeddedPkg/EmbeddedPkg.dec
+++ b/EmbeddedPkg/EmbeddedPkg.dec
@@ -69,9 +69,6 @@ [Guids.common]
   # HII form set GUID for ConsolePrefDxe driver
   gConsolePrefFormSetGuid = { 0x2d2358b4, 0xe96c, 0x484d, { 0xb2, 0xdd, 0x7c, 
0x2e, 0xdf, 0xc7, 0xd5, 0x6f } }
 
-  ## Include/Guid/NvVarStoreFormatted.h
-  gEdkiiNvVarStoreFormattedGuid = { 0xd1a86e3f, 0x0707, 0x4c35, { 0x83, 0xcd, 
0xdc, 0x2c, 0x29, 0xc8, 0x91, 0xa3 } }
-
 [Protocols.common]
   gHardwareInterruptProtocolGuid =  { 0x2890B3EA, 0x053D, 0x1643, { 0xAD, 
0x0C, 0xD6, 0x48, 0x08, 0xDA, 0x3F, 0xF1 } }
   gHardwareInterrupt2ProtocolGuid = { 0x32898322, 0x2da1, 0x474a, { 0xba, 
0xaa, 0xf3, 0xf7, 0xcf, 0x56, 0x94, 0x70 } }
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 58e6ab004882..492bff8b7890 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -412,6 +412,9 @@ [Guids]
   ## Include/Guid/MigratedFvInfo.h
   gEdkiiMigratedFvInfoGuid = { 0xc1ab12f7, 0x74aa, 0x408d, { 0xa2, 0xf4, 0xc6, 
0xce, 0xfd, 0x17, 0x98, 0x71 } }
 
+  ## Include/Guid/NvVarStoreFormatted.h
+  gEdkiiNvVarStoreFormattedGuid = { 0xd1a86e3f, 0x0707, 0x4c35, { 0x83, 0xcd, 
0xdc, 0x2c, 0x29, 0xc8, 0x91, 0xa3 } }
+
   #
   # GUID defined in UniversalPayload
   #
diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
index 45a8ec84ad69..0a2885ba8023 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -104,6 +104,7 @@ [LibraryClasses]
   
VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
   
MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf
   
VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf
+  
NvVarStoreFormattedLib|MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
 
 [LibraryClasses.EBC.PEIM]
   IoLib|MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
@@ -443,6 +444,7 @@ [Components]
   MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
   MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf
   MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf
+  MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
 
 [Components.IA32, Components.X64, Components.AARCH64]
   MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
diff --git 
a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf 
b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
similarity index 96%
rename from 
EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
rename to MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
index e2eed26c5b2d..5e8cd94cc9e0 100644
--- a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
+++ b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
@@ -32,7 +32,6 @@ [Sources]
   NvVarStoreFormattedLib.c
 
 [Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
 
diff --git a/EmbeddedPkg/Include/Guid/NvVarStoreFormatted.h 
b/MdeModulePkg/Include/Guid/NvVarStoreFormatted.h
similarity index 100%
rename from EmbeddedPkg/Include/Guid/NvVarStoreFormatted.h
rename to MdeModulePkg/Include/Guid/NvVarStoreFormatted.h
diff --git 
a/EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c 
b/MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c
similarity index 100%
rename from EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c
rename to MdeModulePkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 25/34] ArmPlatformPkg/NorFlashPlatformLib.h:Move to MdePkg

[Sunil V L]

Migrate NorFlashPlatformLib.h to MdePkg and add a Null
instance of the NorFlashPlatformLib library in MdePkg.

Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Andrew Fish 
Signed-off-by: Sunil V L 
---
 ArmPlatformPkg/ArmPlatformPkg.dec |  4 ---
 MdePkg/MdePkg.dec |  4 +++
 MdePkg/MdePkg.dsc |  1 +
 .../NorFlashPlatformLibNull.inf   | 22 
 .../Include/Library/NorFlashPlatformLib.h |  0
 .../NorFlashPlatformLibNull.c | 26 +++
 6 files changed, 53 insertions(+), 4 deletions(-)
 create mode 100644 
MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.inf
 rename {ArmPlatformPkg => MdePkg}/Include/Library/NorFlashPlatformLib.h (100%)
 create mode 100644 
MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.c

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec 
b/ArmPlatformPkg/ArmPlatformPkg.dec
index dd6e78f62aa1..86559aa6e57d 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -38,10 +38,6 @@ [LibraryClasses]
   #
   LcdPlatformLib|Include/Library/LcdPlatformLib.h
 
-  ##  @libraryclass  Provides a Nor flash interface.
-  #
-  NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h
-
   ##  @libraryclass  Provides an interface to the clock of a PL011 device.
   #
   PL011UartClockLib|Include/Library/PL011UartClockLib.h
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 1762068ffad7..16d01948f746 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -275,6 +275,10 @@ [LibraryClasses]
   ## @libraryclass  Provides function for SMM CPU Rendezvous Library.
   SmmCpuRendezvousLib|Include/Library/SmmCpuRendezvousLib.h
 
+  ##  @libraryclass  Provides a Nor flash interface.
+  #
+  NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h
+
 [LibraryClasses.IA32, LibraryClasses.X64, LibraryClasses.AARCH64]
   ##  @libraryclass  Provides services to generate random number.
   #
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index fd08122f441d..c575390bcff2 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -133,6 +133,7 @@ [Components]
   MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf
   MdePkg/Library/CcProbeLibNull/CcProbeLibNull.inf
   MdePkg/Library/SmmCpuRendezvousLibNull/SmmCpuRendezvousLibNull.inf
+  MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.inf
 
 [Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
   #
diff --git a/MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.inf 
b/MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.inf
new file mode 100644
index ..e4bd85ba7ace
--- /dev/null
+++ b/MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.inf
@@ -0,0 +1,22 @@
+## @file
+# NorFlashPlatformLib null instance
+#
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = NorFlashPlatformLibNull
+  FILE_GUID  = DE9C2866-5C5C-4BD3-9A09-3C4EB7448069
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = NorFlashPlatformLib
+
+[Sources.common]
+  NorFlashPlatformLibNull.c
+
+[Packages]
+  MdePkg/MdePkg.dec
diff --git a/ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h 
b/MdePkg/Include/Library/NorFlashPlatformLib.h
similarity index 100%
rename from ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h
rename to MdePkg/Include/Library/NorFlashPlatformLib.h
diff --git a/MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.c 
b/MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.c
new file mode 100644
index ..cd779f504e40
--- /dev/null
+++ b/MdePkg/Library/NorFlashPlatformLibNull/NorFlashPlatformLibNull.c
@@ -0,0 +1,26 @@
+/** @file
+
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+
+#include 
+
+EFI_STATUS
+NorFlashPlatformInitialization (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+  OUT NOR_FLASH_DESCRIPTION  **NorFlashDescriptions,
+  OUT UINT32 *Count
+  )
+{
+  return EFI_SUCCESS;
+}
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 24/34] ArmVirtPkg: Fix up the paths to PlatformBootManagerLib

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

PlatformBootManagerLib has been moved to OvmfPkg so that other
CPU architectures can reuse. So, update existing paths with the
new location.

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 ArmVirtPkg/ArmVirtQemu.dsc   | 4 ++--
 ArmVirtPkg/ArmVirtQemuKernel.dsc | 4 ++--
 ArmVirtPkg/ArmVirtPkg.ci.yaml| 1 -
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 9112cd6b07dc..0e460d21b2f5 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -71,7 +71,7 @@ [LibraryClasses.common]
 
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
-  
PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  
PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib.inf
   
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
@@ -167,7 +167,7 @@ [PcdsFixedAtBuild.common]
 !if $(TTY_TERMINAL) == TRUE
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
   # Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
-  gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 
0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 
0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
 !else
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
 !endif
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index 21684f3666c8..e3967db53133 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -69,7 +69,7 @@ [LibraryClasses.common]
 
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
-  
PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  
PlatformBootManagerLib|OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib.inf
   
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
@@ -146,7 +146,7 @@ [PcdsFixedAtBuild.common]
 !if $(TTY_TERMINAL) == TRUE
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
   # Set terminal type to TtyTerm, the value encoded is EFI_TTY_TERM_GUID
-  gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 0x7d, 
0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x80, 0x6d, 0x91, 
0x7d, 0xb1, 0x5b, 0x8c, 0x45, 0xa4, 0x8f, 0xe2, 0x5f, 0xdd, 0x51, 0xef, 0x94}
 !else
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
 !endif
diff --git a/ArmVirtPkg/ArmVirtPkg.ci.yaml b/ArmVirtPkg/ArmVirtPkg.ci.yaml
index 1e799dc4e194..552511c2694e 100644
--- a/ArmVirtPkg/ArmVirtPkg.ci.yaml
+++ b/ArmVirtPkg/ArmVirtPkg.ci.yaml
@@ -24,7 +24,6 @@
 ],
 ## Both file path and directory path are accepted.
 "IgnoreFiles": [
-"Library/PlatformBootManagerLib/PlatformBm.c"
 ]
 },
 ## options defined .pytool/Plugin/CompilerPlugin
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 23/34] ArmVirtPkg/PlatformBootManagerLib: Move to OvmfPkg

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

PlatformBootManagerLib in ArmVirtPkg is required for RISC-V
also. So, move it to OvmfPkg.

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Signed-off-by: Sunil V L 
---
 OvmfPkg/OvmfPkg.dec| 7 +++
 .../PlatformBootManagerLibVirt}/PlatformBootManagerLib.inf | 3 +--
 .../Library/PlatformBootManagerLibVirt}/PlatformBm.h   | 0
 .../Library/PlatformBootManagerLibVirt}/PlatformBm.c   | 0
 .../Library/PlatformBootManagerLibVirt}/QemuKernel.c   | 0
 OvmfPkg/OvmfPkg.ci.yaml| 1 +
 6 files changed, 9 insertions(+), 2 deletions(-)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibVirt}/PlatformBootManagerLib.inf (92%)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibVirt}/PlatformBm.h (100%)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibVirt}/PlatformBm.c (100%)
 rename {ArmVirtPkg/Library/PlatformBootManagerLib => 
OvmfPkg/Library/PlatformBootManagerLibVirt}/QemuKernel.c (100%)

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 716c98e084fd..7d2acc5ea0e0 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -463,6 +463,13 @@ [PcdsDynamic, PcdsDynamicEx]
   #
   gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x69
 
+  #
+  # Binary representation of the GUID that determines the terminal type. The
+  # size must be exactly 16 bytes. The default value corresponds to
+  # EFI_VT_100_GUID.
+  #
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 
0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 
0x4D}|VOID*|0x70
+
 [PcdsFeatureFlag]
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
diff --git 
a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
b/OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib.inf
similarity index 92%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
rename to OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib.inf
index 997eb1a4429f..a747ea3feac0 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBootManagerLib.inf
@@ -29,7 +29,6 @@ [Sources]
   QemuKernel.c
 
 [Packages]
-  ArmVirtPkg/ArmVirtPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   OvmfPkg/OvmfPkg.dec
@@ -61,7 +60,7 @@ [FixedPcd]
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
 
 [Pcd]
-  gArmVirtTokenSpaceGuid.PcdTerminalTypeGuidBuffer
+  gUefiOvmfPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
 
 [Guids]
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h 
b/OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBm.h
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.h
rename to OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBm.h
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c 
b/OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBm.c
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c
rename to OvmfPkg/Library/PlatformBootManagerLibVirt/PlatformBm.c
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/QemuKernel.c 
b/OvmfPkg/Library/PlatformBootManagerLibVirt/QemuKernel.c
similarity index 100%
rename from ArmVirtPkg/Library/PlatformBootManagerLib/QemuKernel.c
rename to OvmfPkg/Library/PlatformBootManagerLibVirt/QemuKernel.c
diff --git a/OvmfPkg/OvmfPkg.ci.yaml b/OvmfPkg/OvmfPkg.ci.yaml
index ff022242b018..c6efb9a8e59e 100644
--- a/OvmfPkg/OvmfPkg.ci.yaml
+++ b/OvmfPkg/OvmfPkg.ci.yaml
@@ -22,6 +22,7 @@
 ],
 ## Both file path and directory path are accepted.
 "IgnoreFiles": [
+"Library/PlatformBootManagerLibVirt/PlatformBm.c"
 ],
 "skip": True
 },
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 22/34] ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

PlatformHasAcpiDtDxe is required by other architectures also.
Hence, it is moved to OvmfPkg. So, update the consumers of this
module with the new location.

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +-
 ArmVirtPkg/ArmVirtQemu.dsc| 4 ++--
 ArmVirtPkg/ArmVirtQemuKernel.dsc  | 2 +-
 .../CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf   | 2 +-
 ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf  | 2 +-
 ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc  | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index 7ca7a391d9cf..c975e139a216 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -198,7 +198,7 @@ [PcdsDynamicDefault.common]
   gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0
 
 [PcdsDynamicHii]
-  
gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGuid|0x0|FALSE|NV,BS
+  
gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGuid|0x0|FALSE|NV,BS
 
 

 #
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 9369a88858fd..9112cd6b07dc 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -286,7 +286,7 @@ [PcdsDynamicDefault.common]
 !endif
 
 [PcdsDynamicHii]
-  
gArmVirtTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gArmVirtVariableGuid|0x0|FALSE|NV,BS
+  
gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGuid|0x0|FALSE|NV,BS
 
 !if $(TPM2_CONFIG_ENABLE) == TRUE
   
gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS
@@ -543,7 +543,7 @@ [Components.common]
   #
   # ACPI Support
   #
-  ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
+  OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
 [Components.AARCH64]
   
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
   OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf {
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index 7f7d15d6eee3..21684f3666c8 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -457,7 +457,7 @@ [Components.common]
   #
   # ACPI Support
   #
-  ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
+  OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
 [Components.AARCH64]
   
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
   OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf {
diff --git a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf 
b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
index 4af06b2a6746..7cad40e11f33 100644
--- a/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
+++ b/ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
@@ -36,7 +36,7 @@ [Guids]
   gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL
 
 [Pcd]
-  gArmVirtTokenSpaceGuid.PcdForceNoAcpi
+  gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi
 
 [Depex]
   gEfiVariableArchProtocolGuid
diff --git a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf 
b/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf
index 1cf25780f830..5888fcdc0b26 100644
--- a/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf
+++ b/ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf
@@ -37,7 +37,7 @@ [Guids]
   gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL
 
 [Pcd]
-  gArmVirtTokenSpaceGuid.PcdForceNoAcpi
+  gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi
 
 [Depex]
   TRUE
diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc 
b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
index d4df6dede0fe..17799de845ba 100644
--- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
+++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
@@ -141,7 +141,7 @@ [FV.FvMain]
   #
   # ACPI Support
   #
-  INF ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
+  INF OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
 !if $(ARCH) == AARCH64
   INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
   INF 
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 21/34] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This module is required by other architectures like RISC-V.
Hence, move this to OvmfPkg.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 ArmVirtPkg/ArmVirtPkg.dec| 9 -
 OvmfPkg/OvmfPkg.dec  | 7 +++
 .../PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf| 3 +--
 .../PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c  | 0
 4 files changed, 8 insertions(+), 11 deletions(-)
 rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf 
(89%)
 rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c 
(100%)

diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 4e165f6cd845..d2d325d71ea7 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -33,8 +33,6 @@ [Guids.common]
   gEarlyPL011BaseAddressGuid   = { 0xB199DEA9, 0xFD5C, 0x4A84, { 0x80, 
0x82, 0x2F, 0x41, 0x70, 0x78, 0x03, 0x05 } }
   gEarly16550UartBaseAddressGuid   = { 0xea67ca3e, 0x1f54, 0x436b, { 0x97, 
0x88, 0xd4, 0xeb, 0x29, 0xc3, 0x42, 0x67 } }
 
-  gArmVirtVariableGuid   = { 0x50bea1e5, 0xa2c5, 0x46e9, { 0x9b, 0x3a, 0x59, 
0x59, 0x65, 0x16, 0xb0, 0x0a } }
-
 [PcdsFeatureFlag]
   #
   # Feature Flag PCD that defines whether TPM2 support is enabled
@@ -68,10 +66,3 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
   # Cloud Hypervisor has no other way to pass Rsdp address to the guest except 
use a PCD.
   #
   gArmVirtTokenSpaceGuid.PcdCloudHvAcpiRsdpBaseAddress|0x0|UINT64|0x0005
-
-[PcdsDynamic]
-  #
-  # Whether to force disable ACPI, regardless of the fw_cfg settings
-  # exposed by QEMU
-  #
-  gArmVirtTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x0003
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index f13dd4a61f01..716c98e084fd 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -147,6 +147,7 @@ [Guids]
   gConfidentialComputingSevSnpBlobGuid  = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 
0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}}
   gUefiOvmfPkgPlatformInfoGuid  = {0xdec9b486, 0x1f16, 0x47c7, {0x8f, 
0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}}
   gVMMBootOrderGuid = {0x668f4529, 0x63d0, 0x4bb5, {0xb6, 
0x5d, 0x6f, 0xbb, 0x9d, 0x36, 0xa4, 0x4a}}
+  gOvmfVariableGuid = {0x50bea1e5, 0xa2c5, 0x46e9, {0x9b, 
0x3a, 0x59, 0x59, 0x65, 0x16, 0xb0, 0x0a}}
 
 [Ppis]
   # PPI whose presence in the PPI database signals that the TPM base address
@@ -456,6 +457,12 @@ [PcdsDynamic, PcdsDynamicEx]
   ## This PCD records LASA field in CC EVENTLOG ACPI table.
   gUefiOvmfPkgTokenSpaceGuid.PcdCcEventlogAcpiTableLasa|0|UINT64|0x67
 
+  #
+  # Whether to force disable ACPI, regardless of the fw_cfg settings
+  # exposed by QEMU
+  #
+  gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|0x0|BOOLEAN|0x69
+
 [PcdsFeatureFlag]
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf 
b/OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
similarity index 89%
rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
index e900aa992661..85873f73b2eb 100644
--- a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
+++ b/OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
@@ -19,7 +19,6 @@ [Sources]
   PlatformHasAcpiDtDxe.c
 
 [Packages]
-  ArmVirtPkg/ArmVirtPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
@@ -38,7 +37,7 @@ [Guids]
   gEdkiiPlatformHasDeviceTreeGuid ## SOMETIMES_PRODUCES ## PROTOCOL
 
 [Pcd]
-  gArmVirtTokenSpaceGuid.PcdForceNoAcpi
+  gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi
 
 [Depex]
   gEfiVariableArchProtocolGuid
diff --git a/ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c 
b/OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c
similarity index 100%
rename from ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c
rename to OvmfPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 20/34] UefiCpuPkg: Add CpuTimerDxe module

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This DXE module initializes the timer interrupt handler
and installs the Arch Timer protocol.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 UefiCpuPkg/UefiCpuPkg.dsc|   3 +
 UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf   |  51 
 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h   | 177 ++
 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c   | 294 +++
 UefiCpuPkg/CpuTimerDxe/CpuTimer.uni  |  15 ++
 UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni |  13 +
 6 files changed, 553 insertions(+)
 create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf
 create mode 100644 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h
 create mode 100644 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c
 create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimer.uni
 create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 6ea90507e36f..54ef5edd6eae 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -178,5 +178,8 @@ [Components.IA32, Components.X64]
   UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
   UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
 
+[Components.RISCV64]
+  UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf
+
 [BuildOptions]
   *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
diff --git a/UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf 
b/UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf
new file mode 100644
index ..d7706328b591
--- /dev/null
+++ b/UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf
@@ -0,0 +1,51 @@
+## @file
+# Timer Arch protocol module
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001b
+  BASE_NAME  = CpuTimerDxe
+  MODULE_UNI_FILE= CpuTimer.uni
+  FILE_GUID  = 055DDAC6-9142-4013-BF20-FC2E5BC325C9
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  ENTRY_POINT= TimerDriverInitialize
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+#  VALID_ARCHITECTURES   = RISCV64
+#
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  IoLib
+  CpuLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
+
+[Sources.RISCV64]
+  RiscV64/Timer.h
+  RiscV64/Timer.c
+
+[Protocols]
+  gEfiCpuArchProtocolGuid   ## CONSUMES
+  gEfiTimerArchProtocolGuid ## PRODUCES
+
+[Depex]
+  gEfiCpuArchProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  CpuTimerExtra.uni
diff --git a/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h 
b/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h
new file mode 100644
index ..586eb0cfadb4
--- /dev/null
+++ b/UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h
@@ -0,0 +1,177 @@
+/** @file
+  RISC-V Timer Architectural Protocol definitions
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef TIMER_H_
+#define TIMER_H_
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+//
+// RISC-V use 100us timer.
+// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns 
units
+//
+#define DEFAULT_TIMER_TICK_DURATION  10
+
+extern VOID
+RiscvSetTimerPeriod (
+  UINT32  TimerPeriod
+  );
+
+//
+// Function Prototypes
+//
+
+/**
+  Initialize the Timer Architectural Protocol driver
+
+  @param ImageHandle ImageHandle of the loaded driver
+  @param SystemTable Pointer to the System Table
+
+  @retval EFI_SUCCESSTimer Architectural Protocol created
+  @retval EFI_OUT_OF_RESOURCES   Not enough resources available to initialize 
driver.
+  @retval EFI_DEVICE_ERROR   A device error occured attempting to 
initialize the driver.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverInitialize (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+;
+
+/**
+
+  This function adjusts the period of timer interrupts to the value specified
+  by TimerPeriod.  If the timer period is updated, then the selected timer
+  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If
+  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+  If an error occurs while attempting to update the timer period, then the
+  timer hardware will be put back in its state prior to this call, and
+  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt
+  is disabled.  This is not the same as disabling the CPU's interrupts.
+  Instead, it must either turn off the timer hardware, or it must adjust the
+  interrupt controller so that a CPU interrupt is not generated when the timer
+  

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 19/34] UefiCpuPkg/CpuDxe: Add RISC-V Boot protocol support

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add the support for this protocol which is defined in the spec:
https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 UefiCpuPkg/UefiCpuPkg.dsc  | 12 +++---
 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 --
 2 files changed, 68 insertions(+), 10 deletions(-)

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index f694b3a77c2e..6ea90507e36f 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -122,9 +122,13 @@ [Components]
   UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
   UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
   UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf
-
-[Components.IA32, Components.X64]
   UefiCpuPkg/CpuDxe/CpuDxe.inf
+  UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+!if $(TOOL_CHAIN_TAG) != "XCODE5"
+  UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+!endif
+
+[Components.IA32, Components.X64]
   UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf {
 
   NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
@@ -141,10 +145,6 @@ [Components.IA32, Components.X64]
   UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
   UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
   UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
-  UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
-!if $(TOOL_CHAIN_TAG) != "XCODE5"
-  UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
-!endif
   UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
   UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
   
UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf
diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c 
b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
index 9f557b776a09..7551e0653603 100644
--- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
@@ -2,6 +2,7 @@
   RISC-V CPU DXE driver.
 
   Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All 
rights reserved.
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -12,8 +13,41 @@
 //
 // Global Variables
 //
-STATIC BOOLEAN mInterruptState = FALSE;
-STATIC EFI_HANDLE  mCpuHandle  = NULL;
+STATIC BOOLEAN   mInterruptState = FALSE;
+STATIC EFI_HANDLEmCpuHandle  = NULL;
+STATIC UINTN mBootHartId;
+RISCV_EFI_BOOT_PROTOCOL  gRiscvBootProtocol;
+
+/**
+  Get the boot hartid
+
+  @param  This   Protocol instance structure
+  @param  BootHartId Pointer to the Boot Hart ID variable
+
+  @retval EFI_SUCCESSIf BootHartId is returned
+  @retval EFI_INVALID_PARAMETER  Either "BootHartId" is NULL or "This" is not
+ a valid RISCV_EFI_BOOT_PROTOCOL instance.
+
+**/
+EFI_STATUS
+EFIAPI
+RiscvGetBootHartId (
+  IN RISCV_EFI_BOOT_PROTOCOL  *This,
+  OUT UINTN   *BootHartId
+  )
+{
+  if ((This != ) || (BootHartId == NULL)) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  *BootHartId = mBootHartId;
+  return EFI_SUCCESS;
+}
+
+RISCV_EFI_BOOT_PROTOCOL  gRiscvBootProtocol = {
+  RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
+  RiscvGetBootHartId
+};
 
 EFI_CPU_ARCH_PROTOCOL  gCpu = {
   CpuFlushCpuDataCache,
@@ -284,15 +318,39 @@ InitializeCpu (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS  Status;
+  EFI_STATUS  Status;
+  EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext;
 
-  InitializeCpuExceptionHandlers(NULL);
+  GetFirmwareContextPointer ();
+  ASSERT (FirmwareContext != NULL);
+  if (FirmwareContext == NULL) {
+DEBUG ((DEBUG_ERROR, "Failed to get the pointer of 
EFI_RISCV_FIRMWARE_CONTEXT\n"));
+return EFI_NOT_FOUND;
+  }
+
+  DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, 
FirmwareContext));
+
+  mBootHartId = FirmwareContext->BootHartId;
+  DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, 
mBootHartId));
+
+  InitializeCpuExceptionHandlers (NULL);
 
   //
   // Make sure interrupts are disabled
   //
   DisableInterrupts ();
 
+  //
+  // Install Boot protocol
+  //
+  Status = gBS->InstallProtocolInterface (
+  ,
+  ,
+  EFI_NATIVE_INTERFACE,
+  
+  );
+  ASSERT_EFI_ERROR (Status);
+
   //
   // Install CPU Architectural Protocol
   //
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 18/34] UefiCpuPkg/CpuDxe: Add support for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is migrated from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 UefiCpuPkg/CpuDxe/CpuDxe.inf   |  11 ++
 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 199 +++
 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 307 +
 3 files changed, 517 insertions(+)
 create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
 create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 069a7f2933bd..5a6ead3bfbb6 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -44,6 +44,9 @@ [LibraryClasses.IA32, LibraryClasses.X64]
   MtrrLib
   UefiCpuLib
 
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
+
 [Sources.IA32, Sources.X64]
   Ia32_X64/CpuDxe.c
   Ia32_X64/CpuDxe.h
@@ -62,11 +65,18 @@ [Sources.X64]
   X64/CpuAsm.nasm
   X64/PagingAttribute.c
 
+[Sources.RISCV64]
+  RiscV64/CpuDxe.c
+  RiscV64/CpuDxe.h
+
 [Protocols]
   gEfiCpuArchProtocolGuid   ## PRODUCES
   gEfiMpServiceProtocolGuid ## PRODUCES
   gEfiSmmBase2ProtocolGuid  ## SOMETIMES_CONSUMES
 
+[Protocols.RISCV64]
+  gRiscVEfiBootProtocolGuid ## PRODUCES
+
 [Guids]
   gIdleLoopEventGuid## CONSUMES   ## Event
   gEfiVectorHandoffTableGuid## SOMETIMES_CONSUMES ## 
SystemTable
@@ -83,6 +93,7 @@ [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList  ## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask## 
CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## 
CONSUMES
 
 [Depex]
   TRUE
diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h 
b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
new file mode 100644
index ..49f4e119665a
--- /dev/null
+++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
@@ -0,0 +1,199 @@
+/** @file
+  RISC-V CPU DXE module header file.
+
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All 
rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_DXE_H_
+#define CPU_DXE_H_
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Flush CPU data cache. If the instruction cache is fully coherent
+  with all DMA operations then function can just return EFI_SUCCESS.
+
+  @param  This  Protocol instance structure
+  @param  Start Physical address to start flushing from.
+  @param  LengthNumber of bytes to flush. Round up to chipset
+granularity.
+  @param  FlushType Specifies the type of flush operation to perform.
+
+  @retval EFI_SUCCESS   If cache was flushed
+  @retval EFI_UNSUPPORTED   If flush type is not supported.
+  @retval EFI_DEVICE_ERROR  If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_PHYSICAL_ADDRESS   Start,
+  IN UINT64 Length,
+  IN EFI_CPU_FLUSH_TYPE FlushType
+  );
+
+/**
+  Enables CPU interrupts.
+
+  @param  This  Protocol instance structure
+
+  @retval EFI_SUCCESS   If interrupts were enabled in the CPU
+  @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+  IN EFI_CPU_ARCH_PROTOCOL  *This
+  );
+
+/**
+  Disables CPU interrupts.
+
+  @param  This  Protocol instance structure
+
+  @retval EFI_SUCCESS   If interrupts were disabled in the CPU.
+  @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+  IN EFI_CPU_ARCH_PROTOCOL  *This
+  );
+
+/**
+  Return the state of interrupts.
+
+  @param  This   Protocol instance structure
+  @param  State  Pointer to the CPU's current interrupt state
+
+  @retval EFI_SUCCESSIf interrupts were disabled in the CPU.
+  @retval EFI_INVALID_PARAMETER  State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,
+  OUT BOOLEAN*State
+  );
+
+/**
+  Generates an INIT to the CPU.
+
+  @param  This  Protocol instance structure
+  @param  InitType  Type of CPU INIT to perform
+
+  @retval EFI_SUCCESS   If CPU INIT occurred. This value should never be
+seen.
+  @retval EFI_DEVICE_ERROR  If CPU INIT failed.
+  @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_CPU_INIT_TYPE  InitType
+  );
+
+/**
+  Registers a 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 17/34] UefiCpuPkg/CpuDxe: Refactor to allow other architectures

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Currently, CpuDxe supports only X86 architecture. To add
support for other architectures like RISC-V, this need to
be refactored.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Signed-off-by: Sunil V L 
---
 UefiCpuPkg/CpuDxe/CpuDxe.inf  | 28 ++-
 UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuDxe.h |  0
 UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuGdt.h |  0
 UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuMp.h  |  0
 .../CpuDxe/{ => Ia32_X64}/CpuPageTable.h  |  0
 UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuDxe.c |  0
 UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuGdt.c |  0
 UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuMp.c  |  0
 .../CpuDxe/{ => Ia32_X64}/CpuPageTable.c  |  0
 9 files changed, 15 insertions(+), 13 deletions(-)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuDxe.h (100%)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuGdt.h (100%)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuMp.h (100%)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuPageTable.h (100%)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuDxe.c (100%)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuGdt.c (100%)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuMp.c (100%)
 rename UefiCpuPkg/CpuDxe/{ => Ia32_X64}/CpuPageTable.c (100%)

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 235241899222..069a7f2933bd 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -29,28 +29,30 @@ [LibraryClasses]
   DebugLib
   DxeServicesTableLib
   MemoryAllocationLib
-  MtrrLib
   UefiBootServicesTableLib
   UefiDriverEntryPoint
-  LocalApicLib
-  UefiCpuLib
   UefiLib
   CpuExceptionHandlerLib
   HobLib
   ReportStatusCodeLib
-  MpInitLib
   TimerLib
   PeCoffGetEntryPointLib
 
-[Sources]
-  CpuDxe.c
-  CpuDxe.h
-  CpuGdt.c
-  CpuGdt.h
-  CpuMp.c
-  CpuMp.h
-  CpuPageTable.h
-  CpuPageTable.c
+[LibraryClasses.IA32, LibraryClasses.X64]
+  LocalApicLib
+  MpInitLib
+  MtrrLib
+  UefiCpuLib
+
+[Sources.IA32, Sources.X64]
+  Ia32_X64/CpuDxe.c
+  Ia32_X64/CpuDxe.h
+  Ia32_X64/CpuGdt.c
+  Ia32_X64/CpuGdt.h
+  Ia32_X64/CpuMp.c
+  Ia32_X64/CpuMp.h
+  Ia32_X64/CpuPageTable.h
+  Ia32_X64/CpuPageTable.c
 
 [Sources.IA32]
   Ia32/CpuAsm.nasm
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuDxe.h
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuDxe.h
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuDxe.h
diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuGdt.h
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuGdt.h
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuGdt.h
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuMp.h
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuMp.h
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuMp.h
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h 
b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuPageTable.h
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuPageTable.h
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuPageTable.h
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuDxe.c
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuDxe.c
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuDxe.c
diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuGdt.c
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuGdt.c
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuGdt.c
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuMp.c
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuMp.c
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuMp.c
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c 
b/UefiCpuPkg/CpuDxe/Ia32_X64/CpuPageTable.c
similarity index 100%
rename from UefiCpuPkg/CpuDxe/CpuPageTable.c
rename to UefiCpuPkg/CpuDxe/Ia32_X64/CpuPageTable.c
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 16/34] UefiCpuPkg/CpuExceptionHandlerLib: Add support for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 .../DxeCpuExceptionHandlerLib.inf |   7 +-
 .../SecPeiCpuExceptionHandlerLib.inf  |   7 +-
 .../RiscV64/CpuExceptionHandlerLib.h  | 116 +++
 .../RiscV64/CpuExceptionHandlerLib.c  | 133 ++
 .../RiscV64/SupervisorTrapHandler.S   | 105 ++
 5 files changed, 366 insertions(+), 2 deletions(-)
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index ef07b05c080a..b689e7af56e7 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -18,7 +18,7 @@ [Defines]
 #
 # The following information is for reference only and not required by the 
build tools.
 #
-#  VALID_ARCHITECTURES   = IA32 X64
+#  VALID_ARCHITECTURES   = IA32 X64 RISCV64
 #
 
 [Sources.Ia32]
@@ -38,6 +38,11 @@ [Sources.IA32, Sources.X64]
   Ia32_X64/PeiDxeSmmCpuException.c
   Ia32_X64/DxeException.c
 
+[Sources.RISCV64]
+  RiscV64/SupervisorTrapHandler.S
+  RiscV64/CpuExceptionHandlerLib.c
+  RiscV64/CpuExceptionHandlerLib.h
+
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index 28341abd4493..b490ef5aff8a 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -18,7 +18,7 @@ [Defines]
 #
 # The following information is for reference only and not required by the 
build tools.
 #
-#  VALID_ARCHITECTURES   = IA32 X64
+#  VALID_ARCHITECTURES   = IA32 X64 RISCV64
 #
 
 [Sources.Ia32]
@@ -37,6 +37,11 @@ [Sources.IA32, Sources.X64]
   Ia32_X64/CpuExceptionCommon.c
   Ia32_X64/SecPeiCpuException.c
 
+[Sources.RISCV64]
+  RiscV64/SupervisorTrapHandler.S
+  RiscV64/CpuExceptionHandlerLib.c
+  RiscV64/CpuExceptionHandlerLib.h
+
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h
new file mode 100644
index ..30f47e87552b
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h
@@ -0,0 +1,116 @@
+/** @file
+
+  RISC-V Exception Handler library definition file.
+
+  Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All 
rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+
+#include 
+
+/**
+  Trap Handler for S-mode
+
+**/
+VOID
+SupervisorModeTrap (
+  VOID
+  );
+
+//
+// Index of SMode trap register
+//
+#define SMODE_TRAP_REGS_zero 0
+#define SMODE_TRAP_REGS_ra   1
+#define SMODE_TRAP_REGS_sp   2
+#define SMODE_TRAP_REGS_gp   3
+#define SMODE_TRAP_REGS_tp   4
+#define SMODE_TRAP_REGS_t0   5
+#define SMODE_TRAP_REGS_t1   6
+#define SMODE_TRAP_REGS_t2   7
+#define SMODE_TRAP_REGS_s0   8
+#define SMODE_TRAP_REGS_s1   9
+#define SMODE_TRAP_REGS_a0   10
+#define SMODE_TRAP_REGS_a1   11
+#define SMODE_TRAP_REGS_a2   12
+#define SMODE_TRAP_REGS_a3   13
+#define SMODE_TRAP_REGS_a4   14
+#define SMODE_TRAP_REGS_a5   15
+#define SMODE_TRAP_REGS_a6   16
+#define SMODE_TRAP_REGS_a7   17
+#define SMODE_TRAP_REGS_s2   18
+#define SMODE_TRAP_REGS_s3   19
+#define SMODE_TRAP_REGS_s4   20
+#define SMODE_TRAP_REGS_s5   21
+#define SMODE_TRAP_REGS_s6   22
+#define SMODE_TRAP_REGS_s7   23
+#define SMODE_TRAP_REGS_s8   24
+#define SMODE_TRAP_REGS_s9   25
+#define SMODE_TRAP_REGS_s10  26
+#define SMODE_TRAP_REGS_s11  27
+#define SMODE_TRAP_REGS_t3   28
+#define SMODE_TRAP_REGS_t4   29
+#define SMODE_TRAP_REGS_t5   30
+#define SMODE_TRAP_REGS_t6   31
+#define SMODE_TRAP_REGS_sepc 32
+#define SMODE_TRAP_REGS_sstatus  33
+#define SMODE_TRAP_REGS_sie  34
+#define SMODE_TRAP_REGS_last 35
+
+#define SMODE_TRAP_REGS_OFFSET(x)  ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
+#define SMODE_TRAP_REGS_SIZE  SMODE_TRAP_REGS_OFFSET(last)
+
+#pragma pack(1)
+typedef struct {
+  //
+  // Below are 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 15/34] UefiCpuPkg/CpuExceptionHandlerLib: Refactor to allow other architectures

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Currently, the CpuExceptionHandlerLib library supports only X86.
Refactor the library to allow adding other CPU architectures.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Signed-off-by: Sunil V L 
---
 .../DxeCpuExceptionHandlerLib.inf  | 14 --
 .../PeiCpuExceptionHandlerLib.inf  |  8 
 .../SecPeiCpuExceptionHandlerLib.inf   | 12 +++-
 .../SmmCpuExceptionHandlerLib.inf  |  8 
 .../Xcode5SecPeiCpuExceptionHandlerLib.inf |  6 +++---
 .../{ => Ia32_X64}/CpuExceptionCommon.h|  0
 .../{ => Ia32_X64}/CpuExceptionCommon.c|  0
 .../{ => Ia32_X64}/DxeException.c  |  0
 .../{ => Ia32_X64}/PeiCpuException.c   |  0
 .../{ => Ia32_X64}/PeiDxeSmmCpuException.c |  0
 .../{ => Ia32_X64}/SecPeiCpuException.c|  0
 .../{ => Ia32_X64}/SmmException.c  |  0
 12 files changed, 26 insertions(+), 22 deletions(-)
 rename UefiCpuPkg/Library/CpuExceptionHandlerLib/{ => 
Ia32_X64}/CpuExceptionCommon.h (100%)
 rename UefiCpuPkg/Library/CpuExceptionHandlerLib/{ => 
Ia32_X64}/CpuExceptionCommon.c (100%)
 rename UefiCpuPkg/Library/CpuExceptionHandlerLib/{ => Ia32_X64}/DxeException.c 
(100%)
 rename UefiCpuPkg/Library/CpuExceptionHandlerLib/{ => 
Ia32_X64}/PeiCpuException.c (100%)
 rename UefiCpuPkg/Library/CpuExceptionHandlerLib/{ => 
Ia32_X64}/PeiDxeSmmCpuException.c (100%)
 rename UefiCpuPkg/Library/CpuExceptionHandlerLib/{ => 
Ia32_X64}/SecPeiCpuException.c (100%)
 rename UefiCpuPkg/Library/CpuExceptionHandlerLib/{ => Ia32_X64}/SmmException.c 
(100%)

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index e7a81bebdb13..ef07b05c080a 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -32,11 +32,11 @@ [Sources.X64]
   X64/ArchExceptionHandler.c
   X64/ArchInterruptDefs.h
 
-[Sources.common]
-  CpuExceptionCommon.h
-  CpuExceptionCommon.c
-  PeiDxeSmmCpuException.c
-  DxeException.c
+[Sources.IA32, Sources.X64]
+  Ia32_X64/CpuExceptionCommon.h
+  Ia32_X64/CpuExceptionCommon.c
+  Ia32_X64/PeiDxeSmmCpuException.c
+  Ia32_X64/DxeException.c
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
@@ -56,8 +56,10 @@ [LibraryClasses]
   SerialPortLib
   PrintLib
   SynchronizationLib
-  LocalApicLib
   PeCoffGetEntryPointLib
   MemoryAllocationLib
   DebugLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+  LocalApicLib
   VmgExitLib
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
index 7c2ec3b2db4c..7e7e1a4296de 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
@@ -33,10 +33,10 @@ [Sources.X64]
   X64/ArchInterruptDefs.h
 
 [Sources.common]
-  CpuExceptionCommon.h
-  CpuExceptionCommon.c
-  PeiCpuException.c
-  PeiDxeSmmCpuException.c
+  Ia32_X64/CpuExceptionCommon.h
+  Ia32_X64/CpuExceptionCommon.c
+  Ia32_X64/PeiCpuException.c
+  Ia32_X64/PeiDxeSmmCpuException.c
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index 6a170286c8fc..28341abd4493 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -32,10 +32,10 @@ [Sources.X64]
   X64/ArchExceptionHandler.c
   X64/ArchInterruptDefs.h
 
-[Sources.common]
-  CpuExceptionCommon.h
-  CpuExceptionCommon.c
-  SecPeiCpuException.c
+[Sources.IA32, Sources.X64]
+  Ia32_X64/CpuExceptionCommon.h
+  Ia32_X64/CpuExceptionCommon.c
+  Ia32_X64/SecPeiCpuException.c
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -46,8 +46,10 @@ [LibraryClasses]
   BaseLib
   SerialPortLib
   PrintLib
-  LocalApicLib
   PeCoffGetEntryPointLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+  LocalApicLib
   VmgExitLib
 
 [Pcd]
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
index 9dde07612a04..b7f395f45ab4 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
@@ -33,10 +33,10 @@ [Sources.X64]
   X64/ArchInterruptDefs.h
 
 [Sources.common]
-  CpuExceptionCommon.h
-  CpuExceptionCommon.c
-  PeiDxeSmmCpuException.c
-  SmmException.c
+  Ia32_X64/CpuExceptionCommon.h
+  Ia32_X64/CpuExceptionCommon.c
+  Ia32_X64/PeiDxeSmmCpuException.c
+  Ia32_X64/SmmException.c
 
 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 10/34] OvmfPkg/Sec: Add RISC-V support

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add the SEC module for RISC-V. EDK2 is launched as the payload
for machine mode firmware in RISC-V.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Min Xu 
Cc: Tom Lendacky 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 OvmfPkg/Sec/SecMain.inf|  16 +-
 OvmfPkg/Sec/RiscV64/SecMain.h  |  65 
 OvmfPkg/Sec/RiscV64/SecMain.c  | 573 +
 OvmfPkg/Sec/RiscV64/SecEntry.S |  23 ++
 4 files changed, 676 insertions(+), 1 deletion(-)
 create mode 100644 OvmfPkg/Sec/RiscV64/SecMain.h
 create mode 100644 OvmfPkg/Sec/RiscV64/SecMain.c
 create mode 100644 OvmfPkg/Sec/RiscV64/SecEntry.S

diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf
index 7c80ecaaf49b..76c47778ce8c 100644
--- a/OvmfPkg/Sec/SecMain.inf
+++ b/OvmfPkg/Sec/SecMain.inf
@@ -18,7 +18,7 @@ [Defines]
 #
 # The following information is for reference only and not required by the 
build tools.
 #
-#  VALID_ARCHITECTURES   = IA32 X64 EBC
+#  VALID_ARCHITECTURES   = IA32 X64 EBC RISCV64
 #
 
 [Sources.IA32, Sources.X64]
@@ -34,6 +34,13 @@ [Sources.IA32]
 [Sources.X64]
   X64/SecEntry.nasm
 
+[Sources.RISCV64]
+  SecMainCommon.c
+  SecMainCommon.h
+  RiscV64/SecEntry.S
+  RiscV64/SecMain.c
+  RiscV64/SecMain.h
+
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
@@ -61,11 +68,17 @@ [LibraryClasses.IA32, LibraryClasses.X64]
   PeiServicesLib
   CcProbeLib
 
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
+
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid# PPI ALWAYS_PRODUCED
   gEfiPeiMpInitLibMpDepPpiGuid
   gEfiPeiMpInitLibUpDepPpiGuid
 
+[Ppis.RISCV64]
+  gEfiTemporaryRamDonePpiGuid  ## PRODUCES
+
 [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase
@@ -88,6 +101,7 @@ [Pcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase
   gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
 
 [FeaturePcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire
diff --git a/OvmfPkg/Sec/RiscV64/SecMain.h b/OvmfPkg/Sec/RiscV64/SecMain.h
new file mode 100644
index ..11e3daa090b5
--- /dev/null
+++ b/OvmfPkg/Sec/RiscV64/SecMain.h
@@ -0,0 +1,65 @@
+/** @file
+  Master header file for SecCore.
+
+  Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All 
rights reserved.
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SEC_MAIN_H_
+#define _SEC_MAIN_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "SecMainCommon.h"
+
+/**
+  Entry point to the C language phase of SEC. After the SEC assembly
+  code has initialized some temporary memory and set up the stack,
+  the control is transferred to this function.
+
+  @param SizeOfRam   Size of the temporary memory available for use.
+  @param TempRamBase Base address of temporary ram
+  @param BootFirmwareVolume  Base address of the Boot Firmware Volume.
+**/
+VOID
+NORETURN
+EFIAPI
+SecStartup (
+  IN  UINTN  BootHartId,
+  IN  VOID   *DeviceTreeAddress
+  );
+
+/**
+  Auto-generated function that calls the library constructors for all of the 
module's
+  dependent libraries.  This function must be called by the SEC Core once a 
stack has
+  been established.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+  VOID
+  );
+
+#endif
diff --git a/OvmfPkg/Sec/RiscV64/SecMain.c b/OvmfPkg/Sec/RiscV64/SecMain.c
new file mode 100644
index ..c8c852714a32
--- /dev/null
+++ b/OvmfPkg/Sec/RiscV64/SecMain.c
@@ -0,0 +1,573 @@
+/** @file
+  RISC-V SEC phase module.
+
+  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SecMain.h"
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+  IN CONST EFI_PEI_SERVICES  **PeiServices,
+  IN EFI_PHYSICAL_ADDRESSTemporaryMemoryBase,
+  IN EFI_PHYSICAL_ADDRESSPermanentMemoryBase,
+  IN UINTN   CopySize
+  );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamDone (
+  VOID
+  );
+
+STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI  mTemporaryRamSupportPpi = {
+  TemporaryRamMigration
+};
+
+STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI  mTemporaryRamDonePpi = {
+  TemporaryRamDone
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR  mPrivateDispatchTable[] = {
+  {
+EFI_PEI_PPI_DESCRIPTOR_PPI,
+,
+
+  },
+  {
+(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+,
+
+  },
+};
+
+/** Temporary RAM migration function.

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 14/34] UefiCpuPkg/CpuTimerLib: Add support for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 .../Library/CpuTimerLib/BaseCpuTimerLib.inf   |   3 +
 .../Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++
 2 files changed, 202 insertions(+)
 create mode 100644 UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c

diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf 
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
index a22457b44940..554ce9fe9db8 100644
--- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
@@ -22,6 +22,9 @@ [Sources.IA32, Sources.X64]
   Ia32_X64/CpuTimerLib.c
   Ia32_X64/BaseCpuTimerLib.c
 
+[Sources.RISCV64]
+  RiscV64/CpuTimerLib.c
+
 [Packages]
   MdePkg/MdePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
diff --git a/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c 
b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c
new file mode 100644
index ..9c8efc0f3530
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c
@@ -0,0 +1,199 @@
+/** @file
+  RISC-V instance of Timer Library.
+
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All 
rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Stalls the CPU for at least the given number of ticks.
+
+  Stalls the CPU for at least the given number of ticks. It's invoked by
+  MicroSecondDelay() and NanoSecondDelay().
+
+  @param  Delay A period of time to delay in ticks.
+
+**/
+VOID
+InternalRiscVTimerDelay (
+  IN UINT32  Delay
+  )
+{
+  UINT32  Ticks;
+  UINT32  Times;
+
+  Times  = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+  Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+  do {
+//
+// The target timer count is calculated here
+//
+Ticks = RiscVReadTimer () + Delay;
+Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
+while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 
1))) == 0) {
+  CpuPause ();
+}
+  } while (Times-- > 0);
+}
+
+/**
+  Stalls the CPU for at least the given number of microseconds.
+
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+  @param  MicroSeconds  The minimum number of microseconds to delay.
+
+  @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+  IN UINTN  MicroSeconds
+  )
+{
+  InternalRiscVTimerDelay (
+(UINT32)DivU64x32 (
+  MultU64x32 (
+MicroSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+  100u
+  )
+);
+  return MicroSeconds;
+}
+
+/**
+  Stalls the CPU for at least the given number of nanoseconds.
+
+  Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+  @param  NanoSeconds The minimum number of nanoseconds to delay.
+
+  @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+  IN UINTN  NanoSeconds
+  )
+{
+  InternalRiscVTimerDelay (
+(UINT32)DivU64x32 (
+  MultU64x32 (
+NanoSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+  10u
+  )
+);
+  return NanoSeconds;
+}
+
+/**
+  Retrieves the current value of a 64-bit free running performance counter.
+
+  Retrieves the current value of a 64-bit free running performance counter. The
+  counter can either count up by 1 or count down by 1. If the physical
+  performance counter counts by a larger increment, then the counter values
+  must be translated. The properties of the counter can be retrieved from
+  GetPerformanceCounterProperties().
+
+  @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+  VOID
+  )
+{
+  return (UINT64)RiscVReadTimer ();
+}
+
+/**return
+  Retrieves the 64-bit frequency in Hz and the range of performance counter
+  values.
+
+  If StartValue is not NULL, then the value that the performance counter starts
+  with immediately after is it rolls over is returned in StartValue. If
+  EndValue is not NULL, then the value that the performance counter end with
+  immediately before it rolls over is returned in EndValue. The 64-bit
+  frequency of the performance counter in Hz is always returned. If StartValue
+  is less than EndValue, then the performance counter counts up. If StartValue
+  is greater than EndValue, then the performance counter counts down. For
+  example, a 64-bit free running counter that counts up would have a StartValue
+  of 0 and an EndValue of 0x. A 24-bit free running counter
+  that counts down would have a StartValue of 0xFF and an EndValue of 0.
+
+  @param  StartValue  The value the performance counter starts with 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 13/34] UefiCpuPkg/CpuTimerLib: Refactor to allow other architectures

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Currently, CpuTimerLib library supports only X86 architecture.
Refactor to allow other CPU architectures.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Signed-off-by: Sunil V L 
---
 UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf  | 6 +++---
 .../Library/CpuTimerLib/{ => Ia32_X64}/BaseCpuTimerLib.c| 0
 UefiCpuPkg/Library/CpuTimerLib/{ => Ia32_X64}/CpuTimerLib.c | 0
 3 files changed, 3 insertions(+), 3 deletions(-)
 rename UefiCpuPkg/Library/CpuTimerLib/{ => Ia32_X64}/BaseCpuTimerLib.c (100%)
 rename UefiCpuPkg/Library/CpuTimerLib/{ => Ia32_X64}/CpuTimerLib.c (100%)

diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf 
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
index de0648de91b5..a22457b44940 100644
--- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
@@ -18,9 +18,9 @@ [Defines]
   LIBRARY_CLASS  = TimerLib
   MODULE_UNI_FILE= BaseCpuTimerLib.uni
 
-[Sources]
-  CpuTimerLib.c
-  BaseCpuTimerLib.c
+[Sources.IA32, Sources.X64]
+  Ia32_X64/CpuTimerLib.c
+  Ia32_X64/BaseCpuTimerLib.c
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c 
b/UefiCpuPkg/Library/CpuTimerLib/Ia32_X64/BaseCpuTimerLib.c
similarity index 100%
rename from UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
rename to UefiCpuPkg/Library/CpuTimerLib/Ia32_X64/BaseCpuTimerLib.c
diff --git a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c 
b/UefiCpuPkg/Library/CpuTimerLib/Ia32_X64/CpuTimerLib.c
similarity index 100%
rename from UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
rename to UefiCpuPkg/Library/CpuTimerLib/Ia32_X64/CpuTimerLib.c
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 09/34] OvmfPkg/Sec: Refactor to allow other architectures

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Currently, the Sec module supports only X86 architecture.
Refactor the module to allow other CPU architectures.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Min Xu 
Cc: Tom Lendacky 
Signed-off-by: Sunil V L 
---
 OvmfPkg/Sec/SecMain.inf  |  18 +-
 OvmfPkg/Sec/{ => Ia32_X64}/AmdSev.h  |   0
 OvmfPkg/Sec/SecMainCommon.h  |  73 
 OvmfPkg/Sec/{ => Ia32_X64}/AmdSev.c  |   0
 OvmfPkg/Sec/{ => Ia32_X64}/SecMain.c | 227 +
 OvmfPkg/Sec/SecMainCommon.c  | 238 +++
 6 files changed, 323 insertions(+), 233 deletions(-)
 rename OvmfPkg/Sec/{ => Ia32_X64}/AmdSev.h (100%)
 create mode 100644 OvmfPkg/Sec/SecMainCommon.h
 rename OvmfPkg/Sec/{ => Ia32_X64}/AmdSev.c (100%)
 rename OvmfPkg/Sec/{ => Ia32_X64}/SecMain.c (75%)
 create mode 100644 OvmfPkg/Sec/SecMainCommon.c

diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf
index 561a840f29c5..7c80ecaaf49b 100644
--- a/OvmfPkg/Sec/SecMain.inf
+++ b/OvmfPkg/Sec/SecMain.inf
@@ -21,10 +21,12 @@ [Defines]
 #  VALID_ARCHITECTURES   = IA32 X64 EBC
 #
 
-[Sources]
-  SecMain.c
-  AmdSev.c
-  AmdSev.h
+[Sources.IA32, Sources.X64]
+  SecMainCommon.c
+  SecMainCommon.h
+  Ia32_X64/SecMain.c
+  Ia32_X64/AmdSev.c
+  Ia32_X64/AmdSev.h
 
 [Sources.IA32]
   Ia32/SecEntry.nasm
@@ -42,19 +44,21 @@ [LibraryClasses]
   BaseLib
   DebugLib
   BaseMemoryLib
-  PeiServicesLib
   PcdLib
   CpuLib
-  UefiCpuLib
   DebugAgentLib
   IoLib
   PeCoffLib
   PeCoffGetEntryPointLib
   PeCoffExtraActionLib
   ExtractGuidedSectionLib
+  CpuExceptionHandlerLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+  UefiCpuLib
   LocalApicLib
   MemEncryptSevLib
-  CpuExceptionHandlerLib
+  PeiServicesLib
   CcProbeLib
 
 [Ppis]
diff --git a/OvmfPkg/Sec/AmdSev.h b/OvmfPkg/Sec/Ia32_X64/AmdSev.h
similarity index 100%
rename from OvmfPkg/Sec/AmdSev.h
rename to OvmfPkg/Sec/Ia32_X64/AmdSev.h
diff --git a/OvmfPkg/Sec/SecMainCommon.h b/OvmfPkg/Sec/SecMainCommon.h
new file mode 100644
index ..c3cc16e2c8cf
--- /dev/null
+++ b/OvmfPkg/Sec/SecMainCommon.h
@@ -0,0 +1,73 @@
+/** @file
+  Header file for common functions of Sec.
+
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+  Locates a section within a series of sections
+  with the specified section type.
+
+  The Instance parameter indicates which instance of the section
+  type to return. (0 is first instance, 1 is second...)
+
+  @param[in]   SectionsThe sections to search
+  @param[in]   SizeOfSections  Total size of all sections
+  @param[in]   SectionType The section type to locate
+  @param[in]   InstanceThe section instance number
+  @param[out]  FoundSectionThe FFS section if found
+
+  @retval EFI_SUCCESS   The file and section was found
+  @retval EFI_NOT_FOUND The file and section was not found
+  @retval EFI_VOLUME_CORRUPTED  The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsSectionInstance (
+  IN  VOID   *Sections,
+  IN  UINTN  SizeOfSections,
+  IN  EFI_SECTION_TYPE   SectionType,
+  IN  UINTN  Instance,
+  OUT EFI_COMMON_SECTION_HEADER  **FoundSection
+  );
+
+/**
+  Locates a FFS file with the specified file type and a section
+  within that file with the specified section type.
+
+  @param[in]   FvThe firmware volume to search
+  @param[in]   FileType  The file type to locate
+  @param[in]   SectionType   The section type to locate
+  @param[out]  FoundSection  The FFS section if found
+
+  @retval EFI_SUCCESS   The file and section was found
+  @retval EFI_NOT_FOUND The file and section was not found
+  @retval EFI_VOLUME_CORRUPTED  The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsFileAndSection (
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *Fv,
+  IN  EFI_FV_FILETYPE FileType,
+  IN  EFI_SECTION_TYPESectionType,
+  OUT EFI_COMMON_SECTION_HEADER   **FoundSection
+  );
+
+/**
+  Locates the PEI Core entry point address
+
+  @param[in]  Fv The firmware volume to search
+  @param[out] PeiCoreEntryPoint  The entry point of the PEI Core image
+
+  @retval EFI_SUCCESS   The file and section was found
+  @retval EFI_NOT_FOUND The file and section was not found
+  @retval EFI_VOLUME_CORRUPTED  The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindPeiCoreImageBaseInFv (
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *Fv,
+  OUT  EFI_PHYSICAL_ADDRESS   *PeiCoreImageBase
+  );
diff --git a/OvmfPkg/Sec/AmdSev.c b/OvmfPkg/Sec/Ia32_X64/AmdSev.c
similarity index 100%
rename from OvmfPkg/Sec/AmdSev.c
rename to OvmfPkg/Sec/Ia32_X64/AmdSev.c
diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/Ia32_X64/SecMain.c
similarity index 75%

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 12/34] OvmfPkg/PlatformPei: Add support for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is mostly copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 OvmfPkg/PlatformPei/PlatformPei.inf |   9 +
 OvmfPkg/PlatformPei/RiscV64/Platform.h  |  97 ++
 OvmfPkg/PlatformPei/RiscV64/Fv.c|  81 ++
 OvmfPkg/PlatformPei/RiscV64/MemDetect.c | 212 ++
 OvmfPkg/PlatformPei/RiscV64/Platform.c  | 372 
 5 files changed, 771 insertions(+)
 create mode 100644 OvmfPkg/PlatformPei/RiscV64/Platform.h
 create mode 100644 OvmfPkg/PlatformPei/RiscV64/Fv.c
 create mode 100644 OvmfPkg/PlatformPei/RiscV64/MemDetect.c
 create mode 100644 OvmfPkg/PlatformPei/RiscV64/Platform.c

diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf 
b/OvmfPkg/PlatformPei/PlatformPei.inf
index 683ebf1a440a..0bae88f6d01b 100644
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -33,6 +33,12 @@ [Sources.IA32, Sources.X64]
   Ia32_X64/Platform.h
   Ia32_X64/IntelTdx.c
 
+[Sources.RISCV64]
+  RiscV64/Fv.c
+  RiscV64/MemDetect.c
+  RiscV64/Platform.c
+  RiscV64/Platform.h
+
 [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
   MdePkg/MdePkg.dec
@@ -68,6 +74,9 @@ [LibraryClasses.IA32, LibraryClasses.X64]
   QemuFwCfgSimpleParserLib
   MemEncryptSevLib
 
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
+
 [Pcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize
diff --git a/OvmfPkg/PlatformPei/RiscV64/Platform.h 
b/OvmfPkg/PlatformPei/RiscV64/Platform.h
new file mode 100644
index ..6c23c722a360
--- /dev/null
+++ b/OvmfPkg/PlatformPei/RiscV64/Platform.h
@@ -0,0 +1,97 @@
+/** @file
+  Platform PEI module include file.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_PEI_H_INCLUDED_
+#define PLATFORM_PEI_H_INCLUDED_
+
+VOID
+AddIoMemoryBaseSizeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  UINT64MemorySize
+  );
+
+VOID
+AddIoMemoryRangeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  EFI_PHYSICAL_ADDRESS  MemoryLimit
+  );
+
+VOID
+AddMemoryBaseSizeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  UINT64MemorySize
+  );
+
+VOID
+AddMemoryRangeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  EFI_PHYSICAL_ADDRESS  MemoryLimit
+  );
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  UINT64MemorySize
+  );
+
+VOID
+AddReservedMemoryBaseSizeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  UINT64MemorySize
+  );
+
+VOID
+AddUntestedMemoryRangeHob (
+  EFI_PHYSICAL_ADDRESS  MemoryBase,
+  EFI_PHYSICAL_ADDRESS  MemoryLimit
+  );
+
+VOID
+AddressWidthInitialization (
+  VOID
+  );
+
+EFI_STATUS
+PublishPeiMemory (
+  VOID
+  );
+
+UINT32
+GetSystemMemorySizeBelow4gb (
+  VOID
+  );
+
+VOID
+InitializeRamRegions (
+  VOID
+  );
+
+EFI_STATUS
+PeiFvInitialization (
+  VOID
+  );
+
+EFI_STATUS
+InitializeXen (
+  VOID
+  );
+
+/**
+  Build processor and platform information for the U5 platform
+
+  @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildRiscVSmbiosHobs (
+  VOID
+  );
+
+#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/OvmfPkg/PlatformPei/RiscV64/Fv.c b/OvmfPkg/PlatformPei/RiscV64/Fv.c
new file mode 100644
index ..ff99c1432935
--- /dev/null
+++ b/OvmfPkg/PlatformPei/RiscV64/Fv.c
@@ -0,0 +1,81 @@
+/** @file
+  Build FV related hobs for platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+  and DXE know about them.
+
+  @retval EFI_SUCCESS   Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+  VOID
+  )
+{
+  DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+
+  // Create a memory allocation HOB for the DXE FV.
+  //
+  // If "secure" S3 is needed, then SEC will decompress both PEI and DXE
+  // firmware volumes at S3 resume too, hence we need to keep away the OS from
+  // DXEFV as well. Otherwise we only need to keep away DXE itself from the
+  // DXEFV area.
+  //
+  BuildMemoryAllocationHob (
+PcdGet32 (PcdOvmfPeiMemFvBase),
+PcdGet32 (PcdOvmfPeiMemFvSize),
+EfiBootServicesData
+);
+
+  //
+  // Let DXE know about the DXE FV
+  //
+  BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+  DEBUG ((
+DEBUG_INFO,
+"Platform builds DXE FV at %x, size %x.\n",
+PcdGet32 (PcdOvmfDxeMemFvBase),

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 08/34] OvmfPkg/ResetSystemLib: Add support for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is mostly copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Rebecca Cran 
Cc: Peter Grehan 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 .../ResetSystemLib/BaseResetSystemLib.inf |   6 +
 .../ResetSystemLib/DxeResetSystemLib.inf  |   9 +-
 .../ResetSystemLib/RiscV64/DxeResetShutdown.c |  20 +++
 .../ResetSystemLib/RiscV64/ResetSystemLib.c   | 128 ++
 4 files changed, 162 insertions(+), 1 deletion(-)
 create mode 100644 OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c
 create mode 100644 OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c

diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf 
b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf
index 4397f90a24dd..83cebb45b3db 100644
--- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf
+++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf
@@ -25,6 +25,9 @@ [Sources.IA32, Sources.X64]
   Ia32_X64/BaseResetShutdown.c
   Ia32_X64/ResetSystemLib.c
 
+[Sources.RISCV64]
+  RiscV64/ResetSystemLib.c
+
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
@@ -36,3 +39,6 @@ [LibraryClasses]
   IoLib
   PciLib
   TimerLib
+
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf 
b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf
index 79478453d7cb..abab573f2f06 100644
--- a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf
+++ b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf
@@ -20,13 +20,17 @@ [Defines]
 # The following information is for reference only and not required by the build
 # tools.
 #
-#  VALID_ARCHITECTURES   = IA32 X64
+#  VALID_ARCHITECTURES   = IA32 X64 RISCV64
 #
 
 [Sources.IA32, Sources.X64]
   Ia32_X64/DxeResetShutdown.c
   Ia32_X64/ResetSystemLib.c
 
+[Sources.RISCV64]
+  RiscV64/ResetSystemLib.c
+  RiscV64/DxeResetShutdown.c
+
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
@@ -39,5 +43,8 @@ [LibraryClasses]
   PcdLib
   TimerLib
 
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
+
 [Pcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId ## CONSUMES
diff --git a/OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c 
b/OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c
new file mode 100644
index ..027e235cad11
--- /dev/null
+++ b/OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c
@@ -0,0 +1,20 @@
+/** @file
+  DXE Reset System Library Shutdown API implementation for OVMF.
+
+  Copyright (C) 2020, Red Hat, Inc.
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include // CpuDeadLoop()
+#include  // ResetShutdown()
+
+EFI_STATUS
+EFIAPI
+DxeResetInit (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  return EFI_SUCCESS;
+}
diff --git a/OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c 
b/OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c
new file mode 100644
index ..14f7653aa8de
--- /dev/null
+++ b/OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c
@@ -0,0 +1,128 @@
+/** @file
+  Reset System Library functions for RISC-V
+
+  Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+
+/**
+  This function causes a system-wide reset (cold reset), in which
+  all circuitry within the system returns to its initial state. This type of 
reset
+  is asynchronous to system operation and operates without regard to
+  cycle boundaries.
+
+  If this function returns, it means that the system does not support cold 
reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+  VOID
+  )
+{
+  // Warm Reset via SBI ecall
+  SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+  This function causes a system-wide initialization (warm reset), in which all 
processors
+  are set to their initial state. Pending cycles are not corrupted.
+
+  If this function returns, it means that the system does not support warm 
reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+  VOID
+  )
+{
+  // Warm Reset via SBI ecall
+  SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+  This function causes the system to enter a power state equivalent
+  to the ACPI G2/S5 or G3 states.
+
+  If this function returns, it means that the system does not support shutdown 
reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+  VOID
+  )
+{
+  // Shut down via SBI ecall
+  SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+  This function causes a systemwide reset. The exact type of the reset is
+  defined by the EFI_GUID that follows the Null-terminated Unicode string 
passed
+  into ResetData. If 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 04/34] MdePkg: Add BaseRiscVSbiLib Library for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This library is required to make SBI ecalls from the S-mode EDK2.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Sunil V L 
---
 MdePkg/MdePkg.dec |   4 +
 MdePkg/MdePkg.dsc |   3 +
 .../BaseRiscVSbiLib/BaseRiscVSbiLib.inf   |  25 ++
 MdePkg/Include/Library/BaseRiscVSbiLib.h  | 127 ++
 .../Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 227 ++
 5 files changed, 386 insertions(+)
 create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
 create mode 100644 MdePkg/Include/Library/BaseRiscVSbiLib.h
 create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 8f1bcfdc3e97..1762068ffad7 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -307,6 +307,10 @@ [LibraryClasses.IA32, LibraryClasses.X64]
   ##  @libraryclass  Provides function to support TDX processing.
   TdxLib|Include/Library/TdxLib.h
 
+[LibraryClasses.RISCV64]
+  ##  @libraryclass  Provides function to make ecalls to SBI
+  BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h
+
 [Guids]
   #
   # GUID defined in UEFI2.1/UEFI2.0/EFI1.1
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index cc1ac196a931..fd08122f441d 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -188,4 +188,7 @@ [Components.ARM, Components.AARCH64]
   MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
   MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
 
+[Components.RISCV64]
+  MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+
 [BuildOptions]
diff --git a/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf 
b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
new file mode 100644
index ..d03132bf01c1
--- /dev/null
+++ b/MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
@@ -0,0 +1,25 @@
+## @file
+# RISC-V Library to call SBI ecalls
+#
+#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION = 0x0001001b
+  BASE_NAME   = BaseRiscVSbiLib
+  FILE_GUID   = D742CF3D-E600-4009-8FB5-318073008508
+  MODULE_TYPE = BASE
+  VERSION_STRING  = 1.0
+  LIBRARY_CLASS   = RiscVSbiLib
+
+[Sources]
+  BaseRiscVSbiLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
diff --git a/MdePkg/Include/Library/BaseRiscVSbiLib.h 
b/MdePkg/Include/Library/BaseRiscVSbiLib.h
new file mode 100644
index ..e9886187526a
--- /dev/null
+++ b/MdePkg/Include/Library/BaseRiscVSbiLib.h
@@ -0,0 +1,127 @@
+/** @file
+  Library to call the RISC-V SBI ecalls
+
+  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- Hart - Hardware Thread, similar to a CPU core
+
+  Currently, EDK2 needs to call SBI only to set the time and to do system 
reset.
+
+**/
+
+#ifndef RISCV_SBI_LIB_H_
+#define RISCV_SBI_LIB_H_
+
+#include 
+
+/* SBI Extension IDs */
+#define SBI_EXT_TIME  0x54494D45
+#define SBI_EXT_SRST  0x53525354
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER  0x0
+
+/* SBI function IDs for SRST extension */
+#define SBI_EXT_SRST_RESET  0x0
+
+#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
+#define SBI_SRST_RESET_TYPE_COLD_REBOOT  0x1
+#define SBI_SRST_RESET_TYPE_WARM_REBOOT  0x2
+#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
+
+#define SBI_SRST_RESET_REASON_NONE 0x0
+#define SBI_SRST_RESET_REASON_SYSFAIL  0x1
+
+/* SBI return error codes */
+#define SBI_SUCCESS0
+#define SBI_ERR_FAILED -1
+#define SBI_ERR_NOT_SUPPORTED  -2
+#define SBI_ERR_INVALID_PARAM  -3
+#define SBI_ERR_DENIED -4
+#define SBI_ERR_INVALID_ADDRESS-5
+#define SBI_ERR_ALREADY_AVAILABLE  -6
+#define SBI_ERR_ALREADY_STARTED-7
+#define SBI_ERR_ALREADY_STOPPED-8
+
+#define SBI_LAST_ERR  SBI_ERR_ALREADY_STOPPED
+
+typedef struct {
+  UINT64BootHartId;
+  VOID  *PeiServiceTable;// PEI Service table
+  UINT64FlattenedDeviceTree; // Pointer to Flattened Device tree
+} EFI_RISCV_FIRMWARE_CONTEXT;
+
+//
+// EDK2 OpenSBI firmware extension return status.
+//
+typedef struct {
+  UINTNError; ///< SBI status code
+  UINTNValue; ///< Value returned
+} SBI_RET;
+
+VOID
+EFIAPI
+SbiSetTimer (
+  IN  UINT64  Time
+  );
+
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+  IN  UINTN  ResetType,
+  IN  UINTN  ResetReason
+  );
+
+/**
+  Get firmware context of the calling hart.
+
+  @param[out] FirmwareContext  The firmware context pointer.
+**/
+VOID
+EFIAPI
+GetFirmwareContext (
+  OUT EFI_RISCV_FIRMWARE_CONTEXT  **FirmwareContext
+  );
+
+/**
+  Set firmware context of the calling hart.
+
+  @param[in] FirmwareContext   The firmware context pointer.
+**/
+VOID

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 07/34] OvmfPkg/ResetSystemLib: Refactor to allow other architectures.

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Currently, the ResetSystemLib library supports only X86 architecture.
Refactor it to allow adding other CPU architectures like RISC-V.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Rebecca Cran 
Cc: Peter Grehan 
Signed-off-by: Sunil V L 
---
 OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf   | 6 +++---
 OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf  | 4 ++--
 .../Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf| 2 +-
 OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf| 6 +++---
 OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf | 4 ++--
 .../ResetSystemLib/{ => Ia32_X64}/BaseResetShutdown.c   | 0
 .../ResetSystemLib/{ => Ia32_X64}/BaseResetShutdownBhyve.c  | 0
 .../ResetSystemLib/{ => Ia32_X64}/DxeResetShutdown.c| 0
 .../{ => Ia32_X64}/DxeResetSystemLibMicrovm.c   | 0
 .../Library/ResetSystemLib/{ => Ia32_X64}/ResetSystemLib.c  | 0
 .../ResetSystemLib/{ => Ia32_X64}/ResetSystemLibMicrovm.c   | 0
 11 files changed, 11 insertions(+), 11 deletions(-)
 rename OvmfPkg/Library/ResetSystemLib/{ => Ia32_X64}/BaseResetShutdown.c (100%)
 rename OvmfPkg/Library/ResetSystemLib/{ => Ia32_X64}/BaseResetShutdownBhyve.c 
(100%)
 rename OvmfPkg/Library/ResetSystemLib/{ => Ia32_X64}/DxeResetShutdown.c (100%)
 rename OvmfPkg/Library/ResetSystemLib/{ => 
Ia32_X64}/DxeResetSystemLibMicrovm.c (100%)
 rename OvmfPkg/Library/ResetSystemLib/{ => Ia32_X64}/ResetSystemLib.c (100%)
 rename OvmfPkg/Library/ResetSystemLib/{ => Ia32_X64}/ResetSystemLibMicrovm.c 
(100%)

diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf 
b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf
index 35d317f1e0b3..4397f90a24dd 100644
--- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf
+++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf
@@ -21,9 +21,9 @@ [Defines]
 #  VALID_ARCHITECTURES   = IA32 X64
 #
 
-[Sources]
-  BaseResetShutdown.c
-  ResetSystemLib.c
+[Sources.IA32, Sources.X64]
+  Ia32_X64/BaseResetShutdown.c
+  Ia32_X64/ResetSystemLib.c
 
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf 
b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf
index 74124aed38e8..3e52a9e3d7f9 100644
--- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf
+++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.inf
@@ -25,8 +25,8 @@ [Defines]
 #
 
 [Sources]
-  BaseResetShutdownBhyve.c
-  ResetSystemLib.c
+  Ia32_X64/BaseResetShutdownBhyve.c
+  Ia32_X64/ResetSystemLib.c
 
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf 
b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf
index 564b1d3022a6..c66720771d82 100644
--- a/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf
+++ b/OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf
@@ -23,7 +23,7 @@ [Defines]
 #
 
 [Sources]
-  ResetSystemLibMicrovm.c
+  Ia32_X64/ResetSystemLibMicrovm.c
 
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf 
b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf
index a9b4ce9a..79478453d7cb 100644
--- a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf
+++ b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf
@@ -23,9 +23,9 @@ [Defines]
 #  VALID_ARCHITECTURES   = IA32 X64
 #
 
-[Sources]
-  DxeResetShutdown.c
-  ResetSystemLib.c
+[Sources.IA32, Sources.X64]
+  Ia32_X64/DxeResetShutdown.c
+  Ia32_X64/ResetSystemLib.c
 
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf 
b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf
index ac9c2599642c..6c79492f816b 100644
--- a/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf
+++ b/OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf
@@ -24,8 +24,8 @@ [Defines]
 #
 
 [Sources]
-  ResetSystemLibMicrovm.c
-  DxeResetSystemLibMicrovm.c
+  Ia32_X64/ResetSystemLibMicrovm.c
+  Ia32_X64/DxeResetSystemLibMicrovm.c
 
 [Packages]
   MdeModulePkg/MdeModulePkg.dec
diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c 
b/OvmfPkg/Library/ResetSystemLib/Ia32_X64/BaseResetShutdown.c
similarity index 100%
rename from OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c
rename to OvmfPkg/Library/ResetSystemLib/Ia32_X64/BaseResetShutdown.c
diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdownBhyve.c 
b/OvmfPkg/Library/ResetSystemLib/Ia32_X64/BaseResetShutdownBhyve.c
similarity index 100%
rename from OvmfPkg/Library/ResetSystemLib/BaseResetShutdownBhyve.c
rename to OvmfPkg/Library/ResetSystemLib/Ia32_X64/BaseResetShutdownBhyve.c
diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c 
b/OvmfPkg/Library/ResetSystemLib/Ia32_X64/DxeResetShutdown.c
similarity index 100%
rename from 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 06/34] OvmfPkg/PlatformInitLib: Add support for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/FdtPeim
but added as part of library instead of a separate module.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 .../PlatformInitLib/PlatformInitLib.inf   |  9 ++-
 OvmfPkg/Include/Library/PlatformInitLib.h |  6 ++
 .../PlatformInitLib/RiscV64/PlatformPeiLib.c  | 73 +++
 3 files changed, 87 insertions(+), 1 deletion(-)
 create mode 100644 OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c

diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf 
b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
index d4449e40af61..ef8675999583 100644
--- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
+++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
@@ -19,7 +19,7 @@ [Defines]
 #
 # The following information is for reference only and not required by the 
build tools.
 #
-#  VALID_ARCHITECTURES   = IA32 X64 EBC
+#  VALID_ARCHITECTURES   = IA32 X64 EBC RISCV64
 #
 
 [Sources.IA32, Sources.X64]
@@ -33,6 +33,9 @@ [Sources.IA32]
 [Sources.X64]
   Ia32_X64/IntelTdx.c
 
+[Sources.RISCV64]
+  RiscV64/PlatformPeiLib.c
+
 [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
@@ -58,6 +61,10 @@ [LibraryClasses.IA32, LibraryClasses.X64]
 [LibraryClasses.X64]
   TdxLib
 
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
+  FdtLib
+
 [Pcd]
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
 
diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h 
b/OvmfPkg/Include/Library/PlatformInitLib.h
index c5234bf26d45..1b8d1fad3b49 100644
--- a/OvmfPkg/Include/Library/PlatformInitLib.h
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -285,4 +285,10 @@ PlatformInitEmuVariableNvStore (
   IN VOID  *EmuVariableNvStore
   );
 
+EFI_STATUS
+EFIAPI
+PlatformPeim (
+  VOID
+  );
+
 #endif // PLATFORM_INIT_LIB_H_
diff --git a/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c 
b/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c
new file mode 100644
index ..c5dbc849
--- /dev/null
+++ b/OvmfPkg/Library/PlatformInitLib/RiscV64/PlatformPeiLib.c
@@ -0,0 +1,73 @@
+/** @file
+The library call to pass the device tree to DXE via HOB.
+
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+ The package level header files this module uses
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+
+/**
+  @retval EFI_SUCCESSThe address of FDT is passed in HOB.
+  EFI_UNSUPPORTEDCan't locate FDT.
+**/
+EFI_STATUS
+EFIAPI
+PlatformPeim (
+  VOID
+  )
+{
+  EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext;
+  VOID*FdtPointer;
+  VOID*Base;
+  VOID*NewBase;
+  UINTN   FdtSize;
+  UINTN   FdtPages;
+  UINT64  *FdtHobData;
+
+  FirmwareContext = NULL;
+  GetFirmwareContextPointer ();
+
+  if (FirmwareContext == NULL) {
+DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__));
+return EFI_UNSUPPORTED;
+  }
+
+  FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
+  if (FdtPointer == NULL) {
+DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));
+return EFI_UNSUPPORTED;
+  }
+
+  DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", 
__FUNCTION__, FdtPointer));
+  Base = FdtPointer;
+  ASSERT (Base != NULL);
+  ASSERT (fdt_check_header (Base) == 0);
+
+  FdtSize  = fdt_totalsize (Base);
+  FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
+  NewBase  = AllocatePages (FdtPages);
+  ASSERT (NewBase != NULL);
+  fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));
+
+  FdtHobData = BuildGuidHob (, sizeof *FdtHobData);
+  ASSERT (FdtHobData != NULL);
+  *FdtHobData = (UINTN)NewBase;
+
+  return EFI_SUCCESS;
+}
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 05/34] OvmfPkg/PlatformInitLib: Refactor to allow other architectures

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Currently, PlatformInitLib supports only X86 architecture. So,
refactor to allow adding other architectures like RISC-V.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Signed-off-by: Sunil V L 
---
 .../PlatformInitLib/PlatformInitLib.inf   | 22 ++-
 .../PlatformInitLib/{ => Ia32_X64}/Cmos.c |  0
 .../PlatformInitLib/{ => Ia32_X64}/IntelTdx.c |  0
 .../{ => Ia32_X64}/IntelTdxNull.c |  0
 .../{ => Ia32_X64}/MemDetect.c|  0
 .../PlatformInitLib/{ => Ia32_X64}/Platform.c |  0
 6 files changed, 12 insertions(+), 10 deletions(-)
 rename OvmfPkg/Library/PlatformInitLib/{ => Ia32_X64}/Cmos.c (100%)
 rename OvmfPkg/Library/PlatformInitLib/{ => Ia32_X64}/IntelTdx.c (100%)
 rename OvmfPkg/Library/PlatformInitLib/{ => Ia32_X64}/IntelTdxNull.c (100%)
 rename OvmfPkg/Library/PlatformInitLib/{ => Ia32_X64}/MemDetect.c (100%)
 rename OvmfPkg/Library/PlatformInitLib/{ => Ia32_X64}/Platform.c (100%)

diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf 
b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
index 86a82ad3e084..d4449e40af61 100644
--- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
+++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
@@ -22,16 +22,16 @@ [Defines]
 #  VALID_ARCHITECTURES   = IA32 X64 EBC
 #
 
-[Sources]
-  Cmos.c
-  MemDetect.c
-  Platform.c
+[Sources.IA32, Sources.X64]
+  Ia32_X64/Cmos.c
+  Ia32_X64/MemDetect.c
+  Ia32_X64/Platform.c
 
 [Sources.IA32]
-  IntelTdxNull.c
+  Ia32_X64/IntelTdxNull.c
 
 [Sources.X64]
-  IntelTdx.c
+  Ia32_X64/IntelTdx.c
 
 [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
@@ -45,12 +45,14 @@ [LibraryClasses]
   DebugLib
   IoLib
   HobLib
+  PcdLib
+  PciLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+  MtrrLib
   QemuFwCfgLib
   QemuFwCfgSimpleParserLib
   MemoryAllocationLib
-  MtrrLib
-  PcdLib
-  PciLib
   PeiHardwareInfoLib
 
 [LibraryClasses.X64]
@@ -100,5 +102,5 @@ [FixedPcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase
   gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize
 
-[FeaturePcd]
+[FeaturePcd.IA32, FeaturePcd.X64]
   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
diff --git a/OvmfPkg/Library/PlatformInitLib/Cmos.c 
b/OvmfPkg/Library/PlatformInitLib/Ia32_X64/Cmos.c
similarity index 100%
rename from OvmfPkg/Library/PlatformInitLib/Cmos.c
rename to OvmfPkg/Library/PlatformInitLib/Ia32_X64/Cmos.c
diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c 
b/OvmfPkg/Library/PlatformInitLib/Ia32_X64/IntelTdx.c
similarity index 100%
rename from OvmfPkg/Library/PlatformInitLib/IntelTdx.c
rename to OvmfPkg/Library/PlatformInitLib/Ia32_X64/IntelTdx.c
diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c 
b/OvmfPkg/Library/PlatformInitLib/Ia32_X64/IntelTdxNull.c
similarity index 100%
rename from OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c
rename to OvmfPkg/Library/PlatformInitLib/Ia32_X64/IntelTdxNull.c
diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c 
b/OvmfPkg/Library/PlatformInitLib/Ia32_X64/MemDetect.c
similarity index 100%
rename from OvmfPkg/Library/PlatformInitLib/MemDetect.c
rename to OvmfPkg/Library/PlatformInitLib/Ia32_X64/MemDetect.c
diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c 
b/OvmfPkg/Library/PlatformInitLib/Ia32_X64/Platform.c
similarity index 100%
rename from OvmfPkg/Library/PlatformInitLib/Platform.c
rename to OvmfPkg/Library/PlatformInitLib/Ia32_X64/Platform.c
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34] MdePkg/BaseLib: RISC-V: Add few more helper functions

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Few of the basic helper functions required for any
RISC-V CPU were added in edk2-platforms. To support
qemu virt, they need to be added in BaseLib.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Daniel Schaefer 
Signed-off-by: Sunil V L 
---
 MdePkg/Library/BaseLib/BaseLib.inf|  2 +
 MdePkg/Include/Library/BaseLib.h  | 50 +
 MdePkg/Library/BaseLib/RiscV64/CpuScratch.S   | 31 +++
 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S| 24 +
 .../Library/BaseLib/RiscV64/RiscVInterrupt.S  | 53 +--
 5 files changed, 156 insertions(+), 4 deletions(-)
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 6be5be9428f2..86d7bb080971 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -401,6 +401,8 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
   RiscV64/FlushCache.S  | GCC
+  RiscV64/CpuScratch.S  | GCC
+  RiscV64/ReadTimer.S   | GCC
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index a6f9a194ef1c..9724b84eef89 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -150,6 +150,56 @@ typedef struct {
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
 
+VOID
+  RiscVSetSupervisorScratch (
+ UINT64
+ );
+
+UINT64
+RiscVGetSupervisorScratch (
+  VOID
+  );
+
+VOID
+  RiscVSetSupervisorStvec (
+   UINT64
+   );
+
+UINT64
+RiscVGetSupervisorStvec (
+  VOID
+  );
+
+UINT64
+RiscVGetSupervisorTrapCause (
+  VOID
+  );
+
+VOID
+  RiscVSetSupervisorAddressTranslationRegister (
+UINT64
+);
+
+UINT64
+RiscVReadTimer (
+  VOID
+  );
+
+VOID
+RiscVEnableTimerInterrupt (
+  VOID
+  );
+
+VOID
+RiscVDisableTimerInterrupt (
+  VOID
+  );
+
+VOID
+RiscVClearPendingTimerInterrupt (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 //
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S 
b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
new file mode 100644
index ..dd7adc21eb07
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
@@ -0,0 +1,31 @@
+//--
+//
+// CPU scratch register related functions for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//--
+
+#include 
+
+.data
+.align 3
+.section .text
+
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+csrrw a1, CSR_SSCRATCH, a0
+ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+csrr a0, CSR_SSCRATCH
+ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S 
b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
new file mode 100644
index ..bdddb67618ab
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
@@ -0,0 +1,24 @@
+//--
+//
+// Read CPU timer
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//--
+
+#include 
+
+.data
+.align 3
+.section .text
+
+//
+// Read TIME CSR.
+// @retval a0 : 64-bit timer.
+//
+ASM_FUNC (RiscVReadTimer)
+csrr a0, CSR_TIME
+ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S 
b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
index 87b3468fc7fd..6a1b90a7e45c 100644
--- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
@@ -8,13 +8,13 @@
 //
 
//--
 
+#include 
+
 ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
 ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
 ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
 
-#define  SSTATUS_SIE 0x0002
-#define  CSR_SSTATUS 0x100
-  #define  SSTATUS_SPP_BIT_POSITION  8
+#define  SSTATUS_SPP_BIT_POSITION  8
 
 //
 // This routine disables supervisor mode interrupt
@@ -53,11 +53,56 @@ 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 02/34] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add this protocol GUID definition and the header file required.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Sunil V L 
---
 MdePkg/MdePkg.dec   |  6 
 MdePkg/Include/Protocol/RiscVBootProtocol.h | 32 +
 2 files changed, 38 insertions(+)
 create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index f1ebf9e251c1..8f1bcfdc3e97 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -1915,6 +1915,12 @@ [Protocols]
   ## Include/Protocol/ShellDynamicCommand.h
   gEfiShellDynamicCommandProtocolGuid  = { 0x3c7200e9, 0x005f, 0x4ea4, {0x87, 
0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }}
 
+  #
+  # Protocols defined for RISC-V systems
+  #
+  ## Include/Protocol/RiscVBootProtocol.h
+  gRiscVEfiBootProtocolGuid  = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 
0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
+
 #
 # [Error.gEfiMdePkgTokenSpaceGuid]
 #   0x8001 | Invalid value provided.
diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h 
b/MdePkg/Include/Protocol/RiscVBootProtocol.h
new file mode 100644
index ..cb94f61cd46c
--- /dev/null
+++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h
@@ -0,0 +1,32 @@
+/** @file
+  RISC-V Boot Protocol mandatory for RISC-V UEFI platforms.
+
+  Specification available at
+   https://github.com/riscv-non-isa/riscv-uefi
+
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_BOOT_PROTOCOL_H_
+#define RISCV_BOOT_PROTOCOL_H_
+
+typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL;
+
+#define RISCV_EFI_BOOT_PROTOCOL_REVISION  0x0001
+#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \
+RISCV_EFI_BOOT_PROTOCOL_REVISION
+
+typedef EFI_STATUS
+(EFIAPI *EFI_GET_BOOT_HARTID)(
+  IN RISCV_EFI_BOOT_PROTOCOL   *This,
+  OUT UINTN*BootHartId
+  );
+
+typedef struct _RISCV_EFI_BOOT_PROTOCOL {
+  UINT64 Revision;
+  EFI_GET_BOOT_HARTIDGetBootHartId;
+} RISCV_EFI_BOOT_PROTOCOL;
+
+#endif
-- 
2.25.1



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[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34] MdePkg/Register: Add register definition header files for RISC-V

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.

Cc: Daniel Schaefer 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Signed-off-by: Sunil V L 
---
 .../Include/Register/RiscV64/RiscVEncoding.h  | 125 ++
 MdePkg/Include/Register/RiscV64/RiscVImpl.h   |  25 
 2 files changed, 150 insertions(+)
 create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h
 create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h

diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h 
b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
new file mode 100644
index ..434436b37fcf
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -0,0 +1,125 @@
+/** @file
+  RISC-V CSR encodings
+
+  Copyright (c) 2019, Western Digital Corporation or its affiliates. All 
rights reserved.
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_ENCODING_H_
+#define RISCV_ENCODING_H_
+
+/* clang-format off */
+#define MSTATUS_SIE 0x0002UL
+#define MSTATUS_MIE 0x0008UL
+#define MSTATUS_SPIE_SHIFT  5
+#define MSTATUS_SPIE(1UL << MSTATUS_SPIE_SHIFT)
+#define MSTATUS_UBE 0x0040UL
+#define MSTATUS_MPIE0x0080UL
+#define MSTATUS_SPP_SHIFT   8
+#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
+#define MSTATUS_MPP_SHIFT   11
+#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
+
+#define SSTATUS_SIE MSTATUS_SIE
+#define SSTATUS_SPIE_SHIFT  MSTATUS_SPIE_SHIFT
+#define SSTATUS_SPIEMSTATUS_SPIE
+#define SSTATUS_SPP_SHIFT   MSTATUS_SPP_SHIFT
+#define SSTATUS_SPP MSTATUS_SPP
+
+#define IRQ_S_SOFT1
+#define IRQ_VS_SOFT   2
+#define IRQ_M_SOFT3
+#define IRQ_S_TIMER   5
+#define IRQ_VS_TIMER  6
+#define IRQ_M_TIMER   7
+#define IRQ_S_EXT 9
+#define IRQ_VS_EXT10
+#define IRQ_M_EXT 11
+#define IRQ_S_GEXT12
+#define IRQ_PMU_OVF   13
+
+#define MIP_SSIP(1UL << IRQ_S_SOFT)
+#define MIP_VSSIP   (1UL << IRQ_VS_SOFT)
+#define MIP_MSIP(1UL << IRQ_M_SOFT)
+#define MIP_STIP(1UL << IRQ_S_TIMER)
+#define MIP_VSTIP   (1UL << IRQ_VS_TIMER)
+#define MIP_MTIP(1UL << IRQ_M_TIMER)
+#define MIP_SEIP(1UL << IRQ_S_EXT)
+#define MIP_VSEIP   (1UL << IRQ_VS_EXT)
+#define MIP_MEIP(1UL << IRQ_M_EXT)
+#define MIP_SGEIP   (1UL << IRQ_S_GEXT)
+#define MIP_LCOFIP  (1UL << IRQ_PMU_OVF)
+
+#define SIP_SSIP  MIP_SSIP
+#define SIP_STIP  MIP_STIP
+
+#define PRV_U  0UL
+#define PRV_S  1UL
+#define PRV_M  3UL
+
+#define SATP64_MODE  0xF000ULL
+#define SATP64_ASID  0x0000ULL
+#define SATP64_PPN   0x0FFFULL
+
+#define SATP_MODE_OFF   0UL
+#define SATP_MODE_SV32  1UL
+#define SATP_MODE_SV39  8UL
+#define SATP_MODE_SV48  9UL
+#define SATP_MODE_SV57  10UL
+#define SATP_MODE_SV64  11UL
+
+#define SATP_MODE  SATP64_MODE
+
+/* = User-level CSRs = */
+
+/* User Counters/Timers */
+#define CSR_CYCLE  0xc00
+#define CSR_TIME   0xc01
+
+/* = Supervisor-level CSRs = */
+
+/* Supervisor Trap Setup */
+#define CSR_SSTATUS  0x100
+#define CSR_SEDELEG  0x102
+#define CSR_SIDELEG  0x103
+#define CSR_SIE  0x104
+#define CSR_STVEC0x105
+
+/* Supervisor Configuration */
+#define CSR_SENVCFG  0x10a
+
+/* Supervisor Trap Handling */
+#define CSR_SSCRATCH  0x140
+#define CSR_SEPC  0x141
+#define CSR_SCAUSE0x142
+#define CSR_STVAL 0x143
+#define CSR_SIP   0x144
+
+/* Supervisor Protection and Translation */
+#define CSR_SATP  0x180
+
+/* = Trap/Exception Causes = */
+
+#define CAUSE_MISALIGNED_FETCH  0x0
+#define CAUSE_FETCH_ACCESS  0x1
+#define CAUSE_ILLEGAL_INSTRUCTION   0x2
+#define CAUSE_BREAKPOINT0x3
+#define CAUSE_MISALIGNED_LOAD   0x4
+#define CAUSE_LOAD_ACCESS   0x5
+#define CAUSE_MISALIGNED_STORE  0x6
+#define CAUSE_STORE_ACCESS  0x7
+#define CAUSE_USER_ECALL0x8
+#define CAUSE_SUPERVISOR_ECALL  0x9
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL  0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT  0xc
+#define CAUSE_LOAD_PAGE_FAULT   0xd
+#define CAUSE_STORE_PAGE_FAULT  0xf
+#define CAUSE_FETCH_GUEST_PAGE_FAULT0x14
+#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
+#define CAUSE_VIRTUAL_INST_FAULT0x16
+#define CAUSE_STORE_GUEST_PAGE_FAULT0x17
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h 
b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
new file mode 100644
index ..ee5c2ba60377
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -0,0 +1,25 @@
+/** @file
+  RISC-V package definitions.
+
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All 
rights reserved.
+
+  SPDX-License-Identifier: 

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 00/34] Add support for RISC-V virt machine

[Sunil V L]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add support for RISC-V qemu virt machine. Most of the changes are migrated from
edk2-platforms repo and followed the latest guidelines for EDK2 code 
structuring.

The changes at a high level are,

1) MdePkg:
- Add RISC-V register definitions
- Add RISCV_EFI_BOOT_PROTOCOL related definitions
- Add BaseRiscVSbiLib library to make ecall to machine mode firmware
- Created Null instance of the NorFlashPlatformLib library class
- Moved NorFlashPlatformLib.h from ArmPlatformPkg

2) UefiCpuPkg:
- Refactor modules/libraries as per latest guidelines
- Add RISC-V support in below modules/libraries.
- CpuTimerLib, CpuExceptionHandlerLib, CpuDxe
- Add new CpuTimerDxe module

3) ArmVirtPkg:
- Migrate below libraries/modules to OvmfPkg
- PlatformBootManagerLib, PlatformHasAcpiDtDxe
- Fix up the consumers of these modules

4) OvmfPkg:
- Refactor the libraries/modules as per latest guidelines
- Add RISC-V support for below libraries/modules.
- Sec, ResetSystemLib, PlatformInitLib, PlatformPei
- Add optimized version of NorFlashDxe driver
- Add NorFlashQemuLib (Copied from ArmVirtPkg and SbsaQemu)
- Add new DSC/FDF files to build for RISC-V virt machine

5) MdeModulePkg/EmbeddedPkg:
- Migrated NvVarStoreFormattedLib from EmbeddedPkg to MdeModulePkg
- Fix up the consumers of NvVarStoreFormattedLib
 
Changes since V2:
1) Fixed issues detected by CI 
(https://github.com/tianocore/edk2/pull/3471)
2) Added an extra patch to fix up the consumers of 
NvVarStoreFormattedLib

Changes since V1:
1) Added couple of patches from Ard to optimize the NorFlashDxe in Ovmf.
   Note: There will be a separate patch series in future to update 
existing
   consumers of NorFlashDxe driver.
2) Migrated NvVarStoreFormattedLib from EmbeddedPkg to MdeModulePkg
3) Created Null instance of the NorFlashPlatformLib library class
4) Moved NorFlashPlatformLib.h from ArmPlatformPkg

These changes are available at: 
https://github.com/vlsunil/edk2/tree/RiscV64QemuVirt

The changes are tested on risc-v qemu with an additional patch series to
enable pflash available at https://github.com/vlsunil/qemu/tree/pflash_v3

Cc: Abner Chang 
Cc: Daniel Schaefer 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Rebecca Cran 
Cc: Peter Grehan 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Min Xu 
Cc: Tom Lendacky 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Andrew Fish 
Cc: Jian J Wang 
Cc: Anup Patel 
Cc: Heinrich Schuchardt 

Sunil V L (34):
  MdePkg/Register: Add register definition header files for RISC-V
  MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions
  MdePkg/BaseLib: RISC-V: Add few more helper functions
  MdePkg: Add BaseRiscVSbiLib Library for RISC-V
  OvmfPkg/PlatformInitLib: Refactor to allow other architectures
  OvmfPkg/PlatformInitLib: Add support for RISC-V
  OvmfPkg/ResetSystemLib: Refactor to allow other architectures.
  OvmfPkg/ResetSystemLib: Add support for RISC-V
  OvmfPkg/Sec: Refactor to allow other architectures
  OvmfPkg/Sec: Add RISC-V support
  OvmfPkg/PlatformPei: Refactor to allow other architectures
  OvmfPkg/PlatformPei: Add support for RISC-V
  UefiCpuPkg/CpuTimerLib: Refactor to allow other architectures
  UefiCpuPkg/CpuTimerLib: Add support for RISC-V
  UefiCpuPkg/CpuExceptionHandlerLib: Refactor to allow other
architectures
  UefiCpuPkg/CpuExceptionHandlerLib: Add support for RISC-V
  UefiCpuPkg/CpuDxe: Refactor to allow other architectures
  UefiCpuPkg/CpuDxe: Add support for RISC-V
  UefiCpuPkg/CpuDxe: Add RISC-V Boot protocol support
  UefiCpuPkg: Add CpuTimerDxe module
  ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg
  ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe
  ArmVirtPkg/PlatformBootManagerLib: Move to OvmfPkg
  ArmVirtPkg: Fix up the paths to PlatformBootManagerLib
  ArmPlatformPkg/NorFlashPlatformLib.h:Move to MdePkg
  EmbeddedPkg/NvVarStoreFormattedLib: Migrate to MdeModulePkg
  ArmVirtPkg: Update the references to NvVarStoreFormattedLib
  OvmfPkg: Add NorFlashQemuLib library
  OvmfPkg: Add Qemu NOR flash DXE driver
  OvmfPkg/NorFlashDxe: Avoid switching to array mode during writes
  OvmfPkg/NorFlashDxe: Avoid switching between modes in a tight loop
  OvmfPkg: RiscVVirt: Add Qemu Virt platform support
  Maintainers.txt: Add entry for OvmfPkg/RiscVVirt
  UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file

 ArmPlatformPkg/ArmPlatformPkg.dec |   4 -
 ArmVirtPkg/ArmVirtPkg.dec |   9 -
 EmbeddedPkg/EmbeddedPkg.dec   |   3 -
 MdeModulePkg/MdeModulePkg.dec |   3 +
 MdePkg/MdePkg.dec