[PATCH rtems-lwip v1 0/9] Bring in devel patches and add ZynqMP

[Kinsey Moore]

This brings in a significantly cleaned up version of the remaining
patches on the devel branch and adds support for ZynqMP CGEMs. I have
tested CGEM0 on QEMU and CGEM3 on hardware. I am unable to test on the
BeagleBoneBlack at the moment, so I'd appreciate a double-check to
ensure I haven't broken it.


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[PATCH rtems-lwip v1 1/9] uLan: Update sys_arch and fix additions

[Kinsey Moore]

This updates sys_arch.c and sys_arch.h to the latest versions from the
upstream repository at hash 9e6ce84f2071bf0fbe3922db1cacf00823b2bdc1 and
updates the modifications to be compliant with how this project handles
modifications to upstream sources.
---
 uLan/ports/os/rtems/arch/sys_arch.c |  7 ++-
 uLan/ports/os/rtems/arch/sys_arch.h | 25 +++--
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/uLan/ports/os/rtems/arch/sys_arch.c 
b/uLan/ports/os/rtems/arch/sys_arch.c
index ca7f8be..fa344a1 100644
--- a/uLan/ports/os/rtems/arch/sys_arch.c
+++ b/uLan/ports/os/rtems/arch/sys_arch.c
@@ -269,7 +269,11 @@ sys_thread_new(const char *name, lwip_thread_fn function, 
void *arg, int stack_s
   rtems_status_code res;
 
   res = rtems_task_create(
+#ifdef __rtems__
+rtems_build_name(name[0], name[1], name[2], name[3]),
+#else
 rtems_build_name('L', 'W', 'I', 'P'),
+#endif
 prio,
 stack_size,
 RTEMS_PREEMPT,
@@ -356,6 +360,7 @@ sys_request_irq(unsigned int irqnum, sys_irq_handler_t 
handler,
   return (res != RTEMS_SUCCESSFUL) ? -1 : 0;
 }
 
+#ifdef __rtems__
 sys_prot_t
 sys_arch_protect()
 {
@@ -375,4 +380,4 @@ sys_mbox_trypost_fromisr(sys_mbox_t *q, void *msg)
 {
   return sys_mbox_trypost(q, msg);
 }
-
+#endif
diff --git a/uLan/ports/os/rtems/arch/sys_arch.h 
b/uLan/ports/os/rtems/arch/sys_arch.h
index c89abd4..a80244d 100644
--- a/uLan/ports/os/rtems/arch/sys_arch.h
+++ b/uLan/ports/os/rtems/arch/sys_arch.h
@@ -41,9 +41,8 @@
 
 #include 
 #include 
-#include 
 #include 
-//#include "eth_lwip_default.h"
+#include "arch/eth_lwip_default.h"
 
 /* Typedefs for the various port-specific types. */
 #if defined(NO_SYS) && NO_SYS
@@ -101,8 +100,30 @@ sys_arch_unmask_interrupt_source(unsigned int x)
   bsp_interrupt_vector_enable(x);
 }
 
+#ifndef __rtems__
+static inline sys_prot_t
+sys_arch_protect(void)
+{
+  sys_prot_t pval;
+
+  rtems_interrupt_disable(pval);
+  return pval;
+}
+
+static inline void
+sys_arch_unprotect(sys_prot_t pval)
+{
+  rtems_interrupt_enable(pval);
+}
+
+static inline void
+sys_arch_data_sync_barier(void){
+  _ARM_Data_synchronization_barrier();
+}
+#else
 sys_prot_t sys_arch_protect();
 
 void sys_arch_unprotect(sys_prot_t pval);
+#endif
 
 #endif /* __ARCH_SYS_ARCH_H__ */
-- 
2.30.2

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Re: [tools] tester: Normalize JSON and YAML reports

[Kinsey Moore]

On 6/30/2022 01:34, Sebastian Huber wrote:



On 30/06/2022 07:58, Sebastian Huber wrote:

On 29/06/2022 17:54, Kinsey Moore wrote:

On 6/29/2022 04:34, Sebastian Huber wrote:

On 29/06/2022 11:20, Chris Johns wrote:


On 29 Jun 2022, at 4:42 pm, Sebastian Huber 
 wrote:


On 29/06/2022 08:40, Sebastian Huber wrote:
Report the same data in JSON and YAML reports.  Do not report 
redundant

information.
Update 4671.


This patch changes the JSON reports. Are there already consumers 
for the JSON reports so that we have to be backward compatible?


Could compatibility be added back in if this proves to be an issue?

I am wondering if that could be considered if comparability 
becomes an issue.


The JSON report was added by:

commit 5fcaf843bdb491e2da14dc1af61806ac6d20bae5
Author: Kinsey Moore 
Date:   Wed Aug 21 16:34:12 2019 +

    Add JSON log generation

    Add log formatter hooks and JSON log formatter to the test 
infrastructure

    for consumption by automated processes or report generators.


I am not sure if these automated processes or report generators 
already exist.


The existing attribute names are quite inconsistent, for example 
"Command Line", "passed_count", "wrong-version_count". I would use 
lower case only with "-" as a separator. The JSON report should 
contain all information of a test run.


The new report looks like this:

{
    "command-line": [
    "/opt/rtems/6/bin/rtems-test",
    "--rtems-bsp=xilinx_zynq_a9_qemu",
    "--report-format=json",
    "--report-path=report",
    "build/arm/xilinx_zynq_a9_qemu/testsuites/samples/"
    ],
    "end-time": "2022-06-28T14:08:47.595131",
    "host": 
"Linux-5.3.18-150300.59.76-default-x86_64-with-glibc2.3.4 (Linux 
lupus 5.3.18-150300.59.76-default #1 SMP Thu Jun 16 04:23:47 UTC 
2022 (2cc2ade) x86_64 x86_64)",

    "python": "3.6.15 (default, Sep 23 2021, 15:41:43) [GCC]",
    "reports": [
    {
    "arch": "arm",
    "bsp": "xilinx_zynq_a9_qemu",
    "command-line": "qemu-system-arm -no-reboot -nographic 
-net none -serial null -serial mon:stdio -M xilinx-zynq-a9 -m 256M 
-kernel build/arm/xilinx_zynq_a9_qemu/testsuites/samples/cdtest.exe",

    "end-time": "2022-06-28T12:08:48.161691+00:00",
    "executable": 
"build/arm/xilinx_zynq_a9_qemu/testsuites/samples/cdtest.exe",
    "executable-sha512": 
"413bc8a506053c95a0e1d93942cce9fd0d653f7b3cde42623085ce147aea324f4baeff7ce0102008322fb1341bc2b38defd3925a64144e47e13cc5f32185bf78", 


    "output": [
    "qemu-system-arm: warning: nic cadence_gem.0 has no 
peer",
    "qemu-system-arm: warning: nic cadence_gem.1 has no 
peer",

    "",
    "",
    "*** BEGIN OF TEST CONSTRUCTOR/DESTRUCTOR ***",
    "*** TEST VERSION: 
6.0.0.3302b72754df5f37214e86dd68522189857772c7",

    "*** TEST STATE: EXPECTED_PASS",
    "*** TEST BUILD: RTEMS_DEBUG RTEMS_POSIX_API",
    "*** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB 
bf3f66c29a046ec1c5029e4f919b525947df6245, Newlib e7ffbdb)",
    "GLOBAL: Hey I'm in base class constructor number 1 
for 0x214474.",
    "GLOBAL: Hey I'm in base class constructor number 2 
for 0x214480.",
    "GLOBAL: Hey I'm in derived class constructor 
number 3 for 0x214480.",
    "LOCAL: Hey I'm in base class constructor number 4 
for 0x228864.",

    ...


"WRoZqtoO3A8BDJkUSmRGNOBaaHW1UwAAoQGQAQwAAABck8Bx+K/znDWWTEcA", 



"AKEB2P///wEMVP6TRqQZY+4+srvAAAChAfD///8BDMXOxS0Rhzqx6Old2wAA", 



"oQH4AQwAAADJyx1ZCnZ4l+m/XkMAAKEB0P///wEMN3+9YAwMW8gTHIoPAACh", 



"Adj///8BDBtxsj3zXZF/+UqzfAAAoQHwAQwwMDMeE7mphT6yu8AAAKEB", 


"8P///wEMr2rLCcwzVnf5SrN8AAChAfD///8A",
    "*** END OF GCOV INFO BASE64 ***",
    ""
    ],
    "result": "passed",
    "start-time": "2022-06-28T12:08:47.721822+00:00"
    }
    ],
    "start-time": "2022-06-28T14:08:47.595131"
}

There are no publicly available report generators for the existing 
format, but I do have one I use to generate STR documents for 
delivery using mustache templates and further processing. The 
existing format was designed to be easily consumable by that and 
other simple templating mechanisms by providing structure (t

Re: [tools] tester: Normalize JSON and YAML reports

[Kinsey Moore]

On 6/29/2022 04:34, Sebastian Huber wrote:

On 29/06/2022 11:20, Chris Johns wrote:


On 29 Jun 2022, at 4:42 pm, Sebastian Huber 
 wrote:


On 29/06/2022 08:40, Sebastian Huber wrote:
Report the same data in JSON and YAML reports.  Do not report 
redundant

information.
Update 4671.


This patch changes the JSON reports. Are there already consumers for 
the JSON reports so that we have to be backward compatible?


Could compatibility be added back in if this proves to be an issue?

I am wondering if that could be considered if comparability becomes 
an issue.


The JSON report was added by:

commit 5fcaf843bdb491e2da14dc1af61806ac6d20bae5
Author: Kinsey Moore 
Date:   Wed Aug 21 16:34:12 2019 +

    Add JSON log generation

    Add log formatter hooks and JSON log formatter to the test 
infrastructure

    for consumption by automated processes or report generators.


I am not sure if these automated processes or report generators 
already exist.


The existing attribute names are quite inconsistent, for example 
"Command Line", "passed_count", "wrong-version_count". I would use 
lower case only with "-" as a separator. The JSON report should 
contain all information of a test run.


The new report looks like this:

{
    "command-line": [
    "/opt/rtems/6/bin/rtems-test",
    "--rtems-bsp=xilinx_zynq_a9_qemu",
    "--report-format=json",
    "--report-path=report",
    "build/arm/xilinx_zynq_a9_qemu/testsuites/samples/"
    ],
    "end-time": "2022-06-28T14:08:47.595131",
    "host": "Linux-5.3.18-150300.59.76-default-x86_64-with-glibc2.3.4 
(Linux lupus 5.3.18-150300.59.76-default #1 SMP Thu Jun 16 04:23:47 
UTC 2022 (2cc2ade) x86_64 x86_64)",

    "python": "3.6.15 (default, Sep 23 2021, 15:41:43) [GCC]",
    "reports": [
    {
    "arch": "arm",
    "bsp": "xilinx_zynq_a9_qemu",
    "command-line": "qemu-system-arm -no-reboot -nographic 
-net none -serial null -serial mon:stdio -M xilinx-zynq-a9 -m 256M 
-kernel build/arm/xilinx_zynq_a9_qemu/testsuites/samples/cdtest.exe",

    "end-time": "2022-06-28T12:08:48.161691+00:00",
    "executable": 
"build/arm/xilinx_zynq_a9_qemu/testsuites/samples/cdtest.exe",
    "executable-sha512": 
"413bc8a506053c95a0e1d93942cce9fd0d653f7b3cde42623085ce147aea324f4baeff7ce0102008322fb1341bc2b38defd3925a64144e47e13cc5f32185bf78",

    "output": [
    "qemu-system-arm: warning: nic cadence_gem.0 has no 
peer",
    "qemu-system-arm: warning: nic cadence_gem.1 has no 
peer",

    "",
    "",
    "*** BEGIN OF TEST CONSTRUCTOR/DESTRUCTOR ***",
    "*** TEST VERSION: 
6.0.0.3302b72754df5f37214e86dd68522189857772c7",

    "*** TEST STATE: EXPECTED_PASS",
    "*** TEST BUILD: RTEMS_DEBUG RTEMS_POSIX_API",
    "*** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB 
bf3f66c29a046ec1c5029e4f919b525947df6245, Newlib e7ffbdb)",
    "GLOBAL: Hey I'm in base class constructor number 1 
for 0x214474.",
    "GLOBAL: Hey I'm in base class constructor number 2 
for 0x214480.",
    "GLOBAL: Hey I'm in derived class constructor number 3 
for 0x214480.",
    "LOCAL: Hey I'm in base class constructor number 4 for 
0x228864.",

    ...


"WRoZqtoO3A8BDJkUSmRGNOBaaHW1UwAAoQGQAQwAAABck8Bx+K/znDWWTEcA", 



"AKEB2P///wEMVP6TRqQZY+4+srvAAAChAfD///8BDMXOxS0Rhzqx6Old2wAA", 



"oQH4AQwAAADJyx1ZCnZ4l+m/XkMAAKEB0P///wEMN3+9YAwMW8gTHIoPAACh", 



"Adj///8BDBtxsj3zXZF/+UqzfAAAoQHwAQwwMDMeE7mphT6yu8AAAKEB", 


"8P///wEMr2rLCcwzVnf5SrN8AAChAfD///8A",
    "*** END OF GCOV INFO BASE64 ***",
    ""
    ],
    "result": "passed",
    "start-time": "2022-06-28T12:08:47.721822+00:00"
    }
    ],
    "start-time": "2022-06-28T14:08:47.595131"
}

There are no publicly available report generators for the existing 
format, but I do have one I use to generate STR documents for delivery 
using mustache templates and further processing. The existing format was 
designed to be easily consumable by that and other simple templating 
mechanisms by providing structure (test subsets) and precalculating 
values that would otherwise be implicit in the data. Changes to the 
names of various fields should be 

Re: [PATCH] arm/gicv3: Fix building arm/r52

[Kinsey Moore]

On 6/27/2022 01:27, Sebastian Huber wrote:

On 27/06/2022 05:02, Chris Johns wrote:

On 24/6/2022 7:44 pm, Sebastian Huber wrote:

On 20.06.22 04:03, chr...@rtems.org wrote:

From: Chris Johns 

---
   bsps/include/dev/irq/arm-gicv3.h | 5 +
   1 file changed, 5 insertions(+)

diff --git a/bsps/include/dev/irq/arm-gicv3.h 
b/bsps/include/dev/irq/arm-gicv3.h

index a79368ebdf..aac02fa191 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -335,7 +335,12 @@ static void gicv3_init_cpu_interface(uint32_t 
cpu_index)

 }
       /* Enable interrupt groups 0 and 1 */
+#ifdef ARM_MULTILIB_ARCH_V4
+  WRITE_SR(ICC_IGRPEN0, 0x1);
+  WRITE_SR(ICC_IGRPEN1, 0x1);
+#else
 gic_icc_write(IGRPEN1, 1);
+#endif
 WRITE_SR(ICC_CTLR, 0x0);
   }


I have a different patch to fix this:

https://lists.rtems.org/pipermail/devel/2022-June/072056.html


Does this change work on a real aarch64 with a suitably configured 
TF-A? The
security profile of the TF-A needs to disable EL1 access to these 
registers to

see the issue.


I don't have a hardware to test this change. I can do tests on a 
Cortex-R52 hardware.


For the Cortex-R52, group 0 interrupts are signaled through FIQ 
exceptions and group 1 interrupts are signaled through IRQ exceptions. 
This processor has no secore/non-secure states.
I have reverified that this code works on my ZCU102 (ZynqMP) dev board 
with just the write to IGRPEN1, but I'm not sure it's what Chris would 
consider a suitably configured TF-A since it's a bit stale.



Kinsey

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Re: [PATCH] irq/arm-gicv3.h: Enable interrupt groups 0 and 1

[Kinsey Moore]

On 6/26/2022 22:37, Chris Johns wrote:

On 24/6/2022 7:43 pm, Sebastian Huber wrote:

The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
define) and AArch64 targets.  Use the existing WRITE_SR() abstraction to access
the interrupt group 0 and 1 enable registers.  This fixes the build for the
AArch32 target.

It needs to be tested on hardware before I am OK with it. It also needs EL3
firmware, ie TF-A, to correctly initialise a system.

I would be OK with qemu if it can be shown it honours the security level
correctly. I however have no time to determine this as I have Versal hardware
that did not like the changes.
I, unfortunately, have no way to test this on hardware but I would 
agree. I would not be inclined to trust qemu in this regard.

---
  bsps/include/dev/irq/arm-gicv3.h | 23 ++-
  1 file changed, 6 insertions(+), 17 deletions(-)

diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index a79368ebdf..7db7bad034 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -116,9 +116,11 @@ extern "C" {
  #else /* ARM_MULTILIB_ARCH_V4 */
  
  /* AArch64 GICv3 registers are not named in GCC */

The FreeBSD would suggest this is not entirely true? May be it is for aarch32?
IIRC, a select few were named and usable in GCC, but the vast majority 
were not. This may have gotten better with more recent GCC releases 
since this comment was written more than 2 years ago.



-#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
-#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
+#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0"
+#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0"

This looks like it is only a label change and so it is the same opcode. Is that
correct?

According to the ARMv8 TRM, this is the full proper name for it.



  #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
+#define ICC_IGRPEN0 ICC_IGRPEN0_EL1
+#define ICC_IGRPEN1 ICC_IGRPEN1_EL1
  #define ICC_PMR "S3_0_C4_C6_0, %0"
  #define ICC_EOIR1   "S3_0_C12_C12_1, %0"
  #define ICC_SRE "S3_0_C12_C12_5, %0"
@@ -300,20 +302,6 @@ static void gicv3_init_dist(volatile gic_dist *dist)
}
  }
  
-/*

- * A better way to access these registers than special opcodes
- */
-#define isb() __asm __volatile("isb" : : : "memory")
-
-#define  WRITE_SPECIALREG(reg, _val)\
-  __asm __volatile("msr  " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
-
-#define  gic_icc_write(reg, val)\
-do {\
-  WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \
-  isb();\
-} while (0)
-
  static void gicv3_init_cpu_interface(uint32_t cpu_index)
  {
uint32_t sre_value = 0x7;
@@ -335,7 +323,8 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
}
  
/* Enable interrupt groups 0 and 1 */

-  gic_icc_write(IGRPEN1, 1);'

This has been tested and works on a Versal.


+  WRITE_SR(ICC_IGRPEN0, 0x1);

This crashed in EL1 on a Versal with 2021.2 TF-A.

Why do you need to set this here?


+  WRITE_SR(ICC_IGRPEN1, 0x1);

This instruction also generated an exception. It has been a while but I am
pretty sure I had to comment this one and when I did no interrupts happened. The
code I ported from FreeBSD worked.

I also think the FreeBSD calls are easier to review and so maintain. I find
those ARM type registers difficult to find and check.
The opcode S3_0_C12_C12_7 should be identical in behavior and assembly 
with the name ICC_IGRPEN1_EL1. It's spelled out in the ARMv8 TRM on 
D12-3006.


Kinsey

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Re: [PATCH 1/3] bsp/aarch64: Flush the cache before invalidating it

[Kinsey Moore]

Looks good.

On 6/13/2022 20:39, chr...@rtems.org wrote:

From: Chris Johns 

- Any page tables need to be flushed if the cache is enabled.
   Disabling the cache may only be available in secure mode.
---
  bsps/aarch64/include/bsp/aarch64-mmu.h | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h 
b/bsps/aarch64/include/bsp/aarch64-mmu.h
index b1a471d534..6e589cd6cd 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -362,7 +362,8 @@ aarch64_mmu_enable( void )
  
/* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
  
-  /* Invalidate cache */

+  /* Flush and invalidate cache */
+  rtems_cache_flush_entire_data();
rtems_cache_invalidate_entire_data();
  
/* Enable MMU and cache */

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Re: [PATCH 3/3] aarch64/gicv3: Remove accesses to secure registers

[Kinsey Moore]

On 6/15/2022 09:51, Gedare Bloom wrote:

On Tue, Jun 14, 2022 at 6:56 PM Chris Johns  wrote:

On 14/6/2022 11:44 pm, Gedare Bloom wrote:

On Mon, Jun 13, 2022 at 7:39 PM  wrote:

From: Chris Johns 

---
  bsps/include/dev/irq/arm-gicv3.h | 18 +++---
  1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index 0d3ef9a1c1..a79368ebdf 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -300,12 +300,25 @@ static void gicv3_init_dist(volatile gic_dist *dist)
}
  }

+/*
+ * A better way to access these registers than special opcodes
+ */
+#define isb() __asm __volatile("isb" : : : "memory")
+
+#define  WRITE_SPECIALREG(reg, _val)\
+  __asm __volatile("msr  " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
+
+#define  gic_icc_write(reg, val)\
+do {\
+  WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \
+  isb();\
+} while (0)
+
  static void gicv3_init_cpu_interface(uint32_t cpu_index)
  {
uint32_t sre_value = 0x7;
WRITE_SR(ICC_SRE, sre_value);
WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff));
-  WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0));

This appears unrelated?

The binary pointer effects the secure interrupts and so cannot be touched on
EL1. It traps into EL3. It makes sense to me it is protected. There is no code
in Petalinux or FreeBSD writing to this register.


volatile gic_redist *redist = gicv3_get_redist(cpu_index);
uint32_t waker = redist->icrwaker;
@@ -322,8 +335,7 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
}

/* Enable interrupt groups 0 and 1 */
-  WRITE_SR(ICC_IGRPEN0, 0x1);
-  WRITE_SR(ICC_IGRPEN1, 0x1);
+  gic_icc_write(IGRPEN1, 1);

Removed the write to IGRPEN0?

The write I replaced is touching a secure register and so traps into EL3 when
your TF-A has enabled a secure mode.

The enable is replaced with a write to the EL1 accessible register. This is how
FreeBSD does it so I copied that method rather than the binary opcode approach
which I found complicated.

You need a suitably configured TF-A to run on aarch64. I would be questioning
any TF-A that lets this code run without these changes. The Xilinx 2020.2
vck-190 build of TF-A lets our code run without this patch however 2021.2 had
tightened things. Xilinx and I looked into the history of their TF-A source and
how they build it and came to the conclusion the change in the secure mode has
come from ARM and their TF-A code.


OK, thanks for the explanation. This looks ok to me.


This set of changes makes sense given our previous discussion and the above.


Kinsey

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Re: [PATCH 2/3] bsp/versal: Support more than 4G of RAM

[Kinsey Moore]

On 6/15/2022 09:48, Gedare Bloom wrote:

This was copied from the ZynqMP, should that also use a 64-bit value
for the ram length?

Probably any 64-bit architecture should do so?


I'd agree with that.


Kinsey

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Re: [PATCH] bsp/aarch64: Fix array warning

[Kinsey Moore]

On 6/12/2022 01:30, Chris Johns wrote:

On 12/6/22 12:59 am, Joel Sherrill wrote:

Should this use that obscure pointer macro Sebastian suggests sometimes?

I looked into that and could not get it to work. This works. If you would like
to try please do?
I've been testing for a little while with this exact patch as suggested 
by the warning with no issues. Looks good.


Kinsey

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Re: [PATCH rtems-lwip] lwip: Split sources into origin directories

[Kinsey Moore]

On 5/12/2022 16:30, Vijay Kumar Banerjee wrote:

On Sat, Apr 16, 2022 at 10:48 AM Pavel Pisa  wrote:

Hello Joel,

On Saturday 16 of April 2022 17:26:02 Joel Sherrill wrote:

Ok. Any suggestions for a directory name? :)

I am not in the full sync and I have lost the tracks where
are all RTEMS LwIP repo copies.

Do we speak about https://git.rtems.org/vijay/rtems-lwip.git ?


Yes
Given that a better directory name doesn't appear to be forthcoming, is 
there anything else preventing this patch from going in as a starting 
point to further improvements?



If it is that way then LwIP uses practice to put integration
stuff into "ports" directory so I would leave the structure
under LwIP as it is

   ports/os/rtems/arch/sys_arch.c

Or if you want to somehow separate sources into more repos
then possible but would complicate keep the drivers and targets
in a sync in future.  I am losing tracks of the build tools etc...
I hope that when it settles the simple instructions
would be added on the integration page

   https://devel.rtems.org/wiki/Packages/LWIP

If you need to move ports/os/rtems/arch/sys_arch.c under some directory,
then it should be something like

   rtems-support/ports/os/rtems/arch/sys_arch.c


This would be a good idea. We can put all RTEMS-related ports into a
separate directory. If there's any driver-specific port, that can also
be added there and waf can be taught to pick up the right one
according to the target.
I'm about to start some additional work for lwIP support on ZynqMP. I'll 
see about breaking any code written specifically by RTEMS developers 
(just Vijay at this point) into a rtemslwip directory (similar to 
rtemsbsd in rtems-libbsd).



if the code can be used over all RTEMS targets. Which should be
a goal anyway and I have initiated it such way years ago.
But I am not sure why to not let code in the actual
lwip/ports/drivers together as well. I see that
in devel branch is the most of our TMS570 code wiped
out... hmm.. why. There is

  lwip/ports/drivers/bbb

this location seems to me as OK.
In the suggested changes is

{lwip/ports/drivers => uLan/ports/driver/tms570_emac}/phy_dp83848h.c

I agree with move of all TMS570 specific code under

   /ports/driver/tms570_emac


I agree with this approach, as it allows adding sources with
problematic license (like STM) into its own directory and a warning
can be added to waf while building those targets.


Again if all these shuffles are done only for some license changes
I would prefer to be noticed and I think that I would not be blocked
by any of my former studnets nor the faculty to relicense code.
I would inform the faculty (where I am only left from former group,
where I have lead part of this development, part was at my company)
as well as students.

I would prefer if real developer names who invested time into work
are included at least as Authors in the files but the copyright can
be moved to RTEMS foundation or whatever.

But as I have said I have lost track and hope that stuff will survive
in some form till the time when I have some free time or studnet
to work on the project as his/her theses, GSoC etc...
I have used the code with external OMK make, I agree that this
is not right way forward but I wait for outcome of these who
have more experience with RSB and related tools and propose
integration.


As long as the code is licensed appropriately for inclusion in this 
project, I see no reason to relicense it under most conditions.



Kinsey

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Re: GCC version for RTEMS 6?

[Kinsey Moore]

On 5/24/2022 17:29, Chris Johns wrote:

On 24/5/2022 5:01 pm, Sebastian Huber wrote:

On 24/05/2022 08:43, Sebastian Huber wrote:

On 24/05/2022 02:32, Chris Johns wrote:

On 6/5/2022 4:16 pm, Sebastian Huber wrote:

- aarch64 bsps

These BSPs generated lots of warnings in the testsuite due to this line:

https://git.rtems.org/rtems/tree/bsps/aarch64/include/bsp/start.h#n175

The warning is about comparing arrays. I have not looked deeper.

This can be fixed by using RTEMS_OBFUSCATE_VARIABLE().

Sorry, I do not know how to use this macro to remove the warning?

For this macro you need a stack variable.

I guess the warning could be also removed using this compiler note:

rtems/bsps/aarch64/include/bsp/start.h:175:28: note: use
'_vector_table_end[0] != _vector_table_size[0]' to compare the addresses


I have done this and it is quieter now.


What is the purpose of AArch64_start_set_vector_base()? Do we need this at all
on the aarch64 target?

Also why is this function exposed by ?

I do not know. I am only the messenger :)

Kinsey?


It's definitely necessary for all AArch64 targets. It sets the active 
vector table so that RTEMS can intercept exceptions of all varieties at 
EL1. It could probably be folded into start.S at the appropriate 
location if that's what you're asking.


As far as why it's exposed by bsp.h, that's likely incidental since I 
was following the design of the ARM code when I wrote this.



Kinsey

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[PATCH rtems-source-builder v1] source-builder: Handle utf8 in path

[Kinsey Moore]

It's possible for an environment to have unicode characters in its
paths. This was recently exposed by the latest newlib update and RSB
fails under Python 2.7 in this situation. This resolves the issue by
ensuring that the paths are encoded and decoded as necessary.

Related issue that caused the change in newlib:
https://github.com/golang/go/issues/27836
---
 source-builder/sb/path.py | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/source-builder/sb/path.py b/source-builder/sb/path.py
index b27cf14..d36e12a 100644
--- a/source-builder/sb/path.py
+++ b/source-builder/sb/path.py
@@ -58,7 +58,7 @@ def host(path):
 
 def shell(path):
 if isinstance(path, bytes):
-path = path.decode('ascii')
+path = path.decode('utf8')
 if path is not None:
 if windows or windows_posix:
 path = path.encode('ascii', 'ignore').decode('ascii')
@@ -189,11 +189,11 @@ def removeall(path):
 # get to the max path length on Windows.
 #
 def _isdir(path):
-hpath = host(path)
+hpath = host(path).encode('utf8')
 return os.path.isdir(hpath) and not os.path.islink(hpath)
 
 def _remove_node(path):
-hpath = host(path)
+hpath = host(path).encode('utf8')
 if not os.path.islink(hpath) and not os.access(hpath, os.W_OK):
 os.chmod(hpath, stat.S_IWUSR)
 if _isdir(path):
@@ -216,7 +216,7 @@ def removeall(path):
 _remove_node(dir)
 
 path = shell(path)
-hpath = host(path)
+hpath = host(path).encode('utf8')
 
 if os.path.exists(hpath):
 _remove(path)
@@ -317,11 +317,11 @@ def get_size(path, depth = -1):
 # get to the max path length on Windows.
 #
 def _isdir(path):
-hpath = host(path)
+hpath = host(path).encode('utf8')
 return os.path.isdir(hpath) and not os.path.islink(hpath)
 
 def _node_size(path):
-hpath = host(path)
+hpath = host(path).encode('utf8')
 size = 0
 if not os.path.islink(hpath):
 size = os.path.getsize(hpath)
@@ -345,7 +345,7 @@ def get_size(path, depth = -1):
 return size
 
 path = shell(path)
-hpath = host(path)
+hpath = host(path).encode('utf8')
 size = 0
 
 if os.path.exists(hpath):
-- 
2.30.2

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[PATCH rtems-source-builder v1 0/1] Python 2.7 utf8 handling

[Kinsey Moore]

I just discovered this when trying to update my CI that was running
Python 2.7. I have since bumped that to Python 3 to avoid the issue, but
the following patch resolves it.


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Re: RTEMS-specific Newlib patches for aarch64

[Kinsey Moore]

On 4/22/2022 07:28, Sebastian Huber wrote:

On 17/03/2022 13:30, Kinsey Moore wrote:

On 3/17/2022 05:00, Sebastian Huber wrote:

Hello,

the current Newlib build fails for aarch64 due to RTEMS-specific 
patches:


  CC   libc/string/libc_a-wcscmp.o
../../../gnu-mirror-gcc-0f001dd/newlib/libc/machine/aarch64/setjmp.S:29:10: 
fatal error: ../asmdefs.h: No such file or directory

   29 | #include <../asmdefs.h>
  |  ^~

Why are these patches not in upstream Newlib?

The only patch I'm aware of should be for ILP32 support in the 
hand-coded AArch64 assembly in newlib.


The short answer as to why the patch isn't upstream is that newlib 
hasn't committed it yet.


The longer answer is that the hand-coded AArch64 ASM in newlib is 
sourced from ARM's optimized-routines repository. I provided a patch 
to newlib's specifications at which point they suggested I get it 
committed upstream in the optimized-routines repo, first. I did that 
and then requested they pull the changes, but they were in the middle 
of a release cycle. Having the patch locally was the interim solution 
while we waited for that release to finish and for newlib to pull in 
the changes. I'll take a look and see what the current status on that 
is and what changes prompted the patch to break.


I don't see open pull requests in

https://github.com/ARM-software/optimized-routines/pulls

What is the status with respect to a Newlib integration?

All the necessary changes have been integrated into the 
optimized-routines repository. I just pinged the newlib list about 
integrating those changes since there doesn't seem to have been any 
movement toward that goal.



Kinsey

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[PATCH] wscript: Allow start code to be written in C

[Kinsey Moore]

Start code for most platforms requires hand-coded ASM but some can be
bootstrapped entirely in C, especially for paravirtualized platforms.
This change allows start code to be written in C where possible instead
of requiring architecture-specific ASM to bridge to C.
---
 wscript | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/wscript b/wscript
index 0291b6025a..59ab96c43d 100755
--- a/wscript
+++ b/wscript
@@ -561,7 +561,11 @@ class StartFileItem(Item):
 super(StartFileItem, self).__init__(uid, data)
 
 def do_build(self, bld, bic):
-tgt = self.asm(bld, bic, self.data["source"], self.get(bld, "target"))
+source = self.data["source"]
+if os.path.splitext(source[0])[1] == ".S":
+tgt = self.asm(bld, bic, source, self.get(bld, "target"))
+else:
+tgt = self.cc(bld, bic, source, self.get(bld, "target"))
 node = bld.bldnode.make_node(tgt)
 try:
 bld.start_files.append(node)
-- 
2.30.2

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[PATCH rtems-lwip] lwip: Split sources into origin directories

[Kinsey Moore]

Moving forward, each origin directory should have its own top-level
COPYING.origin file to describe its license as well as a ORIGIN.origin
file to describe where the code is sourced from.
---
 COPYING.lwip  | 25 ++
 COPYING.uLan  | 33 +++
 ORIGIN.lwip   |  2 ++
 ORIGIN.uLan   |  2 ++
 README| 14 
 lwip.py   | 10 +++---
 .../ports/driver/tms570_emac}/eth_lwip.c  |  0
 .../ports/driver/tms570_emac}/eth_lwip.h  |  0
 .../driver/tms570_emac}/eth_lwip_default.h|  0
 .../ports/driver/tms570_emac}/phy_dp83848h.c  |  0
 .../ports/driver/tms570_emac}/phy_dp83848h.h  |  0
 .../ports/driver/tms570_emac}/ti_drv_emac.h   |  0
 .../ports/driver/tms570_emac}/ti_drv_mdio.h   |  0
 .../ports/driver/tms570_emac}/tms570_emac.h   |  0
 .../ports/driver/tms570_emac}/tms570_netif.c  |  0
 .../ports/driver/tms570_emac}/tms570_netif.h  |  0
 {lwip => uLan}/ports/os/lwipopts.h|  0
 {lwip => uLan}/ports/os/rtems/arch/cc.h   |  0
 {lwip => uLan}/ports/os/rtems/arch/perf.h |  0
 {lwip => uLan}/ports/os/rtems/arch/sys_arch.c |  0
 {lwip => uLan}/ports/os/rtems/arch/sys_arch.h |  0
 21 files changed, 81 insertions(+), 5 deletions(-)
 create mode 100644 COPYING.lwip
 create mode 100644 COPYING.uLan
 create mode 100644 ORIGIN.lwip
 create mode 100644 ORIGIN.uLan
 create mode 100644 README
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/eth_lwip.c (100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/eth_lwip.h (100%)
 rename {lwip/ports/drivers => 
uLan/ports/driver/tms570_emac}/eth_lwip_default.h (100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/phy_dp83848h.c 
(100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/phy_dp83848h.h 
(100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/ti_drv_emac.h 
(100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/ti_drv_mdio.h 
(100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/tms570_emac.h 
(100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/tms570_netif.c 
(100%)
 rename {lwip/ports/drivers => uLan/ports/driver/tms570_emac}/tms570_netif.h 
(100%)
 rename {lwip => uLan}/ports/os/lwipopts.h (100%)
 rename {lwip => uLan}/ports/os/rtems/arch/cc.h (100%)
 rename {lwip => uLan}/ports/os/rtems/arch/perf.h (100%)
 rename {lwip => uLan}/ports/os/rtems/arch/sys_arch.c (100%)
 rename {lwip => uLan}/ports/os/rtems/arch/sys_arch.h (100%)

diff --git a/COPYING.lwip b/COPYING.lwip
new file mode 100644
index 000..90465f5
--- /dev/null
+++ b/COPYING.lwip
@@ -0,0 +1,25 @@
+Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without 
modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+3. The name of the author may not be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 
EVENT
+SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
diff --git a/COPYING.uLan b/COPYING.uLan
new file mode 100644
index 000..e23898b
--- /dev/null
+++ b/COPYING.uLan
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without 
modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *this list of conditions and the following disclaimer in the documentation
+ *and/or other materials provided 

[PATCH v2] wscript: Allow substitution outside values

[Kinsey Moore]

This expands the ability to substitute variables outside the current
limitation of values in options to asflags, cflags, cppflags, cxxflags,
ldflags, and includes. It is possible for all of these flags to utilize
user-defined information in config.ini, especially for paths to external
resources.
---
 wscript | 54 --
 1 file changed, 28 insertions(+), 26 deletions(-)

diff --git a/wscript b/wscript
index 4d63dbc66f..eb5761c53d 100755
--- a/wscript
+++ b/wscript
@@ -239,6 +239,8 @@ class Item(object):
 return
 
 def substitute(self, ctx, value):
+if isinstance(value, list):
+return [self.substitute(ctx, subvalue) for subvalue in value]
 if isinstance(value, str):
 try:
 return Template(value).substitute(EnvWrapper(ctx.env))
@@ -272,10 +274,10 @@ class Item(object):
 if target is None:
 target = os.path.splitext(source)[0] + ".o"
 bld(
-asflags=self.data["asflags"],
-cppflags=self.data["cppflags"],
+asflags=self.substitute(bld, self.data["asflags"]),
+cppflags=self.substitute(bld, self.data["cppflags"]),
 features="asm_explicit_target asm c",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + self.substitute(bld, 
self.data["includes"]),
 source=[source],
 target=target,
 )
@@ -285,10 +287,10 @@ class Item(object):
 if target is None:
 target = os.path.splitext(source)[0] + ".o"
 bld(
-cflags=self.data["cflags"],
-cppflags=cppflags + self.data["cppflags"],
+cflags=self.substitute(bld, self.data["cflags"]),
+cppflags=cppflags + self.substitute(bld, self.data["cppflags"]),
 features="c",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + self.substitute(bld, 
self.data["includes"]),
 rule="${CC} ${CFLAGS} ${CPPFLAGS} ${DEFINES_ST:DEFINES} 
${CPPPATH_ST:INCPATHS} -c ${SRC[0]} -o ${TGT}",
 source=[source] + deps,
 target=target,
@@ -299,10 +301,10 @@ class Item(object):
 if target is None:
 target = os.path.splitext(source)[0] + ".o"
 bld(
-cppflags=cppflags + self.data["cppflags"],
-cxxflags=self.data["cxxflags"],
+cppflags=cppflags + self.substitute(bld, self.data["cppflags"]),
+cxxflags=self.substitute(bld, self.data["cxxflags"]),
 features="cxx",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + self.substitute(bld, 
self.data["includes"]),
 rule="${CXX} ${CXXFLAGS} ${CPPFLAGS} ${DEFINES_ST:DEFINES} 
${CPPPATH_ST:INCPATHS} -c ${SRC[0]} -o ${TGT}",
 source=[source] + deps,
 target=target,
@@ -574,11 +576,11 @@ class ObjectsItem(Item):
 
 def do_build(self, bld, bic):
 bld.objects(
-asflags=self.data["cppflags"],
-cflags=self.data["cflags"],
-cppflags=self.data["cppflags"],
-cxxflags=self.data["cxxflags"],
-includes=bic.includes + self.data["includes"],
+asflags=self.substitute(bld, self.data["cppflags"]),
+cflags=self.substitute(bld, self.data["cflags"]),
+cppflags=self.substitute(bld, self.data["cppflags"]),
+cxxflags=self.substitute(bld, self.data["cxxflags"]),
+includes=bic.includes + self.substitute(bld, 
self.data["includes"]),
 source=self.data["source"],
 target=self.uid,
 )
@@ -599,10 +601,10 @@ class BSPItem(Item):
 
 def do_build(self, bld, bic):
 bld(
-cflags=self.data["cflags"],
-cppflags=self.data["cppflags"],
+cflags=self.substitute(bld, self.data["cflags"]),
+cppflags=self.substitute(bld, self.data["cppflags"]),
 features="c cstlib",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + self.substitute(bld, 
self.data["includes"]),
 install_path="${BSP_LIBDIR}",
 source=self.data["source"],
 target="rtemsbsp",
@@ -620,11 +622,11 @@ class LibraryItem(Item):
 
 def do_build(self, bld, bic):
 bld(
-cflags=self.data["cflags"],
-cppflags=self.data["cppflags"],
-cxxflags=self.data["cxxflags"],
+cflags=self.substitute(bld, self.data["cflags"]),
+cppflags=self.substitute(bld, self.data["cppflags"]),
+cxxflags=self.substitute(bld, self.data["cxxflags"]),
 features="c cxx cstlib",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + self.substitute(bld, 
self.data["includes"]),
 install_path=self.data["install-path"],
 

Re: [PATCH v1 1/2] wscript: Allow defines to be used for substitution

[Kinsey Moore]

On 4/13/2022 13:38, Sebastian Huber wrote:

On 13/04/2022 20:06, Kinsey Moore wrote:

On 4/13/2022 00:53, Sebastian Huber wrote:

On 12/04/2022 20:55, Kinsey Moore wrote:
This allows options set as defines to the compiler to be used as 
targets

for substitution using the syntax ${DEFINES:define_target}. These need
special handling since they are not in a form that is trivially 
consumed

by the mapping code.
---
  wscript | 4 
  1 file changed, 4 insertions(+)

diff --git a/wscript b/wscript
index 4d63dbc66f..9de9d67b91 100755
--- a/wscript
+++ b/wscript
@@ -107,6 +107,10 @@ class EnvWrapper(object):
  except IndexError:
  fmt = "{}"
  if isinstance(v, list):
+    if fields[0] == "DEFINES":
+    for D in v:
+    if D.startswith(fields[1]+'='):
+    return 
"{}".format(D.split("=")[1].strip('"'))

  return " ".join([fmt.format(w) for w in v])
  return fmt.format(v)


Sorry, I don't understand what this is supposed to do. Could you 
please give me an example use case?




Currently, this is being used with the other substitution patch to 
allow critical external resources for the Deos BSPs to be placed at 
user-defined locations. In the BSP for RTEMS5, this was being 
provided as a variable to `make` and being substituted into paths in 
the various Makefiles. I had thought to codify this input a little 
more strictly as a BSP configuration option in config.ini to make it 
more obvious or even a required part of the `waf configure` step. The 
BSP option, when set as a compiler define, can be used in 
substitutions to reference these external paths.


Ok, so you want to use this for command line defines using -D option? 
I am strongly opposed to the use of command line defines. Why can't 
you place the defines in bspopts.h or cpuopts.h?


I'm going to drop this patch from the set as I've found a way around the 
need for dealing with -D defines using env-assign. This was only in 
place because it was how the RTEMS5 BSP provided that information. 
Fortunately, it wasn't a hard requirement.



I'll resubmit v2 of the other patch now that I've reworked it.


Thanks,

Kinsey

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Re: [PATCH v1 2/2] wscript: Allow substitution outside values

[Kinsey Moore]

On 4/13/2022 00:48, Sebastian Huber wrote:

On 12/04/2022 20:55, Kinsey Moore wrote:

diff --git a/wscript b/wscript
index 9de9d67b91..e2fc047ea8 100755
--- a/wscript
+++ b/wscript
@@ -276,10 +276,10 @@ class Item(object):
  if target is None:
  target = os.path.splitext(source)[0] + ".o"
  bld(
-    asflags=self.data["asflags"],
-    cppflags=self.data["cppflags"],
+    asflags=[self.substitute(bld, asflag) for asflag in 
self.data["asflags"]],
+    cppflags=[self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],


Could you please add a self.substitute_list(bld, values) or add list 
support to self.substitute(bld, value).



I'll incorporate this into the next version of the patch set.


Thanks,

Kinsey

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Re: [PATCH v1 1/2] wscript: Allow defines to be used for substitution

[Kinsey Moore]

On 4/13/2022 00:53, Sebastian Huber wrote:

On 12/04/2022 20:55, Kinsey Moore wrote:

This allows options set as defines to the compiler to be used as targets
for substitution using the syntax ${DEFINES:define_target}. These need
special handling since they are not in a form that is trivially consumed
by the mapping code.
---
  wscript | 4 
  1 file changed, 4 insertions(+)

diff --git a/wscript b/wscript
index 4d63dbc66f..9de9d67b91 100755
--- a/wscript
+++ b/wscript
@@ -107,6 +107,10 @@ class EnvWrapper(object):
  except IndexError:
  fmt = "{}"
  if isinstance(v, list):
+    if fields[0] == "DEFINES":
+    for D in v:
+    if D.startswith(fields[1]+'='):
+    return "{}".format(D.split("=")[1].strip('"'))
  return " ".join([fmt.format(w) for w in v])
  return fmt.format(v)


Sorry, I don't understand what this is supposed to do. Could you 
please give me an example use case?




Currently, this is being used with the other substitution patch to allow 
critical external resources for the Deos BSPs to be placed at 
user-defined locations. In the BSP for RTEMS5, this was being provided 
as a variable to `make` and being substituted into paths in the various 
Makefiles. I had thought to codify this input a little more strictly as 
a BSP configuration option in config.ini to make it more obvious or even 
a required part of the `waf configure` step. The BSP option, when set as 
a compiler define, can be used in substitutions to reference these 
external paths.



Kinsey

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[PATCH v1 2/2] wscript: Allow substitution outside values

[Kinsey Moore]

This expands the ability to substitute variables outside the current
limitation of values in options to asflags, cflags, cppflags, cxxflags,
ldflags, and includes. It is possible for all of these flags to utilize
user-defined information in config.ini, especially for paths to external
resources.
---
 wscript | 52 ++--
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/wscript b/wscript
index 9de9d67b91..e2fc047ea8 100755
--- a/wscript
+++ b/wscript
@@ -276,10 +276,10 @@ class Item(object):
 if target is None:
 target = os.path.splitext(source)[0] + ".o"
 bld(
-asflags=self.data["asflags"],
-cppflags=self.data["cppflags"],
+asflags=[self.substitute(bld, asflag) for asflag in 
self.data["asflags"]],
+cppflags=[self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],
 features="asm_explicit_target asm c",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + [self.substitute(bld, inc) for inc in 
self.data["includes"]],
 source=[source],
 target=target,
 )
@@ -289,10 +289,10 @@ class Item(object):
 if target is None:
 target = os.path.splitext(source)[0] + ".o"
 bld(
-cflags=self.data["cflags"],
-cppflags=cppflags + self.data["cppflags"],
+cflags=[self.substitute(bld, cflag) for cflag in 
self.data["cflags"]],
+cppflags=cppflags + [self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],
 features="c",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + [self.substitute(bld, inc) for inc in 
self.data["includes"]],
 rule="${CC} ${CFLAGS} ${CPPFLAGS} ${DEFINES_ST:DEFINES} 
${CPPPATH_ST:INCPATHS} -c ${SRC[0]} -o ${TGT}",
 source=[source] + deps,
 target=target,
@@ -303,10 +303,10 @@ class Item(object):
 if target is None:
 target = os.path.splitext(source)[0] + ".o"
 bld(
-cppflags=cppflags + self.data["cppflags"],
-cxxflags=self.data["cxxflags"],
+cppflags=cppflags + [self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],
+cxxflags=[self.substitute(bld, cxxflag) for cxxflag in 
self.data["cxxflags"]],
 features="cxx",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + [self.substitute(bld, inc) for inc in 
self.data["includes"]],
 rule="${CXX} ${CXXFLAGS} ${CPPFLAGS} ${DEFINES_ST:DEFINES} 
${CPPPATH_ST:INCPATHS} -c ${SRC[0]} -o ${TGT}",
 source=[source] + deps,
 target=target,
@@ -578,11 +578,11 @@ class ObjectsItem(Item):
 
 def do_build(self, bld, bic):
 bld.objects(
-asflags=self.data["cppflags"],
-cflags=self.data["cflags"],
-cppflags=self.data["cppflags"],
-cxxflags=self.data["cxxflags"],
-includes=bic.includes + self.data["includes"],
+asflags=[self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],
+cflags=[self.substitute(bld, cflag) for cflag in 
self.data["cflags"]],
+cppflags=[self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],
+cxxflags=[self.substitute(bld, cxxflag) for cxxflag in 
self.data["cxxflags"]],
+includes=bic.includes + [self.substitute(bld, inc) for inc in 
self.data["includes"]],
 source=self.data["source"],
 target=self.uid,
 )
@@ -603,10 +603,10 @@ class BSPItem(Item):
 
 def do_build(self, bld, bic):
 bld(
-cflags=self.data["cflags"],
-cppflags=self.data["cppflags"],
+cflags=[self.substitute(bld, cflag) for cflag in 
self.data["cflags"]],
+cppflags=[self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],
 features="c cstlib",
-includes=bic.includes + self.data["includes"],
+includes=bic.includes + [self.substitute(bld, inc) for inc in 
self.data["includes"]],
 install_path="${BSP_LIBDIR}",
 source=self.data["source"],
 target="rtemsbsp",
@@ -624,11 +624,11 @@ class LibraryItem(Item):
 
 def do_build(self, bld, bic):
 bld(
-cflags=self.data["cflags"],
-cppflags=self.data["cppflags"],
-cxxflags=self.data["cxxflags"],
+cflags=[self.substitute(bld, cflag) for cflag in 
self.data["cflags"]],
+cppflags=[self.substitute(bld, cppflag) for cppflag in 
self.data["cppflags"]],
+cxxflags=[self.substitute(bld, cxxflag) for cxxflag in 
self.data["cxxflags"]],
 features="c cxx cstlib",
-includes=bic.includes + self.data["includes"],
+

[PATCH v1 1/2] wscript: Allow defines to be used for substitution

[Kinsey Moore]

This allows options set as defines to the compiler to be used as targets
for substitution using the syntax ${DEFINES:define_target}. These need
special handling since they are not in a form that is trivially consumed
by the mapping code.
---
 wscript | 4 
 1 file changed, 4 insertions(+)

diff --git a/wscript b/wscript
index 4d63dbc66f..9de9d67b91 100755
--- a/wscript
+++ b/wscript
@@ -107,6 +107,10 @@ class EnvWrapper(object):
 except IndexError:
 fmt = "{}"
 if isinstance(v, list):
+if fields[0] == "DEFINES":
+for D in v:
+if D.startswith(fields[1]+'='):
+return "{}".format(D.split("=")[1].strip('"'))
 return " ".join([fmt.format(w) for w in v])
 return fmt.format(v)
 
-- 
2.30.2

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[PATCH v1 0/2] Add more substitution capabilities

[Kinsey Moore]

This patch set adds more substitution capabilities to the build system
such that BSP configuration options can be used in flags and include
paths.


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Re: [PATCH] rtems-docs: add example booting aarch64 image on Xilinx ZCU102

[Kinsey Moore]

All the content here looks great! Thanks Alan


Kinsey

On 3/18/2022 11:04, Alan Cudmore wrote:

This patch is for the rtems-docs repo. I added details on the procedure I
used to boot RTEMS images on the Xilinx ZCU102 board. I applied this patch,
and  generated the HTML docs, and everything looks ok to me.
Thanks,
Alan

---
  user/bsps/aarch64/xilinx-zynqmp.rst | 138 
  1 file changed, 138 insertions(+)

diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst
b/user/bsps/aarch64/xilinx-zynqmp.rst
index ca232de..3d55c4c 100644
--- a/user/bsps/aarch64/xilinx-zynqmp.rst
+++ b/user/bsps/aarch64/xilinx-zynqmp.rst
@@ -44,6 +44,144 @@ When booting via u-boot, RTEMS must be packaged into a
u-boot image or booted
  as a raw binary since u-boot does not currently support ELF64 which is
required
  for AArch64 ELF binaries.

+
+Example: Booting a RTEMS image on the ZCU102 ZynqMP board
+-
+
+This example will walk through the steps needed for booting RTEMS from a
SD card on the
+`ZCU102 ZynqMP board. <
https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html>`_ The
reference for setting up a SD card and obtaining pre-built boot images is
`here. <
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841858/Board+bring+up+using+pre-built+images

`_

+
+Hardware Setup
+^^
+
+Set the dip switch SW6 according to the table below. This will allow the
board to boot from the SD card. Connect a Micro-USB cable to the USB UART
interface J83. This is a quad USB UART interface which will show up on the
development host computer as four different serial or tty devices. Use the
first channel for the console UART. It should be set to 115k baud.
+
++---+
+| Dip Switch JW6|
++--+--+--+--+
+|  ON  |  OFF |  OFF |  OFF |
++--+--+--+--+
+
+Prepare a SD card with a bootable partition
+
+
+The goal is to have a bootable SD card with a partition that is formatted
with the FAT file system. The file system will contain the boot artifacts
including BOOT.bin and the u-boot image. The RTEMS image will be placed on
this volume. To create the bootable SD card, follow the directions `here. <
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842385/How+to+format+SD+card+for+SD+boot

`_

+
+Once you have the card formatted correctly, you need to place the files
from `this archive <
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2202763266/2021.2+Release#Downloads>`_
on the FAT partition. The following file was used for this example:
`xilinx-vck190-v2021.2-final.bsp <
https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-vck190-v2021.2-final.bsp

`_

+
+In order to download these files, you need to have a Xilinx account login.
As an alternative, you can download a bootable image for Ubuntu 20.04 and
write it to an SD card using a utility such as `Balena Etcher <
https://www.balena.io/etcher>`_  or dd. The Ubuntu image is available
`here. `_ Download the image for the
Zynq Ultrascale+ MPSoC Development boards, uncompress it and write it to
the SD card. This image creates multiple partitions, but we only need to
use the FAT partition with the boot artifacts on it.
+
+Verify that the board can boot from the SD card
+^^^
+
+It is worth booting the board from the SD card before trying to boot
RTEMS. Insert the card and power on the board. You should see the messages
on the first console indicating the various boot loader stages and
eventually the Linux kernel. The goal is to interrupt u-boot when given the
chance to access the u-boot command prompt.
+
+Build RTEMS with examples
+^
+
+Build the RTEMS `xilinx-zynqmp-lp64-zu3eg` BSP. Use the ticker.exe sample
which can be found in the directory:
+
+.. code-block:: shell
+
+  build/aarch64/xilinx-zynqmp-lp64-zu3eg/testsuites/samples
+
+Prepare the RTEMS image
+^^^
+
+Prepare your RTEMS image to boot from u-boot with the following commands:
+
+.. code-block:: shell
+
+  $ aarch64-rtems6-objcopy -Obinary ticker.exe ticker.bin
+  $ gzip -9 ticker.bin
+  $ mkimage -A arm64 -O rtems -T kernel -a 0x1000 -e 0x1000 -n
RTEMS -d ticker.bin.gz rtems.img
+
+Boot the RTEMS image
+
+Copy the prepared RTEMS image to the SD card and insert the SD crd in the
ZCU102 board. Power on the board.
+When you see the prompt on the console to interupt u-boot, hit a key to
bring up the u-boot command prompt. On the u-boot command prompt you can
boot your RTEMS image:
+
+.. code-block:: shell
+
+  Zynq-MP> fatload mmc 0:1 0x1000 rtems.img
+  Zynq-MP> bootm 0x1000
+
+This is the entire boot sequence:
+
+.. code-block:: shell
+
+  Pre-FSBL boot Started
+  Xilinx Zynq MP First Stage Boot Loader
+  Release 2020.2   Nov 18 2020  -  11:46:01
+  NOTICE:  

Re: [PATCH 00/13] Refactor Arm GICv3 support

[Kinsey Moore]

These changes look good other than the nit in the first patch.

On 3/18/2022 02:19, Sebastian Huber wrote:

Separate the Interrupt Manager implementation from the generic Arm GICv3
support.  Move parts of the Arm GICv3 support into a new header file.  This
helps to support systems with a clustered structure in which multiple GICv3
instances are present.  For example, two clusters of two Cortex-R52 cores where
each cluster has a dededicated GICv3 instance.

Sebastian Huber (13):
   bsps: Add 
   bsps: Add gicv3_sgi_ppi_is_pending()
   bsps: Add gicv3_trigger_sgi()
   bsps: Add gicv3_ppi_set_pending()
   bsps: Add gicv3_ppi_clear_pending()
   bsps: Add gicv3_sgi_ppi_is_enabled()
   bsps: Add gicv3_sgi_ppi_enable()
   bsps: Add gicv3_sgi_ppi_disable()
   bsps: Move gicv3_init_dist()
   bsps: Move gicv3_init_cpu_interface()
   bsps: Add gicv3_sgi_ppi_set_priority()
   bsps: Add gicv3_sgi_ppi_get_priority()
   bsps: Add gicv3_get_attributes()

  bsps/include/dev/irq/arm-gicv3.h | 366 +++
  bsps/shared/dev/irq/arm-gicv3.c  | 286 ++--
  spec/build/bsps/aarch64/grp.yml  |   1 +
  spec/build/bsps/arm/grp.yml  |   1 +
  4 files changed, 389 insertions(+), 265 deletions(-)
  create mode 100644 bsps/include/dev/irq/arm-gicv3.h


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Re: [PATCH 01/13] bsps: Add

[Kinsey Moore]

Nit in the commit message: "dededicated"

On 3/18/2022 02:19, Sebastian Huber wrote:

Separate the Interrupt Manager implementation from the generic Arm GICv3
support.  Move parts of the Arm GICv3 support into a new header file.  This
helps to support systems with a clustered structure in which multiple GICv3
instances are present.  For example, two clusters of two Cortex-R52 cores where
each cluster has a dededicated GICv3 instance.
---
  bsps/include/dev/irq/arm-gicv3.h | 162 +++
  bsps/shared/dev/irq/arm-gicv3.c  | 122 +--
  spec/build/bsps/aarch64/grp.yml  |   1 +
  spec/build/bsps/arm/grp.yml  |   1 +
  4 files changed, 165 insertions(+), 121 deletions(-)
  create mode 100644 bsps/include/dev/irq/arm-gicv3.h

diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
new file mode 100644
index 00..60bc315962
--- /dev/null
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup arm_gic
+ *
+ * @brief This header file contains interfaces to access an Arm GICv3.
+ */
+
+/*
+ * Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_DEV_IRQ_ARM_GICV3_H
+#define _RTEMS_DEV_IRQ_ARM_GICV3_H
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PRIORITY_DEFAULT 127
+
+#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
+#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
+#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
+#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
+#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
+#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
+#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
+#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
+#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
+
+#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
+#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)
+#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
+#define ICC_SGIR_IRM BSP_BIT32(40)
+#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)
+#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)
+#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
+#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)
+#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)
+#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)
+#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)
+#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)
+#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
+#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)
+#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)
+#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
+
+#ifdef ARM_MULTILIB_ARCH_V4
+/* cpuif->iccicr */
+#define ICC_CTLR"p15, 0, %0, c12, c12, 4"
+
+/* cpuif->iccpmr */
+#define ICC_PMR "p15, 0, %0,  c4,  c6, 0"
+
+/* cpuif->iccbpr */
+#define ICC_BPR0"p15, 0, %0, c12,  c8, 3"
+#define ICC_BPR1"p15, 0, %0, c12, c12, 3"
+
+/* cpuif->icciar */
+#define ICC_IAR0"p15, 0, %0, c12,  c8, 0"
+#define ICC_IAR1"p15, 0, %0, c12, c12, 0"
+
+/* cpuif->icceoir */
+#define ICC_EOIR0   "p15, 0, %0, c12,  c8, 1"
+#define ICC_EOIR1   "p15, 0, %0, c12, c12, 1"
+
+#define ICC_SRE "p15, 0, %0, c12, c12, 5"
+
+#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
+#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
+
+#define MPIDR   "p15, 0, %0, c0, c0, 5"
+
+#define 

[PATCH rtems-source-builder] 6/7: Update AArch64 newlib patch

[Kinsey Moore]

The existing patch fails to build with the latest newlib. This picks up
an updated patch that compiles with both older and newer newlib.
---
 rtems/config/tools/rtems-gcc-10-newlib-head.cfg   | 4 ++--
 rtems/config/tools/rtems-gcc-head-newlib-head.cfg | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
index cb26aa0..22a88ba 100644
--- a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
@@ -13,8 +13,8 @@
 %patch add gcc -p1 
https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
 %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch 
afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
 
-%patch add newlib -p1 
https://devel.rtems.org/raw-attachment/ticket/4510/0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch
-%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch 
BHRMimj6ztKPHQFxypI8RwPmno96B56eVQGx5dtCtcOb+qICMrQC1fa0jP3JrR8RGJI4y61RoYvpnj6EbTmRKA==
+%patch add newlib -p1 
https://devel.rtems.org/raw-attachment/ticket/4510/0001-aarch64-Add-ILP32-ABI-support-in-assembly-v2.patch
+%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly-v2.patch 
7ca237eabfd5b382713186e1fc290dfc999a353315795ecb8dd0d22fcd1ab7f5bf31f4329954adab91ad04c100dcac0e86d406fdbce8f82cf9dc23842c88caf6
 
 %define newlib_version 332df71
 %define newlib_external 1
diff --git a/rtems/config/tools/rtems-gcc-head-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-head-newlib-head.cfg
index 6aaad8d..b2bc78f 100644
--- a/rtems/config/tools/rtems-gcc-head-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-head-newlib-head.cfg
@@ -13,8 +13,8 @@
 %source set newlib --rsb-file=newlib-%{newlib_version}.tar.gz 
https://codeload.github.com/RTEMS/sourceware-mirror-newlib-cygwin/tar.gz/%{newlib_version}
 %hash sha512 newlib-%{newlib_version}.tar.gz 
ec6db480d5e21f8de520a3c33a22dc08a2be56a6fb817d31d5f16c2f564df4907c1e3f3e7c1cf2368eed1d93b3811cabc1cdffb922d3df05ba7fe960eabd265b
 
-%patch add newlib -p1 
https://devel.rtems.org/raw-attachment/ticket/4510/0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch
-%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch 
BHRMimj6ztKPHQFxypI8RwPmno96B56eVQGx5dtCtcOb+qICMrQC1fa0jP3JrR8RGJI4y61RoYvpnj6EbTmRKA==
+%patch add newlib -p1 
https://devel.rtems.org/raw-attachment/ticket/4510/0001-aarch64-Add-ILP32-ABI-support-in-assembly-v2.patch
+%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly-v2.patch 
7ca237eabfd5b382713186e1fc290dfc999a353315795ecb8dd0d22fcd1ab7f5bf31f4329954adab91ad04c100dcac0e86d406fdbce8f82cf9dc23842c88caf6
 
 %define with_threads 1
 %define with_plugin 0
-- 
2.30.2

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Re: RTEMS-specific Newlib patches for aarch64

[Kinsey Moore]

On 3/17/2022 10:43, Sebastian Huber wrote:

On 17/03/2022 16:40, Kinsey Moore wrote:

with current newlib (ed32020)


This is not the current Newlib. There are a couple of build system 
patches on top of it.


I guess the problem is that one location in the patch uses #include 
<...> and not #include "...'.


Ah, I was looking at the github repo which is perpetually stale by a 
couple of days. I'll check the most recent one and get the patch updated.



Kinsey

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Re: RTEMS-specific Newlib patches for aarch64

[Kinsey Moore]

On 3/17/2022 07:30, Kinsey Moore wrote:

On 3/17/2022 05:00, Sebastian Huber wrote:

Hello,

the current Newlib build fails for aarch64 due to RTEMS-specific 
patches:


  CC   libc/string/libc_a-wcscmp.o
../../../gnu-mirror-gcc-0f001dd/newlib/libc/machine/aarch64/setjmp.S:29:10: 
fatal error: ../asmdefs.h: No such file or directory

   29 | #include <../asmdefs.h>
  |  ^~

Why are these patches not in upstream Newlib?

The only patch I'm aware of should be for ILP32 support in the 
hand-coded AArch64 assembly in newlib.


The short answer as to why the patch isn't upstream is that newlib 
hasn't committed it yet.


The longer answer is that the hand-coded AArch64 ASM in newlib is 
sourced from ARM's optimized-routines repository. I provided a patch 
to newlib's specifications at which point they suggested I get it 
committed upstream in the optimized-routines repo, first. I did that 
and then requested they pull the changes, but they were in the middle 
of a release cycle. Having the patch locally was the interim solution 
while we waited for that release to finish and for newlib to pull in 
the changes. I'll take a look and see what the current status on that 
is and what changes prompted the patch to break.


I just rebuilt this on the current RTEMS6 GCC10 branch with current 
newlib (ed32020) and had no problems building it. It's odd that the file 
is missing given that it's newly written by the patch. What else is 
necessary to reproduce the build failure?



Kinsey

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Re: Movement of confdefs instance into a static library

[Kinsey Moore]

On 3/17/2022 08:35, Sebastian Huber wrote:

On 17/03/2022 14:22, Kinsey Moore wrote:

On 3/17/2022 00:39, Sebastian Huber wrote:

Hello Kinsey,

On 16/03/2022 22:57, Kinsey Moore wrote:
Is moving the confdefs instance into a shared library supported and 
expected to work?


yes, but the order in which the linker resolves the dependencies is 
very important. You have to make sure that the custom configuration 
is resolved before the default configuration.




I was also able to resolve the linker errors by specifying some of 
the link flags multiple times or creating a linker group.


These are ways to address the ordering. It would help if you can 
show the linker command lines and the error messages.



The link command is:

arm-rtems6-gcc testsuites/fstests/fserror/test.c.113.o 
-o/home/kinsey/rtems-development/rtems-ddci/build/arm/deos/testsuites/fstests/imfs_fserror.exe 
-Wl,-Bstatic -L. -ltestimfs -lrtemstest -lrtemscpu -lrtemsbsp 
-Wl,-Bdynamic -qrtems -march=armv7-a -mfpu=neon -mfloat-abi=hard 
-mthumb -gdwarf-2 -fPIC -Wl,--gc-sections 
-L/home/kinsey/rtems-development/rtems-ddci/bsps/arm/shared/start 
-L/home/kinsey/rtems-development/rtems-ddci/bsps/arm/deos/start 
-Wl,-call_shared -Wl,-no-undefined /desk/arm/lib/libkernel.so 
/desk/arm/lib/libdeos653pal.so -L/desk/arm/appbin -ltime-prl 
-lface653 -lgcc-so -Wl,--wrap=printf -Wl,--wrap=puts -Wl,--wrap=putchar


I think the problem is that you don't use -qrtems and your start file 
has no dependency on a configuration symbol (for example 
_ISR_Stack_area_begin). You have to make sure that somehow the 
configuration in libtestimfs.a is pulled in.


Ok, thanks. -qrtems is still present in that line just after the static 
link options, but I'll see if I can add a dependency in the start file.



Kinsey

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Re: Movement of confdefs instance into a static library

[Kinsey Moore]

On 3/17/2022 00:39, Sebastian Huber wrote:

Hello Kinsey,

On 16/03/2022 22:57, Kinsey Moore wrote:
Is moving the confdefs instance into a shared library supported and 
expected to work?


yes, but the order in which the linker resolves the dependencies is 
very important. You have to make sure that the custom configuration is 
resolved before the default configuration.




I was also able to resolve the linker errors by specifying some of 
the link flags multiple times or creating a linker group.


These are ways to address the ordering. It would help if you can show 
the linker command lines and the error messages.



The link command is:

arm-rtems6-gcc testsuites/fstests/fserror/test.c.113.o 
-o/home/kinsey/rtems-development/rtems-ddci/build/arm/deos/testsuites/fstests/imfs_fserror.exe 
-Wl,-Bstatic -L. -ltestimfs -lrtemstest -lrtemscpu -lrtemsbsp 
-Wl,-Bdynamic -qrtems -march=armv7-a -mfpu=neon -mfloat-abi=hard -mthumb 
-gdwarf-2 -fPIC -Wl,--gc-sections 
-L/home/kinsey/rtems-development/rtems-ddci/bsps/arm/shared/start 
-L/home/kinsey/rtems-development/rtems-ddci/bsps/arm/deos/start 
-Wl,-call_shared -Wl,-no-undefined /desk/arm/lib/libkernel.so 
/desk/arm/lib/libdeos653pal.so -L/desk/arm/appbin -ltime-prl -lface653 
-lgcc-so -Wl,--wrap=printf -Wl,--wrap=puts -Wl,--wrap=putchar



The newly introduced linking flags toward the end are:

-Wl,-call_shared -Wl,-no-undefined /desk/arm/lib/libkernel.so 
/desk/arm/lib/libdeos653pal.so -L/desk/arm/appbin -ltime-prl -lface653 
-lgcc-so



The first error is:

/home/kinsey/rtems-development/tools/lib/gcc/arm-rtems6/10.3.1/../../../../arm-rtems6/bin/ld: 
./librtemscpu.a(threadsetstate.c.59.o): in function 
`_Thread_Scheduler_get_home':
/home/kinsey/rtems-development/rtems-ddci/build/arm/deos/../../../cpukit/include/rtems/score/threadimpl.h:1533: 
undefined reference to `_Scheduler_Table'



The remainder can be found here:

https://pbot.rmdir.de/DVjoVpxIMVsciAh69jzNuQ


Thanks,

Kinsey

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Re: RTEMS-specific Newlib patches for aarch64

[Kinsey Moore]

On 3/17/2022 05:00, Sebastian Huber wrote:

Hello,

the current Newlib build fails for aarch64 due to RTEMS-specific patches:

  CC   libc/string/libc_a-wcscmp.o
../../../gnu-mirror-gcc-0f001dd/newlib/libc/machine/aarch64/setjmp.S:29:10: 
fatal error: ../asmdefs.h: No such file or directory

   29 | #include <../asmdefs.h>
  |  ^~

Why are these patches not in upstream Newlib?

The only patch I'm aware of should be for ILP32 support in the 
hand-coded AArch64 assembly in newlib.


The short answer as to why the patch isn't upstream is that newlib 
hasn't committed it yet.


The longer answer is that the hand-coded AArch64 ASM in newlib is 
sourced from ARM's optimized-routines repository. I provided a patch to 
newlib's specifications at which point they suggested I get it committed 
upstream in the optimized-routines repo, first. I did that and then 
requested they pull the changes, but they were in the middle of a 
release cycle. Having the patch locally was the interim solution while 
we waited for that release to finish and for newlib to pull in the 
changes. I'll take a look and see what the current status on that is and 
what changes prompted the patch to break.



Kinsey

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Movement of confdefs instance into a static library

[Kinsey Moore]

Hi,
I'm working on porting Deos integration from RTEMS 5 to RTEMS 6. This requires 
linking with their shared objects and I've run into a few linking issues with 
the testsuite. I've narrowed the problems down to the way that some of the 
tests are built: any test that has its confdefs instance in a static library 
throws linker errors (missing/duplicate symbols) with the extra linking that 
occurs. This includes most of the tests under testsuites/fstests as well as 
quite a few in libtests (and possibly more). If I reintegrate the source files 
from the new static libraries directly into the executable generation step 
(i.e. imfsfserror.yml instead of libimfs.yml) as is done in RTEMS 5, the linker 
errors go away.


Is moving the confdefs instance into a shared library supported and expected to 
work?

I was also able to resolve the linker errors by specifying some of the link 
flags multiple times or creating a linker group.

Thanks,
Kinsey
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Re: [PATCH] SMP: Fix start multitasking for some targets

[Kinsey Moore]

The AArch64 changes look reasonable and resolve the bug I observed in 
both the test case you provided as well as the test where I initially 
discovered it.



Thanks,

Kinsey

On 3/8/2022 12:28, Sebastian Huber wrote:

The previous SMP multitasking start assumed that the initial heir thread of a
processor starts execution in _Thread_Handler().  The _Thread_Handler() sets
the interrupt state explicitly by _ISR_Set_level() before it calls the thread
entry.  Under certain timing conditions, processors may perform an initial
context switch to a thread which already executes its thread body (see
smptests/smpstart01).  In this case, interrupts are disabled after the context
switch on targets which do not save/restore the interrupt state during a
context switch (aarch64, arm, and riscv).

Close #4627.
---
  cpukit/score/cpu/aarch64/cpu_asm.S  | 17 +
  .../score/cpu/aarch64/include/rtems/score/cpu.h |  4 
  cpukit/score/cpu/arm/cpu_asm.S  | 12 
  cpukit/score/cpu/arm/include/rtems/score/cpu.h  |  4 
  .../score/cpu/riscv/include/rtems/score/cpu.h   |  4 
  cpukit/score/cpu/riscv/riscv-context-switch.S   | 15 +++
  cpukit/score/src/threadstartmultitasking.c  |  3 +++
  7 files changed, 59 insertions(+)

diff --git a/cpukit/score/cpu/aarch64/cpu_asm.S 
b/cpukit/score/cpu/aarch64/cpu_asm.S
index 2379698336..6321acde90 100644
--- a/cpukit/score/cpu/aarch64/cpu_asm.S
+++ b/cpukit/score/cpu/aarch64/cpu_asm.S
@@ -202,5 +202,22 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_restore)
str x5, [x2, #PER_CPU_OFFSET_EXECUTING]
  #endif
  
+	b	.L_check_is_executing

+
+DEFINE_FUNCTION_AARCH64(_AArch64_Start_multitasking)
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   /* Sanitize input for ILP32 ABI */
+   mov w0, w0
+#endif
+
+   mov x1, x0
+   GET_SELF_CPU_CONTROLreg_2
+
+   /* Switch the stack to the temporary interrupt stack of this processor 
*/
+   add sp, x2, #(PER_CPU_INTERRUPT_FRAME_AREA + 
CPU_INTERRUPT_FRAME_SIZE)
+
+   /* Enable interrupts */
+   msr DAIFClr, #0x2
+
b   .L_check_is_executing
  #endif
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index e1d9f0a5c2..fdc0e3d929 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -285,6 +285,10 @@ void _CPU_Context_Initialize(
{
  context->is_executing = is_executing;
}
+
+  RTEMS_NO_RETURN void _AArch64_Start_multitasking( Context_Control *heir );
+
+  #define _CPU_Start_multitasking( _heir ) _AArch64_Start_multitasking( _heir )
  #endif
  
  #define _CPU_Context_Restart_self( _the_context ) \

diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S
index 54d6f70b0d..d52a43f70d 100644
--- a/cpukit/score/cpu/arm/cpu_asm.S
+++ b/cpukit/score/cpu/arm/cpu_asm.S
@@ -181,6 +181,18 @@ DEFINE_FUNCTION_ARM(_CPU_Context_restore)
/* Update the executing */
str r5, [r2, #PER_CPU_OFFSET_EXECUTING]
  
+	b	.L_check_is_executing

+
+DEFINE_FUNCTION_ARM(_ARM_Start_multitasking)
+   mov r1, r0
+   GET_SELF_CPU_CONTROLr2
+
+   /* Switch the stack to the temporary interrupt stack of this processor 
*/
+   add sp, r2, #(PER_CPU_INTERRUPT_FRAME_AREA + 
CPU_INTERRUPT_FRAME_SIZE)
+
+   /* Enable IRQ interrupts */
+   cpsie   i
+
b   .L_check_is_executing
  #endif
  
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h

index da521528a4..7ac180ac26 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -443,6 +443,10 @@ void _CPU_Context_Initialize(
{
  context->is_executing = is_executing;
}
+
+  RTEMS_NO_RETURN void _ARM_Start_multitasking( Context_Control *heir );
+
+  #define _CPU_Start_multitasking( _heir ) _ARM_Start_multitasking( _heir )
  #endif
  
  #define _CPU_Context_Restart_self( _the_context ) \

diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h 
b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 05ef2709ba..471c6c6c3e 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -509,6 +509,10 @@ static inline void _CPU_Context_Set_is_executing(
context->is_executing = is_executing;
  }
  
+RTEMS_NO_RETURN void _RISCV_Start_multitasking( Context_Control *heir );

+
+#define _CPU_Start_multitasking( _heir ) _RISCV_Start_multitasking( _heir )
+
  #endif /* RTEMS_SMP */
  
  /** Type that can store a 32-bit integer or a pointer. */

diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S 
b/cpukit/score/cpu/riscv/riscv-context-switch.S
index 3c0368886e..cfaff444b0 100644
--- a/cpukit/score/cpu/riscv/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -40,6 +40,9 

Re: [PATCH 1/2] cpukit/aarch64: Keep state across context switch

[Kinsey Moore]

On 3/8/2022 02:52, Sebastian Huber wrote:

On 28/02/2022 20:18, Kinsey Moore wrote:


On 2/28/2022 12:19, Sebastian Huber wrote:

On 26/02/2022 08:03, Kinsey Moore wrote:

On 2/26/2022 00:53, Sebastian Huber wrote:

On 26/02/2022 00:41, Kinsey Moore wrote:
This may also be an issue for ARM, RISC-V and others as it 
doesn't appear that ARM saves CPSR during context switch and I 
couldn't tell that RISC-V does this either, though I'm less 
familiar with it.


This doesn't look like the right way to fix this issue.

There is currently the assumption that all processors start 
multitasking with a context switch to _Thread_Handler() which sets 
the interrupt level. It is possible to construct a scenario in 
which we start multitasking with a migration of a thread which 
already executed the _Thread_Handler() prologue. This would result 
in an execution with disabled interrupts. I think the proper fix 
for this scenario is to enable interrupts in 
_CPU_SMP_Prepare_start_multitasking().


Doing a context switch with interrupts disabled is a fatal 
application error on all architectures with


#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE

or enabled SMP support.

Ok, great. I was wondering if that was the case and this is 
definitely the kind of feedback I was looking for. I'll adjust the 
patch set to reflect that. I still wonder if this is an issue on 
other SMP CPU ports, though, since most of them don't implement 
that hook, either.


I would like to have a closer look at this next week then I am back 
from holidays.


Enabling interrupts in _CPU_SMP_Prepare_start_multitasking() would 
not work since we use the interrupt stack at this point. We should 
add a ticket and a test case for this (I can do this next week). How 
did you observe this bug?


I was only able to observe this bug once the 2/2 patch is applied and 
that optimization opens a race condition (adding a few no-ops to the 
Per_CPU_Control accessor prevents it from appearing) in the 
sppercpudata01 test on SMP configurations since the task is migrating 
across CPUs as CPUs are coming online. The race condition resolves 
nominally in 90% of cases so while it's not a frequent failure it is 
reproducible.


I added a ticket and a test case:

http://devel.rtems.org/ticket/4627

Could you please check if the test case fails currently on your 
aarch64 target?


I have verified that this test case fails under QEMU and on the hardware 
target.


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[PATCH rtems-docs] cpu-supplement: Add note about device memory

[Kinsey Moore]

Add information about restricted use of device memory for ARM and
AArch64.
---
 cpu-supplement/aarch64.rst | 5 +
 cpu-supplement/arm.rst | 6 ++
 2 files changed, 11 insertions(+)

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
index 2b3d620..4576663 100644
--- a/cpu-supplement/aarch64.rst
+++ b/cpu-supplement/aarch64.rst
@@ -73,6 +73,11 @@ A flat 64-bit or 32-bit memory model is supported depending 
on the selected mult
 variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
 for a flat memory model is handled.
 
+Note that memcpy() and memset() must not be used on device memory as those
+functions are hand-optimized and will take advantage of unaligned accesses.
+"As per ARM"(https://developer.arm.com/documentation/ka004708/latest), 
unaligned
+accesses are not permitted for device memory.
+
 Interrupt Processing
 
 
diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index ac9e8c6..03a2cd2 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -132,6 +132,12 @@ Memory Model
 A flat 32-bit memory model is supported.  The board support package must take
 care of initializing the MMU if necessary.
 
+Note that architecture variants which support unaligned accesses must not use
+memcpy() or memset() on device memory as those functions are hand-optimized and
+will take advantage of unaligned accesses where available. "As per ARM"
+(https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Alignment-support/Unaligned-data-access-restrictions-in-ARMv7-and-ARMv6),
+unaligned accesses are not permitted for device memory.
+
 Interrupt Processing
 
 
-- 
2.30.2

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rtems-lwip file locations and licensing

[Kinsey Moore]

I was looking though the rtems-lwip tree in adding license files and it struck 
me that we currently have code with possibly different licenses and from 
different external sources merged into the same tree with possibly differing 
paths from the original source locations. There is at least one file in the 
uLan sources that does not have an embedded license and the current setup makes 
discerning its license confusing. I could add what I think is the correct 
license, but I'd much prefer not to add licenses to the code given that I'm not 
the author.

That said, I'd like to suggest that we keep code from each external source in 
its own directory. Currently, the external sources are upstream lwIP and the 
uLan projects with their code being merged into a single tree with some changes 
to the location of uLan's files. My suggestion would move all uLan code to a 
uLan/ directory in the root of the rtems-lwip repository and each 
COPYING. license file as well. Each new driver source would get its own 
directory and COPYING file in the root of the repository as necessary.

Thanks,
Kinsey
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[PATCH rtems-lwip] Add missing COPYING files from lwip and uLan

[Kinsey Moore]

These are the original COPYING files from the upstream projects.
---
 COPYING.lwip | 25 +
 COPYING.uLan | 33 +
 2 files changed, 58 insertions(+)
 create mode 100644 COPYING.lwip
 create mode 100644 COPYING.uLan

diff --git a/COPYING.lwip b/COPYING.lwip
new file mode 100644
index 000..90465f5
--- /dev/null
+++ b/COPYING.lwip
@@ -0,0 +1,25 @@
+Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without 
modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice,
+   this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+3. The name of the author may not be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 
EVENT
+SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
diff --git a/COPYING.uLan b/COPYING.uLan
new file mode 100644
index 000..e23898b
--- /dev/null
+++ b/COPYING.uLan
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without 
modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *this list of conditions and the following disclaimer in the documentation
+ *and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 
IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 
EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
-- 
2.30.2

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Re: [PATCH 1/2] cpukit/aarch64: Keep state across context switch

[Kinsey Moore]

On 2/28/2022 12:19, Sebastian Huber wrote:

On 26/02/2022 08:03, Kinsey Moore wrote:

On 2/26/2022 00:53, Sebastian Huber wrote:

On 26/02/2022 00:41, Kinsey Moore wrote:
This may also be an issue for ARM, RISC-V and others as it doesn't 
appear that ARM saves CPSR during context switch and I couldn't 
tell that RISC-V does this either, though I'm less familiar with it.


This doesn't look like the right way to fix this issue.

There is currently the assumption that all processors start 
multitasking with a context switch to _Thread_Handler() which sets 
the interrupt level. It is possible to construct a scenario in which 
we start multitasking with a migration of a thread which already 
executed the _Thread_Handler() prologue. This would result in an 
execution with disabled interrupts. I think the proper fix for this 
scenario is to enable interrupts in 
_CPU_SMP_Prepare_start_multitasking().


Doing a context switch with interrupts disabled is a fatal 
application error on all architectures with


#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE

or enabled SMP support.

Ok, great. I was wondering if that was the case and this is 
definitely the kind of feedback I was looking for. I'll adjust the 
patch set to reflect that. I still wonder if this is an issue on 
other SMP CPU ports, though, since most of them don't implement that 
hook, either.


I would like to have a closer look at this next week then I am back 
from holidays.


Enabling interrupts in _CPU_SMP_Prepare_start_multitasking() would not 
work since we use the interrupt stack at this point. We should add a 
ticket and a test case for this (I can do this next week). How did you 
observe this bug?


I was only able to observe this bug once the 2/2 patch is applied and 
that optimization opens a race condition (adding a few no-ops to the 
Per_CPU_Control accessor prevents it from appearing) in the 
sppercpudata01 test on SMP configurations since the task is migrating 
across CPUs as CPUs are coming online. The race condition resolves 
nominally in 90% of cases so while it's not a frequent failure it is 
reproducible.



Kinsey

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Re: [PATCH 2/2] cpukit/aarch64: Add Per_CPU_Control accessor

[Kinsey Moore]

On 2/26/2022 12:50, Gedare Bloom wrote:

this part looks ok


Thanks, I'm going to hold off on committing this part because the 
optimization shaved enough time off of task execution that it exposed 
the bug described in the other patch which is why they're bundled.



Kinsey



On Fri, Feb 25, 2022 at 5:51 PM Kinsey Moore  wrote:

Add an architecture-specific implementation for
_CPU_Get_current_per_CPU_control() to reduce overhead for getting the
current CPU's Per_CPU_Control structure.
---
  .../cpu/aarch64/include/rtems/score/cpuimpl.h | 23 +++
  1 file changed, 23 insertions(+)

diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index 90fd48ad4e..ffdef2f30a 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -125,6 +125,29 @@ typedef struct {
uint64_t register_fpcr;
  } CPU_Interrupt_frame;

+#ifdef RTEMS_SMP
+
+static inline
+struct Per_CPU_Control *_AARCH64_Get_current_per_CPU_control( void )
+{
+  struct Per_CPU_Control *cpu_self;
+  uint64_t value;
+
+  __asm__ volatile (
+"mrs %0, TPIDR_EL1" : "=" ( value ) : : "memory"
+  );
+
+  /* Use EL1 Thread ID Register (TPIDR_EL1) */
+  cpu_self = (struct Per_CPU_Control *)(uintptr_t)value;
+
+  return cpu_self;
+}
+
+#define _CPU_Get_current_per_CPU_control() \
+  _AARCH64_Get_current_per_CPU_control()
+
+#endif /* RTEMS_SMP */
+
  void _CPU_Context_volatile_clobber( uintptr_t pattern );

  void _CPU_Context_validate( uintptr_t pattern );
--
2.30.2

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Re: [PATCH 1/2] cpukit/aarch64: Keep state across context switch

[Kinsey Moore]

On 2/26/2022 00:53, Sebastian Huber wrote:

On 26/02/2022 00:41, Kinsey Moore wrote:
This may also be an issue for ARM, RISC-V and others as it doesn't 
appear that ARM saves CPSR during context switch and I couldn't tell 
that RISC-V does this either, though I'm less familiar with it.


This doesn't look like the right way to fix this issue.

There is currently the assumption that all processors start 
multitasking with a context switch to _Thread_Handler() which sets the 
interrupt level. It is possible to construct a scenario in which we 
start multitasking with a migration of a thread which already executed 
the _Thread_Handler() prologue. This would result in an execution with 
disabled interrupts. I think the proper fix for this scenario is to 
enable interrupts in _CPU_SMP_Prepare_start_multitasking().


Doing a context switch with interrupts disabled is a fatal application 
error on all architectures with


#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE

or enabled SMP support.

Ok, great. I was wondering if that was the case and this is definitely 
the kind of feedback I was looking for. I'll adjust the patch set to 
reflect that. I still wonder if this is an issue on other SMP CPU ports, 
though, since most of them don't implement that hook, either.



Thanks,

Kinsey

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[PATCH 1/2] cpukit/aarch64: Keep state across context switch

[Kinsey Moore]

If a task migrates to a newly turned-up CPU as the first task it
executes, no guarantees are made about whether interrupts are enabled
and it is possible for a task to change interrupt enable states during
the migration. This preserves interrupt state across context switches.
---
 cpukit/score/cpu/aarch64/cpu_asm.S | 4 
 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 7 ---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/cpukit/score/cpu/aarch64/cpu_asm.S 
b/cpukit/score/cpu/aarch64/cpu_asm.S
index 2379698336..4234b428aa 100644
--- a/cpukit/score/cpu/aarch64/cpu_asm.S
+++ b/cpukit/score/cpu/aarch64/cpu_asm.S
@@ -83,6 +83,8 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
stp fp,  lr,  [x0, #0x50]
mov x4,  sp
str x4,  [x0, #0x60]
+   mrs x5,  daif
+   str x5,  [x0, #0x78]
 
 #ifdef AARCH64_MULTILIB_VFP
add x5, x0, #AARCH64_CONTEXT_CONTROL_D8_OFFSET
@@ -151,6 +153,8 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
ldp fp,  lr,  [x1, #0x50]
ldr x4,  [x1, #0x60]
mov sp,  x4
+   ldr x5,  [x1, #0x78]
+   msr daif, x5
ret
 
 /*
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index e1d9f0a5c2..2f252bf2f4 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -127,16 +127,16 @@
 #define AARCH64_CONTEXT_CONTROL_THREAD_ID_OFFSET 0x70
 
 #ifdef AARCH64_MULTILIB_VFP
-  #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x78
+  #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x80
 #endif
 
 #define AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 0x68
 
 #ifdef RTEMS_SMP
   #if defined(AARCH64_MULTILIB_VFP)
-#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xb8
+#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xc0
   #else
-#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x78
+#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x80
   #endif
 #endif
 
@@ -174,6 +174,7 @@ typedef struct {
   uint64_t register_sp;
   uint64_t isr_dispatch_disable;
   uint64_t thread_id;
+  uint64_t daif;
 #ifdef AARCH64_MULTILIB_VFP
   uint64_t register_d8;
   uint64_t register_d9;
-- 
2.30.2

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[PATCH 2/2] cpukit/aarch64: Add Per_CPU_Control accessor

[Kinsey Moore]

Add an architecture-specific implementation for
_CPU_Get_current_per_CPU_control() to reduce overhead for getting the
current CPU's Per_CPU_Control structure.
---
 .../cpu/aarch64/include/rtems/score/cpuimpl.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index 90fd48ad4e..ffdef2f30a 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -125,6 +125,29 @@ typedef struct {
   uint64_t register_fpcr;
 } CPU_Interrupt_frame;
 
+#ifdef RTEMS_SMP
+
+static inline
+struct Per_CPU_Control *_AARCH64_Get_current_per_CPU_control( void )
+{
+  struct Per_CPU_Control *cpu_self;
+  uint64_t value;
+
+  __asm__ volatile (
+"mrs %0, TPIDR_EL1" : "=" ( value ) : : "memory"
+  );
+
+  /* Use EL1 Thread ID Register (TPIDR_EL1) */
+  cpu_self = (struct Per_CPU_Control *)(uintptr_t)value;
+
+  return cpu_self;
+}
+
+#define _CPU_Get_current_per_CPU_control() \
+  _AARCH64_Get_current_per_CPU_control()
+
+#endif /* RTEMS_SMP */
+
 void _CPU_Context_volatile_clobber( uintptr_t pattern );
 
 void _CPU_Context_validate( uintptr_t pattern );
-- 
2.30.2

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Re: [PATCH 1/2] cpukit/aarch64: Keep state across context switch

[Kinsey Moore]

This may also be an issue for ARM, RISC-V and others as it doesn't 
appear that ARM saves CPSR during context switch and I couldn't tell 
that RISC-V does this either, though I'm less familiar with it.



Kinsey

On 2/25/2022 17:33, Kinsey Moore wrote:

If a task migrates to a newly turned-up CPU as the first task it
executes, no guarantees are made about whether interrupts are enabled
and it is possible for a task to change interrupt enable states during
the migration. This preserves interrupt state across context switches.
---
  cpukit/score/cpu/aarch64/cpu_asm.S | 4 
  cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 7 ---
  2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/cpukit/score/cpu/aarch64/cpu_asm.S 
b/cpukit/score/cpu/aarch64/cpu_asm.S
index 2379698336..4234b428aa 100644
--- a/cpukit/score/cpu/aarch64/cpu_asm.S
+++ b/cpukit/score/cpu/aarch64/cpu_asm.S
@@ -83,6 +83,8 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
stp fp,  lr,  [x0, #0x50]
mov x4,  sp
str x4,  [x0, #0x60]
+   mrs x5,  daif
+   str x5,  [x0, #0x78]
  
  #ifdef AARCH64_MULTILIB_VFP

add x5, x0, #AARCH64_CONTEXT_CONTROL_D8_OFFSET
@@ -151,6 +153,8 @@ DEFINE_FUNCTION_AARCH64(_CPU_Context_switch)
ldp fp,  lr,  [x1, #0x50]
ldr x4,  [x1, #0x60]
mov sp,  x4
+   ldr x5,  [x1, #0x78]
+   msr daif, x5
ret
  
  /*

diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index e1d9f0a5c2..2f252bf2f4 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -127,16 +127,16 @@
  #define AARCH64_CONTEXT_CONTROL_THREAD_ID_OFFSET 0x70
  
  #ifdef AARCH64_MULTILIB_VFP

-  #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x78
+  #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x80
  #endif
  
  #define AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 0x68
  
  #ifdef RTEMS_SMP

#if defined(AARCH64_MULTILIB_VFP)
-#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xb8
+#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xc0
#else
-#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x78
+#define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x80
#endif
  #endif
  
@@ -174,6 +174,7 @@ typedef struct {

uint64_t register_sp;
uint64_t isr_dispatch_disable;
uint64_t thread_id;
+  uint64_t daif;
  #ifdef AARCH64_MULTILIB_VFP
uint64_t register_d8;
uint64_t register_d9;

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[PATCH] spec/microblaze: Use configurable RAM size

[Kinsey Moore]

When committed, the MicroBlaze RAM size was hard-coded to 16MB. This
changes the default to 256MB and sets the KCU105 BSPs to 2GB since that
is what the board has on it.
---
 .../bsps/microblaze/microblaze_fpga/grp.yml   |  2 ++
 .../microblaze/microblaze_fpga/linkcmds.yml   |  2 +-
 .../microblaze/microblaze_fpga/optramlen.yml  | 21 +++
 3 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml

diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
index 3069ff2ff8..11df1802f1 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml
@@ -33,6 +33,8 @@ links:
   uid: opticachesize
 - role: build-dependency
   uid: optintcbaseaddress
+- role: build-dependency
+  uid: optramlen
 - role: build-dependency
   uid: opttimerbaseaddress
 - role: build-dependency
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
index d478e86fb6..9a3ca11b51 100644
--- a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
+++ b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml
@@ -35,7 +35,7 @@ content: |
   MEMORY
 {
 BRAM (AIW) : ORIGIN = 0x, LENGTH = 0x1
-RAM   : ORIGIN = _TEXT_START_ADDR, LENGTH = 0x100
+RAM   : ORIGIN = _TEXT_START_ADDR, LENGTH = 
${BSP_MICROBLAZE_FPGA_RAM_LENGTH}
 }
 
   REGION_ALIAS ("REGION_START", BRAM);
diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml 
b/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml
new file mode 100644
index 00..748b78f0a2
--- /dev/null
+++ b/spec/build/bsps/microblaze/microblaze_fpga/optramlen.yml
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research (OAR)
+default: 0x1000
+default-by-variant:
+- value: 0x8000
+  variants:
+  - microblaze/kcu105.*
+description: |
+  length of memory area available to the BSP
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_RAM_LENGTH
+type: build
-- 
2.30.2

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[PATCH v3 5/5] cpukit/libdebugger: Add MicroBlaze support

[Kinsey Moore]

Add MicroBlaze support for libdebugger. This uses only software break
type instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.

Also of note, this implementation for MicroBlaze would typically use the
brki instruction for software break, but instead uses an illegal opcode
to manage software breaks as exceptions. This is due to poor interaction
with the debug hardware where the debug hardware will intercept software
breaks instead of allowing the software break vector to execute.
---
 .../libdebugger/rtems-debugger-microblaze.c   | 1393 +
 .../cpu/microblaze/include/rtems/score/cpu.h  |   24 +
 spec/build/cpukit/libdebugger.yml |2 +
 spec/build/cpukit/objdbgmicroblaze.yml|   15 +
 spec/build/cpukit/optlibdebugger.yml  |1 +
 5 files changed, 1435 insertions(+)
 create mode 100644 cpukit/libdebugger/rtems-debugger-microblaze.c
 create mode 100644 spec/build/cpukit/objdbgmicroblaze.yml

diff --git a/cpukit/libdebugger/rtems-debugger-microblaze.c 
b/cpukit/libdebugger/rtems-debugger-microblaze.c
new file mode 100644
index 00..377a731664
--- /dev/null
+++ b/cpukit/libdebugger/rtems-debugger-microblaze.c
@@ -0,0 +1,1393 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSLibdebugger
+ *
+ * @brief MicroBlaze libdebugger implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define TARGET_DEBUG 0
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+#include 
+
+/* Defined by linkcmds.base */
+extern char bsp_section_text_begin[];
+extern char bsp_section_text_end[];
+extern char bsp_section_fast_text_begin[];
+extern char bsp_section_fast_text_end[];
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "rtems-debugger-target.h"
+#include "rtems-debugger-threads.h"
+
+#if TARGET_DEBUG
+#include 
+#endif
+
+/*
+ * Number of registers.
+ */
+#define RTEMS_DEBUGGER_NUMREGS 57
+
+/*
+ * Number of bytes per type of register.
+ */
+#define RTEMS_DEBUGGER_REG_BYTES4
+
+/* Debugger registers layout. See microblaze-core.xml in GDB source. */
+#define REG_R00
+#define REG_R11
+#define REG_R22
+#define REG_R33
+#define REG_R44
+#define REG_R55
+#define REG_R66
+#define REG_R77
+#define REG_R88
+#define REG_R99
+#define REG_R10   10
+#define REG_R11   11
+#define REG_R12   12
+#define REG_R13   13
+#define REG_R14   14
+#define REG_R15   15
+#define REG_R16   16
+#define REG_R17   17
+#define REG_R18   18
+#define REG_R19   19
+#define REG_R20   20
+#define REG_R21   21
+#define REG_R22   22
+#define REG_R23   23
+#define REG_R24   24
+#define REG_R25   25
+#define REG_R26   26
+#define REG_R27   27
+#define REG_R28   28
+#define REG_R29   29
+#define REG_R30   30
+#define REG_R31   31
+#define REG_PC32
+#define REG_MS33
+#define REG_EA34
+#define REG_ES35
+#define REG_FS36
+#define REG_BT37
+#define REG_PV0   38
+#define REG_PV1   39
+#define REG_PV2   40
+#define REG_PV3   41
+#define REG_PV4   42
+#define REG_PV5   43
+#define REG_PV6   44
+#define REG_PV7   45
+#define REG_PV8   46
+#define REG_PV9   47
+#define REG_PV10  48
+#define REG_PV11  49
+#define REG_ED50
+#define REG_PID   51
+#define REG_ZP52
+#define REG_TBLX  53
+#define REG_TBLSX 54
+#define REG_TBLLO 55
+#define REG_TBLHI 56
+
+/**
+ * Register offset table with the total as the last entry.
+ *
+ * Check this table in gdb with the command:
+ *
+ *   maint print registers
+ */
+static const size_t 

[PATCH v3 3/5] microblaze: Decouple exceptions from interrupts

[Kinsey Moore]

Exception handling should be enabled at all times during execution to
ensure that exceptions are not ignored which would cause further
problems. This separates use of the exception enable bit from use of the
interrupt enable bit in the machine status register so that they can be
manipulated independently.
---
 bsps/microblaze/microblaze_fpga/start/crtinit.S   |  3 +++
 cpukit/score/cpu/microblaze/cpu.c |  6 +++---
 cpukit/score/cpu/microblaze/include/rtems/score/cpu.h | 10 +-
 3 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S 
b/bsps/microblaze/microblaze_fpga/start/crtinit.S
index a9779404b2..d56bee3b19 100644
--- a/bsps/microblaze/microblaze_fpga/start/crtinit.S
+++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S
@@ -81,6 +81,9 @@ _crtinit:
 #ifndef __rtems__
brlid   r15, main  /* Execute 
the program */
 #else
+   mfs r3, rmsr
+   ori r3, r3, 0x100  /* Set 
Exception Enable MSR flag */
+   mts rmsr, r3
brlid   r15, boot_card
 #endif /* __rtems__ */
addir5, r0, 0
diff --git a/cpukit/score/cpu/microblaze/cpu.c 
b/cpukit/score/cpu/microblaze/cpu.c
index fe55ef5546..1e829a4714 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -142,9 +142,9 @@ void _CPU_ISR_Set_level( uint32_t level )
   _CPU_MSR_GET( microblaze_switch_reg );
 
   if ( level == 0 ) {
-microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE);
+microblaze_switch_reg |= MICROBLAZE_MSR_IE;
   } else {
-microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE);
+microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE);
   }
 
   _CPU_MSR_SET( microblaze_switch_reg );
@@ -158,7 +158,7 @@ uint32_t _CPU_ISR_Get_level( void )
 
   /* This is unique. The MSR register contains an interrupt enable flag where
* most other architectures have an interrupt disable flag. */
-  return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0;
+  return ( level & MICROBLAZE_MSR_IE ) == 0;
 }
 
 void _CPU_ISR_install_vector(
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h 
b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index 5ca0609e91..181d247c5f 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -212,7 +212,7 @@ typedef struct {
   { \
 unsigned int _new_msr;  \
 _CPU_MSR_GET(_isr_cookie); \
-_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
 _CPU_MSR_SET(_new_msr); \
   }
 
@@ -221,9 +221,9 @@ typedef struct {
 uint32_t _microblaze_interrupt_enable; \
 uint32_t _microblaze_switch_reg; \
 \
-_microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE | 
MICROBLAZE_MSR_EE); \
+_microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE); \
 _CPU_MSR_GET(_microblaze_switch_reg); \
-_microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+_microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE); \
 _microblaze_switch_reg |= _microblaze_interrupt_enable; \
 _CPU_MSR_SET(_microblaze_switch_reg); \
   }
@@ -232,7 +232,7 @@ typedef struct {
   { \
 unsigned int _new_msr;  \
 _CPU_MSR_SET(_isr_cookie); \
-_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
 _CPU_MSR_SET(_new_msr); \
   }
 
@@ -242,7 +242,7 @@ uint32_t _CPU_ISR_Get_level( void );
 
 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
 {
-  return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) != 0;
+  return ( level & MICROBLAZE_MSR_IE ) != 0;
 }
 
 void _CPU_Context_Initialize(
-- 
2.30.2

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[PATCH v3 4/5] cpukit/libdebugger: Avoid cascade for interrupts

[Kinsey Moore]

This updates behavior of libdebugger to handle debug exceptions in
interrupt context by temporarily removing a software breakpoint,
stepping, and then resuming afterward.
---
 cpukit/libdebugger/rtems-debugger-target.c | 105 +++--
 cpukit/libdebugger/rtems-debugger-target.h |   5 +
 2 files changed, 104 insertions(+), 6 deletions(-)

diff --git a/cpukit/libdebugger/rtems-debugger-target.c 
b/cpukit/libdebugger/rtems-debugger-target.c
index c298a62357..2b55c93513 100644
--- a/cpukit/libdebugger/rtems-debugger-target.c
+++ b/cpukit/libdebugger/rtems-debugger-target.c
@@ -167,6 +167,32 @@ rtems_debugger_target_reg_table_size(void)
   return 0;
 }
 
+bool
+rtems_debugger_target_swbreak_is_configured( uintptr_t addr )
+{
+  size_t i;
+  rtems_debugger_target_swbreak *swbreaks;
+  rtems_debugger_target *target = rtems_debugger->target;
+
+  if ( target == NULL ) {
+return false;
+  }
+
+  swbreaks = target->swbreaks.block;
+
+  if ( swbreaks == NULL ) {
+return false;
+  }
+
+  for ( i = 0; i < target->swbreaks.level; ++i ) {
+if ( (uintptr_t) swbreaks[ i ].address == addr ) {
+  return true;
+}
+  }
+
+  return false;
+}
+
 int
 rtems_debugger_target_swbreak_control(bool insert, uintptr_t addr, DB_UINT 
kind)
 {
@@ -323,13 +349,81 @@ rtems_debugger_target_swbreak_remove(void)
   return r;
 }
 
+uintptr_t saved_break_address = 0;
+rtems_id saved_tid = 0;
+
+static rtems_debugger_target_exc_action
+soft_step_and_continue(CPU_Exception_frame* frame)
+{
+  uintptr_t  break_address;
+  rtems_debugger_target *target = rtems_debugger->target;
+  Thread_Control*thread = _Thread_Get_executing();
+  const rtems_id tid = thread->Object.id;
+  rtems_debugger_thread  fake_debugger_thread;
+
+  /*
+   * If this was a hwbreak, cascade. If this is a swbreak replace the contents
+   * of the instruction, step then return the swbreak's contents.
+   */
+  if ((target->capabilities & RTEMS_DEBUGGER_TARGET_CAP_SWBREAK) == 0) {
+target_printk("rtems-db: exception in an interrupt, cascading\n");
+rtems_debugger_unlock();
+return rtems_debugger_target_exc_cascade;
+  }
+
+  break_address = rtems_debugger_target_frame_pc( frame );
+  if ( rtems_debugger_target_swbreak_is_configured( break_address ) == false ) 
{
+target_printk("rtems-db: exception in an interrupt, cascading\n");
+rtems_debugger_unlock();
+return rtems_debugger_target_exc_cascade;
+  }
+
+  /* Remove the current breakpoint */
+  rtems_debugger_target_swbreak_control(
+false,
+break_address,
+target->breakpoint_size
+  );
+
+  /* Save off thread ID and break address for later usage */
+  saved_tid = tid;
+  saved_break_address = break_address;
+
+  /* Populate the fake rtems_debugger_thread */
+  fake_debugger_thread.flags |= RTEMS_DEBUGGER_THREAD_FLAG_STEP;
+  fake_debugger_thread.frame = frame;
+  target_printk("rtems-db: stepping to the next instruction\n");
+  rtems_debugger_target_thread_stepping(_debugger_thread);
+
+  /* rtems_debugger_unlock() not called until the step is resolved */
+  return rtems_debugger_target_exc_step;
+}
+
 rtems_debugger_target_exc_action
 rtems_debugger_target_exception(CPU_Exception_frame* frame)
 {
+  Thread_Control* thread = _Thread_Get_executing();
+  const rtems_id  tid = thread->Object.id;
+
+  /* Resolve outstanding step+continue */
+  if ( saved_break_address != 0 && tid == saved_tid ) {
+rtems_debugger_target_swbreak_control(
+  true,
+  saved_break_address,
+  rtems_debugger->target->breakpoint_size
+);
+saved_break_address = saved_tid = 0;
+
+/* Release the debugger lock now that the step+continue is complete */
+target_printk("rtems-db: resuming after step\n");
+rtems_debugger_unlock();
+return rtems_debugger_target_exc_consumed;
+  }
+
+  rtems_debugger_lock();
+
   if (!rtems_interrupt_is_in_progress()) {
 rtems_debugger_threads*  threads = rtems_debugger->threads;
-Thread_Control*  thread = _Thread_Get_executing();
-const rtems_id   tid = thread->Object.id;
 rtems_id*excludes;
 uintptr_tpc;
 const rtems_debugger_thread_stepper* stepper;
@@ -340,8 +434,6 @@ rtems_debugger_target_exception(CPU_Exception_frame* frame)
   " frame:%08" PRIxPTR "\n",
   tid, (intptr_t) thread, (intptr_t) frame);
 
-rtems_debugger_lock();
-
 /*
  * If the thread is in the debugger recover. If the access is from gdb
  * continue else shutdown and let the user know.
@@ -430,9 +522,10 @@ rtems_debugger_target_exception(CPU_Exception_frame* frame)
 return rtems_debugger_target_exc_consumed;
   }
 
-  rtems_debugger_printf("rtems-db: exception in an interrupt, cascading\n");
+  target_printk("[} tid:%08" PRIx32 ": exception in interrupt context\n", tid);
 
-  return rtems_debugger_target_exc_cascade;

[PATCH v3 0/5] Add MicroBlaze libdebugger support

[Kinsey Moore]

Changes from v2:
* Removed interrupt hooks in favor of step and continue behavior


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[PATCH v3 2/5] cpukit/libdebugger: Add pure swbreak capability

[Kinsey Moore]

Add a capability that allows for implementations that operate purely
using software breaks. Due to this implementation method, software
breaks must not be restored until just before returning control to the
thread itself and will be handled by the implementation through thread
switch and interrupt hooks.
---
 cpukit/libdebugger/rtems-debugger-target.h  | 14 +++---
 cpukit/libdebugger/rtems-debugger-threads.c |  4 +++-
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/cpukit/libdebugger/rtems-debugger-target.h 
b/cpukit/libdebugger/rtems-debugger-target.h
index 1e132fb28c..7836f93bd6 100644
--- a/cpukit/libdebugger/rtems-debugger-target.h
+++ b/cpukit/libdebugger/rtems-debugger-target.h
@@ -49,9 +49,17 @@ extern "C" {
 /**
  * Target capabilities mask.
  */
-#define RTEMS_DEBUGGER_TARGET_CAP_SWBREAK   (1 << 0)
-#define RTEMS_DEBUGGER_TARGET_CAP_HWBREAK   (1 << 1)
-#define RTEMS_DEBUGGER_TARGET_CAP_HWWATCH   (1 << 2)
+#define RTEMS_DEBUGGER_TARGET_CAP_SWBREAK  (1 << 0)
+#define RTEMS_DEBUGGER_TARGET_CAP_HWBREAK  (1 << 1)
+#define RTEMS_DEBUGGER_TARGET_CAP_HWWATCH  (1 << 2)
+/*
+ * This target capability indicates that the target implementation uses a pure
+ * software break implementation which must not allow breakpoints to be
+ * inserted before the actual switch to the thread, be it in interrupt context
+ * or otherwise. Such implementations must necessarily implement a thread
+ * switch hook and interrupt hooks to handle these situations.
+ */
+#define RTEMS_DEBUGGER_TARGET_CAP_PURE_SWBREAK (1 << 3)
 
 /**
  * Types of hardware breakpoints.
diff --git a/cpukit/libdebugger/rtems-debugger-threads.c 
b/cpukit/libdebugger/rtems-debugger-threads.c
index c628c0250e..841199bfe3 100644
--- a/cpukit/libdebugger/rtems-debugger-threads.c
+++ b/cpukit/libdebugger/rtems-debugger-threads.c
@@ -355,9 +355,11 @@ rtems_debugger_thread_system_resume(bool detaching)
   current = rtems_debugger_thread_current(threads);
   if (current != NULL) {
 size_t i;
+rtems_debugger_target* target = rtems_debugger->target;
 if (rtems_debugger_verbose())
   rtems_debugger_printf("rtems-db: sys:: resuming\n");
-if (!detaching) {
+if (!detaching
+  && (target->capabilities & RTEMS_DEBUGGER_TARGET_CAP_PURE_SWBREAK) == 0) 
{
   r = rtems_debugger_target_swbreak_insert();
   if (r == 0)
 r = rtems_debugger_target_hwbreak_insert();
-- 
2.30.2

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[PATCH v3 1/5] cpukit/libdebugger: Avoid missed swbreak removal

[Kinsey Moore]

It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost. This ensures that the original instruction is
restored when a software break is removed.
---
 cpukit/libdebugger/rtems-debugger-target.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/cpukit/libdebugger/rtems-debugger-target.c 
b/cpukit/libdebugger/rtems-debugger-target.c
index 04b274909b..c298a62357 100644
--- a/cpukit/libdebugger/rtems-debugger-target.c
+++ b/cpukit/libdebugger/rtems-debugger-target.c
@@ -191,6 +191,22 @@ rtems_debugger_target_swbreak_control(bool insert, 
uintptr_t addr, DB_UINT kind)
 if (loc == swbreaks[i].address) {
   size_t remaining;
   if (!insert) {
+if (target->breakpoint_size > 4)
+  memcpy(loc, swbreaks[i].contents, target->breakpoint_size);
+else {
+  switch (target->breakpoint_size) {
+  case 4:
+loc[3] = swbreaks[i].contents[3];
+  case 3:
+loc[2] = swbreaks[i].contents[2];
+  case 2:
+loc[1] = swbreaks[i].contents[1];
+  case 1:
+loc[0] = swbreaks[i].contents[0];
+break;
+  }
+}
+rtems_debugger_target_cache_sync([i]);
 --target->swbreaks.level;
 remaining = (target->swbreaks.level - i) * swbreak_size;
 memmove([i], [i + 1], remaining);
-- 
2.30.2

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Re: [PATCH v1 3/5] cpukit/microblaze: Add interrupt hooks

[Kinsey Moore]

On 2/18/2022 14:37, Gedare Bloom wrote:

On Fri, Feb 18, 2022 at 6:50 AM Kinsey Moore  wrote:

On 2/17/2022 20:31, Chris Johns wrote:

On 18/2/22 8:58 am, Kinsey Moore wrote:

On 2/17/2022 15:31, Chris Johns wrote:

On 18/2/22 7:12 am, Kinsey Moore wrote:

On 2/17/2022 13:53, Chris Johns wrote:

Who is setting breaks points in interrupts?

Where I encountered issues was setting breaks in library functions that I was
stepping through in non-interrupt context, particularly in memset(). ISR
handlers can also call into this library code and libdebugger bails when
application debugging intersects with ISR handler execution.

Interesting use case. Does this effect all archs? I think it does.

It does to an extent. Stepping through with inverse breakpoints on ARM and
single-step mode on AArch64 wouldn't encounter this issue, but software
breakpoints placed in those shared functions would cause the same problems I'm
seeing on MicroBlaze. ARM may not see this issue at all if it makes hardware
breakpoints available, but I don't remember whether it does.

Hmm .. the GDB solution is to place the instruction back and step then return
the break point. I am not sure if this is possible and less intrusive to the 
system?

Does this solution means the interrupts have extra overheads?

In the nominal case (libdebugger not running), the overhead is less than
30 instructions per interrupt execution which could theoretically be
optimized a bit by integrating the handler dispatch into the ISR_Handler
assembly instead of having it be a stand-alone C function. In the case
where libdebugger is running, the overhead is the nominal overhead plus
O(n) on the number of software breakpoints installed. If I had to hazard
a guess on the incremental number of instructions per software break,
I'd put it at 50 or so on top of the overhead of the call chain to get
there.

Kinsey

I think this will be undesirable in production. Can we find a way to
make it conditional compilation?
As mentioned in the RTEMS discord, I'm going to pursue elimination of 
the interrupt hooks in favor of a slight change to the behavior of 
libdebugger on software break in interrupt context that should solve 
similar issues across all libdebugger backends that use software breaks 
in any capacity.


Kinsey

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[PATCH v2 6/6] cpukit/libdebugger: Add MicroBlaze support

[Kinsey Moore]

Add MicroBlaze support for libdebugger. This uses only software break
type instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.

Also of note, this implementation for MicroBlaze would typically use the
brki instruction for software break, but instead uses an illegal opcode
to manage software breaks as exceptions. This is due to poor interaction
with the debug hardware where the debug hardware will intercept software
breaks instead of allowing the software break vector to execute.
---
 .../libdebugger/rtems-debugger-microblaze.c   | 1462 +
 .../cpu/microblaze/include/rtems/score/cpu.h  |   24 +
 spec/build/cpukit/libdebugger.yml |2 +
 spec/build/cpukit/objdbgmicroblaze.yml|   15 +
 spec/build/cpukit/optlibdebugger.yml  |1 +
 5 files changed, 1504 insertions(+)
 create mode 100644 cpukit/libdebugger/rtems-debugger-microblaze.c
 create mode 100644 spec/build/cpukit/objdbgmicroblaze.yml

diff --git a/cpukit/libdebugger/rtems-debugger-microblaze.c 
b/cpukit/libdebugger/rtems-debugger-microblaze.c
new file mode 100644
index 00..13b43b287b
--- /dev/null
+++ b/cpukit/libdebugger/rtems-debugger-microblaze.c
@@ -0,0 +1,1462 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSLibdebugger
+ *
+ * @brief MicroBlaze libdebugger implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define TARGET_DEBUG 0
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+#include 
+
+/* Defined by linkcmds.base */
+extern char bsp_section_text_begin[];
+extern char bsp_section_text_end[];
+extern char bsp_section_fast_text_begin[];
+extern char bsp_section_fast_text_end[];
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "rtems-debugger-target.h"
+#include "rtems-debugger-threads.h"
+
+#if TARGET_DEBUG
+#include 
+#endif
+
+/*
+ * Number of registers.
+ */
+#define RTEMS_DEBUGGER_NUMREGS 57
+
+/*
+ * Number of bytes per type of register.
+ */
+#define RTEMS_DEBUGGER_REG_BYTES4
+
+/* Debugger registers layout. See microblaze-core.xml in GDB source. */
+#define REG_R00
+#define REG_R11
+#define REG_R22
+#define REG_R33
+#define REG_R44
+#define REG_R55
+#define REG_R66
+#define REG_R77
+#define REG_R88
+#define REG_R99
+#define REG_R10   10
+#define REG_R11   11
+#define REG_R12   12
+#define REG_R13   13
+#define REG_R14   14
+#define REG_R15   15
+#define REG_R16   16
+#define REG_R17   17
+#define REG_R18   18
+#define REG_R19   19
+#define REG_R20   20
+#define REG_R21   21
+#define REG_R22   22
+#define REG_R23   23
+#define REG_R24   24
+#define REG_R25   25
+#define REG_R26   26
+#define REG_R27   27
+#define REG_R28   28
+#define REG_R29   29
+#define REG_R30   30
+#define REG_R31   31
+#define REG_PC32
+#define REG_MS33
+#define REG_EA34
+#define REG_ES35
+#define REG_FS36
+#define REG_BT37
+#define REG_PV0   38
+#define REG_PV1   39
+#define REG_PV2   40
+#define REG_PV3   41
+#define REG_PV4   42
+#define REG_PV5   43
+#define REG_PV6   44
+#define REG_PV7   45
+#define REG_PV8   46
+#define REG_PV9   47
+#define REG_PV10  48
+#define REG_PV11  49
+#define REG_ED50
+#define REG_PID   51
+#define REG_ZP52
+#define REG_TBLX  53
+#define REG_TBLSX 54
+#define REG_TBLLO 55
+#define REG_TBLHI 56
+
+/**
+ * Register offset table with the total as the last entry.
+ *
+ * Check this table in gdb with the command:
+ *
+ *   maint print registers
+ */
+static const size_t 

[PATCH v2 5/6] cpukit/microblaze: Create interrupt flag

[Kinsey Moore]

The MicroBlaze Machine Status Register (MSR) does not have a flag that
designates the current execution status of the interrupt handler other
than the Interrupt Enable (IE) bit which may be unset for other reasons.
This makes use of R13 to signal the current interrupt nesting
encompassing the entirety of interrupt execution versus the more limited
scope of ISR_NEST_LEVEL. R13 would typically be used as a TLS data
pointer, but is currently unused by RTEMS. This interrupt flag is
necessary for a pure software break libdebugger backend implementation
since interrupt execution status must be known during thread dispatch.
---
 cpukit/score/cpu/microblaze/cpu_asm.S | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 6bd81eedd9..5bb1a944b0 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -41,6 +41,17 @@
.align 2
 
 _ISR_Handler:
+   /*
+* Increment interrupt context flag. This TLS register is coopted for
+* this purpose since it is not used by RTEMS. R2 would suffice as well,
+* but would need to be added to Context_Control. This is used by
+* libdebugger since ISR_NEST_LEVEL is not sufficient to indicate
+* execution in interrupt context after the stack is switched back for
+* thread dispatch. There is no MSR bit to indicate Interrupt in
+* Progress.
+*/
+   addik r13, r13, 1
+
/* Save stack frame */
swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
@@ -153,5 +164,8 @@ quick_exit:
/* Remove stack frame */
addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
 
+   /* Decrement interrupt context flag */
+   addik r13, r13, -1
+
rtid r14, 0
nop
-- 
2.30.2

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[PATCH v2 4/6] microblaze: Decouple exceptions from interrupts

[Kinsey Moore]

Exception handling should be enabled at all times during execution to
ensure that exceptions are not ignored which would cause further
problems. This separates use of the exception enable bit from use of the
interrupt enable bit in the machine status register so that they can be
manipulated independently.
---
 bsps/microblaze/microblaze_fpga/start/crtinit.S   |  3 +++
 cpukit/score/cpu/microblaze/cpu.c |  6 +++---
 cpukit/score/cpu/microblaze/include/rtems/score/cpu.h | 10 +-
 3 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S 
b/bsps/microblaze/microblaze_fpga/start/crtinit.S
index a9779404b2..d56bee3b19 100644
--- a/bsps/microblaze/microblaze_fpga/start/crtinit.S
+++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S
@@ -81,6 +81,9 @@ _crtinit:
 #ifndef __rtems__
brlid   r15, main  /* Execute 
the program */
 #else
+   mfs r3, rmsr
+   ori r3, r3, 0x100  /* Set 
Exception Enable MSR flag */
+   mts rmsr, r3
brlid   r15, boot_card
 #endif /* __rtems__ */
addir5, r0, 0
diff --git a/cpukit/score/cpu/microblaze/cpu.c 
b/cpukit/score/cpu/microblaze/cpu.c
index 960ac1bfea..259053f88a 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -142,9 +142,9 @@ void _CPU_ISR_Set_level( uint32_t level )
   _CPU_MSR_GET( microblaze_switch_reg );
 
   if ( level == 0 ) {
-microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE);
+microblaze_switch_reg |= MICROBLAZE_MSR_IE;
   } else {
-microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE);
+microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE);
   }
 
   _CPU_MSR_SET( microblaze_switch_reg );
@@ -158,7 +158,7 @@ uint32_t _CPU_ISR_Get_level( void )
 
   /* This is unique. The MSR register contains an interrupt enable flag where
* most other architectures have an interrupt disable flag. */
-  return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0;
+  return ( level & MICROBLAZE_MSR_IE ) == 0;
 }
 
 void _CPU_ISR_install_vector(
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h 
b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index 9c6b213e20..253810ad59 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -212,7 +212,7 @@ typedef struct {
   { \
 unsigned int _new_msr;  \
 _CPU_MSR_GET(_isr_cookie); \
-_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
 _CPU_MSR_SET(_new_msr); \
   }
 
@@ -221,9 +221,9 @@ typedef struct {
 uint32_t _microblaze_interrupt_enable; \
 uint32_t _microblaze_switch_reg; \
 \
-_microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE | 
MICROBLAZE_MSR_EE); \
+_microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE); \
 _CPU_MSR_GET(_microblaze_switch_reg); \
-_microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+_microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE); \
 _microblaze_switch_reg |= _microblaze_interrupt_enable; \
 _CPU_MSR_SET(_microblaze_switch_reg); \
   }
@@ -232,7 +232,7 @@ typedef struct {
   { \
 unsigned int _new_msr;  \
 _CPU_MSR_SET(_isr_cookie); \
-_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \
+_new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \
 _CPU_MSR_SET(_new_msr); \
   }
 
@@ -242,7 +242,7 @@ uint32_t _CPU_ISR_Get_level( void );
 
 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
 {
-  return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) != 0;
+  return ( level & MICROBLAZE_MSR_IE ) != 0;
 }
 
 void _CPU_Context_Initialize(
-- 
2.30.2

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[PATCH v2 3/6] cpukit/microblaze: Add interrupt hooks

[Kinsey Moore]

Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze libdebugger
backend to prevent software breaks from occurring in interrupt context.
---
 cpukit/score/cpu/microblaze/cpu.c | 42 +++
 cpukit/score/cpu/microblaze/cpu_asm.S | 12 ++
 .../cpu/microblaze/include/rtems/score/cpu.h  | 17 
 3 files changed, 71 insertions(+)

diff --git a/cpukit/score/cpu/microblaze/cpu.c 
b/cpukit/score/cpu/microblaze/cpu.c
index fe55ef5546..960ac1bfea 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -229,3 +229,45 @@ void _MicroBlaze_Debug_handle( CPU_Exception_frame *ef )
 
   rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) ef );
 }
+
+MicroBlaze_Interrupt_hook installed_preint_hook = NULL;
+
+void _MicroBlaze_Pre_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+)
+{
+  if ( old_hook != NULL ) {
+*old_hook = installed_preint_hook;
+  }
+
+  installed_preint_hook = new_hook;
+}
+
+void _MicroBlaze_Pre_Interrupt_hook()
+{
+  if ( installed_preint_hook != NULL ) {
+installed_preint_hook();
+  }
+}
+
+MicroBlaze_Interrupt_hook installed_postint_hook = NULL;
+
+void _MicroBlaze_Post_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+)
+{
+  if ( old_hook != NULL ) {
+*old_hook = installed_postint_hook;
+  }
+
+  installed_postint_hook = new_hook;
+}
+
+void _MicroBlaze_Post_Interrupt_hook()
+{
+  if ( installed_postint_hook != NULL ) {
+installed_postint_hook();
+  }
+}
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 0a2c5d8fff..6bd81eedd9 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -82,6 +82,15 @@ switch_to_interrupt_stack:
swi r4, r1, 0
 
 on_interrupt_stack:
+   /*
+* Temporarily stash param 1 into r2 which is a special register not
+* used by RTEMS
+*/
+   addik r2, r5, 0
+   bralid r15, _MicroBlaze_Pre_Interrupt_hook
+   nop
+   addik r5, r2, 0
+
/* Add 1 to ISR_NEST_LEVEL */
lwi r3, r0, _Per_CPU_Information + 8
addik r3, r3, 1
@@ -120,6 +129,9 @@ after_stack_switch:
/* Fall through to quick exit */
 
 quick_exit:
+   bralid r15, _MicroBlaze_Post_Interrupt_hook
+   nop
+
/* Simple return from nested interrupt */
/* Restore registers */
lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h 
b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index 5ca0609e91..9c6b213e20 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -362,6 +362,23 @@ void _CPU_Context_switch(
   Context_Control  *heir
 );
 
+/* Interrupt hooks used by libdebugger */
+typedef void ( *MicroBlaze_Interrupt_hook )( void );
+
+void _MicroBlaze_Pre_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+);
+
+void _MicroBlaze_Pre_Interrupt_hook( void );
+
+void _MicroBlaze_Post_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+);
+
+void _MicroBlaze_Post_Interrupt_hook( void );
+
 /* Selects the appropriate resume function based on CEF state */
 RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame );
 
-- 
2.30.2

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[PATCH v2 2/6] cpukit/libdebugger: Add pure swbreak capability

[Kinsey Moore]

Add a capability that allows for implementations that operate purely
using software breaks. Due to this implementation method, software
breaks must not be restored until just before returning control to the
thread itself and will be handled by the implementation through thread
switch and interrupt hooks.
---
 cpukit/libdebugger/rtems-debugger-target.h  | 14 +++---
 cpukit/libdebugger/rtems-debugger-threads.c |  4 +++-
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/cpukit/libdebugger/rtems-debugger-target.h 
b/cpukit/libdebugger/rtems-debugger-target.h
index 1e132fb28c..7836f93bd6 100644
--- a/cpukit/libdebugger/rtems-debugger-target.h
+++ b/cpukit/libdebugger/rtems-debugger-target.h
@@ -49,9 +49,17 @@ extern "C" {
 /**
  * Target capabilities mask.
  */
-#define RTEMS_DEBUGGER_TARGET_CAP_SWBREAK   (1 << 0)
-#define RTEMS_DEBUGGER_TARGET_CAP_HWBREAK   (1 << 1)
-#define RTEMS_DEBUGGER_TARGET_CAP_HWWATCH   (1 << 2)
+#define RTEMS_DEBUGGER_TARGET_CAP_SWBREAK  (1 << 0)
+#define RTEMS_DEBUGGER_TARGET_CAP_HWBREAK  (1 << 1)
+#define RTEMS_DEBUGGER_TARGET_CAP_HWWATCH  (1 << 2)
+/*
+ * This target capability indicates that the target implementation uses a pure
+ * software break implementation which must not allow breakpoints to be
+ * inserted before the actual switch to the thread, be it in interrupt context
+ * or otherwise. Such implementations must necessarily implement a thread
+ * switch hook and interrupt hooks to handle these situations.
+ */
+#define RTEMS_DEBUGGER_TARGET_CAP_PURE_SWBREAK (1 << 3)
 
 /**
  * Types of hardware breakpoints.
diff --git a/cpukit/libdebugger/rtems-debugger-threads.c 
b/cpukit/libdebugger/rtems-debugger-threads.c
index c628c0250e..841199bfe3 100644
--- a/cpukit/libdebugger/rtems-debugger-threads.c
+++ b/cpukit/libdebugger/rtems-debugger-threads.c
@@ -355,9 +355,11 @@ rtems_debugger_thread_system_resume(bool detaching)
   current = rtems_debugger_thread_current(threads);
   if (current != NULL) {
 size_t i;
+rtems_debugger_target* target = rtems_debugger->target;
 if (rtems_debugger_verbose())
   rtems_debugger_printf("rtems-db: sys:: resuming\n");
-if (!detaching) {
+if (!detaching
+  && (target->capabilities & RTEMS_DEBUGGER_TARGET_CAP_PURE_SWBREAK) == 0) 
{
   r = rtems_debugger_target_swbreak_insert();
   if (r == 0)
 r = rtems_debugger_target_hwbreak_insert();
-- 
2.30.2

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[PATCH v2 0/6] Add MicroBlaze libdebugger support

[Kinsey Moore]

Differences from v1:
* Patch 1/6: Commit message reworded
* Patch 4/6: Added for independent exception control
* Patch 6/6: Reworked to use illegal opcode instead of
 architecture-defined software break instruction


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[PATCH v2 1/6] cpukit/libdebugger: Avoid missed swbreak removal

[Kinsey Moore]

It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost. This ensures that the original instruction is
restored when a software break is removed.
---
 cpukit/libdebugger/rtems-debugger-target.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/cpukit/libdebugger/rtems-debugger-target.c 
b/cpukit/libdebugger/rtems-debugger-target.c
index 04b274909b..c298a62357 100644
--- a/cpukit/libdebugger/rtems-debugger-target.c
+++ b/cpukit/libdebugger/rtems-debugger-target.c
@@ -191,6 +191,22 @@ rtems_debugger_target_swbreak_control(bool insert, 
uintptr_t addr, DB_UINT kind)
 if (loc == swbreaks[i].address) {
   size_t remaining;
   if (!insert) {
+if (target->breakpoint_size > 4)
+  memcpy(loc, swbreaks[i].contents, target->breakpoint_size);
+else {
+  switch (target->breakpoint_size) {
+  case 4:
+loc[3] = swbreaks[i].contents[3];
+  case 3:
+loc[2] = swbreaks[i].contents[2];
+  case 2:
+loc[1] = swbreaks[i].contents[1];
+  case 1:
+loc[0] = swbreaks[i].contents[0];
+break;
+  }
+}
+rtems_debugger_target_cache_sync([i]);
 --target->swbreaks.level;
 remaining = (target->swbreaks.level - i) * swbreak_size;
 memmove([i], [i + 1], remaining);
-- 
2.30.2

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Re: [PATCH v1 3/5] cpukit/microblaze: Add interrupt hooks

[Kinsey Moore]

On 2/17/2022 20:31, Chris Johns wrote:

On 18/2/22 8:58 am, Kinsey Moore wrote:

On 2/17/2022 15:31, Chris Johns wrote:

On 18/2/22 7:12 am, Kinsey Moore wrote:

On 2/17/2022 13:53, Chris Johns wrote:

Who is setting breaks points in interrupts?

Where I encountered issues was setting breaks in library functions that I was
stepping through in non-interrupt context, particularly in memset(). ISR
handlers can also call into this library code and libdebugger bails when
application debugging intersects with ISR handler execution.

Interesting use case. Does this effect all archs? I think it does.

It does to an extent. Stepping through with inverse breakpoints on ARM and
single-step mode on AArch64 wouldn't encounter this issue, but software
breakpoints placed in those shared functions would cause the same problems I'm
seeing on MicroBlaze. ARM may not see this issue at all if it makes hardware
breakpoints available, but I don't remember whether it does.

Hmm .. the GDB solution is to place the instruction back and step then return
the break point. I am not sure if this is possible and less intrusive to the 
system?

Does this solution means the interrupts have extra overheads?
In the nominal case (libdebugger not running), the overhead is less than 
30 instructions per interrupt execution which could theoretically be 
optimized a bit by integrating the handler dispatch into the ISR_Handler 
assembly instead of having it be a stand-alone C function. In the case 
where libdebugger is running, the overhead is the nominal overhead plus 
O(n) on the number of software breakpoints installed. If I had to hazard 
a guess on the incremental number of instructions per software break, 
I'd put it at 50 or so on top of the overhead of the call chain to get 
there.


Kinsey

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Re: [PATCH v1 3/5] cpukit/microblaze: Add interrupt hooks

[Kinsey Moore]

On 2/17/2022 15:31, Chris Johns wrote:

On 18/2/22 7:12 am, Kinsey Moore wrote:

On 2/17/2022 13:53, Chris Johns wrote:

On 16/2/22 7:38 am, Kinsey Moore wrote:

Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze libdebugger
backend to prevent software breaks from occurring in interrupt context.

I am unsure what problem this is resolving?

This is resolving an issue specific to libdebugger backends that use only
software breaks without any additional architecture support. When entering
interrupt context, breakpoints of all varieties must be disabled or libdebugger
may be called into from interrupt context which libdebugger ignores as something
that needs to be passed to the fatal error handler. Microblaze in particular has
no way to set hardware breakpoints, watchpoints, or single-step operation from
the CPU (even if they exist in some configurations) and no way to disable
software breaks upon entry to interrupt context without hooks of this variety.

Why is this specific to software break points? A hardware break point in a
similar situation will trigger an exception.
In other architectures (at least AArch64 and I believe ARM as well, I 
make no claims as to how i386 operates), transition to 
interrupt/exception context implicitly disables hardware breakpoints and 
other debugging modes and they must be explicitly re-enabled to 
encounter this type of problem.



Who is setting breaks points in interrupts?

Where I encountered issues was setting breaks in library functions that I was
stepping through in non-interrupt context, particularly in memset(). ISR
handlers can also call into this library code and libdebugger bails when
application debugging intersects with ISR handler execution.

Interesting use case. Does this effect all archs? I think it does.


It does to an extent. Stepping through with inverse breakpoints on ARM 
and single-step mode on AArch64 wouldn't encounter this issue, but 
software breakpoints placed in those shared functions would cause the 
same problems I'm seeing on MicroBlaze. ARM may not see this issue at 
all if it makes hardware breakpoints available, but I don't remember 
whether it does.



Kinsey

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Re: [PATCH v1 3/5] cpukit/microblaze: Add interrupt hooks

[Kinsey Moore]

On 2/17/2022 13:53, Chris Johns wrote:

On 16/2/22 7:38 am, Kinsey Moore wrote:

Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze libdebugger
backend to prevent software breaks from occurring in interrupt context.

I am unsure what problem this is resolving?
This is resolving an issue specific to libdebugger backends that use 
only software breaks without any additional architecture support. When 
entering interrupt context, breakpoints of all varieties must be 
disabled or libdebugger may be called into from interrupt context which 
libdebugger ignores as something that needs to be passed to the fatal 
error handler. Microblaze in particular has no way to set hardware 
breakpoints, watchpoints, or single-step operation from the CPU (even if 
they exist in some configurations) and no way to disable software breaks 
upon entry to interrupt context without hooks of this variety.

Who is setting breaks points in interrupts?


Where I encountered issues was setting breaks in library functions that 
I was stepping through in non-interrupt context, particularly in 
memset(). ISR handlers can also call into this library code and 
libdebugger bails when application debugging intersects with ISR handler 
execution.



Kinsey

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Re: [PATCH v1 1/5] cpukit/libdebugger: Avoid missed swbreak removal

[Kinsey Moore]

On 2/17/2022 13:17, Chris Johns wrote:

On 16/2/22 7:38 am, Kinsey Moore wrote:

It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost.

Should this


This ensures that when a software break is removed,
its original instruction is restored.

be...

This ensures a software break is removed and the original instruction is 
restored.

?


I'll update the wording to clarify in v2.


Thanks,

Kinsey

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[PATCH v1 5/5] cpukit/libdebugger: Add MicroBlaze support

[Kinsey Moore]

Add MicroBlaze support for libdebugger. This uses only software break
instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.
---
 .../libdebugger/rtems-debugger-microblaze.c   | 1440 +
 .../cpu/microblaze/include/rtems/score/cpu.h  |   24 +
 spec/build/cpukit/libdebugger.yml |2 +
 spec/build/cpukit/objdbgmicroblaze.yml|   15 +
 spec/build/cpukit/optlibdebugger.yml  |1 +
 5 files changed, 1482 insertions(+)
 create mode 100644 cpukit/libdebugger/rtems-debugger-microblaze.c
 create mode 100644 spec/build/cpukit/objdbgmicroblaze.yml

diff --git a/cpukit/libdebugger/rtems-debugger-microblaze.c 
b/cpukit/libdebugger/rtems-debugger-microblaze.c
new file mode 100644
index 00..3e7f9a141d
--- /dev/null
+++ b/cpukit/libdebugger/rtems-debugger-microblaze.c
@@ -0,0 +1,1440 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSLibdebugger
+ *
+ * @brief MicroBlaze libdebugger implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define TARGET_DEBUG 0
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+#include 
+
+/* Defined by linkcmds.base */
+extern char bsp_section_text_begin[];
+extern char bsp_section_text_end[];
+extern char bsp_section_fast_text_begin[];
+extern char bsp_section_fast_text_end[];
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "rtems-debugger-target.h"
+#include "rtems-debugger-threads.h"
+
+#if TARGET_DEBUG
+#include 
+#endif
+
+/*
+ * Number of registers.
+ */
+#define RTEMS_DEBUGGER_NUMREGS 57
+
+/*
+ * Number of bytes per type of register.
+ */
+#define RTEMS_DEBUGGER_REG_BYTES4
+
+/* Debugger registers layout. See microblaze-core.xml in GDB source. */
+#define REG_R00
+#define REG_R11
+#define REG_R22
+#define REG_R33
+#define REG_R44
+#define REG_R55
+#define REG_R66
+#define REG_R77
+#define REG_R88
+#define REG_R99
+#define REG_R10   10
+#define REG_R11   11
+#define REG_R12   12
+#define REG_R13   13
+#define REG_R14   14
+#define REG_R15   15
+#define REG_R16   16
+#define REG_R17   17
+#define REG_R18   18
+#define REG_R19   19
+#define REG_R20   20
+#define REG_R21   21
+#define REG_R22   22
+#define REG_R23   23
+#define REG_R24   24
+#define REG_R25   25
+#define REG_R26   26
+#define REG_R27   27
+#define REG_R28   28
+#define REG_R29   29
+#define REG_R30   30
+#define REG_R31   31
+#define REG_PC32
+#define REG_MS33
+#define REG_EA34
+#define REG_ES35
+#define REG_FS36
+#define REG_BT37
+#define REG_PV0   38
+#define REG_PV1   39
+#define REG_PV2   40
+#define REG_PV3   41
+#define REG_PV4   42
+#define REG_PV5   43
+#define REG_PV6   44
+#define REG_PV7   45
+#define REG_PV8   46
+#define REG_PV9   47
+#define REG_PV10  48
+#define REG_PV11  49
+#define REG_ED50
+#define REG_PID   51
+#define REG_ZP52
+#define REG_TBLX  53
+#define REG_TBLSX 54
+#define REG_TBLLO 55
+#define REG_TBLHI 56
+
+/**
+ * Register offset table with the total as the last entry.
+ *
+ * Check this table in gdb with the command:
+ *
+ *   maint print registers
+ */
+static const size_t microblaze_reg_offsets[ RTEMS_DEBUGGER_NUMREGS + 1 ] = {
+  REG_R0 * 4,
+  REG_R1 * 4,
+  REG_R2 * 4,
+  REG_R3 * 4,
+  REG_R4 * 4,
+  REG_R5 * 4,
+  REG_R6 * 4,
+  REG_R7 * 4,
+  REG_R8 * 4,
+  REG_R9 * 4,
+  REG_R10 * 4,
+  REG_R11 * 4,
+  REG_R12 * 4,
+  REG_R13 * 4,
+  REG_R14 * 4,
+  REG_R15 * 4,
+  REG_R16 * 4,
+  REG_R17 * 4,
+  REG_R18 * 4,
+  REG_R19 * 4,
+  REG_R20 * 4,
+ 

[PATCH v1 4/5] cpukit/microblaze: Create interrupt flag

[Kinsey Moore]

The MicroBlaze Machine Status Register (MSR) does not have a flag that
designates the current execution status of the interrupt handler other
than the Interrupt Enable (IE) bit which may be unset for other reasons.
This makes use of R13 to signal the current interrupt nesting
encompassing the entirety of interrupt execution versus the more limited
scope of ISR_NEST_LEVEL. R13 would typically be used as a TLS data
pointer, but is currently unused by RTEMS. This interrupt flag is
necessary for a pure software break libdebugger backend implementation
since interrupt execution status must be known during thread dispatch.
---
 cpukit/score/cpu/microblaze/cpu_asm.S | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 6bd81eedd9..1d18f7d95c 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -41,6 +41,17 @@
.align 2
 
 _ISR_Handler:
+   /*
+* Set interrupt context flag. This TLS register is coopted for this
+* purpose since it is not used by RTEMS. R2 would suffice as well, but
+* would need to be added to Context_Control. This is used by
+* libdebugger since ISR_NEST_LEVEL is not sufficient to indicate
+* execution in interrupt context after the stack is switched back for
+* thread dispatch. There is no MSR bit to indicate Interrupt in
+* Progress.
+*/
+   addik r13, r13, 1
+
/* Save stack frame */
swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
@@ -153,5 +164,8 @@ quick_exit:
/* Remove stack frame */
addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
 
+   /* Clear interrupt context flag */
+   addik r13, r13, -1
+
rtid r14, 0
nop
-- 
2.30.2

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[PATCH v1 3/5] cpukit/microblaze: Add interrupt hooks

[Kinsey Moore]

Add hooks for manipulating system state before and after interrupts are
run. These hooks serve primarily to allow the MicroBlaze libdebugger
backend to prevent software breaks from occurring in interrupt context.
---
 cpukit/score/cpu/microblaze/cpu.c | 42 +++
 cpukit/score/cpu/microblaze/cpu_asm.S | 12 ++
 .../cpu/microblaze/include/rtems/score/cpu.h  | 17 
 3 files changed, 71 insertions(+)

diff --git a/cpukit/score/cpu/microblaze/cpu.c 
b/cpukit/score/cpu/microblaze/cpu.c
index fe55ef5546..960ac1bfea 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -229,3 +229,45 @@ void _MicroBlaze_Debug_handle( CPU_Exception_frame *ef )
 
   rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) ef );
 }
+
+MicroBlaze_Interrupt_hook installed_preint_hook = NULL;
+
+void _MicroBlaze_Pre_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+)
+{
+  if ( old_hook != NULL ) {
+*old_hook = installed_preint_hook;
+  }
+
+  installed_preint_hook = new_hook;
+}
+
+void _MicroBlaze_Pre_Interrupt_hook()
+{
+  if ( installed_preint_hook != NULL ) {
+installed_preint_hook();
+  }
+}
+
+MicroBlaze_Interrupt_hook installed_postint_hook = NULL;
+
+void _MicroBlaze_Post_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+)
+{
+  if ( old_hook != NULL ) {
+*old_hook = installed_postint_hook;
+  }
+
+  installed_postint_hook = new_hook;
+}
+
+void _MicroBlaze_Post_Interrupt_hook()
+{
+  if ( installed_postint_hook != NULL ) {
+installed_postint_hook();
+  }
+}
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 0a2c5d8fff..6bd81eedd9 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -82,6 +82,15 @@ switch_to_interrupt_stack:
swi r4, r1, 0
 
 on_interrupt_stack:
+   /*
+* Temporarily stash param 1 into r2 which is a special register not
+* used by RTEMS
+*/
+   addik r2, r5, 0
+   bralid r15, _MicroBlaze_Pre_Interrupt_hook
+   nop
+   addik r5, r2, 0
+
/* Add 1 to ISR_NEST_LEVEL */
lwi r3, r0, _Per_CPU_Information + 8
addik r3, r3, 1
@@ -120,6 +129,9 @@ after_stack_switch:
/* Fall through to quick exit */
 
 quick_exit:
+   bralid r15, _MicroBlaze_Post_Interrupt_hook
+   nop
+
/* Simple return from nested interrupt */
/* Restore registers */
lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h 
b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index 5ca0609e91..9c6b213e20 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -362,6 +362,23 @@ void _CPU_Context_switch(
   Context_Control  *heir
 );
 
+/* Interrupt hooks used by libdebugger */
+typedef void ( *MicroBlaze_Interrupt_hook )( void );
+
+void _MicroBlaze_Pre_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+);
+
+void _MicroBlaze_Pre_Interrupt_hook( void );
+
+void _MicroBlaze_Post_Interrupt_install_hook(
+  MicroBlaze_Interrupt_hook  new_hook,
+  MicroBlaze_Interrupt_hook *old_hook
+);
+
+void _MicroBlaze_Post_Interrupt_hook( void );
+
 /* Selects the appropriate resume function based on CEF state */
 RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame );
 
-- 
2.30.2

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[PATCH v1 2/5] cpukit/libdebugger: Add pure swbreak capability

[Kinsey Moore]

Add a capability that allows for implementations that operate purely
using software breaks. Due to this implementation method, software
breaks must not be restored until just before returning control to the
thread itself and will be handled by the implementation through thread
switch and interrupt hooks.
---
 cpukit/libdebugger/rtems-debugger-target.h  | 14 +++---
 cpukit/libdebugger/rtems-debugger-threads.c |  4 +++-
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/cpukit/libdebugger/rtems-debugger-target.h 
b/cpukit/libdebugger/rtems-debugger-target.h
index 1e132fb28c..7836f93bd6 100644
--- a/cpukit/libdebugger/rtems-debugger-target.h
+++ b/cpukit/libdebugger/rtems-debugger-target.h
@@ -49,9 +49,17 @@ extern "C" {
 /**
  * Target capabilities mask.
  */
-#define RTEMS_DEBUGGER_TARGET_CAP_SWBREAK   (1 << 0)
-#define RTEMS_DEBUGGER_TARGET_CAP_HWBREAK   (1 << 1)
-#define RTEMS_DEBUGGER_TARGET_CAP_HWWATCH   (1 << 2)
+#define RTEMS_DEBUGGER_TARGET_CAP_SWBREAK  (1 << 0)
+#define RTEMS_DEBUGGER_TARGET_CAP_HWBREAK  (1 << 1)
+#define RTEMS_DEBUGGER_TARGET_CAP_HWWATCH  (1 << 2)
+/*
+ * This target capability indicates that the target implementation uses a pure
+ * software break implementation which must not allow breakpoints to be
+ * inserted before the actual switch to the thread, be it in interrupt context
+ * or otherwise. Such implementations must necessarily implement a thread
+ * switch hook and interrupt hooks to handle these situations.
+ */
+#define RTEMS_DEBUGGER_TARGET_CAP_PURE_SWBREAK (1 << 3)
 
 /**
  * Types of hardware breakpoints.
diff --git a/cpukit/libdebugger/rtems-debugger-threads.c 
b/cpukit/libdebugger/rtems-debugger-threads.c
index c628c0250e..841199bfe3 100644
--- a/cpukit/libdebugger/rtems-debugger-threads.c
+++ b/cpukit/libdebugger/rtems-debugger-threads.c
@@ -355,9 +355,11 @@ rtems_debugger_thread_system_resume(bool detaching)
   current = rtems_debugger_thread_current(threads);
   if (current != NULL) {
 size_t i;
+rtems_debugger_target* target = rtems_debugger->target;
 if (rtems_debugger_verbose())
   rtems_debugger_printf("rtems-db: sys:: resuming\n");
-if (!detaching) {
+if (!detaching
+  && (target->capabilities & RTEMS_DEBUGGER_TARGET_CAP_PURE_SWBREAK) == 0) 
{
   r = rtems_debugger_target_swbreak_insert();
   if (r == 0)
 r = rtems_debugger_target_hwbreak_insert();
-- 
2.30.2

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[PATCH v1 0/5] Add libdebugger support for MicroBlaze

[Kinsey Moore]

This patch set adds libdebugger support for the MicroBlaze CPU port
along with the support necessary for a pure software-break
implementation of a libdebugger backend. This also fixes a bug
discovered during development.


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[PATCH v1 1/5] cpukit/libdebugger: Avoid missed swbreak removal

[Kinsey Moore]

It is possible to remove software breaks without actually restoring the
original instruction to memory. When this happens, the original
instruction is lost. This ensures that when a software break is removed,
its original instruction is restored.
---
 cpukit/libdebugger/rtems-debugger-target.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/cpukit/libdebugger/rtems-debugger-target.c 
b/cpukit/libdebugger/rtems-debugger-target.c
index 04b274909b..c298a62357 100644
--- a/cpukit/libdebugger/rtems-debugger-target.c
+++ b/cpukit/libdebugger/rtems-debugger-target.c
@@ -191,6 +191,22 @@ rtems_debugger_target_swbreak_control(bool insert, 
uintptr_t addr, DB_UINT kind)
 if (loc == swbreaks[i].address) {
   size_t remaining;
   if (!insert) {
+if (target->breakpoint_size > 4)
+  memcpy(loc, swbreaks[i].contents, target->breakpoint_size);
+else {
+  switch (target->breakpoint_size) {
+  case 4:
+loc[3] = swbreaks[i].contents[3];
+  case 3:
+loc[2] = swbreaks[i].contents[2];
+  case 2:
+loc[1] = swbreaks[i].contents[1];
+  case 1:
+loc[0] = swbreaks[i].contents[0];
+break;
+  }
+}
+rtems_debugger_target_cache_sync([i]);
 --target->swbreaks.level;
 remaining = (target->swbreaks.level - i) * swbreak_size;
 memmove([i], [i + 1], remaining);
-- 
2.30.2

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[PATCH v2 4/5] cpukit/microblaze: Clarify interrupt frame usage

[Kinsey Moore]

Avoid use of magic numbers in favor of named constants and add MSR to
the interrupt frame so that thread dispatch can occur on exceptions as
well.
---
 .../microblaze_fpga/start/_interrupt_handler.S   |  4 +++-
 cpukit/score/cpu/microblaze/cpu_asm.S| 16 
 .../cpu/microblaze/include/rtems/score/cpuimpl.h |  3 ++-
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S 
b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
index b817503922..c24807c3e0 100644
--- a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
+++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
@@ -31,6 +31,8 @@
 
 */
 
+#include 
+
.text
.globl _interrupt_handler# Interrupt Handler Label
.align 2
@@ -41,7 +43,7 @@
nop
 #else /* __rtems__ */
/* Subtract stack frame */
-   addik r1, r1, -52
+   addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
 
swi r5, r1, 8
 
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 246b397b9e..4dfc55ffbf 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -53,6 +53,8 @@ _ISR_Handler:
swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+   mfs r3, rmsr
+   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
 
/* Disable dispatching */
lwi r3, r0, _Per_CPU_Information + 16
@@ -76,7 +78,7 @@ _ISR_Handler:
 switch_to_interrupt_stack:
add r4, r0, r1
lwi r1, r0, _Per_CPU_Information + 4
-   addik r1, r1, -52
+   addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
swi r4, r1, 0
 
 on_interrupt_stack:
@@ -118,6 +120,8 @@ after_stack_switch:
 quick_exit:
/* Simple return from nested interrupt */
/* Restore registers */
+   lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
+   mts  rmsr, r3
lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
lwi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
lwi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
@@ -133,14 +137,14 @@ quick_exit:
lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
 
/* Remove stack frame */
-   addik r1, r1, 52
+   addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
 
rtid r14, 0
nop
 
 thread_dispatch:
/* Reserve stack */
-   addik r1, r1, -52
+   addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
/* Save scratch registers */
swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
@@ -155,11 +159,15 @@ thread_dispatch:
swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+   mfs r3, rmsr
+   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
 
bralid r15, _Thread_Dispatch
nop
 
/* Restore scratch registers */
+   lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
+   mts  rmsr, r3
lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
lwi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
lwi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
@@ -174,6 +182,6 @@ thread_dispatch:
lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
/* Free stack space */
-   addik r1, r1, 52
+   addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
 
bri quick_exit
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
index 3d0167dd40..0573759d52 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
@@ -49,7 +49,7 @@
  */
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
-#define CPU_INTERRUPT_FRAME_SIZE 52
+#define CPU_INTERRUPT_FRAME_SIZE 56
 
 #define MICROBLAZE_INTERRUPT_FRAME_R3   0
 #define MICROBLAZE_INTERRUPT_FRAME_R4   4
@@ -64,6 +64,7 @@
 #define MICROBLAZE_INTERRUPT_FRAME_R14 40
 #define MICROBLAZE_INTERRUPT_FRAME_R15 44
 #define MICROBLAZE_INTERRUPT_FRAME_R18 48
+#define MICROBLAZE_INTERRUPT_FRAME_MSR 52
 
 #ifndef ASM
 
-- 
2.30.2

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[PATCH v2 3/5] cpukit/microblaze: Add exception extensions

[Kinsey Moore]

Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and
mark this functionality as available on MicroBlaze.
---
 .../cpu/microblaze/include/rtems/score/cpu.h  |  38 
 .../microblaze-exception-extensions.S | 177 ++
 .../microblaze-exception-extensions.c | 173 +
 spec/build/cpukit/cpumicroblaze.yml   |   2 +
 spec/build/cpukit/optexceptionextensions.yml  |   1 +
 5 files changed, 391 insertions(+)
 create mode 100644 
cpukit/score/cpu/microblaze/microblaze-exception-extensions.S
 create mode 100644 
cpukit/score/cpu/microblaze/microblaze-exception-extensions.c

diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h 
b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index fe0d9a8996..5ca0609e91 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -194,6 +194,10 @@ typedef struct {
 #define MICROBLAZE_MSR_C   ( 1 << 2 )
 #define MICROBLAZE_MSR_IE  ( 1 << 1 )
 
+#define MICROBLAZE_ESR_DS  ( 1 << 12 )
+#define MICROBLAZE_ESR_EC_MASK   0x1f
+#define MICROBLAZE_ESR_ESS_MASK  0x7f
+#define MICROBLAZE_ESR_ESS_SHIFT 5
 
 #define _CPU_MSR_GET( _msr_value ) \
   do { \
@@ -358,6 +362,40 @@ void _CPU_Context_switch(
   Context_Control  *heir
 );
 
+/* Selects the appropriate resume function based on CEF state */
+RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame );
+
+RTEMS_NO_RETURN void _MicroBlaze_Exception_resume_from_exception(
+  CPU_Exception_frame *frame
+);
+
+RTEMS_NO_RETURN void _MicroBlaze_Exception_resume_from_break(
+  CPU_Exception_frame *frame
+);
+
+/*
+ * Only functions for exception cases since debug exception frames will never
+ * need dispatch
+ */
+RTEMS_NO_RETURN void _CPU_Exception_dispatch_and_resume(
+  CPU_Exception_frame *frame
+);
+
+void _CPU_Exception_disable_thread_dispatch( void );
+
+int _CPU_Exception_frame_get_signal( CPU_Exception_frame *frame );
+
+void _CPU_Exception_frame_set_resume(
+  CPU_Exception_frame *frame,
+  void*address
+);
+
+void _CPU_Exception_frame_make_resume_next_instruction(
+  CPU_Exception_frame *frame
+);
+
+uint32_t *_MicroBlaze_Get_return_address( CPU_Exception_frame *ef );
+
 RTEMS_NO_RETURN void _CPU_Context_restore(
   Context_Control *new_context
 );
diff --git a/cpukit/score/cpu/microblaze/microblaze-exception-extensions.S 
b/cpukit/score/cpu/microblaze/microblaze-exception-extensions.S
new file mode 100644
index 00..252e901393
--- /dev/null
+++ b/cpukit/score/cpu/microblaze/microblaze-exception-extensions.S
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUMicroBlaze
+ *
+ * @brief MicroBlaze exception extensions ASM implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+   .text
+.globl _CPU_Exception_dispatch_and_resume
+.globl _MicroBlaze_Exception_resume_from_exception
+.globl _MicroBlaze_Exception_resume_from_break
+   .align 2
+
+_CPU_Exception_dispatch_and_resume:
+   /* Subtract 1 from ISR_NEST_LEVEL */
+   lwi r3, r0, _Per_CPU_Information + 8
+   addik r3, r3, -1
+   swi r3, r0, _Per_CPU_Information + 8
+
+   /* Subtract 1 from THREAD_DISPATCH_DISABLE_LEVEL */
+   lwi r3, r0, _Per_CPU_Information + 16
+   addik r3, r3, -1
+   swi r3, r0, _Per_CPU_Information + 16
+
+   /* Is THREAD_DISPATCH_DISABLE_LEVEL != 0? */
+   bnei r3, _MicroBlaze_Exception_resume_from_exception
+
+   /* Is DISPATCH_NEEDED == 0? */
+   lwi r3, r0, 

Re: [PATCH v1 1/5] cpukit/microblaze: Add exception framework

[Kinsey Moore]

On 2/2/2022 01:22, Sebastian Huber wrote:

Hello Kinsey,

could you please use the _CPU_* and CPU_* prefixes only for items 
which are defined by the CPU port interface:


cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h

Architecture-specific interfaces should have an architecture-specific 
prefix, for example _Microblaze_* and MICROBLAZE_*.


The code for the optional exception resume should be in a separate 
file and not in cpu.c.


I'll get these changes integrated and a new patch set up once some other 
conflicting patches are committed.



Thanks,

Kinsey

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[PATCH v2 5/5] cpukit/microblaze: Simplify dispatch assembly

[Kinsey Moore]

The dispatch code was unnecessarily saving and restoring an extra
interrupt frame. This avoids the extra frame and folds the dispatch call
into a fallthrough to the interrupt frame restoration code.
---
 cpukit/score/cpu/microblaze/cpu_asm.S | 48 ++-
 1 file changed, 3 insertions(+), 45 deletions(-)

diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 4dfc55ffbf..0a2c5d8fff 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -115,7 +115,9 @@ after_stack_switch:
beqi r3, quick_exit
 
/* Return to interrupted thread and make it do a dispatch */
-   bri thread_dispatch
+   bralid r15, _Thread_Dispatch
+   nop
+   /* Fall through to quick exit */
 
 quick_exit:
/* Simple return from nested interrupt */
@@ -141,47 +143,3 @@ quick_exit:
 
rtid r14, 0
nop
-
-thread_dispatch:
-   /* Reserve stack */
-   addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
-   /* Save scratch registers */
-   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
-   swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
-   swi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
-   swi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
-   swi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
-   swi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
-   swi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
-   swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
-   swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
-   swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
-   swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
-   swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
-   swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
-   mfs r3, rmsr
-   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
-
-   bralid r15, _Thread_Dispatch
-   nop
-
-   /* Restore scratch registers */
-   lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
-   mts  rmsr, r3
-   lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
-   lwi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
-   lwi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
-   lwi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
-   lwi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
-   lwi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
-   lwi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
-   lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
-   lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
-   lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
-   lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
-   lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
-   lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
-   /* Free stack space */
-   addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
-
-   bri quick_exit
-- 
2.30.2

___
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[PATCH v2 2/5] cpukit/microblaze: Add debug vector and handler

[Kinsey Moore]

This patch adds a vector for debug events along with a hook similar to
the exception framework. The debug vector generates an exception frame
for use by libdebugger.
---
 .../start/_debug_sw_break_handler.S   | 106 ++
 bsps/microblaze/shared/start/start.S  |   7 +-
 cpukit/score/cpu/microblaze/cpu.c |  26 +
 .../cpu/microblaze/include/rtems/score/cpu.h  |   9 ++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 +
 5 files changed, 148 insertions(+), 1 deletion(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S

diff --git a/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S 
b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S
new file mode 100644
index 00..872f49
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroBlaze
+ *
+ * @brief MicroBlaze debug trap handler implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+   .text
+   .globl _debug_sw_break_handler# HW Exception Handler Label
+   .extern _MicroBlaze_Debug_handle
+   .align 2
+
+   _debug_sw_break_handler:
+   /* The stack used here does not matter since debug cannot recurse */
+
+   /* Subtract exception frame */
+   addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE)
+
+   /* Store program state */
+   swi  r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2
+   swi  r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3
+   swi  r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4
+   swi  r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5
+   swi  r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6
+   swi  r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7
+   swi  r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8
+   swi  r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9
+   swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10
+   swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11
+   swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12
+   swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13
+   swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14
+   swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15
+   swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16
+   swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17
+   swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18
+   swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19
+   swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20
+   swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21
+   swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22
+   swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23
+   swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24
+   swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25
+   swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26
+   swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27
+   swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28
+   swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29
+   swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30
+   swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31
+
+   /* Retrieve and store MSR */
+   mfs r3, rmsr
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR
+
+   /* Retrieve and store EAR */
+   mfs r3, rear
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR
+
+   /* Retrieve and store ESR */
+   mfs r3, resr
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR
+
+   /* Retrieve and store BTR */
+   mfs r3, rbtr
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR
+
+   /* Calculate and store original stack pointer */
+   addik r3, r1, CPU_EXCEPTION_FRAME_SIZE
+   swi r3, r1, 

[PATCH v2 1/5] cpukit/microblaze: Add exception framework

[Kinsey Moore]

This patch updates the CPU_Exception_frame to include all necessary
registers, combines hardware snd software exception handlers into a
shared vector, provides an architecture-specific hook for taking
control of exception handling, and moves exception handling over to
actually using the CPU_Exception_frame instead of a minimal interrupt
stack frame. As the significant contents of _exception_handler.S have
been entirely rewritten, the copyright information on this file has been
updated to reflect that.
---
 .../start/_exception_handler.S| 129 --
 .../start/_hw_exception_handler.S |  52 ---
 bsps/microblaze/shared/start/start.S  |   7 +-
 cpukit/score/cpu/microblaze/cpu.c |  85 
 cpukit/score/cpu/microblaze/cpu_asm.S |  13 --
 .../cpu/microblaze/include/rtems/score/cpu.h  | 106 +-
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 -
 7 files changed, 283 insertions(+), 110 deletions(-)
 delete mode 100644 
bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S

diff --git a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S 
b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S
index 1d96b694a7..c3c05796a4 100644
--- a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S
+++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S
@@ -1,52 +1,103 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
+/* SPDX-License-Identifier: BSD-2-Clause */
 
-/* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroBlaze
+ *
+ * @brief MicroBlaze exception handler implementation
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are
-   met:
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
-   1.  Redistributions source code must retain the above copyright notice,
-   this list of conditions and the following disclaimer.
-
-   2.  Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-   3.  Neither the name of Xilinx nor the names of its contributors may be
-   used to endorse or promote products derived from this software without
-   specific prior written permission.
-
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
-   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*/
+#include 
 
.text
.globl _exception_handler# Exception Handler Label
.align 2
 
_exception_handler:
-#ifndef __rtems__
-   rtsdr17, 0
-   nop
-#else /* __rtems__ */
-   /* Subtract stack frame */
-   addik r1, r1, -52
+   /* Subtract exception frame */
+   addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE)
+
+   /* Store program state */
+  

[PATCH v1 3/5] cpukit/microblaze: Add exception extensions

[Kinsey Moore]

Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and
mark this functionality as available on MicroBlaze.
---
 cpukit/score/cpu/microblaze/cpu.c | 133 +
 cpukit/score/cpu/microblaze/cpu_asm.S | 137 ++
 .../cpu/microblaze/include/rtems/score/cpu.h  |  38 +
 spec/build/cpukit/optexceptionextensions.yml  |   1 +
 4 files changed, 309 insertions(+)

diff --git a/cpukit/score/cpu/microblaze/cpu.c 
b/cpukit/score/cpu/microblaze/cpu.c
index c75aa0f147..009d93793f 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -43,6 +43,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -230,3 +231,135 @@ void _CPU_Debug_handle( CPU_Exception_frame *ef )
 
   rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) ef );
 }
+
+RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame )
+{
+  /* Break in progress */
+  if ( ( frame->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+_CPU_Exception_resume_from_break( frame );
+  }
+
+  /* Exception in progress */
+  if ( ( frame->msr & MICROBLAZE_MSR_EIP ) != 0 ) {
+_CPU_Exception_resume_from_exception( frame );
+  }
+
+  /* Execution should never reach this point */
+  rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
+}
+
+void _CPU_Exception_disable_thread_dispatch( void )
+{
+  Per_CPU_Control *cpu_self = _Per_CPU_Get();
+
+  /* Increment interrupt nest and thread dispatch disable level */
+  ++cpu_self->thread_dispatch_disable_level;
+  ++cpu_self->isr_nest_level;
+}
+
+/* -1 means not mappable/recoverable */
+int _CPU_Exception_frame_get_signal( CPU_Exception_frame *ef )
+{
+  uint32_t EC = ef->esr & MICROBLAZE_ESR_EC_MASK;
+
+  /* Break in progress */
+  if ( ( ef->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+return -1;
+  }
+
+  switch ( EC ) {
+   case 0x0:  /* Stream */
+   case 0x7:  /* Privileged or Stack Protection */
+ return -1;
+
+   case 0x5:  /* Divide */
+   case 0x6:  /* FPU */
+ return SIGFPE;
+
+   case 0x3:  /* Instruction Abort */
+   case 0x4:  /* Data Abort */
+ return SIGSEGV;
+
+   case 0x1:  /* Unaligned access */
+   case 0x2:  /* Illegal op-code */
+   default:
+ return SIGILL;
+  }
+}
+
+void _CPU_Exception_frame_set_resume( CPU_Exception_frame *ef, void *address )
+{
+  /* Break in progress */
+  if ( ( ef->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+ef->r16 = address;
+return;
+  }
+
+  /* Exception in progress */
+  if ( ( ef->msr & MICROBLAZE_MSR_EIP ) != 0 ) {
+ef->r17 = address;
+return;
+  }
+
+  Per_CPU_Control *cpu_self = _Per_CPU_Get();
+
+  /* Interrupt in progress must be determined by stack pointer location */
+  if (
+ef->r1 >= (uint32_t) cpu_self->interrupt_stack_low
+&& ef->r1 < (uint32_t) cpu_self->interrupt_stack_high
+  ) {
+ef->r14 = address;
+return;
+  }
+
+  /* Default to normal link register */
+  ef->r15 = address;
+}
+
+/*
+ * This returns the target return address, not necessarily the address of the
+ * instruction that caused exception. These are the same if it's a MMU 
exception
+ * and the BTR overrides the return address if the exception occurred in a 
delay
+ * slot. */
+uint32_t *_MicroBlaze_Get_return_address( CPU_Exception_frame *ef )
+{
+  /* Break in progress */
+  if ( ( ef->msr & MICROBLAZE_MSR_BIP ) != 0 ) {
+return ef->r16;
+  }
+
+  /* Exception in progress */
+  if ( ( ef->msr & MICROBLAZE_MSR_EIP ) != 0 ) {
+if ( ( ef->esr & MICROBLAZE_ESR_DS ) != 0 ) {
+  return ef->btr;
+}
+
+return ef->r17;
+  }
+
+  Per_CPU_Control *cpu_self = _Per_CPU_Get();
+
+  /* Interrupt in progress must be determined by stack pointer location */
+  if (
+ef->r1 >= (uint32_t) cpu_self->interrupt_stack_low
+&& ef->r1 < (uint32_t) cpu_self->interrupt_stack_high
+  ) {
+return ef->r14;
+  }
+
+  /* Default to normal link register */
+  return ef->r15;
+}
+
+/*
+ * This can only change the resume address in the case of an exception in a
+ * branch delay slot instruction.
+ */
+void _CPU_Exception_frame_make_resume_next_instruction(
+  CPU_Exception_frame *ef
+)
+{
+  uintptr_t ret_addr = (uintptr_t) _MicroBlaze_Get_return_address( ef );
+
+  _CPU_Exception_frame_set_resume( ef, (uint32_t *) ret_addr );
+}
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 92cf15e901..bf5080d2e1 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -38,6 +38,9 @@
 
.text
.globl _ISR_Handler
+.globl _CPU_Exception_dispatch_and_resume
+.globl _CPU_Exception_resume_from_exception
+.globl _CPU_Exception_resume_from_break
.align 2
 
 _ISR_Handler:
@@ -179,3 +182,137 @@ thread_dispatch:
addik r1, r1, 52
 
bri quick_exit
+
+_CPU_Exception_dispatch_and_resume:
+   /* Subtract 1 from ISR_NEST_LEVEL */
+   lwi r3, r0, _Per_CPU_Information + 8
+   addik r3, r3, 

[PATCH v1 1/5] cpukit/microblaze: Add exception framework

[Kinsey Moore]

This patch updates the CPU_Exception_frame to include all necessary
registers, combines hardware snd software exception handlers into a
shared vector, provides an architecture-specific hook for taking
control of exception handling, and moves exception handling over to
actually using the CPU_Exception_frame instead of a minimal interrupt
stack frame. As the significant contents of _exception_handler.S have
been entirely rewritten, the copyright information on this file has been
updated to reflect that.
---
 .../start/_exception_handler.S| 129 --
 .../start/_hw_exception_handler.S |  52 ---
 bsps/microblaze/shared/start/start.S  |   7 +-
 cpukit/score/cpu/microblaze/cpu.c |  85 
 cpukit/score/cpu/microblaze/cpu_asm.S |  13 --
 .../cpu/microblaze/include/rtems/score/cpu.h  | 106 +-
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 -
 7 files changed, 283 insertions(+), 110 deletions(-)
 delete mode 100644 
bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S

diff --git a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S 
b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S
index 1d96b694a7..25caf63d9c 100644
--- a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S
+++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S
@@ -1,52 +1,103 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
+/* SPDX-License-Identifier: BSD-2-Clause */
 
-/* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze exception handler implementation
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are
-   met:
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
-   1.  Redistributions source code must retain the above copyright notice,
-   this list of conditions and the following disclaimer.
-
-   2.  Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-   3.  Neither the name of Xilinx nor the names of its contributors may be
-   used to endorse or promote products derived from this software without
-   specific prior written permission.
-
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
-   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*/
+#include 
 
.text
.globl _exception_handler# Exception Handler Label
.align 2
 
_exception_handler:
-#ifndef __rtems__
-   rtsdr17, 0
-   nop
-#else /* __rtems__ */
-   /* Subtract stack frame */
-   addik r1, r1, -52
+   /* Subtract exception frame */
+   addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE)
+
+   /* Store program state */
+  

[PATCH v1 5/5] cpukit/microblaze: Simplify dispatch assembly

[Kinsey Moore]

The dispatch code was unnecessarily saving and restoring an extra
interrupt frame. This avoids the extra frame and folds the dispatch call
into a fallthrough to the interrupt frame restoration code.
---
 cpukit/score/cpu/microblaze/cpu_asm.S | 48 ++-
 1 file changed, 2 insertions(+), 46 deletions(-)

diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S 
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 62bb8075bd..e7861b5f91 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -118,9 +118,9 @@ after_stack_switch:
beqi r3, quick_exit
 
/* Return to interrupted thread and make it do a dispatch */
-   addik r14, r0, thread_dispatch
-   rtid r14, 0
+   bralid r15, _Thread_Dispatch
nop
+   /* Fall through to quick exit */
 
 quick_exit:
/* Simple return from nested interrupt */
@@ -147,50 +147,6 @@ quick_exit:
rtid r14, 0
nop
 
-thread_dispatch:
-   /* Reserve stack */
-   addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
-   /* Save scratch registers */
-   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
-   swi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
-   swi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
-   swi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
-   swi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
-   swi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
-   swi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
-   swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
-   swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
-   swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
-   swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
-   swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
-   swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
-   mfs r3, rmsr
-   swi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_RMS
-
-   bralid r15, _Thread_Dispatch
-   nop
-
-   /* Restore scratch registers */
-   lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_RMS
-   mts  rmsr, r3
-   lwi  r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
-   lwi  r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
-   lwi  r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
-   lwi  r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
-   lwi  r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
-   lwi  r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
-   lwi  r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
-   lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
-   lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
-   lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
-   lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
-   lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
-   lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
-   /* Free stack space */
-   addik r1, r1, CPU_INTERRUPT_FRAME_SIZE
-
-   bri quick_exit
-
 _CPU_Exception_dispatch_and_resume:
/* Subtract 1 from ISR_NEST_LEVEL */
lwi r3, r0, _Per_CPU_Information + 8
-- 
2.30.2

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[PATCH v1 2/5] cpukit/microblaze: Add debug vector and handler

[Kinsey Moore]

This patch adds a vector for debug events along with a hook similar to
the exception framework. The debug vector generates an exception frame
for use by libdebugger.
---
 .../start/_debug_sw_break_handler.S   | 106 ++
 bsps/microblaze/shared/start/start.S  |   7 +-
 cpukit/score/cpu/microblaze/cpu.c |  26 +
 .../cpu/microblaze/include/rtems/score/cpu.h  |   9 ++
 .../bsps/microblaze/microblaze_fpga/obj.yml   |   1 +
 5 files changed, 148 insertions(+), 1 deletion(-)
 create mode 100644 
bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S

diff --git a/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S 
b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S
new file mode 100644
index 00..ebf69f6d53
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/start/_debug_sw_break_handler.S
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsMicroblaze
+ *
+ * @brief MicroBlaze debug trap handler implementation
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+   .text
+   .globl _debug_sw_break_handler# HW Exception Handler Label
+   .extern _CPU_Debug_handle
+   .align 2
+
+   _debug_sw_break_handler:
+   /* The stack used here does not matter since debug cannot recurse */
+
+   /* Subtract exception frame */
+   addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE)
+
+   /* Store program state */
+   swi  r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2
+   swi  r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3
+   swi  r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4
+   swi  r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5
+   swi  r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6
+   swi  r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7
+   swi  r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8
+   swi  r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9
+   swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10
+   swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11
+   swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12
+   swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13
+   swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14
+   swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15
+   swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16
+   swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17
+   swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18
+   swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19
+   swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20
+   swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21
+   swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22
+   swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23
+   swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24
+   swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25
+   swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26
+   swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27
+   swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28
+   swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29
+   swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30
+   swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31
+
+   /* Retrieve and store MSR */
+   mfs r3, rmsr
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR
+
+   /* Retrieve and store EAR */
+   mfs r3, rear
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR
+
+   /* Retrieve and store ESR */
+   mfs r3, resr
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR
+
+   /* Retrieve and store BTR */
+   mfs r3, rbtr
+   swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR
+
+   /* Calculate and store original stack pointer */
+   addik r3, r1, CPU_EXCEPTION_FRAME_SIZE
+   swi r3, r1, 

Re: [PATCH v2] cpukit: Prevent error with disabled stack checker

[Kinsey Moore]

On 1/27/2022 09:57, Sebastian Huber wrote:

On 27/01/2022 16:37, Kinsey Moore wrote:

+*** TEST STACKCHK02 ***
+ STACK USAGE BY THREAD
+ID NAME  LOW    HIGH CURRENT AVAIL   
USED
+0x09010001 IDLE  0x10104940 0x1010713f 0x10107140  
10224 N/A
+0x0a010001 UI1   0x10109950 0x1010c14f 0x1010c150  
10224 N/A

+Stack usage information not available
+
+*** END OF TEST STACKCHK02 ***


In an SMP system you get this "Stack usage information not available" 
for each processor. I would simply print nothing if there is no 
information available.



Will do, new patch incoming shortly.


Kinsey

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[PATCH v2] cpukit: Prevent error with disabled stack checker

[Kinsey Moore]

When the stack checker is not enabled, the stack checker reporting
function can still be called. This prevents that call from performing a
null memory access in trying to find the high water mark if the stack
checker was never initialized.

This also introduces a test to ensure this call does not cause a crash.

Closes #4588
---
 cpukit/libmisc/stackchk/check.c   |  6 ++
 spec/build/testsuites/libtests/grp.yml|  2 +
 spec/build/testsuites/libtests/stackchk02.yml | 19 ++
 testsuites/libtests/stackchk02/init.c | 67 +++
 testsuites/libtests/stackchk02/stackchk02.doc | 16 +
 testsuites/libtests/stackchk02/stackchk02.scn |  8 +++
 6 files changed, 118 insertions(+)
 create mode 100644 spec/build/testsuites/libtests/stackchk02.yml
 create mode 100644 testsuites/libtests/stackchk02/init.c
 create mode 100644 testsuites/libtests/stackchk02/stackchk02.doc
 create mode 100644 testsuites/libtests/stackchk02/stackchk02.scn

diff --git a/cpukit/libmisc/stackchk/check.c b/cpukit/libmisc/stackchk/check.c
index a2b63345d9..386cb0d97d 100644
--- a/cpukit/libmisc/stackchk/check.c
+++ b/cpukit/libmisc/stackchk/check.c
@@ -410,6 +410,12 @@ static bool Stack_check_Dump_stack_usage(
   void *low;
   void *high_water_mark;
 
+  /* This is likely to occur if the stack checker is not actually enabled */
+  if ( stack->area == NULL ) {
+rtems_printf(printer, "Stack usage information not available\n");
+return false;
+  }
+
   low  = Stack_check_Usable_stack_start(stack);
   size = Stack_check_Usable_stack_size(stack);
 
diff --git a/spec/build/testsuites/libtests/grp.yml 
b/spec/build/testsuites/libtests/grp.yml
index cd5cc210e2..4717081312 100644
--- a/spec/build/testsuites/libtests/grp.yml
+++ b/spec/build/testsuites/libtests/grp.yml
@@ -249,6 +249,8 @@ links:
   uid: stackchk
 - role: build-dependency
   uid: stackchk01
+- role: build-dependency
+  uid: stackchk02
 - role: build-dependency
   uid: stat
 - role: build-dependency
diff --git a/spec/build/testsuites/libtests/stackchk02.yml 
b/spec/build/testsuites/libtests/stackchk02.yml
new file mode 100644
index 00..4a4cbf9660
--- /dev/null
+++ b/spec/build/testsuites/libtests/stackchk02.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research (OAR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+features: c cprogram
+includes: []
+ldflags: []
+links: []
+source:
+- testsuites/libtests/stackchk02/init.c
+stlib: []
+target: testsuites/libtests/stackchk02.exe
+type: build
+use-after: []
+use-before: []
diff --git a/testsuites/libtests/stackchk02/init.c 
b/testsuites/libtests/stackchk02/init.c
new file mode 100644
index 00..0904e37c68
--- /dev/null
+++ b/testsuites/libtests/stackchk02/init.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup libtests
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#define CONFIGURE_INIT
+
+#include 
+
+#define CONFIGURE_APPLICATION_NEEDS_SIMPLE_CONSOLE_DRIVER
+#define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER
+
+#define TASK_STACK_SIZE (RTEMS_MINIMUM_STACK_SIZE*3)
+
+#define CONFIGURE_MAXIMUM_TASKS   1
+
+#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
+
+#include 
+
+#include 
+
+const char rtems_test_name[] = "STACKCHK02";
+
+rtems_task Init(
+  rtems_task_argument argument
+)
+{
+  TEST_BEGIN();
+
+  rtems_stack_checker_report_usage();
+
+  TEST_END();
+  rtems_test_exit( 0 );
+}
diff --git 

Re: [PATCH] cpukit: Prevent error with disabled stack checker

[Kinsey Moore]

On 1/27/2022 01:20, Sebastian Huber wrote:

On 26/01/2022 23:07, Kinsey Moore wrote:
diff --git a/cpukit/libmisc/stackchk/check.c 
b/cpukit/libmisc/stackchk/check.c

index a2b63345d9..9119f8d940 100644
--- a/cpukit/libmisc/stackchk/check.c
+++ b/cpukit/libmisc/stackchk/check.c
@@ -487,6 +487,12 @@ void rtems_stack_checker_report_usage_with_plugin(
    uint32_t cpu_max;
    uint32_t cpu_index;
  +  /* Make sure that the stack checker is enabled */
+  if ( Stack_check_Interrupt_stack[ 0 ].area == NULL ) {
+    rtems_printf(printer, "RTEMS Stack Checker not enabled\n");
+    return;
+  }
+
    rtems_printf(
   printer,
   " STACK USAGE BY THREAD\n"


This check is insufficient in SMP configurations. It also prevents a 
stack report without the stack usage information.
This should be sufficient for SMP because it only needs to verify that 
the CPU interrupt stack information has been initialized for one CPU to 
know whether initialization has been run at all and that the appropriate 
hooks are in place.


I would move the check to Stack_check_Dump_stack_usage(). Simply 
report nothing if stack == NULL.



I'll move the check so that a stack report is still generated.


Kinsey

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[PATCH] cpukit: Prevent error with disabled stack checker

[Kinsey Moore]

When the stack checker is not enabled, the stack checker reporting
function can still be called. This prevents that call from performing a
null memory access in trying to find the high water mark if the stack
checker was never initialized.

This also introduces a test to ensure this call does not cause a crash.

Closes #4588
---
 cpukit/libmisc/stackchk/check.c   |  6 ++
 spec/build/testsuites/libtests/grp.yml|  2 +
 spec/build/testsuites/libtests/stackchk02.yml | 19 ++
 testsuites/libtests/stackchk02/init.c | 67 +++
 testsuites/libtests/stackchk02/stackchk02.doc | 16 +
 testsuites/libtests/stackchk02/stackchk02.scn |  4 ++
 6 files changed, 114 insertions(+)
 create mode 100644 spec/build/testsuites/libtests/stackchk02.yml
 create mode 100644 testsuites/libtests/stackchk02/init.c
 create mode 100644 testsuites/libtests/stackchk02/stackchk02.doc
 create mode 100644 testsuites/libtests/stackchk02/stackchk02.scn

diff --git a/cpukit/libmisc/stackchk/check.c b/cpukit/libmisc/stackchk/check.c
index a2b63345d9..9119f8d940 100644
--- a/cpukit/libmisc/stackchk/check.c
+++ b/cpukit/libmisc/stackchk/check.c
@@ -487,6 +487,12 @@ void rtems_stack_checker_report_usage_with_plugin(
   uint32_t cpu_max;
   uint32_t cpu_index;
 
+  /* Make sure that the stack checker is enabled */
+  if ( Stack_check_Interrupt_stack[ 0 ].area == NULL ) {
+rtems_printf(printer, "RTEMS Stack Checker not enabled\n");
+return;
+  }
+
   rtems_printf(
  printer,
  " STACK USAGE BY THREAD\n"
diff --git a/spec/build/testsuites/libtests/grp.yml 
b/spec/build/testsuites/libtests/grp.yml
index cd5cc210e2..4717081312 100644
--- a/spec/build/testsuites/libtests/grp.yml
+++ b/spec/build/testsuites/libtests/grp.yml
@@ -249,6 +249,8 @@ links:
   uid: stackchk
 - role: build-dependency
   uid: stackchk01
+- role: build-dependency
+  uid: stackchk02
 - role: build-dependency
   uid: stat
 - role: build-dependency
diff --git a/spec/build/testsuites/libtests/stackchk02.yml 
b/spec/build/testsuites/libtests/stackchk02.yml
new file mode 100644
index 00..4a4cbf9660
--- /dev/null
+++ b/spec/build/testsuites/libtests/stackchk02.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: test-program
+cflags: []
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research (OAR)
+cppflags: []
+cxxflags: []
+enabled-by: true
+features: c cprogram
+includes: []
+ldflags: []
+links: []
+source:
+- testsuites/libtests/stackchk02/init.c
+stlib: []
+target: testsuites/libtests/stackchk02.exe
+type: build
+use-after: []
+use-before: []
diff --git a/testsuites/libtests/stackchk02/init.c 
b/testsuites/libtests/stackchk02/init.c
new file mode 100644
index 00..0904e37c68
--- /dev/null
+++ b/testsuites/libtests/stackchk02/init.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup libtests
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#define CONFIGURE_INIT
+
+#include 
+
+#define CONFIGURE_APPLICATION_NEEDS_SIMPLE_CONSOLE_DRIVER
+#define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER
+
+#define TASK_STACK_SIZE (RTEMS_MINIMUM_STACK_SIZE*3)
+
+#define CONFIGURE_MAXIMUM_TASKS   1
+
+#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
+
+#include 
+
+#include 
+
+const char rtems_test_name[] = "STACKCHK02";
+
+rtems_task Init(
+  rtems_task_argument argument
+)
+{
+  TEST_BEGIN();
+
+  rtems_stack_checker_report_usage();
+
+  TEST_END();
+  rtems_test_exit( 0 );
+}
diff --git 

Re: [PATCH rtems-tools] tiers: Add AArch64 to tier 1

[Kinsey Moore]

On 1/19/2022 09:41, Kinsey Moore wrote:


On 1/19/2022 09:13, Sebastian Huber wrote:

On 19/01/2022 15:42, Kinsey Moore wrote:

On 1/18/2022 10:23, Sebastian Huber wrote:

On 18/01/2022 17:19, Kinsey Moore wrote:

Hardware test results have recently been posted for AArch64.

Closes #4581


It would be nice if you could run also the new validation tests on 
this branch:


https://git.rtems.org/sebh/rtems.git/log/?h=validation

It looks like when running with that branch, tar02 and psxftw01 are 
consistently failing with a PC in the stack since sometime after 
68b0db358c81a7f770a44ceb819197bdc320bc99 which is what the other 
test run used. I'll have to track that down.


Thanks for testing. It would be good to do a git bisect to figure out 
the problem.

I'm currently doing that now and should have it narrowed down soon.



It looks like this was actually just a bad partial build and a full 
rebuild resolved the two failures.



Kinsey

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Re: [PATCH rtems-tools] tiers: Add AArch64 to tier 1

[Kinsey Moore]

On 1/19/2022 09:13, Sebastian Huber wrote:

On 19/01/2022 15:42, Kinsey Moore wrote:

On 1/18/2022 10:23, Sebastian Huber wrote:

On 18/01/2022 17:19, Kinsey Moore wrote:

Hardware test results have recently been posted for AArch64.

Closes #4581


It would be nice if you could run also the new validation tests on 
this branch:


https://git.rtems.org/sebh/rtems.git/log/?h=validation

It looks like when running with that branch, tar02 and psxftw01 are 
consistently failing with a PC in the stack since sometime after 
68b0db358c81a7f770a44ceb819197bdc320bc99 which is what the other test 
run used. I'll have to track that down.


Thanks for testing. It would be good to do a git bisect to figure out 
the problem.

I'm currently doing that now and should have it narrowed down soon.




ts-performance-no-clock-0 gets test-too-long, but passes with 
modified tester timeouts and all the other validation tests pass just 
fine.


Great, did the ts-validation-intr test run also? It fails on my Qemu 
simulator.

Yes, that test was included in the validation tests and passed.


I think the issue with ts-performance-no-clock-0 is the size of the 
data cache. However, the data cache is an important factor for the 
performance data, so there is no way around this.


Good to know. We may want to bump up the default test-too-long limit if 
this is going to be the case.



Kinsey

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Re: [PATCH rtems-tools] tiers: Add AArch64 to tier 1

[Kinsey Moore]

On 1/18/2022 10:23, Sebastian Huber wrote:

On 18/01/2022 17:19, Kinsey Moore wrote:

Hardware test results have recently been posted for AArch64.

Closes #4581


It would be nice if you could run also the new validation tests on 
this branch:


https://git.rtems.org/sebh/rtems.git/log/?h=validation

It looks like when running with that branch, tar02 and psxftw01 are 
consistently failing with a PC in the stack since sometime after 
68b0db358c81a7f770a44ceb819197bdc320bc99 which is what the other test 
run used. I'll have to track that down.


ts-performance-no-clock-0 gets test-too-long, but passes with modified 
tester timeouts and all the other validation tests pass just fine.


Kinsey

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[PATCH rtems-tools] tiers: Add AArch64 to tier 1

[Kinsey Moore]

Hardware test results have recently been posted for AArch64.

Closes #4581
---
 config/rtems-bsps-tiers.ini | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/config/rtems-bsps-tiers.ini b/config/rtems-bsps-tiers.ini
index 875c5df..ba9e6b5 100644
--- a/config/rtems-bsps-tiers.ini
+++ b/config/rtems-bsps-tiers.ini
@@ -21,10 +21,11 @@
 # Tier 1: no build errors and no unexpected tests failures on hardware.
 #
 [tier-1]
-archs = arm, i386, powerpc
+archs = arm, i386, powerpc, aarch64
 bsps_arm = beagleboneblack, imx7, xilinx_zynq_zedboard
 bsps_i386 = pc686
 bsps_powerpc = qoriq_e500
+bsps_aarch64 = xilinx_zynqmp_lp64_zu3eg, xilinx_zynqmp_ilp32_zu3eg
 
 #
 # Tier 2: no build errors and no unexpected tests failures on hardware and
-- 
2.30.2

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RE: [PATCH 0/3] aarch64: boot in to EL1NS

[Kinsey Moore]

These changes look good. I'm glad you were able to simplify this a bit.

As for the test failures, they all fall into that category of timing sensitive 
tests that QEMU breaks with large bursts of near-simultaneous timer ticks.

Kinsey

-Original Message-
From: devel  On Behalf Of Gedare Bloom
Sent: Thursday, January 6, 2022 16:23
To: devel@rtems.org
Subject: Re: [PATCH 0/3] aarch64: boot in to EL1NS

rtems-test results for xilinx-zynqmp_lp64_qemu with RTEMS_SMP:

Passed:632
Failed:  5
User Input:  5
Expected Fail:   0
Indeterminate:   3
Benchmark:   3
Timeout: 1
Test too long:   1
Invalid: 0
Wrong Version:   0
Wrong Build: 0
Wrong Tools: 0
Wrong Header:0
--
Total: 650
Failures:
 spintrcritical24.exe
 smpschededf01.exe
 smpmrsp01.exe
 spintrcritical21.exe
 smpschedaffinity02.exe

On Thu, Jan 6, 2022 at 3:13 PM Gedare Bloom  wrote:
>
> This patch series resolves a lingering problem with the
> aarch64 port for the versal, which uses gicv3, that it
> is not possible to initialize the GIC distributor and
> redistributor (cpuif) while in the non-secure world.
> Previously we added a configuration option to allow
> running RTEMS in secure world as a way to overcome
> this problem, but that is not the right thing to do
> in general. Only trusted firmware is expected to run
> in secure world, and it is not supported to run an SMP
> kernel in secure world, so this problem needs a different
> fix.
>
> We now use the bsp_start_hook_0 to initialize the GIC from
> EL3 secure before stepping down to EL1NS.
> This hook is only called when execution begins in EL3S, which is the
> case for the versal running on qemu. GIC initialization is still
> attempted again during the generic IRQ initialization. BSPs that
> start in EL2 or EL1, or that use gicv2, behave as before, but the
> BSP-specific SMP initialization for xilinx-zynqmp moves from hook_0
> to hook_1.
>
> rtems-test results for xilinx-versal_lp64_qemu:
> Passed:578
> Failed:  2
> User Input:  5
> Expected Fail:   0
> Indeterminate:   0
> Benchmark:   3
> Timeout: 1
> Test too long:   2
> Invalid: 0
> Wrong Version:   0
> Wrong Build: 0
> Wrong Tools: 0
> Wrong Header:0
> --
> Total: 591
> Failures:
>  sp69.exe
>  spintrcritical21.exe
>
> --
>
> rtems-test results for xilinx-zynqmp_lp64_qemu:
>
> Passed:577
> Failed:  1
> User Input:  5
> Expected Fail:   0
> Indeterminate:   3
> Benchmark:   3
> Timeout: 1
> Test too long:   1
> Invalid: 0
> Wrong Version:   0
> Wrong Build: 0
> Wrong Tools: 0
> Wrong Header:0
> --
> Total: 591
> Failures:
>  spintrcritical21.exe
>
> --
>
> Gedare Bloom (3):
>   bsps/aarch64: refactor register init and hooks
>   arm/gicv3: refactor DIST initialization to helper
>   aarch64: always boot into EL1NS
>
>  bsps/aarch64/shared/start/start.S | 127 ++
>  .../xilinx-versal/start/bspstarthooks.c   |   3 +-
>  .../xilinx-zynqmp/start/bspstarthooks.c   |  12 +-
>  bsps/shared/dev/irq/arm-gicv3.c   |  75 +--
>  spec/build/bsps/aarch64/a53/grp.yml   |   2 -
>  spec/build/bsps/aarch64/a72/grp.yml   |   2 -
>  spec/build/bsps/aarch64/optisns.yml   |  20 ---
>  spec/build/bsps/aarch64/xilinx-versal/grp.yml |   2 -
>  spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml |   2 -
>  9 files changed, 109 insertions(+), 136 deletions(-)
>  delete mode 100644 spec/build/bsps/aarch64/optisns.yml
>
> --
> 2.25.1
>
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[PATCH rtems-docs] cpu-supplement: Add aarch64 to index

[Kinsey Moore]

This was never updated when AArch64 documentation was added.
---
 cpu-supplement/index.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cpu-supplement/index.rst b/cpu-supplement/index.rst
index 951d6b7..733ffcc 100644
--- a/cpu-supplement/index.rst
+++ b/cpu-supplement/index.rst
@@ -24,6 +24,7 @@ RTEMS CPU Architecture Supplement (|version|).
 
preface
port
+   aarch64
arm
atmel_avr
blackfin
-- 
2.30.2

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[PATCH rtems-libbsd] Import arm64 in_cksum.h correctly

[Kinsey Moore]

When this file was brought in, it came from the wrong location or
freebsd-org hash. This corrects the file such that freebsd-to-rtems.py
runs cleanly.
---
 freebsd/sys/arm64/include/machine/in_cksum.h | 43 +++-
 1 file changed, 6 insertions(+), 37 deletions(-)

diff --git a/freebsd/sys/arm64/include/machine/in_cksum.h 
b/freebsd/sys/arm64/include/machine/in_cksum.h
index d55b838b..522ba005 100644
--- a/freebsd/sys/arm64/include/machine/in_cksum.h
+++ b/freebsd/sys/arm64/include/machine/in_cksum.h
@@ -1,6 +1,4 @@
 /*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
  *
@@ -31,7 +29,6 @@
  * from tahoe: in_cksum.c  1.2 86/01/05
  * from:   @(#)in_cksum.c  1.3 (Berkeley) 1/19/91
  * from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
- * from: src/sys/alpha/include/in_cksum.h,v 1.7 2005/03/02 21:33:20 joerg
  * $FreeBSD$
  */
 
@@ -40,44 +37,16 @@
 
 #include 
 
+#ifdef _KERNEL
 #definein_cksum(m, len)in_cksum_skip(m, len, 0)
-
+u_short in_addword(u_short sum, u_short b);
+u_short in_cksum_skip(struct mbuf *m, int len, int skip);
+u_int do_cksum(const void *, int);
 #if defined(IPVERSION) && (IPVERSION == 4)
-/*
- * It it useful to have an Internet checksum routine which is inlineable
- * and optimized specifically for the task of computing IP header checksums
- * in the normal case (where there are no options and the header length is
- * therefore always exactly five 32-bit words.
- */
-#ifdef __CC_SUPPORTS___INLINE
-
-static __inline void
-in_cksum_update(struct ip *ip)
-{
-   int __tmpsum;
-   __tmpsum = (int)ntohs(ip->ip_sum) + 256;
-   ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
-}
-
-#else
-
-#definein_cksum_update(ip) 
\
-   do {\
-   int __tmpsum;   \
-   __tmpsum = (int)ntohs(ip->ip_sum) + 256;\
-   ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));\
-   } while(0)
-
-#endif
+u_int in_cksum_hdr(const struct ip *);
 #endif
 
-#ifdef _KERNEL
-#if defined(IPVERSION) && (IPVERSION == 4)
-u_int in_cksum_hdr(const struct ip *ip);
-#endif
-u_short in_addword(u_short sum, u_short b);
 u_short in_pseudo(u_int sum, u_int b, u_int c);
-u_short in_cksum_skip(struct mbuf *m, int len, int skip);
-#endif
 
+#endif /* _KERNEL */
 #endif /* _MACHINE_IN_CKSUM_H_ */
-- 
2.30.2

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Re: arm64 support for libbsd

[Kinsey Moore]

On 12/15/2021 01:32, Sebastian Huber wrote:

Hello Kinsey,

I didn't work with libbsd for a while and noticed now that there are 
changes after calling:


./freebsd-to-rtems.py -R
./freebsd-to-rtems.py

git status
modified:   freebsd/sys/arm64/include/machine/in_cksum.h

I don't know how you imported the in_cksum.h, but there should be no 
modified files after running the script.


I could swear I imported that correctly and even verified that the 
import was clean, but either that wasn't the case or I had a 
non-clean/correct freebsd-org tree. I've verified that everything still 
compiles correctly with the changes and will submit patches for the 
affected branches.



Kinsey

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Re: [PATCH v2 1/3] aarch64: add internal API for secure monitor call (smc)

[Kinsey Moore]

On 12/13/2021 19:56, Gedare Bloom wrote:

On Mon, Dec 13, 2021 at 9:55 AM Kinsey Moore  wrote:

Everything else looks good. Just one nit below.

On 12/11/2021 10:16, Gedare Bloom wrote:

---
   cpukit/score/cpu/aarch64/aarch64-smc.c| 72 
   .../aarch64/include/rtems/score/aarch64-smc.h | 83 +++
   spec/build/cpukit/cpuaarch64.yml  |  2 +
   3 files changed, 157 insertions(+)
   create mode 100644 cpukit/score/cpu/aarch64/aarch64-smc.c
   create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h

diff --git a/cpukit/score/cpu/aarch64/aarch64-smc.c 
b/cpukit/score/cpu/aarch64/aarch64-smc.c
new file mode 100644
index 00..c531d074d8
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-smc.c
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ *  @file
+ *
+ *  @brief This source file contains the implementation of
+ *_AArch64_SMC_Invoke().
+ */
+
+/*
+ * Copyright (C) 2021 Gedare Bloom 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+
+int _AArch64_SMC_Invoke(
+  uint32_t function_id,
+  uintptr_t arg0,
+  uintptr_t arg1,
+  uintptr_t arg2,
+  uintptr_t arg3,
+  uintptr_t arg4,
+  uintptr_t arg5,
+  uintptr_t arg6,

The SMC arguments here should be uint64_t for all AArch64 calls
regardless of ABI.


This shouldn't matter, since AArch64 calls will have LP64? I guess I
can change it. My thinking was that if we want to later add
_AArch32_SMC_Invoke() it can have almost the exact same prototype as
this function (except the return type but even that is a pointer),
which might simplify some programming.
The problem is that AArch64 has the LP64 and ILP32 ABIs which both use 
SMC64 since ILP32 is really just normal AArch64 instructions, memory 
space, and 64-bit registers under the hood. AArch32/ARMv7 has the same 
data model as AArch64/ILP32, but AArch32/ARMv7 uses SMC32 calls since 
it's 32-bit registers. This all assumes that I've read/remember the 
specs correctly.



+  AArch64_SMC_Return *result
+) {
+  int rv;
+
+  /* This only works for SMC that return 4 or fewer results. It may be extended
+   * up to the full 18 return results specified for SMC64, but then we would
+   * need to allocate a callee-saved register for *result */
+  __asm__ volatile(
+"smc  #0\n"
+"mov  %0, x0\n"
+"ldr  x15, [sp]\n"
+"cbz  x15, 0f\n"
+"stp  x0, x1, [x15]\n"
+"stp  x2, x3, [x15, #16]\n"
+"0:\n"
+: "=r" ( rv )
+:
+: "x0", "x1", "x2", "x3", "x15"
+  );
+
+  return rv;
+}
+
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h
new file mode 100644
index 00..e80cc1e99b
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief This header file provides API to wrap secure monitor calls (smc).
+ */
+
+/*
+ * Copyright (C) 2021 Gedare Bloom 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+

Re: [PATCH v2 1/3] aarch64: add internal API for secure monitor call (smc)

[Kinsey Moore]

Everything else looks good. Just one nit below.

On 12/11/2021 10:16, Gedare Bloom wrote:

---
  cpukit/score/cpu/aarch64/aarch64-smc.c| 72 
  .../aarch64/include/rtems/score/aarch64-smc.h | 83 +++
  spec/build/cpukit/cpuaarch64.yml  |  2 +
  3 files changed, 157 insertions(+)
  create mode 100644 cpukit/score/cpu/aarch64/aarch64-smc.c
  create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h

diff --git a/cpukit/score/cpu/aarch64/aarch64-smc.c 
b/cpukit/score/cpu/aarch64/aarch64-smc.c
new file mode 100644
index 00..c531d074d8
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-smc.c
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ *  @file
+ *
+ *  @brief This source file contains the implementation of
+ *_AArch64_SMC_Invoke().
+ */
+
+/*
+ * Copyright (C) 2021 Gedare Bloom 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+
+int _AArch64_SMC_Invoke(
+  uint32_t function_id,
+  uintptr_t arg0,
+  uintptr_t arg1,
+  uintptr_t arg2,
+  uintptr_t arg3,
+  uintptr_t arg4,
+  uintptr_t arg5,
+  uintptr_t arg6,


The SMC arguments here should be uint64_t for all AArch64 calls 
regardless of ABI.




+  AArch64_SMC_Return *result
+) {
+  int rv;
+
+  /* This only works for SMC that return 4 or fewer results. It may be extended
+   * up to the full 18 return results specified for SMC64, but then we would
+   * need to allocate a callee-saved register for *result */
+  __asm__ volatile(
+"smc  #0\n"
+"mov  %0, x0\n"
+"ldr  x15, [sp]\n"
+"cbz  x15, 0f\n"
+"stp  x0, x1, [x15]\n"
+"stp  x2, x3, [x15, #16]\n"
+"0:\n"
+: "=r" ( rv )
+:
+: "x0", "x1", "x2", "x3", "x15"
+  );
+
+  return rv;
+}
+
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h
new file mode 100644
index 00..e80cc1e99b
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/aarch64-smc.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief This header file provides API to wrap secure monitor calls (smc).
+ */
+
+/*
+ * Copyright (C) 2021 Gedare Bloom 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_AARCH64_SMC_H
+#define 

[PATCH] bsps/aarch64: Remove erroneous cache feature

[Kinsey Moore]

The AArch64 cache implementation does not define
rtems_cache_disable_data(), but declares that it does via
CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of
_CPU_cache_disable_data() is sufficient to enable this functionality
without the erroneous cache feature flag.

Closes #4569
---
 bsps/aarch64/shared/cache/cache.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/bsps/aarch64/shared/cache/cache.c 
b/bsps/aarch64/shared/cache/cache.c
index 9e7446a077..fc1766c2b9 100644
--- a/bsps/aarch64/shared/cache/cache.c
+++ b/bsps/aarch64/shared/cache/cache.c
@@ -47,8 +47,6 @@
 
 #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
 
-#define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA
-
 #define AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ( (size_t) 64 )
 #define AARCH64_CACHE_PREPARE_MVA(mva) (const void *) \
   RTEMS_ALIGN_DOWN ( (size_t) mva, AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT )
-- 
2.30.2

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[PATCH] spec: Update location of cadence I2C

[Kinsey Moore]

When the cadence I2C code was moved to a shared directory, the
references were updated but the install locations weren't. This updates
the install locations to match what out-of-tree applications expect.
---
 spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml | 4 +++-
 spec/build/bsps/arm/xilinx-zynq/obj.yml | 6 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml 
b/spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml
index fd9d51dfa9..fa269d61ad 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/objcadencei2c.yml
@@ -9,10 +9,12 @@ enabled-by: true
 includes: []
 install:
 - destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
+- destination: ${BSP_INCLUDEDIR}/dev/i2c
   source:
   - bsps/include/dev/i2c/cadence-i2c-regs.h
   - bsps/include/dev/i2c/cadence-i2c.h
-  - bsps/aarch64/xilinx-zynqmp/include/bsp/i2c.h
 links: []
 source:
 - bsps/shared/dev/i2c/cadence-i2c.c
diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml 
b/spec/build/bsps/arm/xilinx-zynq/obj.yml
index bc675cd38c..dcac09126b 100644
--- a/spec/build/bsps/arm/xilinx-zynq/obj.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml
@@ -14,10 +14,12 @@ install:
   - bsps/arm/xilinx-zynq/include/tm27.h
 - destination: ${BSP_INCLUDEDIR}/bsp
   source:
-  - bsps/include/dev/i2c/cadence-i2c-regs.h
-  - bsps/include/dev/i2c/cadence-i2c.h
   - bsps/arm/xilinx-zynq/include/bsp/i2c.h
   - bsps/arm/xilinx-zynq/include/bsp/irq.h
+- destination: ${BSP_INCLUDEDIR}/dev/i2c
+  source:
+  - bsps/include/dev/i2c/cadence-i2c-regs.h
+  - bsps/include/dev/i2c/cadence-i2c.h
 links: []
 source:
 - bsps/arm/shared/cache/cache-l2c-310.c
-- 
2.30.2

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[PATCH 2/2] cpukit: Consistize OAR copyright headers

[Kinsey Moore]

These two OAR copyright headers are the only two in the codebase with
a format that differs from the typical OAR copyright header. This makes
all of the OAR copyright headers consistent.
---
 cpukit/score/cpu/arm/include/rtems/score/cpu.h | 2 +-
 cpukit/score/src/stackallocatorforidle.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h 
b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index b8e3604fbb..c8d4442417 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -12,7 +12,7 @@
  *
  *  Copyright (c) 2007 Ray Xu 
  *
- *  Copyright (c) 2006 OAR Corporation
+ *  Copyright (c) 2006 On-Line Applications Research Corporation (OAR)
  *
  *  Copyright (c) 2002 Advent Networks, Inc.
  *Jay Monkman 
diff --git a/cpukit/score/src/stackallocatorforidle.c 
b/cpukit/score/src/stackallocatorforidle.c
index 7a8a05fae6..76b6ace1f4 100644
--- a/cpukit/score/src/stackallocatorforidle.c
+++ b/cpukit/score/src/stackallocatorforidle.c
@@ -1,7 +1,7 @@
 /*
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (C) 2021 OAR Corporation
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
-- 
2.30.2

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[PATCH 1/2] cpukit: Enable debug for SMP AArch64

[Kinsey Moore]

Ensure when both RTEMS_DEBUG is specified and pointers are large that
enough space is allocated to accomodate the Per_CPU_Control structure.
This changes the calculation to be more compositional instead of trying
to list out every permutation of options possible.
---
 cpukit/include/rtems/score/percpu.h | 31 -
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/cpukit/include/rtems/score/percpu.h 
b/cpukit/include/rtems/score/percpu.h
index 6081653a86..0794f15f69 100644
--- a/cpukit/include/rtems/score/percpu.h
+++ b/cpukit/include/rtems/score/percpu.h
@@ -38,18 +38,31 @@
 extern "C" {
 #endif
 
-#if defined(RTEMS_SMP)
-  #if defined(RTEMS_PROFILING)
-#define PER_CPU_CONTROL_SIZE_APPROX \
-  ( 512 + CPU_PER_CPU_CONTROL_SIZE + CPU_INTERRUPT_FRAME_SIZE )
-  #elif defined(RTEMS_DEBUG) || CPU_SIZEOF_POINTER > 4
-#define PER_CPU_CONTROL_SIZE_APPROX \
-  ( 256 + CPU_PER_CPU_CONTROL_SIZE + CPU_INTERRUPT_FRAME_SIZE )
+#if defined( RTEMS_SMP )
+  #if defined( RTEMS_PROFILING )
+#define PER_CPU_CONTROL_SIZE_PROFILING 332
+  #else
+#define PER_CPU_CONTROL_SIZE_PROFILING 0
+  #endif
+
+  #if defined( RTEMS_DEBUG )
+#define PER_CPU_CONTROL_SIZE_DEBUG 76
   #else
-#define PER_CPU_CONTROL_SIZE_APPROX \
-  ( 180 + CPU_PER_CPU_CONTROL_SIZE + CPU_INTERRUPT_FRAME_SIZE )
+#define PER_CPU_CONTROL_SIZE_DEBUG 0
   #endif
 
+  #if CPU_SIZEOF_POINTER > 4
+#define PER_CPU_CONTROL_SIZE_BIG_POINTER 76
+  #else
+#define PER_CPU_CONTROL_SIZE_BIG_POINTER 0
+  #endif
+
+  #define PER_CPU_CONTROL_SIZE_BASE 180
+  #define PER_CPU_CONTROL_SIZE_APPROX \
+( PER_CPU_CONTROL_SIZE_BASE + CPU_PER_CPU_CONTROL_SIZE + \
+CPU_INTERRUPT_FRAME_SIZE + PER_CPU_CONTROL_SIZE_PROFILING + \
+PER_CPU_CONTROL_SIZE_DEBUG + PER_CPU_CONTROL_SIZE_BIG_POINTER )
+
   /*
* This ensures that on SMP configurations the individual per-CPU controls
* are on different cache lines to prevent false sharing.  This define can be
-- 
2.30.2

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[PATCH rtems-source-builder] rtems-gcc-10-newlib-head: Uncomment patch lines

[Kinsey Moore]

These lines were accidentally committed with a leading + which resulted
in them being non-functional. This restores them to functionality such
that the patch gets downloaded and applied appropriately.
---
 rtems/config/tools/rtems-gcc-10-newlib-head.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg 
b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
index f648080..29b56c0 100644
--- a/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
+++ b/rtems/config/tools/rtems-gcc-10-newlib-head.cfg
@@ -13,8 +13,8 @@
 %patch add gcc -p1 
https://devel.rtems.org/raw-attachment/ticket/4215/0001-nios2-Remove-custom-instruction-warnings.patch
 %hash sha512 0001-nios2-Remove-custom-instruction-warnings.patch 
afd8a5e6bdcc5b75d5fbbf558bdf56ccac400521a6eec9d88cc95f6be67c481f2dbf8faa0f6ddc1e4ac7c56a84938714d80e46e9cf80ec4b8fcd739986449881
 
-+%patch add newlib -p1 
https://devel.rtems.org/raw-attachment/ticket/4510/0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch
-+%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch 
BHRMimj6ztKPHQFxypI8RwPmno96B56eVQGx5dtCtcOb+qICMrQC1fa0jP3JrR8RGJI4y61RoYvpnj6EbTmRKA==
+%patch add newlib -p1 
https://devel.rtems.org/raw-attachment/ticket/4510/0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch
+%hash sha512 0001-aarch64-Add-ILP32-ABI-support-in-assembly.patch 
BHRMimj6ztKPHQFxypI8RwPmno96B56eVQGx5dtCtcOb+qICMrQC1fa0jP3JrR8RGJI4y61RoYvpnj6EbTmRKA==
 
 %define newlib_version eb03ac1
 %define newlib_external 1
-- 
2.30.2

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[PATCH] bsps/aarch64: Restore interrupt nesting

[Kinsey Moore]

Fixing the debug mask flag broke nested interrupts. This restores that
functionality.
---
 bsps/aarch64/include/dev/irq/arm-gic-arch.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h 
b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
index 049a1c8555..f1b6fdc03d 100644
--- a/bsps/aarch64/include/dev/irq/arm-gic-arch.h
+++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h
@@ -49,8 +49,10 @@ extern "C" {
 static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
 {
   uint32_t interrupt_level = _CPU_ISR_Get_level();
-  _CPU_ISR_Set_level(1);
+  /* Enable interrupts for nesting */
+  _CPU_ISR_Set_level(0);
   bsp_interrupt_handler_dispatch(vector);
+  /* Restore interrupts to previous level */
   _CPU_ISR_Set_level(interrupt_level);
 }
 
-- 
2.30.2

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