Re: [PSES] Ground Fingers routed in CPU pin fields

2021-11-29 Thread Istvan Novak

Hi Charles,

Having a trace shorted to ground at one end and leaving open at the 
other end creates a quarter-wave resonator.


If for sake of example the propagation delay on the particular layer is 
160ps/", 250mils has 40ps and the period at the quarter-wave resonance 
is 4*40ps=160ps, which is around 6GHz.  At that frequency (and 
increasingly as we approach that frequency) the insertion loss, 
reflection and crosstalk will be higher. Whether this creates a problem, 
depends on the signaling speed and signaling budget.


Best regards,

Istvan Novak

Samtec


On 11/29/2021 1:55 PM, Charles Grasso wrote:

Hello all and I hope your Thanksgiving went well!

I am seeking some guidance on the effect (detrimental or otherwise) on
adding short (say 250mils) ground fingers in between high speed 
differential
pairs at their source. i.e at the IC pin field. The ground finger only 
has a via
at the entrance to the pin field and not at the final destination 250 
mils away.


Does anyone know of (or have experience of ) any issues this may cause?


--

Charles Grasso

Dish Technologies

 (c) 303-204-2974

(h) 303-317-5530

(e ) charles.gra...@dish.com

(e2) chasgra...@gmail.com

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Re: [PSES] SV: [PSES] Ground copper fill on signal layer on multilayer PCB

2020-02-21 Thread Istvan Novak

Hi Amund,

Since your potential problem appears to be at relatively low 
frequencies, an alternative to edge plating would be stitching the 
ground planes along the board edges with closely spaced vias.  We have 
done this at SUN Microsystems also as a preventive measure. On the other 
hand, you should also consider the possibility that the leaking happens 
not through the edge of the board but through components connected to 
internal traces but sitting on the top or bottom of the board.  What I 
am saying is that it is not necessarily the edge of the board that 
radiates.  You could check this by poking around with a close-field 
probe, even uncalibrated unshielded home-made small loop or monopole 
antennas might give you a useful hint where the noise is coming from.  
You could also put absorbing sheets to the edge of the board to see if 
it makes a difference in the overall radiation.


Best regards,

Istvan Novak

Samtec



On 2/19/2020 1:50 AM, Amund Westin wrote:


Hi Ken

No, I have not considered edge-plating. I’ll look into this now.

We have some high frequency noise (400-500MHz) from differential lines 
leaking out from an inner layer of a multilayer pcb. Edge-plating 
might be a good solution.


Thanks for the tip.

BR
Amund

*Fra:* IBM Ken
*Sendt:* 18. februar 2020 23:18
*Til:* EMC-PSTC@LISTSERV.IEEE.ORG
*Emne:* Re: [PSES] Ground copper fill on signal layer on multilayer PCB

Hi Amund!  Have you also considered edge-plating?  Are you trying to 
reduce radiated noise outside your product, or cross-talk within the 
product (or both)?


On Tue, Feb 18, 2020 at 3:03 AM Amund Westin <mailto:am...@westin-emission.no>> wrote:


Between two solid ground planes, we have a signal layer, routing
high speed differential lines.

What do you recommend:

 1. fill the remaining area with copper in the signal layer
 2. fill only the border of the layer (5mm ground copper trace
around the layer edge)
 3. no fill at all

Best regards

Amund

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Re: [PSES] DC/DC EMI Input Filter Stability

2019-06-04 Thread Istvan Novak

Hi James,

If you consider input filters for DC-DC converter inputs (not a must, 
but a good idea), you want to have one filter for each converter input.? 
In such a case if you design each converter with its own input filter to 
be stable, there will be no problem.? I have been designing computer 
systems with many DC-DC converters in the past 22 years (also up to a 
dozen converter inputs connected together without input filters) and 
there were no issues around this.? The key is not to save on high-ESR 
bulk capacitors connected across the input of each DC-DC converter.? In 
practice I have found the loop stability on the output side to be much 
more challenging to solve, but that should be handled differently.


You can find a few additional considerations in

http://www.electrical-integrity.com/Paper_download_files/DC12_11-MP2.pdf and

http://www.electrical-integrity.com/Paper_download_files/DC17_PAPER_11_OverviewComparisonPowerConverterStability_Hartman.pdf

Regards,

Istvan Novak

Samtec



On 6/4/2019 3:45 AM, James Pawson (U3C) wrote:


Morning all,

I?m designing an EMI filter for a DC input power line that has four 
DC/DC converters all running off it.


I know that the output impedance of the EMI filter needs to be much 
lower than the input impedance of the DC/DC converter to prevent 
oscillation/instability. But what happens when there are multiple 
DC/DC converters running in parallel from the same input? How do the 
input impedances interact? Do they appear in parallel or do the 
control loops isolate stability issues to individual converters?


My understanding from this paper - 
http://www.ti.com/lit/an/slua929a/slua929a.pdf - is that the control 
loop and output filter of the DC/DC contributes to the stability 
analysis. If so, then *each DC/DC can be considered individually* with 
the filter being designed to have margin to the lowest input impedance 
of all of the converters. This is instead of just adding all the input 
impedances in parallel.


Is my understanding correct?

Thanks in advance,

James

James Pawson

EMC Problem Solver

**

*Unit 3 Compliance*

Design for EMC / Pre Compliance / Problem Solving / EMC Testing / 
Consultancy / Environmental & Vibration


www.unit3compliance.co.uk <http://www.unit3compliance.co.uk/> -- 07811 
139957


Opening Hours: Tuesday to Friday, 0830 to 1800. Closed Monday.

Connect with me on LinkedIn 
<https://www.linkedin.com/in/james-pawson-unit-3-compliance/>


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Re: [PSES] Using a TDR for Shielding Effectiveness measurements

2018-04-20 Thread Istvan Novak
As long as we can assume that the propagation medium and the DUT are 
linear and time invariant, the time-domain response can be easily 
transformed to frequency-response data.  This is true also in the other 
direction: vector network analyzers today can be set to operate like TDR 
instruments as far as their displayed data is concerned. The dynamic 
range limitation is likely more relevant.

Regards,
Istvan Novak



Ken Javor wrote:
Re: [PSES] Using a TDR for Shielding Effectiveness measurements Given 
the few responses to date, I’ll fess up to cluelessness and curiosity. 
Aside from the obvious dynamic range limitation working in the time 
domain, if you limit yourself to the time domain, how do you map SE 
vs. frequency?


And given the inherent wide band nature of a TDR signal, I can’t see 
it being radiated properly. I’m thinking you would have to use 
something like an ASTM 4936 coaxial test fixture in order to main 
signal integrity up to the reflection point where the sample material 
puck is installed.




Ken Javor
Phone: (256) 650-5261



*From: *"Grasso, Charles" <charles.gra...@dish.com>
*Reply-To: *"Grasso, Charles" <charles.gra...@dish.com>
*Date: *Thu, 19 Apr 2018 15:23:27 +
*To: *<EMC-PSTC@LISTSERV.IEEE.ORG>
*Conversation: *Using a TDR for Shielding Effectiveness measurements
*Subject: *[PSES] Using a TDR for Shielding Effectiveness measurements

Hello all,

In lieu of using shielded chambers/spectrum analyzers and such, has 
anyone used a TDR for
performing shielding effectiveness measurements?  The simplicity is 
tempting – but I am

dubious about the dynamic range?

I have poked about in the usual place – but didn’t find any definitive 
studies. (I suppose

that is a clue in and of itself!)

Thanks

Charles Grasso
(w) 303-706-5467

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Re: [PSES] Using a TDR for Shielding Effectiveness measurements

2018-04-20 Thread Istvan Novak

Ken,
Actually what I was referring to: we can transmit a pulse (or rather a 
step, if it is a TDR), measure the response with an oscilloscope in the 
time domain and as long as the DUT is linear and time invariant, we can 
take the time-domain data from the oscilloscope, transform it into the 
frequency domain with Fourier transform, and if we do it properly, the 
result will be exactly the same that we would get with a vector-network 
analyzer, minus the dynamic range.

Best regards,
Istvan Novak



On 4/20/2018 11:00 AM, Ken Javor wrote:

My response was predicated on a purely time domain measurement.  If we are
going to transmit a pulse but measure in the frequency domain, then there is
no dynamic range limitation, assuming we have a pre-selected front end to
our receiver.  And if we are making a frequency domain measurement, then any
set of suitable transmit antennas will do, as we are only looking at some
fraction of the pulse spectrum at any one time; no need to transmit the
entire pulse spectrum simultaneously.

But if those are the ground rules, then any impulse generator laying around
the lab, from the old days when they were used to calibrate EMI receivers,
would suffice.

Ken Javor
Phone: (256) 650-5261




From: Istvan Novak <istvan.no...@oracle.com>
Date: Fri, 20 Apr 2018 08:28:09 -0400
To: Ken Javor <ken.ja...@emccompliance.com>, <EMC-PSTC@listserv.ieee.org>
Subject: Re: [PSES] Using a TDR for Shielding Effectiveness measurements

As long as we can assume that the propagation medium and the DUT are
linear and time invariant, the time-domain response can be easily
transformed to frequency-response data.  This is true also in the other
direction: vector network analyzers today can be set to operate like TDR
instruments as far as their displayed data is concerned. The dynamic
range limitation is likely more relevant.
Regards,
Istvan Novak



Ken Javor wrote:

Re: [PSES] Using a TDR for Shielding Effectiveness measurements Given
the few responses to date, I¹ll fess up to cluelessness and curiosity.
Aside from the obvious dynamic range limitation working in the time
domain, if you limit yourself to the time domain, how do you map SE
vs. frequency?

And given the inherent wide band nature of a TDR signal, I can¹t see
it being radiated properly. I¹m thinking you would have to use
something like an ASTM 4936 coaxial test fixture in order to main
signal integrity up to the reflection point where the sample material
puck is installed.



Ken Javor
Phone: (256) 650-5261



*From: *"Grasso, Charles" <charles.gra...@dish.com>
*Reply-To: *"Grasso, Charles" <charles.gra...@dish.com>
*Date: *Thu, 19 Apr 2018 15:23:27 +
*To: *<EMC-PSTC@LISTSERV.IEEE.ORG>
*Conversation: *Using a TDR for Shielding Effectiveness measurements
*Subject: *[PSES] Using a TDR for Shielding Effectiveness measurements

Hello all,

In lieu of using shielded chambers/spectrum analyzers and such, has
anyone used a TDR for
performing shielding effectiveness measurements?  The simplicity is
tempting ­ but I am
dubious about the dynamic range?

I have poked about in the usual place ­ but didn¹t find any definitive
studies. (I suppose
that is a clue in and of itself!)

Thanks

Charles Grasso
(w) 303-706-5467

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Re: [PSES] [SI-LIST] Re: Measurement Dilema - THE EXPLANATION!

2018-04-09 Thread Istvan Novak

Hi Doug,

It was great to chat with you.
Here is a brief summary of the technical details we spoke (Doug, correct 
me if I cite something incorrectly).


Staying with the question how could someone show and demonstrate the 
amount of current the oscillator pumps into the circuit, there are a 
couple of simple possibilities:
- measuring the current flowing in the wire between the oscillator 
output and the probes.  With this we need to be careful so that the 
measuring probe and instrument wont alter the setup's behavior too much.
- measuring the change of DC supply current going into the oscillator 
between unloaded state (its output disconnected from the probes), versus 
when the oscillator output is connected to the probes.  Here we have a 
better chance to create a setup that only minimally alters the original 
scenario: we can use a miniature battery powered current meter.  We can 
also measure the DC supply current on the oscillator separately when we 
connect a tuned circuit to its output drawing approximately 40mA at 
specific harmonics.


When we do one or both of the above tests while we rearrange the probe 
cables to get maximum signal on the oscilloscope input, we can notice 
that the AC current supplied by the oscillator has two distinct states: 
there is a case when the oscillator supplies several times ten 
milliamperes, but there is also another state, when the oscillator 
hardly supplies any AC current.  This letter case can further be tested 
by inserting a very small capacitance between the oscillator output and 
the probe loops: we will still get about the same big signal on the 
oscilloscope input.  When I reproduced Doug's experiment at home, this 
latter case was accidentally the first I stumbled across.  This case 
corresponds to a parallel resonance instead of a series resonance, 
requiring only a very small amount of current feeding the circuit.  The 
Q of the tuned circuit will amplify the small injected current, so the 
current flowing in the ground lead wire of the oscilloscope probe is 
comparable to what we get in the series resonance case.  As we keep 
moving the probe cables, we can 'tune' the circuit through a set of 
series and parallel resonances.


Thanks again Doug for sharing your interesting experiments!

Regards,
Istvan Novak


Istvan Novak wrote:

Great! Lets talk over the phone, will call you after work.

At the end though I think SI-list readers may also be interested in ways
we come up with to demonstrate further aspects of your intriguing
experiment.

Regards,

Istvan Novak


On 4/6/2018 1:49 AM, Douglas Smith wrote:

Actually the oscillator is producing about the same current it would into a 
short circuit, 40 mA) because it is driving a very low impedance of a series 
resonant circuit!
Istvan, let’s talk on the phone to save s lot of typing.
Doug Smith Sent from my iPhone IPhone: 408-858-4528 Office: 702-570-6108 Email: 
d...@dsmith.org Website: http://dsmith.org
On Thu, Apr 5, 2018 at 21:07, Istvan Novak <istvan.no...@verizon.net> wrote:
Doug,

Thank you for sharing your interesting experiments. These always
trigger my curiosity to look a little further. In my basement lab I
came up with a small series of experiments to separate the possible
different coupling mechanisms from the oscillator to the oscilloscope
input. Though I did not intend to replicate your exact setup, I believe
it was conceptually and essentially similar enough that the results may
apply to a large number of setups, including yours. From all of the
different tests my conclusion is that the oscillator is not supplying a
significant amount of current to produce the effect in question. I have
not had the good fortune yet to see your full live demonstration, plus
as you say you have much more data than what you publish, so it very
well could be that you already have done similar experiments and came to
similar conclusions. Therefore I would like to hear the thoughts of
those list members who did not attend your demonstrations, what kind of
experiments would they suggest to prove or disprove my conclusion.

Regards,

Istvan Novak



On 1/30/2018 12:06 PM, Douglas Smith wrote:

I did that experiment a long time ago, almost 30 years ago, when
developing this experiment, which is described in my book.

Reducing ground lead length to near zero eliminates the effect almost
completely with no other changes in the experimental setup. You still
see a little effect about 1/50 of before, due to the shield transfer
impedance of the probe cables. A tiny ground lead always swamps shield
transfer impedance of practical shielded cables. I do that experiment
for my classes as an extension of this experiment.

My live experiments are always more complete than the versions I
publish both to keep published versions reasonably short and to
provide extra value to live experiments. I usually have ten times the
data I actually publish!

Doug Smith
Sent from my iPhone
IPhone: 408-858-4528
Office: 702-57

Re: [PSES] Power Integrity Question

2018-04-09 Thread Istvan Novak

Yes and no.
The coupling path was closing through the user PCB...


John Woodgate wrote:


That should be warned about in the data sheet. Internal EMC problems 
tend to be rare, which is good, but because they are rare, there 
should be warnings if they can occur.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associateswww.woodjohn.uk
Rayleigh, Essex UK
On 2018-04-09 13:19, Istvan Novak wrote:
And examples can be even more strange: we had DC-DC converter modules 
failing to work properly because one of the converter's power pins 
feeding an internal linear regulator picked up noise from the same 
converter.


Regards,
Istvan Novak



John Woodgate wrote:
I agree. One particular point is keeping a trace connected to an 
inverting input very short, even if that means including a 
low-value  'stopper' resistor close to the chip. That point has 
quasi-infinite sensitivity but infinitesimal impedance only within 
the op-amp pass band. Above the pass-band, it is an antenna 
connected to a diode. And yes, it can pick up power rail noise.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-09 04:27, Doug Smith wrote:

Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that 
you mention, do have response to GHz noise even 1 MHz unity gain 
opamps! Low frequency op amps can  generate a DC offset on their 
inputs from GHz digital noise or radio signals, a common problem 
for the last  45 years since I first observed it. Power supply 
rejection of op amps goes to pot pretty quickly with frequency as 
well. High frequency effects therefore are important even to low 
speed analog circuits. In some ways, one must lay out the low 
frequency analog circuit using microwave techniques to keep RF 
noise at bay. The circuit features must be keep really small,, 
including the bypass capacitors being kept extremely close (< 100 
mils) to the op amp.


45 years ago, faced with opamp problems from RF noise I developed 
some techniques for keeping the op amps happy. I discuss these in 
my upcoming course.


Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
--
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
Web: http://www.dsmith.org
--





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Re: [PSES] Power Integrity Question

2018-04-09 Thread Istvan Novak
And examples can be even more strange: we had DC-DC converter modules 
failing to work properly because one of the converter's power pins 
feeding an internal linear regulator picked up noise from the same 
converter.


Regards,
Istvan Novak



John Woodgate wrote:
I agree. One particular point is keeping a trace connected to an 
inverting input very short, even if that means including a low-value  
'stopper' resistor close to the chip. That point has quasi-infinite 
sensitivity but infinitesimal impedance only within the op-amp pass 
band. Above the pass-band, it is an antenna connected to a diode. And 
yes, it can pick up power rail noise.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-09 04:27, Doug Smith wrote:

Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that 
you mention, do have response to GHz noise even 1 MHz unity gain 
opamps! Low frequency op amps can  generate a DC offset on their 
inputs from GHz digital noise or radio signals, a common problem for 
the last  45 years since I first observed it. Power supply rejection 
of op amps goes to pot pretty quickly with frequency as well. High 
frequency effects therefore are important even to low speed analog 
circuits. In some ways, one must lay out the low frequency analog 
circuit using microwave techniques to keep RF noise at bay. The 
circuit features must be keep really small,, including the bypass 
capacitors being kept extremely close (< 100 mils) to the op amp.


45 years ago, faced with opamp problems from RF noise I developed 
some techniques for keeping the op amps happy. I discuss these in my 
upcoming course.


Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
--
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
Web: http://www.dsmith.org
--





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Re: [PSES] Power Integrity Question

2018-04-08 Thread Istvan Novak

Ken,

Again, there is no generic answer, it depends on the circuit you feed.  
Generic low speed logic can be fairly tolerant to noise, but today's 
high-speed digital chips also have a lot of analog-like circuits: PLL, 
oscillators, SerDes drivers and receivers.  Dependent on their 
construction, their tolerance to noise can be very different.  If we are 
lucky, we get that requirement from the device's data sheet, so that we 
can decide about acceptable limits rail by rail and device by device.


Dips usually dont kill a device, it may cause 'only' functional errors.  
A spike can cause damage to the chips, but only if it appears on the 
semiconductor itself.  But we do not have direct access to the 
semiconductor to measure the voltage, and as opposed to signal 
integrity, where we can deembed the package and can reliably infer the 
waveform on the silicon from a waveform measured at the pin and from a 
package model, we almost never have a model for the power path of the 
package to do the same deembedding with power noise.


Regards,
Istvan Novak



Ken Javor wrote:
Re: [PSES] Power Integrity Question Then let’s slightly rephrase the 
question. What sort of ripple causes problems? Is it dips - how much? 
Spikes – again, how much?  Let’s confine this to digital logic. Analog 
is easier because there is defined power supply ripple rejection for 
parts plus the noise sources aren’t high speed.


Ken Javor
Phone: (256) 650-5261



*From: *John Woodgate <j...@woodjohn.uk>
*Date: *Sun, 8 Apr 2018 08:09:47 +0100
*To: *Ken Javor <ken.ja...@emccompliance.com>, 
<EMC-PSTC@LISTSERV.IEEE.ORG>

*Subject: *Re: [PSES] Power Integrity Question



A specific target would typically be 'less than 1/3 of the value known 
to just provoke trouble'.



John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk <http://www.woodjohn.uk> 
<http://www.woodjohn.uk>

Rayleigh, Essex UK

On 2018-04-08 04:25, Ken Javor wrote:


Re: [PSES] Power Integrity Question If the answer to how much
ripple is too much, or how little ripple is good enough is in all
cases, “it depends,” then does that mean that the pursuit of power
integrity has a purely functional pass/fail criteria; i.e., that
the unit operates properly, as opposed to a specific target on
ripple level?

 Ken Javor
 Phone: (256) 650-5261





*From: *John Woodgate <j...@woodjohn.uk> <mailto:j...@woodjohn.uk>
<mailto:j...@woodjohn.uk>
*Date: *Sat, 7 Apr 2018 17:58:36 +0100
*To: *Ken Javor <ken.ja...@emccompliance.com>
<mailto:ken.ja...@emccompliance.com>
<mailto:ken.ja...@emccompliance.com> ,
<EMC-PSTC@LISTSERV.IEEE.ORG> <mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
<mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
*Subject: *Re: [PSES] Power Integrity Question



I don't think that there is a general rule that doesn't have so
many exceptions as to be useless. Even a 'simple' audio power
amplifier can show this. A conventional linear amplifier can have
very good PSRR (power supply rejection ratio) but a Class D
amplifier has zero dB PSRR - none at all.


 John Woodgate OOO-Own Opinions Only
 J M Woodgate and Associates www.woodjohn.uk
<http://www.woodjohn.uk> <http://www.woodjohn.uk>
<http://www.woodjohn.uk> <http://www.woodjohn.uk>
 Rayleigh, Essex UK

 On 2018-04-07 17:41, Ken Javor wrote:



Power Integrity Question There are many learned
books/papers/discussions on how to achieve proper power
integrity by way of proper PCB layout and proper capacitor
decoupling techniques, but what is the goal?  I don't mean the
functional goal, which is obvious, but rather what is the
metric?  Is it ripple voltage peak-to-peak, maximum excursion,
minimum excursion, some rms value, or...?

  This question is decoupled from achieving PI for the purpose
of controlling radiated emissions: just asking how close to
pure unadulterated dc a dc rail must be in order to be
considered properly functional.

  Understand the answer will be different for an analog rail
vs. a digital one, and for different digital rails, but
appreciate insight into what constitutes acceptable power
quality for all dc rails used in a typical piece of electronics.

  Thank you,

  Ken Javor
  Phone: (256) 650-5261


   -
 


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Re: [PSES] Power Integrity Question

2018-04-07 Thread Istvan Novak

Hi Ken,

Good question, and as you already suspect, there is no clear, generic 
answer (and for the same reason there is no such thing as typical 
electronics).  Having practiced this art for decades, and teaching 
courses (up to five days in length) on the subject, the best we can do 
is to explain all possible factors that eventually the responsible 
designer has to take into account.


You will find pieces of the answer in various books and on the 
publications posted on my website, for instance

http://www.electrical-integrity.com/Paper_download_files/Ansoft_EMI_Workshop_SUN_for_22Aug07_v2.pdf

Regards,
Istvan Novak

Ken Javor wrote:
Power Integrity Question There are many learned 
books/papers/discussions on how to achieve proper power integrity by 
way of proper PCB layout and proper capacitor decoupling techniques, 
but what is the goal?  I don't mean the functional goal, which is 
obvious, but rather what is the metric?  Is it ripple voltage 
peak-to-peak, maximum excursion, minimum excursion, some rms value, or...?


This question is decoupled from achieving PI for the purpose of 
controlling radiated emissions: just asking how close to pure 
unadulterated dc a dc rail must be in order to be considered properly 
functional.


Understand the answer will be different for an analog rail vs. a 
digital one, and for different digital rails, but appreciate insight 
into what constitutes acceptable power quality for all dc rails used 
in a typical piece of electronics.


Thank you,

Ken Javor
Phone: (256) 650-5261


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Re: Q on Correlation of Votage ripple with a Spectrum Analyser

2003-07-27 Thread istvan novak

Charles,

Doing this kind of correlation is very difficult for the following reasons:
- unless you measure a very simple and dummy system, hardware today is
so complex that you cant predict for sure its activity; it is a strong
function
of time.
-tThe spectrum analyzer and scope will look at the same signal
in different ways: analog spectrum analyzers have a seep time and settling
time determining the frequency and aperture of visit each frequency.
If you have a spectrumn analyzer used for compliance tests,
probably the CISPR filter is on.  Scopes on the other hand (digital scopes)
undersample the signal, whether it is called real-time or not.  Memory
and displey refresh rate does not allow scopes to display and process all
data points of high-frequency signals.  Real-time scopes do it for a
given time window, but it is usually way less than the time constant of
a CISPR filter on the spectrum analyzer.
- connection to the source makes a big difference.  I assume when you
calibrated the reading with a sine wave, a coaxial cable with coax
connectors
at both ends was used.  Presumably the product does not have a coaxial
connector on the Vcc plane, so you have to make your own connection or
use a hand-held probe.  This is very extra noise usually gets in the path,
and
the scope reading becomes unrealistically high.  I have found no active
scope probes so far, which would give a correct reading in a noisy
environment.
We hopefully should not see noise on the Vcc planes more than a few
hundred mV.  In contrast, many scope probes can pick up spikes as big as
volts from the environment.  If you want to measure noise levels below
100mVpp,
double-shielded coax is necessary in noisy environments.  Here the 'noisy
environment' refers to the close vicinity of the point you test.  The
simplest
test is: take your present probe, and hook up a good double-shielded coax
to the same points.  Check both readings on the same scope at the same time,
and compare.

I hope this helps.

Best regards,
Istvan Novak
SUN Microsystems


From: Charles Grasso cgrassospri...@earthlink.net
To: Ken Javor ken.ja...@emccompliance.com; Emc-Pstc
emc-p...@ieee.org
Sent: Saturday, July 26, 2003 9:11 PM
Subject: RE: Q on Correlation of Votage ripple with a Spectrum Analyser



 Hi all,

 Actually I was using a good ole Spectrim Analyser
 so I sidestepped the windowing issue/software issues
 altogether.

 What I was(am)trying to do was match the max voltage
 as measured on a scope with the value as measured
 on a SA.

 I first calibrated myslef using a known source - a sine wave.
 The amplitudes fell in just as theory predicted. Encouraged,
 I then probed the Vcc plane on a product I was working on
 and was not so happy!!

 Any ideas?

 -Original Message-
 From: Ken Javor [mailto:ken.ja...@emccompliance.com]
 Sent: Saturday, July 26, 2003 4:19 PM
 To: Charles Grasso; Emc-Pstc
 Subject: Re: Q on Correlation of Votage ripple with a Spectrum Analyser


 I presented a paper on that very subject about a decade ago at one of the
 EMC TD magazine EMC symposia.  I used a Fluke Scopemeter and some FFT
 software that came with it.  The Fluke interfaced to the PC through an
 optically isolated RS-232 protocol.  It worked quite well from a
 pre-compliance or troubleshooting point-of-view.  You could use time
 windowing to separate the signals deriving from leading and falling edges
 from the signals deriving from the pulse itself.  I used LISNMATE and
 LISNMARK mode separation devices to show that the rising/falling edge
 signals were common mode, while the pulse itself generated differential
mode
 signals.

  From: Charles Grasso cgrassospri...@earthlink.net
  Reply-To: Charles Grasso cgrassospri...@earthlink.net
  Date: Sat, 26 Jul 2003 16:18:36 -0700
  To: Emc-Pstc emc-p...@ieee.org
  Subject: Q on Correlation of Votage ripple with a Spectrum Analyser
 
 
  Hi All,
 
 
  Has anyone tried correlating the voltage ripple
  as seen on a scope with the amplitudes measured
  on a Spectrum Analyser?
 
  I tried doing that the other day with ..umm. minimal
  success. I think that due to the comples convoltions
  that would have to occur when FFT'ing an irregular
  voltage shape.
 
  Charles Grasso
  Echostar Communications.
 
  ---
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Re: Q on Correlation of Votage ripple with a Spectrum Analyser

2003-07-27 Thread istvan novak

Charles,

Instead of using the 1GHz single-ended scope probe, have you tried to
connect the same coax cable that you made with the seriers 50 ohms for the
SA to connect to the scope?  With a 50-ohm input impedance setting on the
scope, the loading of the planes would be exactly the same.

As I mentioned earlier, we checked many scope probes, from Tektronix,
Agilent, LeCroy, including some of the new 4-6GHz bandwidth single-ended and
differential probes.  They all pick up more or less noise from the
environment, and not necessarily through the input connection pins or wires.
You can take your scope probe, with its input pins open or shorted, and take
the infinite persistance scope reading, while you move the probe close to a
high-power, high-speed computer board (no connection, just put the probe an
inch close).  Or, just simply take a desktop light with a transformer in its
base, and flip the switch a few times.  You will be amased how much noise
these probes can pick up through the unshielded (or poorly shielded)
front-end amplifier and through the cable connecting to the scope.

Best regards,
Istvan



From: Charles Grasso cgrassospri...@earthlink.net
To: Ken Javor ken.ja...@emccompliance.com; istvan novak
istvan.no...@worldnet.att.net; Emc-Pstc emc-p...@ieee.org
Sent: Sunday, July 27, 2003 4:26 PM
Subject: RE: Q on Correlation of Votage ripple with a Spectrum Analyser



 This is getting pretty intense for a Sunday!!
 Both Mr. Javor and Mr Novak make excellent
 observations. Both center on the method of measurment
 as a point of concern.

 To measure the voltage ripple I used a high
 badwidth (1GHz) sigle ended probe with very
 short leads. In order to establish the error
 margin, I used the null experiment technique.
 (I don't have a diff probe with sufficient
 bandwidth to hand).

 I then used a piece of coax with very short
 leads (just like Mr Javor recommends)
 and a 50ohm resistor in series with the
 signal to feed the same voltage ripple to
 a SA. Clearly there is a voltage division here
 but thats easily accounted for. My concern is that
 the impedance of the planes is so much lower
 than the 50ohm input of the SA and I wanted
 to match that as much as possible.

 I belive I have taken care of as much of the
 measurement problem as possible.

 Still, the maximum voltages between the two
 measurments do not come close at all.




 -Original Message-
 From: owner-emc-p...@majordomo.ieee.org
 [mailto:owner-emc-p...@majordomo.ieee.org]On Behalf Of Ken Javor
 Sent: Sunday, July 27, 2003 10:27 AM
 To: istvan novak; Charles Grasso; Emc-Pstc
 Subject: Re: Q on Correlation of Votage ripple with a Spectrum Analyser



 Mr. Novak makes some excellent points.  I was under the assumption that
the
 phrase voltage ripple implied conducted emission measurements at a LISN
 port.  Hence my comments on mode separation.  Across a spectrum of even 30
 MHz, any normal scope probe I know of (1 or 10 M Ohm in parallel with
 5/10/20 pF) will present a varying load to the measured waveform.   I know
 there are some broadband active differential probes with low shunt
capacity,
 but I have no experience using them.  The scope should be made to look
like
 a flat 50 Ohm load to help correlate to a spectrum analyzer.  Instead of
 using long leads to make measurements from one point of the Vcc plane to
 another, I would make coaxial measurements from one point on the Vcc plane
 to chassis ground or the reference/image plane if one exists, and then
make
 the same measurement at another point on the Vcc plane, and compare the
 waveforms, perhaps using a built-in math function if your scope has
that.
 Of course this technique requires the reference/image plane/chassis ground
 to be an equipotential plane...

 By coaxial measurement I mean using coax rather than a scope probe, and
 terminating the shield at the reference point, while extending the center
 conductor just far enough to connect to the point of interest on the Vcc
 plane.  Theoretically, an even better technique would be to have a place
on
 the board where the power plane reference was available circumferentially
 around a Vcc via, and connect the coax shield to the reference plane and
the
 center conductor to the Vcc contact.  Given a 50 Ohm load at the other end
 (with a blocking cap to protect it), and an FFT capability with enough
 memory, I believe you could achieve correlation with the individual
spectral
 components measured by a spectrum analyzer (which of course would also
need
 a blocking cap with this config).


  From: istvan novak istvan.no...@worldnet.att.net
  Date: Sun, 27 Jul 2003 11:02:02 -0400
  To: Charles Grasso cgrassospri...@earthlink.net, Ken Javor
  ken.ja...@emccompliance.com, Emc-Pstc emc-p...@ieee.org
  Subject: Re: Q on Correlation of Votage ripple with a Spectrum Analyser
 
  Charles,
 
  Doing this kind of correlation is very difficult for the following
 reasons:
  - unless you measure a very simple and dummy system, hardware

magnetic field measuring instruments and probes

2002-06-20 Thread Istvan Novak
Hi list members,

Could someone suggest or refer me to pointers/manufacturers of probes and 
instruments to measure magnetic close field in the 10kHz to 10MHz frequency 
range?  High accuracy is not important, values to be measured would be around 
0.5mT and up.

Thanks

Istvan Novak
SUN Microsystems