Re: EMC Circuit Board Design

[Robert Macy]

Thank you.

Good point about current.

It's amazing that the same people that would *never* attach a 1 inch wire
(sticking up into space) to the clock signal would allow a 1 inch long slot
that has over 30mA of current flowing around it -- when they're equivalent
radiators.

   - Robert -


-Original Message-
From: cetest 
To: Robert Macy ; rehel...@mmm.com ;
emc-p...@majordomo.ieee.org 
List-Post: emc-pstc@listserv.ieee.org
Date: Monday, January 24, 2000 12:34 PM
Subject: RE: EMC Circuit Board Design


>Very good contribution Robert,
>
>One enhancement to point  7:
>
>It's the current edge that you want to reduce in speed, not the voltage
edge
>!!!
>
>This is something very generic in EMC: Look at the current, not the voltage
>!!
>
>Regards,
>
>Gert Gremmen
>
>ce-test, qualified testing
>



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RE: EMC Circuit Board Design

[cetest]

Very good contribution Robert,

One enhancement to point  7:

It's the current edge that you want to reduce in speed, not the voltage edge
!!!

This is something very generic in EMC: Look at the current, not the voltage
!!

Regards,

Gert Gremmen

ce-test, qualified testing

>-Original Message-
>From: owner-emc-p...@ieee.org [mailto:owner-emc-p...@ieee.org]On Behalf
>Of Robert Macy
>Sent: Sunday, January 23, 2000 8:42 PM
>To: rehel...@mmm.com; emc-p...@majordomo.ieee.org
>Subject: Re: EMC Circuit Board Design
>
>
>
>Here are a set of rules worth recommending:
>
>Engineering design checks:
>1  Avoid "spaghetti logic" block diagram.  Make certain there's a good flow
>of functionality across and around the PCB.  This includes using
>the concept
>of transferring INFORMATION not ENERGY (except where one must, like with
>clock distribution, but even then, if the clock goes a long way, use a
>buffer)
>2  ABSOLUTELY check the design for bus "contention".  Not the debilitating
>kind that stops the functionality, but that pesky little 1 nS of overlap
>from sloppy digital design.  It's like using two make-before-break switches
>for a 3 way light bulb in your home.  It will all work, but you will get
>some dramatic action at each transition.
>
>PCB Layout:
>1  Go on and off the board along one edge as close together as possible.
>*IF* a connection must come on or off from some where else make it a high
>common mode impedance connection with beads (for dc leads) and common mode
>chokes for higher frequency signals.  On the PCB reference the trace(s) to
>CHASSIS gnd area where the traces have been isolated by going through high
>impedances. Bridge between chassis referenced area to PCB gnd referenced
>area using the high impedance component.
>2  Interleave PWR GND and SIGNAL GND traces at the connectors to
>lower their
>impedances.  Particularly high speed lines need their own gnd returns.
>3  Use short runs, few "meandering" traces.
>4  Bypass caps: use all the same value, the thermal relief pads
>all the same
>dimensions.
>5  Have traces maintain good distances between edges and cutouts.  [This to
>insure a good low impedance ground return path for current.]
>6  On particularly "hot" traces include the ground return path and don't
>(unless absolutely necessary) "jump" layers.  Use 2 traces, if possible and
>if you must jump layers (like bus lines) add 2 ground vias around
>the signal
>via.
>7  Lower the rise time to minimum speeds with SERIES source terminations.
>Use a resistor 22-50 in series plus a bead if you have room.   DO NOT EVER
>LOWER THE RISE TIME OF A LOW IMPEDANCE SOURCE WITH A CAPACITOR.
>8 Keep high speed traces inside the layers, don't route them on
>the surface,
>you'll reduce the radiation by around 14 dB.
>9 Stack up the board with traces as close to the GND & VCC planes as
>possible (like 4-5 mils even for a 4, or 6 layer board)  This will
>lower the
>impedance of the trace *and* reduce crosstalk.
>10  Use minimum number of vias to prevent turning the GND & VCC planes into
>Swiss cheese.  Sometimes blind vias will help.
>11  Where the traces for the bus lines turn and jump layers, don't allow
>your PCB designer to line up all the vias with the vias so close that they
>create a cutout slot!  Stagger the vias' positions, or do
>something, to make
>certain there's room for adequate metal between each via.
>12  Discourage the use of high speed clocks such as 125MHz, 1.25GHz, etc.
>with the argument that using such high speed clocks demonstrates a
>designer's weakness because he can't make his design work with slower
>clocks.  Demand the clock frequency be no higher than 20MHz, because we all
>know how to solve those problems.  
>
>- Robert -
>
>-Original Message-
>From: rehel...@mmm.com 
>To: emc-p...@majordomo.ieee.org 
>Date: Friday, January 21, 2000 5:39 AM
>Subject: EMC Circuit Board Design
>
>
>>Dear List-Members,
>>
>>I am requesting information/opinions/etc. on the following:
>>
>>When circuit boards are designed, what are the common mistakes that the
>>circuit board designers make regarding EMC (multi-layer boards in
>>particular)?
>>
>>You can respond to me directly but I would prefer a response to
>the list as
>>I believe that the question is of interest to many on this list-server. In
>>either event I will compile the responses and resend the
>compilation later.
>>
>>Thanks for your time,
>>
>>Bob Heller
>>3M Company
>>
>
>
>
>-
>This message is comi

Re: EMC Circuit Board Design

[Robert Macy]

Here are a set of rules worth recommending:

Engineering design checks:
1  Avoid "spaghetti logic" block diagram.  Make certain there's a good flow
of functionality across and around the PCB.  This includes using the concept
of transferring INFORMATION not ENERGY (except where one must, like with
clock distribution, but even then, if the clock goes a long way, use a
buffer)
2  ABSOLUTELY check the design for bus "contention".  Not the debilitating
kind that stops the functionality, but that pesky little 1 nS of overlap
from sloppy digital design.  It's like using two make-before-break switches
for a 3 way light bulb in your home.  It will all work, but you will get
some dramatic action at each transition.

PCB Layout:
1  Go on and off the board along one edge as close together as possible.
*IF* a connection must come on or off from some where else make it a high
common mode impedance connection with beads (for dc leads) and common mode
chokes for higher frequency signals.  On the PCB reference the trace(s) to
CHASSIS gnd area where the traces have been isolated by going through high
impedances. Bridge between chassis referenced area to PCB gnd referenced
area using the high impedance component.
2  Interleave PWR GND and SIGNAL GND traces at the connectors to lower their
impedances.  Particularly high speed lines need their own gnd returns.
3  Use short runs, few "meandering" traces.
4  Bypass caps: use all the same value, the thermal relief pads all the same
dimensions.
5  Have traces maintain good distances between edges and cutouts.  [This to
insure a good low impedance ground return path for current.]
6  On particularly "hot" traces include the ground return path and don't
(unless absolutely necessary) "jump" layers.  Use 2 traces, if possible and
if you must jump layers (like bus lines) add 2 ground vias around the signal
via.
7  Lower the rise time to minimum speeds with SERIES source terminations.
Use a resistor 22-50 in series plus a bead if you have room.   DO NOT EVER
LOWER THE RISE TIME OF A LOW IMPEDANCE SOURCE WITH A CAPACITOR.
8 Keep high speed traces inside the layers, don't route them on the surface,
you'll reduce the radiation by around 14 dB.
9 Stack up the board with traces as close to the GND & VCC planes as
possible (like 4-5 mils even for a 4, or 6 layer board)  This will lower the
impedance of the trace *and* reduce crosstalk.
10  Use minimum number of vias to prevent turning the GND & VCC planes into
Swiss cheese.  Sometimes blind vias will help.
11  Where the traces for the bus lines turn and jump layers, don't allow
your PCB designer to line up all the vias with the vias so close that they
create a cutout slot!  Stagger the vias' positions, or do something, to make
certain there's room for adequate metal between each via.
12  Discourage the use of high speed clocks such as 125MHz, 1.25GHz, etc.
with the argument that using such high speed clocks demonstrates a
designer's weakness because he can't make his design work with slower
clocks.  Demand the clock frequency be no higher than 20MHz, because we all
know how to solve those problems.  

- Robert -

-Original Message-
From: rehel...@mmm.com 
To: emc-p...@majordomo.ieee.org 
List-Post: emc-pstc@listserv.ieee.org
Date: Friday, January 21, 2000 5:39 AM
Subject: EMC Circuit Board Design


>Dear List-Members,
>
>I am requesting information/opinions/etc. on the following:
>
>When circuit boards are designed, what are the common mistakes that the
>circuit board designers make regarding EMC (multi-layer boards in
>particular)?
>
>You can respond to me directly but I would prefer a response to the list as
>I believe that the question is of interest to many on this list-server. In
>either event I will compile the responses and resend the compilation later.
>
>Thanks for your time,
>
>Bob Heller
>3M Company
>



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RE: RE: EMC Circuit Board Design

[cetest]

The first thing I do when encountering board with
too high emissions (small band) at an impair
multitude of the metal box oscillator, is adding
a resistor (chip) in series with it's output.
Depending of the load this may vary form
22 - 150 Ohms. This alone helps often
to bring a board in compliance.

Any standard buffer will do the same.

You know, if any metal can oscillator manufacturer
wants to stand out to it's competitors, he has the
rise time of it's output signal as most important
parameter. Low rise time means high short circuit current.
During each edge of the square wave this full value
of short circuit current is allowed to flow, as the load
is mainly capacitive. This is especially relevant on
multi-layer boards where wiring has almost no inductance.

>-Original Message-
>From: owner-emc-p...@ieee.org [mailto:owner-emc-p...@ieee.org]On Behalf
>Of Allen Tudor
>Sent: Friday, January 21, 2000 5:38 PM
>To: cet...@cetest.nl; emc-p...@majordomo.ieee.org; rehel...@mmm.com
>Subject: Re: RE: EMC Circuit Board Design
>
>
>
>What do you recommend  other than metal can oscillators in item 5 below?
>
>Allen Tudor, Compliance Engineer
>PairGain Technologies  tel:  (919)875-3382
>6531 Meridien Drive fax: (919)876-1817
>Raleigh, NC  27616   email:
>allen_tu...@pairgain.com
>
>
>>>> "cetest"  01/21 9:50 AM >>>
>
>The most common mistakes carried out on PCB are:
>
>
>1 Use 2-layer instead of multi-layer boards
>2 Permit high F clocks to go trough long traces (> 4 Mhz)
>3 Place connectors all over the surface instead of corner or edge
>4 Let input and out lines of analog and power circuits run
>unfiltered to the
>cable
>5 Use metal can oscillators (too high current drive)
>6 Empty copper-fill grounded through thin traces (copper fill is of no use
>to emi)
>7 Create 2 different ground planes that will compete for "real emc ground".
>8
>
>
>Regards,
>
>Gert Gremmen
>
>ce-test qualified testing
>
>==
>http://www.cetest.nl
>Do you know our
>CE/E mark True type Font ?
>http://www.cetest.nl/cettf.htm
>==
>
>
>
>
>
>
>>-Original Message-
>>From: owner-emc-p...@ieee.org [mailto:owner-emc-p...@ieee.org]On Behalf
>>Of rehel...@mmm.com
>>Sent: Friday, January 21, 2000 1:48 PM
>>To: emc-p...@majordomo.ieee.org
>>Subject: EMC Circuit Board Design
>>
>>
>>
>>
>>
>>Dear List-Members,
>>
>>I am requesting information/opinions/etc. on the following:
>>
>>When circuit boards are designed, what are the common mistakes that the
>>circuit board designers make regarding EMC (multi-layer boards in
>>particular)?
>>
>>You can respond to me directly but I would prefer a response to
>the list as
>>I believe that the question is of interest to many on this list-server. In
>>either event I will compile the responses and resend the
>compilation later.
>>
>>Thanks for your time,
>>
>>Bob Heller
>>3M Company
>>
>>
>>
>>-
>>This message is coming from the emc-pstc discussion list.
>>To cancel your subscription, send mail to majord...@ieee.org
>>with the single line: "unsubscribe emc-pstc" (without the
>>quotes).  For help, send mail to ed.pr...@cubic.com,
>>jim_bac...@monarch.com, ri...@sdd.hp.com, or
>>roger.volgst...@compaq.com (the list administrators).
>>
>>
>
>
>
>-
>This message is coming from the emc-pstc discussion list.
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>with the single line: "unsubscribe emc-pstc" (without the
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>
>
>
>
>-
>This message is coming from the emc-pstc discussion list.
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>with the single line: "unsubscribe emc-pstc" (without the
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>jim_bac...@monarch.com, ri...@sdd.hp.com, or
>roger.volgst...@compaq.com (the list administrators).
>
>



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RE: EMC Circuit Board Design

[Barry Ma]

Yes, what Earl Morse said is very important! Always keep in mind we have to 
carefully take care of BOTH signal trace and return path. If the reference plan 
is solid, the return path would automatically make it's way to form a least 
loop area with signal trace. (Why? least loop area -> least inductance -> least 
impedance in RF). 

Barry Ma
Anritsu
b...@anritsu.com
---
On Fri, 21 January 2000, "Morse, Earl" wrote:

> The number one problem with PCB board routing that we encounter that can be
> attributed to the layout personnel is:
> 
> Routing high speed signal traces without regard for return current paths.
> 
> Either the signals are routed across splits in the reference plane or the
> signal switches layers and the new reference plane doesn't have a good path
> to the old plane.  Both problems result in higher emissions and poor signal
> integrity.
> 
> Earl Morse
> Portable Division EMC Design
> Compaq Computer Corporation
> Phone:  281.927.3607
> Pager:  713.717.0824
> Fax:  281.927.3654
> Email:  earl.mo...@compaq.com  
> 
> Emissions Control Laboratory
> 10320 Rodgers Road, EC106
> Houston, TX  77070
> 
> 
> -Original Message-
> From:rehel...@mmm.com [mailto:rehel...@mmm.com]
> Sent:Friday, January 21, 2000 6:48 AM
> To:emc-p...@majordomo.ieee.org
> Subject:EMC Circuit Board Design
> 
> Dear List-Members,
> 
> I am requesting information/opinions/etc. on the following:
> 
> When circuit boards are designed, what are the common mistakes that the
> circuit board designers make regarding EMC (multi-layer boards in particular)?
> 
> You can respond to me directly but I would prefer a response to the list as
> I believe that the question is of interest to many on this list-server. In
> either event I will compile the responses and resend the compilation later.
> 
> Thanks for your time,
> 
> Bob Heller
> 3M Company


__

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Re: RE: EMC Circuit Board Design

[Wolfgang Josenhans]

We design oscillators out of discrete components to meet the minimum drive
requirements.

 If a can oscillator is used, RC terminations and power filtering is usually
required to keep the harmonics from flowing into other ciruits.

Regards,

Wolf Josenhans




"Allen Tudor"  on 01/21/2000 10:38:09 AM

Please respond to "Allen Tudor" 

Sent by:  "Allen Tudor" 


To:   cet...@cetest.nl, emc-p...@majordomo.ieee.org, rehel...@mmm.com
cc:(Wolfgang Josenhans/MW/US/3Com)
Subject:  Re: RE: EMC Circuit Board Design




What do you recommend  other than metal can oscillators in item 5 below?

Allen Tudor, Compliance Engineer
PairGain Technologies  tel:  (919)875-3382
6531 Meridien Drive fax: (919)876-1817
Raleigh, NC  27616   email:  allen_tu...@pairgain.com


>>> "cetest"  01/21 9:50 AM >>>

The most common mistakes carried out on PCB are:


1 Use 2-layer instead of multi-layer boards
2 Permit high F clocks to go trough long traces (> 4 Mhz)
3 Place connectors all over the surface instead of corner or edge
4 Let input and out lines of analog and power circuits run unfiltered to the
cable
5 Use metal can oscillators (too high current drive)
6 Empty copper-fill grounded through thin traces (copper fill is of no use
to emi)
7 Create 2 different ground planes that will compete for "real emc ground".
8


Regards,

Gert Gremmen

ce-test qualified testing

==
http://www.cetest.nl
Do you know our
CE/E mark True type Font ?
http://www.cetest.nl/cettf.htm
==






>-Original Message-
>From: owner-emc-p...@ieee.org [mailto:owner-emc-p...@ieee.org]On Behalf
>Of rehel...@mmm.com
>Sent: Friday, January 21, 2000 1:48 PM
>To: emc-p...@majordomo.ieee.org
>Subject: EMC Circuit Board Design
>
>
>
>
>
>Dear List-Members,
>
>I am requesting information/opinions/etc. on the following:
>
>When circuit boards are designed, what are the common mistakes that the
>circuit board designers make regarding EMC (multi-layer boards in
>particular)?
>
>You can respond to me directly but I would prefer a response to the list as
>I believe that the question is of interest to many on this list-server. In
>either event I will compile the responses and resend the compilation later.
>
>Thanks for your time,
>
>Bob Heller
>3M Company
>
>
>
>-
>This message is coming from the emc-pstc discussion list.
>To cancel your subscription, send mail to majord...@ieee.org
>with the single line: "unsubscribe emc-pstc" (without the
>quotes).  For help, send mail to ed.pr...@cubic.com,
>jim_bac...@monarch.com, ri...@sdd.hp.com, or
>roger.volgst...@compaq.com (the list administrators).
>
>



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RE: EMC Circuit Board Design

[Morse, Earl]

The number one problem with PCB board routing that we encounter that can be
attributed to the layout personnel is:

Routing high speed signal traces without regard for return current paths.

Either the signals are routed across splits in the reference plane or the
signal switches layers and the new reference plane doesn't have a good path
to the old plane.  Both problems result in higher emissions and poor signal
integrity.

Earl Morse
Portable Division EMC Design
Compaq Computer Corporation
Phone:  281.927.3607
Pager:  713.717.0824
Fax:  281.927.3654
Email:  earl.mo...@compaq.com  

Emissions Control Laboratory
10320 Rodgers Road, EC106
Houston, TX  77070


-Original Message-
From:   rehel...@mmm.com [mailto:rehel...@mmm.com]
Sent:   Friday, January 21, 2000 6:48 AM
To: emc-p...@majordomo.ieee.org
Subject:EMC Circuit Board Design




Dear List-Members,

I am requesting information/opinions/etc. on the following:

When circuit boards are designed, what are the common
mistakes that the
circuit board designers make regarding EMC (multi-layer
boards in
particular)?

You can respond to me directly but I would prefer a response
to the list as
I believe that the question is of interest to many on this
list-server. In
either event I will compile the responses and resend the
compilation later.

Thanks for your time,

Bob Heller
3M Company



-
This message is coming from the emc-pstc discussion list.
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Re: RE: EMC Circuit Board Design

[Allen Tudor]

What do you recommend  other than metal can oscillators in item 5 below?

Allen Tudor, Compliance Engineer
PairGain Technologies  tel:  (919)875-3382
6531 Meridien Drive fax: (919)876-1817
Raleigh, NC  27616   email:  allen_tu...@pairgain.com


>>> "cetest"  01/21 9:50 AM >>>

The most common mistakes carried out on PCB are:


1 Use 2-layer instead of multi-layer boards
2 Permit high F clocks to go trough long traces (> 4 Mhz)
3 Place connectors all over the surface instead of corner or edge
4 Let input and out lines of analog and power circuits run unfiltered to the
cable
5 Use metal can oscillators (too high current drive)
6 Empty copper-fill grounded through thin traces (copper fill is of no use
to emi)
7 Create 2 different ground planes that will compete for "real emc ground".
8


Regards,

Gert Gremmen

ce-test qualified testing

==
http://www.cetest.nl 
Do you know our
CE/E mark True type Font ?
http://www.cetest.nl/cettf.htm 
==






>-Original Message-
>From: owner-emc-p...@ieee.org [mailto:owner-emc-p...@ieee.org]On Behalf
>Of rehel...@mmm.com 
>Sent: Friday, January 21, 2000 1:48 PM
>To: emc-p...@majordomo.ieee.org 
>Subject: EMC Circuit Board Design
>
>
>
>
>
>Dear List-Members,
>
>I am requesting information/opinions/etc. on the following:
>
>When circuit boards are designed, what are the common mistakes that the
>circuit board designers make regarding EMC (multi-layer boards in
>particular)?
>
>You can respond to me directly but I would prefer a response to the list as
>I believe that the question is of interest to many on this list-server. In
>either event I will compile the responses and resend the compilation later.
>
>Thanks for your time,
>
>Bob Heller
>3M Company
>
>
>
>-
>This message is coming from the emc-pstc discussion list.
>To cancel your subscription, send mail to majord...@ieee.org 
>with the single line: "unsubscribe emc-pstc" (without the
>quotes).  For help, send mail to ed.pr...@cubic.com,
>jim_bac...@monarch.com, ri...@sdd.hp.com, or
>roger.volgst...@compaq.com (the list administrators).
>
>



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RE: EMC Circuit Board Design

[Flinders, Randall]

Just a side note that Mr. Montrose will be speaking at the Feb. 10th meeting of 
the Orange County Chapter of the IEEE EMC Society.  If you would like to attend 
the presentation, contact me at the number shown below.

Regards,


Randy Flinders
Chairman
Orange County Chapter
IEEE EMC Society
r.flind...@ieee.org
(714) 513-8012
(714) 513-8265 Fax

Note: The opinions expressed herein are personal and in no way represent the 
position of the IEEE, The EMC Society, or my employer.

-Original Message-
From: owner-emc-p...@ieee.org [mailto:owner-emc-p...@ieee.org]On Behalf
Of teck...@apcc.com
Sent: Friday, January 21, 2000 6:28 AM
To: rehel...@mmm.com
Cc: emc-p...@majordomo.ieee.org
Subject: Re: EMC Circuit Board Design



There are a number of good books available on the subject.  There are two
that I would recommend to start with.

Printed Circuit Board Design Techniques for EMC Compliance
Mark I. Montrose
IEEE Press
ISBN 0-7803-1131-0
IEEE Order Number PC5595

Noise Reduction Techniques in Electronic Systems
Henry W. Ott
John Wiley and Sons
ISBN 0-471-85068-3

The first book is a very good reference on PCB design.  It covers most
aspects of design for EMC compliance including layer stack-up, grounding,
decoupling, clock circuits and ESD.

The second book concentrates more on system design.  It has some
information on circuit board layout, but it does not concentrate on the
subject.  It does give a good description of emissions and susceptibility
issues.  If you are looking to gain a good understanding of the basics of
electrical noise, this is the book to start with.

Ted Eckert
Regulatory Compliance Engineer
American Power Conversion Corporation
teck...@apcc.com

The items contained in this e-mail reflect the personal opinions of the
writer and are only provided for the assistance of the reader.  The writer
is not speaking in an official capacity for APC nor representing APC$B!G(Bs
official position on any matter.



Please respond to rehel...@mmm.com

To:   emc-p...@majordomo.ieee.org
cc:(bcc: Ted Eckert/SDD/NAM/APCC)
From: rehel...@mmm.com on 01/21/2000 06:47 AM
Subject:  EMC Circuit Board Design



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RE: EMC Circuit Board Design

[cetest]

The most common mistakes carried out on PCB are:


1 Use 2-layer instead of multi-layer boards
2 Permit high F clocks to go trough long traces (> 4 Mhz)
3 Place connectors all over the surface instead of corner or edge
4 Let input and out lines of analog and power circuits run unfiltered to the
cable
5 Use metal can oscillators (too high current drive)
6 Empty copper-fill grounded through thin traces (copper fill is of no use
to emi)
7 Create 2 different ground planes that will compete for "real emc ground".
8


Regards,

Gert Gremmen

ce-test qualified testing

==
http://www.cetest.nl
Do you know our
CE/E mark True type Font ?
http://www.cetest.nl/cettf.htm
==






>-Original Message-
>From: owner-emc-p...@ieee.org [mailto:owner-emc-p...@ieee.org]On Behalf
>Of rehel...@mmm.com
>Sent: Friday, January 21, 2000 1:48 PM
>To: emc-p...@majordomo.ieee.org
>Subject: EMC Circuit Board Design
>
>
>
>
>
>Dear List-Members,
>
>I am requesting information/opinions/etc. on the following:
>
>When circuit boards are designed, what are the common mistakes that the
>circuit board designers make regarding EMC (multi-layer boards in
>particular)?
>
>You can respond to me directly but I would prefer a response to the list as
>I believe that the question is of interest to many on this list-server. In
>either event I will compile the responses and resend the compilation later.
>
>Thanks for your time,
>
>Bob Heller
>3M Company
>
>
>
>-
>This message is coming from the emc-pstc discussion list.
>To cancel your subscription, send mail to majord...@ieee.org
>with the single line: "unsubscribe emc-pstc" (without the
>quotes).  For help, send mail to ed.pr...@cubic.com,
>jim_bac...@monarch.com, ri...@sdd.hp.com, or
>roger.volgst...@compaq.com (the list administrators).
>
>



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roger.volgst...@compaq.com (the list administrators).

Re: EMC Circuit Board Design

[teckert]

There are a number of good books available on the subject.  There are two
that I would recommend to start with.

Printed Circuit Board Design Techniques for EMC Compliance
Mark I. Montrose
IEEE Press
ISBN 0-7803-1131-0
IEEE Order Number PC5595

Noise Reduction Techniques in Electronic Systems
Henry W. Ott
John Wiley and Sons
ISBN 0-471-85068-3

The first book is a very good reference on PCB design.  It covers most
aspects of design for EMC compliance including layer stack-up, grounding,
decoupling, clock circuits and ESD.

The second book concentrates more on system design.  It has some
information on circuit board layout, but it does not concentrate on the
subject.  It does give a good description of emissions and susceptibility
issues.  If you are looking to gain a good understanding of the basics of
electrical noise, this is the book to start with.

Ted Eckert
Regulatory Compliance Engineer
American Power Conversion Corporation
teck...@apcc.com

The items contained in this e-mail reflect the personal opinions of the
writer and are only provided for the assistance of the reader.  The writer
is not speaking in an official capacity for APC nor representing APC’s
official position on any matter.



Please respond to rehel...@mmm.com

To:   emc-p...@majordomo.ieee.org
cc:(bcc: Ted Eckert/SDD/NAM/APCC)
From: rehel...@mmm.com on 01/21/2000 06:47 AM
Subject:  EMC Circuit Board Design






Dear List-Members,

I am requesting information/opinions/etc. on the following:

When circuit boards are designed, what are the common mistakes that the
circuit board designers make regarding EMC (multi-layer boards in
particular)?

You can respond to me directly but I would prefer a response to the list as
I believe that the question is of interest to many on this list-server. In
either event I will compile the responses and resend the compilation later.

Thanks for your time,

Bob Heller
3M Company



-
This message is coming from the emc-pstc discussion list.
To cancel your subscription, send mail to majord...@ieee.org
with the single line: "unsubscribe emc-pstc" (without the
quotes).  For help, send mail to ed.pr...@cubic.com,
jim_bac...@monarch.com, ri...@sdd.hp.com, or
roger.volgst...@compaq.com (the list administrators).

RE: EMC Circuit Board Design

[WOODS]

Most of the mistakes are by the design engineers and not the pcb designers.
The mistakes are:

*   Mixing of I/O devices with clocks, processors and similar noisy
digital devices
*   Inadequate power/ground isolation of noisy digital devices
*   Inadequate I/O filtering
*   Failure to shunt ESD and EFT on I/O lines to chassis ground (not
digital ground)
*   High impedance ground traces (too narrow and/or too long)
*   Connecting I/O shields to the pcb and not to the chassis
*   Inadequate physical isolation of power line filters from noisy
circuits and traces

Richard Woods

--
From:  rehel...@mmm.com [SMTP:rehel...@mmm.com]
Sent:  Friday, January 21, 2000 7:48 AM
To:  emc-p...@majordomo.ieee.org
Subject:  EMC Circuit Board Design




Dear List-Members,

I am requesting information/opinions/etc. on the following:

When circuit boards are designed, what are the common mistakes that
the
circuit board designers make regarding EMC (multi-layer boards in
particular)?

You can respond to me directly but I would prefer a response to the
list as
I believe that the question is of interest to many on this
list-server. In
either event I will compile the responses and resend the compilation
later.

Thanks for your time,

Bob Heller
3M Company



-
This message is coming from the emc-pstc discussion list.
To cancel your subscription, send mail to majord...@ieee.org
with the single line: "unsubscribe emc-pstc" (without the
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jim_bac...@monarch.com, ri...@sdd.hp.com, or
roger.volgst...@compaq.com (the list administrators).


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