Re: [Bug c++/47791] finish function is using literal value instead of a #defined one
Hello Everyone,
Here is a patch to fix this bug. Please let me know if it is OK for
me to commit this into trunk.
Here is the Changelog entry:
===
2012-01-28 Balaji V. Iyer bvi...@gmail.com
* optimize.c (maybe_clone_body): Replace '0' in finish_function
parameter with FF_DEFAULT.
* decl.c (end_cleanup_fn): Likewise.
* method.c (synthesize_method): Likewise.
* pt.c (instantiate_decl): Likewise.
* decl2.c (finish_objects): Likewise.
(finish_static_storage_duration_function): Likewise.
* parser.c (cp_parser_lambda_body): Replaced all occurances of '0', '1',
and '2' in finish_function parameters with FF_DEFAULT,
FF_PRE_PARSED, and FF_INCLASS_INLINE, respectively.
* semantics.c (maybe_add_lambda_conv_op): Replaced '2' in
finish_function with FF_INCLASS_INLINE.
* cp-tree.h: Added FF_DEFAULT, FF_PRE_PARSED and FF_INCLASS_INLINE.
Thanks,
Balaji V. Iyer.
On Sat, Jan 28, 2012 at 12:56 AM, pinskia at gcc dot gnu.org
gcc-bugzi...@gcc.gnu.org wrote:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47791
Andrew Pinski pinskia at gcc dot gnu.org changed:
What |Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed| |2012-01-28
Summary|finish function is using |finish function is using
|absolute value instead of |literal value instead of a
|the #defined one |#defined one
Ever Confirmed|0 |1
--- Comment #2 from Andrew Pinski pinskia at gcc dot gnu.org 2012-01-28
05:56:07 UTC ---
Confirmed,
--
Configure bugmail: http://gcc.gnu.org/bugzilla/userprefs.cgi?tab=email
--- You are receiving this mail because: ---
You reported the bug.
Index: cp/optimize.c
===
--- cp/optimize.c (revision 183668)
+++ cp/optimize.c (working copy)
@@ -415,7 +415,7 @@
cp_function_chain-can_throw = !TREE_NOTHROW (fn);
/* Now, expand this function into RTL, if appropriate. */
- finish_function (0);
+ finish_function (FF_DEFAULT);
BLOCK_ABSTRACT_ORIGIN (DECL_INITIAL (clone)) = DECL_INITIAL (fn);
if (alias)
{
Index: cp/decl.c
===
--- cp/decl.c (revision 183668)
+++ cp/decl.c (working copy)
@@ -6592,7 +6592,7 @@
static void
end_cleanup_fn (void)
{
- expand_or_defer_fn (finish_function (0));
+ expand_or_defer_fn (finish_function (FF_DEFAULT));
pop_from_top_level ();
}
Index: cp/method.c
===
--- cp/method.c (revision 183668)
+++ cp/method.c (working copy)
@@ -771,7 +771,7 @@
}
finish_function_body (stmt);
- expand_or_defer_fn (finish_function (0));
+ expand_or_defer_fn (finish_function (FF_DEFAULT));
input_location = save_input_location;
Index: cp/pt.c
===
--- cp/pt.c (revision 183668)
+++ cp/pt.c (working copy)
@@ -18750,7 +18750,7 @@
local_specializations = saved_local_specializations;
/* Finish the function. */
- d = finish_function (0);
+ d = finish_function (FF_DEFAULT);
expand_or_defer_fn (d);
}
Index: cp/semantics.c
===
--- cp/semantics.c (revision 183668)
+++ cp/semantics.c (working copy)
@@ -9332,7 +9332,7 @@
finish_compound_stmt (compound_stmt);
finish_function_body (body);
- expand_or_defer_fn (finish_function (2));
+ expand_or_defer_fn (finish_function (SF_INCLASS_INLINE));
/* Generate the body of the conversion op. */
@@ -9346,7 +9346,7 @@
finish_compound_stmt (compound_stmt);
finish_function_body (body);
- expand_or_defer_fn (finish_function (2));
+ expand_or_defer_fn (finish_function (FF_INCLASS_INLINE));
if (nested)
pop_function_context ();
Index: cp/decl2.c
===
--- cp/decl2.c (revision 183668)
+++ cp/decl2.c (working copy)
@@ -2833,7 +2833,7 @@
/* Finish up. */
finish_compound_stmt (body);
- fn = finish_function (0);
+ fn = finish_function (FF_DEFAULT);
if (method_type == 'I')
{
@@ -2975,7 +2975,7 @@
{
/* Close out the function. */
finish_compound_stmt (body);
- expand_or_defer_fn (finish_function (0));
+ expand_or_defer_fn (finish_function (FF_DEFAULT));
}
/* Return the information about the indicated PRIORITY level. If no
Index: cp/parser.c
===
--- cp/parser.c (revision
[Cilkplus] Updated Copyright year in all Cilkplus specific files
Hello Everyone, I just updated the copyright year in all the cilkplus specific files in the Cilkplus branch. I also corrected a wordwrap problem in one of the files. Here is the patch for what I updated. Thanks, Balaji V. Iyer. Index: pragma_simd.c === --- pragma_simd.c (revision 183162) +++ pragma_simd.c (working copy) @@ -1,7 +1,7 @@ /* This file is part of the Intel(R) Cilk(TM) Plus support - This file contains routines to handle PRAGMA SIMD assignments by the - vectorizer. - Copyright (C) 2011 Free Software Foundation, Inc. + This file contains routines to handle PRAGMA SIMD + assignments by the vectorizer. + Copyright (C) 2011, 2012 Free Software Foundation, Inc. Contributed by Balaji V. Iyer balaji.v.i...@intel.com, Intel Corporation Index: cp/cilk.c === --- cp/cilk.c (revision 183162) +++ cp/cilk.c (working copy) @@ -1,5 +1,5 @@ /* C++ Functions to handle Intel(R) Cilk(TM) Plus Specific functions. - Copyright (C) 2011 Free Software Foundation, Inc. + Copyright (C) 2011, 2012 Free Software Foundation, Inc. Contributed by Balaji V. Iyer balaji.v.i...@intel.com, Intel Corporation. Index: cilk.c === --- cilk.c (revision 183162) +++ cilk.c (working copy) @@ -1,6 +1,6 @@ /* This file is part of the Intel(R) Cilk(TM) Plus support This file contains the CilkPlus Intrinsics - Copyright (C) 2011 Free Software Foundation, Inc. + Copyright (C) 2011, 2012 Free Software Foundation, Inc. Contributed by Balaji V. Iyer balaji.v.i...@intel.com, Intel Corporation Index: cilk.h === --- cilk.h (revision 183162) +++ cilk.h (working copy) @@ -1,6 +1,6 @@ /* This file is part of the Intel(R) Cilk(TM) Plus support This file contains Cilk Support files. - Copyright (C) 2011 Free Software Foundation, Inc. + Copyright (C) 2011, 2012 Free Software Foundation, Inc. Contributed by Balaji V. Iyer balaji.v.i...@intel.com, Intel Corporation Index: cilk-spawn.c === --- cilk-spawn.c (revision 183162) +++ cilk-spawn.c (working copy) @@ -1,6 +1,6 @@ /* This file is part of the Intel(R) Cilk(TM) Plus support This file contains cilk functions for C language support - Copyright (C) 2011 Free Software Foundation, Inc. + Copyright (C) 2011, 2012 Free Software Foundation, Inc. Contributed by Balaji V. Iyer balaji.v.i...@intel.com, Intel Corporation
[Cilkplus] Patches about Array Notations
Hello Everyone, Here are seven patches about array notations that were submitted to GCC patches mailing list for the Cilkplus branch. If anyone finds any problems or have any objections, please let me know. Otherwise, I will check them into the Cilkplus branch Monday. Here are the patch emails: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg00691.html http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01397.html http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01398.html http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01473.html http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01581.html http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01667.html http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01698.html Thanks, Balaji V. Iyer.
RE: Code Motion after Machine Dependent Reorganization??
Hello All, I looked at FINAL_PRESCAN_INSN, and as Ian mentioned, I do not have any CFG info or the basic block pointers. I really would like to reporoduce that information at that stage. I looked at passes.c and the cfgbuild.c, and if I do thefollowing: ind_basic_blocks(get_insns()); Compute_bb_for_insn(); Will this both lines above create a valid CFG and put the appropriate basic block boundaries. Or is there a way I can find the basic block boundaries (that's all I need, nothing else) by just looking at the RTL? I am using GCC 4.0.2 Any help is highly appreciated! Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Ian Lance Taylor [mailto:i...@google.com] Sent: Tuesday, December 30, 2008 2:38 PM To: Balaji V. Iyer Cc: gcc@gcc.gnu.org Subject: Re: Code Motion after Machine Dependent Reorganization?? Balaji V. Iyer bvi...@ncsu.edu writes: Thanks for your help. What I mainly want to do is to make some hardware decisions by looking at the instructions inside a Basic block. Ths is why I was using the FOR_EACH_BB function. When and where can I intercept the RTL such that I can get the RTL that matches the output assembly equivalents? I am willing to add my own hook if necessary. If you want to look at RTL which precisely matches the output assembly, then you should use FINAL_PRESCAN_INSN. You won't get basic block markers, though. If you want to look at RTL which is pretty close to the output assembly, and for which the basic blocks are reasonably valid, then you should write a pass which runs somewhere after the second scheduling pass. Ian
Code Motion after Machine Dependent Reorganization??
Hello Everyone,
I am currently working on the OpenRISC port of GCC. There isn't much
significant backend optimization implemented, its just a straightforward
port.
Now, is it possible for the code to move between Basic blocks (or
even inside the basic blocks) after machine dependent reorganization
stage? If so, how can I stop it from happening.. or can I?
I printed out the RTL dump using the following code during the machine
dependent reorganization
FOR_EACH_BB(bb) {
for (insn = bb_head(bb); insn != bb_end(bb); insn = NEXT_INSN(insn))
{
if (INSN_P(insn))
print_rtl_single(insn);
}
}
Then I compared with the assembly output and the RTL-equivalent and they
do not come out in the same order.. A couple instructions were even
moved outside a basic-block... Am I going through the instruction chain
in the wrong way?
Any help is deeply appreciated!
Thanks,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Candidate,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
RE: Code Motion after Machine Dependent Reorganization??
I forgot to mention one important part..I am using GCC 4.0.2
Hello Everyone,
I am currently working on the OpenRISC port of GCC. There isn't much
significant backend optimization implemented, its just a straightforward
port.
Now, is it possible for the code to move between Basic blocks (or
even inside the basic blocks) after machine dependent reorganization
stage? If so, how can I stop it from happening.. or can I?
I printed out the RTL dump using the following code during the machine
dependent reorganization
FOR_EACH_BB(bb) {
for (insn = bb_head(bb); insn != bb_end(bb); insn = NEXT_INSN(insn))
{
if (INSN_P(insn))
print_rtl_single(insn);
}
}
Then I compared with the assembly output and the RTL-equivalent and they
do not come out in the same order.. A couple instructions were even
moved outside a basic-block... Am I going through the instruction chain
in the wrong way?
Any help is deeply appreciated!
Thanks,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Candidate,
Center for Efficient, Scalable and Reliable Computing, Department of
Electrical and Computer Engineering, North Carolina State University.
RE: Code Motion after Machine Dependent Reorganization??
Ian,
Thanks for your help. What I mainly want to do is to make some
hardware decisions by looking at the instructions inside a Basic block.
Ths is why I was using the FOR_EACH_BB function.
When and where can I intercept the RTL such that I can get the
RTL that matches the output assembly equivalents? I am willing to add my
own hook if necessary.
Thanks!
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Candidate,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
-Original Message-
From: Ian Lance Taylor [mailto:i...@google.com]
Sent: Tuesday, December 30, 2008 10:51 AM
To: Balaji V. Iyer
Cc: gcc@gcc.gnu.org
Subject: Re: Code Motion after Machine Dependent Reorganization??
Balaji V. Iyer bvi...@ncsu.edu writes:
I printed out the RTL dump using the following code during the machine
dependent reorganization
FOR_EACH_BB(bb) {
for (insn = bb_head(bb); insn != bb_end(bb); insn =
NEXT_INSN(insn)) {
if (INSN_P(insn))
print_rtl_single(insn);
}
}
Then I compared with the assembly output and the RTL-equivalent and
they do not come out in the same order.. A couple instructions were
even moved outside a basic-block... Am I going through the instruction
chain in the wrong way?
The CFG is not valid at the point of the machine reorg pass, mainly for
historical reasons. You can see all the insns reliably by doing
for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
Ian
Machine Dependent Reorganization Question
Hello Everyone, I have a couple questions. 1) Is the machine dependent reorganization phase occuring after or before the register allocation phase? 2) Also, is it possible for me to add my own demands (or suggestions) into the register allocator? Any help is greatly appreciated! Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
RE: Machine Dependent Reorganization Question
Thank you Ian for your quick response. This is what I want to do: I want the scheduling phase to say an RTX X must be allocated registers from Register CLASS A. So how can I tell register allocator to do this? Thanks, -Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Ian Lance Taylor [mailto:i...@google.com] Sent: Monday, December 15, 2008 4:22 PM To: Balaji V. Iyer Cc: gcc@gcc.gnu.org Subject: Re: Machine Dependent Reorganization Question Balaji V. Iyer bvi...@ncsu.edu writes: 1) Is the machine dependent reorganization phase occuring after or before the register allocation phase? After. See passes.c. 2) Also, is it possible for me to add my own demands (or suggestions) into the register allocator? It really depends on what you mean. There are command line options like -ffixed-REG. If you edit the CPU.md file you can specify register classes for particular insns. If you want to rewrite the instruction stream you can do your own register allocation by replacing some pseudo-regs with hard regs. Ian
Register Allocation Question.
Hello Everyone, I have a question regarding the register allocation steps in GCC. I am creating an hypothetical example to make things easy. My processor has 2 set of register fiels with 1-16 in Class1 and 16-32 in class 2 Let's say I have an RTL X with destination register R1, But if I want to schedule this RTL to Class2. What can I do? I see that GCC doesn't change the register number if it already holds a hard-register. Any help is highly appreciated. Please CC me in your response since I am not a subscribed member. Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
RE: GCC Eliminates my Custom RTL ..How to stop this?
Thank you for your response Andrew.
This is what I am trying to achieve. I want to indicate to my processor
at certain points of execution to do certain control behavior. I am
trying to do this by inserting a specialized instruction that will do
so.
I am not using the unspec model. I created a new RTL in rtl.def, then I
am inserting that RTL at fixed points of my code, and have a constraint
in my .md file to catch that RTL and convert it into an instruction.
Any help is highly appreciated!
Please CC me in your response since I am not subscribed to this account.
Thanks,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Candidate,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
-Original Message-
From: Andrew Haley [mailto:[EMAIL PROTECTED]
Sent: Monday, October 27, 2008 6:07 AM
To: Balaji V. Iyer
Cc: gcc@gcc.gnu.org
Subject: Re: GCC Eliminates my Custom RTL ..How to stop this?
Balaji V. Iyer wrote:
I am trying to add new RTL into the GCC 4.0.2 OpenRISC port and I
am trying to insert them into ccertain parts of the instruction
stream. For testing, I am trying to insert it in the start of every
basic block.Here is the code for what I am trying to do.
rtx newInsn = gen_rtx_MY_NEW_INSN(...); rtx bbInsn;
FOR_EACH_BB(bb) {
bbInsn = BB_HEAD(bb);
emit_insn_before(newInsn, bbInsn);
}
This code is working fine when we are having no optimization. But when
I have -O1, -O2 or -O3, the newInsn does'nt appear in every basic
block.
It looks like the optimization phases is deleting this instruction.
My question is, how can I tell GCC to never remove this instruction
(or RTL)? This instruction doesn't take any register values or write
any registers, just accepts an immediate field.
What sort of instruction is it? Are you using an UNSPEC to model some
special CPU hardware? gcc will remove instructions that don't do
anything.
Have a look at side_effects_p() in rtlanal.c.
Andrew.
GCC Eliminates my Custom RTL ..How to stop this?
Hello Everyone,
I am trying to add new RTL into the GCC 4.0.2 OpenRISC port and I am
trying to insert them into ccertain parts of the instruction stream. For
testing, I am trying to insert it in the start of every basic block.Here
is the code for what I am trying to do.
rtx newInsn = gen_rtx_MY_NEW_INSN(...);
rtx bbInsn;
FOR_EACH_BB(bb) {
bbInsn = BB_HEAD(bb);
emit_insn_before(newInsn, bbInsn);
}
This code is working fine when we are having no optimization. But when I
have -O1, -O2 or -O3, the newInsn does'nt appear in every basic block.
It looks like the optimization phases is deleting this instruction.
My question is, how can I tell GCC to never remove this instruction
(or RTL)? This instruction doesn't take any register values or write any
registers, just accepts an immediate field.
Any help is greatly appreciated!
Thanks,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Candidate,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
Inserting Custom RTLs by the Haifa Scheduler
Hello Everyone, I am currently working on OpenRISC port of GCC-4.0.2, and I have to insert a custom RTL (which gets translated to an instruction) at fixed parts of the code. I have created the custom instruction (by modifying RTL.DEF) and then put the appropritae constraints in my .md file. Now, I want this instructoin to be inserted at specific points...How can I do it? What function shiould I call to output this RTL? Any help is highly appreciated! Please CC me in the answer since I am not a subscribed member of GCC. Regards, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
Adding NEW Specialized RTL into GCC
Hello Everyone, I am trying to add a specialized RTL into GCC. The main point of this RTL is to add specialized instructions during scheduling (so there is no specific regions such as every basic block or every function beginning/end where I can predict ahead of time before scheduling to insert). So what are the steps necessary for me to acomplish this? Any help is greatly appreciated, Thanks, Balaji V. Iyer. PS. Please CC me in your response since I am not subscribed to this mailing list. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
STRIP NOPS Question
Hello Everyone, In GCC I found a MACRO called STRIP_NOPS and it is defined as the following: #define STRIP_NOPS(EXP) \ while ((TREE_CODE (EXP) == NOP_EXPR \ || TREE_CODE (EXP) == CONVERT_EXPR\ || TREE_CODE (EXP) == NON_LVALUE_EXPR)\ TREE_OPERAND (EXP, 0) != error_mark_node\ (TYPE_MODE (TREE_TYPE (EXP))\ == TYPE_MODE (TREE_TYPE (TREE_OPERAND (EXP, 0) \ (EXP) = TREE_OPERAND (EXP, 0) I am currently having a VLIW architecture and I want to put NOPs between the dependent instructions... So if I disable this #define, then will it do the trick? Can someone please explain to me ohw this works? Any help is greatly appreciated! Please CC me in your response since I am not a subscribed to this list. Yours Sincerely, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
MAX_CONSTRAINT VALUE
Hello Everyone,
I am currently working on OpenRISC port of GCC and I am trying to
add more constraints to the machine-dependent part and the default
number of constrant seem to be only 30 (and obviously I have more than
30 constraints, and thus it was failing). I tried making this a #define
value and moved this to the machine dependent part. This is advantageous
because now the backend designer has more flexibility.
Here is the patch for it (if a value is not provided, then the
default value of 30 is assumed). I tried to build this for x86 and arm
and they seem to work fine with no problems.
Here is the patch for it (I am working on GCC 4.0.2).
==
diff -Naur gcc.old/recog.c gcc.new/recog.c
--- gcc.old/recog.c 2008-04-14 19:57:58.5 -0400
+++ gcc.new/recog.c 2008-04-14 20:08:31.34375 -0400
@@ -2039,7 +2039,7 @@
= (recog_data.constraints[i][0] == '=' ? OP_OUT
: recog_data.constraints[i][0] == '+' ? OP_INOUT
: OP_IN);
-
+
gcc_assert (recog_data.n_alternatives = MAX_RECOG_ALTERNATIVES);
}
diff -Naur gcc.old/recog.h gcc.new/recog.h
--- gcc.old/recog.h 2008-04-14 19:57:58.5 -0400
+++ gcc.new/recog.h 2008-04-14 19:54:44.828125000 -0400
@@ -20,7 +20,12 @@
02111-1307, USA. */
/* Random number that should be large enough for all purposes. */
-#define MAX_RECOG_ALTERNATIVES 30
+
+#ifdef TARGET_MAX_RECOG_ALTERNATIVES
+#define MAX_RECOG_ALTERNATIVES TARGET_MAX_RECOG_ALTERNATIVES
+#else
+#define MAX_RECOG_ALTERNATIVES 30
+#endif
/* Types of operands. */
enum op_type {
diff -Naur gcc.old/target-def.h gcc.new/target-def.h
--- gcc.old/target-def.h2008-04-14 19:58:00.46875 -0400
+++ gcc.new/target-def.h2008-04-14 19:54:45.71875 -0400
@@ -187,6 +187,11 @@
#define TARGET_ASM_MARK_DECL_PRESERVED hook_void_constcharptr
#endif
+#ifndef TARGET_MAX_RECOG_ALTERNATIVES
+#define TARGET_MAX_RECOG_ALTERNATIVES 32
+#endif
+
+
#define TARGET_ASM_ALIGNED_INT_OP \
{TARGET_ASM_ALIGNED_HI_OP, \
TARGET_ASM_ALIGNED_SI_OP, \
==
Thanks,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Student,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
Help with GCC on Cygwin
Hello Everyone, I am trying to do some development on the C Compiler in Cygwin and I am doing the following to build it: $ ../gcc-4.0.2/gcc/configure --prefix=/home/Balaji/Software_Tools/install --enable-languages=c The problem i am getting is this: $ make all install TARGET_CPU_DEFAULT= \ HEADERS=auto-host.h ansidecl.h config/i386/xm-cygwin.h DEFINES= \ /bin/sh ../gcc-4.0.2/gcc/mkconfig.sh config.h TARGET_CPU_DEFAULT= \ HEADERS=config/i386/i386.h config/i386/unix.h config/i386/bsd.h config/ i386/gas.h config/dbxcoff.h config/i386/cygming.h config/i386/cygwin.h defaults. h DEFINES= \ /bin/sh ../gcc-4.0.2/gcc/mkconfig.sh tm.h TARGET_CPU_DEFAULT= \ HEADERS=auto-host.h ansidecl.h config/i386/xm-cygwin.h DEFINES= \ /bin/sh ../gcc-4.0.2/gcc/mkconfig.sh bconfig.h /home/Balaji/Software_Tools/gcc-4.0.2/compile gcc -c -g -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-protot ypes -Wold-style-definition-DHAVE_CONFIG_H -DGENERATOR_FILE -I. -Ibuild -I.. /gcc-4.0.2/gcc -I../gcc-4.0.2/gcc/build -I../gcc-4.0.2/gcc/../include -I../gcc-4 .0.2/gcc/../libcpp/include -o build/genmodes.o ../gcc-4.0.2/gcc/genmodes.c /home/Balaji/Software_Tools/gcc-4.0.2/compile gcc -c -g -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-protot ypes -Wold-style-definition-DHAVE_CONFIG_H -DGENERATOR_FILE -I. -Ibuild -I.. /gcc-4.0.2/gcc -I../gcc-4.0.2/gcc/build -I../gcc-4.0.2/gcc/../include -I../gcc-4 .0.2/gcc/../libcpp/include -o build/errors.o ../gcc-4.0.2/gcc/errors.c make: *** No rule to make target `../build-i686-pc-cygwin/libiberty/libiberty.a' , needed by `build/genmodes.exe'. Stop. I am currently using cygwin on a x86 machine, gcc version 4.0.2 (I have to use this version...can't use a diferent one), Any help is very highly appreciated! Thanking You, Yours Sincerely, Balaji V. Iyer. PS. Here is the output I received right after I ran the configur command. checking build system type... i686-pc-cygwin checking host system type... i686-pc-cygwin checking target system type... i686-pc-cygwin checking LIBRARY_PATH variable... ok checking GCC_EXEC_PREFIX variable... ok checking whether to place generated files in the source directory... no checking whether a default linker was specified... no checking whether a default assembler was specified... no checking for gcc... gcc checking for C compiler default output file name... a.exe checking whether the C compiler works... yes checking whether we are cross compiling... no checking for suffix of executables... .exe checking for suffix of object files... o checking whether we are using the GNU C compiler... yes checking whether gcc accepts -g... yes checking for gcc option to accept ANSI C... none needed checking whether gcc and cc understand -c and -o together... yes checking how to run the C preprocessor... gcc -E checking for inline... inline checking for long long int... yes checking for __int64... no checking for egrep... grep -E checking for ANSI C header files... yes checking for sys/types.h... yes checking for sys/stat.h... yes checking for stdlib.h... yes checking for string.h... yes checking for memory.h... yes checking for strings.h... yes checking for inttypes.h... yes checking for stdint.h... yes checking for unistd.h... yes checking for void *... yes checking size of void *... 4 checking for short... yes checking size of short... 2 checking for int... yes checking size of int... 4 checking for long... yes checking size of long... 4 checking for long long... yes checking size of long long... 8 checking whether gcc accepts -Wno-long-long... yes checking whether gcc accepts -Wno-variadic-macros... no checking whether gcc accepts -Wold-style-definition... yes checking valgrind.h usability... no checking valgrind.h presence... no checking for valgrind.h... no checking whether make sets $(MAKE)... yes checking for gawk... gawk checking whether ln -s works... yes checking whether ln works... yes checking for ranlib... ranlib checking for a BSD compatible install... /usr/bin/install -c checking for cmp's capabilities... gnucompare checking for mktemp... yes checking for makeinfo... makeinfo checking for modern makeinfo... yes checking for recent Pod::Man... yes checking for flex... flex checking for bison... bison checking for nm... nm checking for ar... ar checking for GNU C library... no checking for ANSI C header files... (cached) yes checking whether time.h and sys/time.h may both be included... yes checking whether string.h and strings.h may both be included... yes checking for sys/wait.h that is POSIX.1 compatible... yes checking for limits.h... yes checking for stddef.h... yes checking for string.h... (cached) yes checking for strings.h... (cached) yes checking for stdlib.h... (cached) yes checking for time.h... yes checking for iconv.h... yes checking for fcntl.h... yes checking
RE: Help with GCC on Cygwin
subdirectories: target-libmudflap target-libffi target-boehm-gc target-zlib target-libjava target-libada target-libstdc++-v3 target-libgfortran zlib fastjar target-libobjc (Any other directories should still work fine.) checking for bison... bison checking for bison... bison -y checking for gm4... no checking for gnum4... no checking for m4... m4 checking for flex... flex checking for flex... flex checking for makeinfo... makeinfo checking for i686-pc-cygwin-ar... no checking for ar... ar checking for i686-pc-cygwin-as... no checking for as... as checking for i686-pc-cygwin-dlltool... no checking for dlltool... dlltool checking for i686-pc-cygwin-ld... /usr/lib/gcc/i686-pc-cygwin/3.4.4/../../../../i686-pc-cygwin/bin/ld.exe checking for i686-pc-cygwin-nm... no checking for nm... nm checking for i686-pc-cygwin-ranlib... no checking for ranlib... ranlib checking for i686-pc-cygwin-windres... no checking for windres... windres checking for i686-pc-cygwin-objcopy... no checking for objcopy... objcopy checking for i686-pc-cygwin-objdump... no checking for objdump... objdump checking for i686-pc-cygwin-ar... no checking for ar... ar checking for i686-pc-cygwin-as... no checking for as... as checking for i686-pc-cygwin-dlltool... no checking for dlltool... dlltool checking for i686-pc-cygwin-ld... no checking for ld... ld checking for i686-pc-cygwin-nm... no checking for nm... nm checking for i686-pc-cygwin-ranlib... no checking for ranlib... ranlib checking for i686-pc-cygwin-windres... no checking for windres... windres checking whether to enable maintainer-specific portions of Makefiles... no checking if symbolic links between directories work... yes updating cache ./config.cache creating ./config.status creating Makefile Any help is highly appreciated! Yours Sincerely, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Ian Lance Taylor [mailto:[EMAIL PROTECTED] Sent: Wednesday, March 05, 2008 12:39 AM To: Balaji V. Iyer Cc: gcc@gcc.gnu.org; [EMAIL PROTECTED] Subject: Re: Help with GCC on Cygwin Balaji V. Iyer [EMAIL PROTECTED] writes: I am trying to do some development on the C Compiler in Cygwin and I am doing the following to build it: gcc@gcc.gnu.org is the wrong mailing list. Please send any further e-mail to [EMAIL PROTECTED] Thanks. $ ../gcc-4.0.2/gcc/configure Run ../gcc-4.0.2/configure, not ../gcc-4.0.2/gcc/configure. Ian
Adding extra instructions in the Ready List
Hello Everyone, I am currently working with GCC 4.0.2 (The OpenRISC port). Is it possible to add extra instructions (for example, NOPS) into the instruction ready list. Is it possible for me to do it in TARGET_MACHINE_SCHED_REORDER2? I tried to just do the following rtx new_insn = gen_nop(); Insert_Into_List(ready_list, new_insn); return *n_ready; But it is complaining sometime later in the scheduler that it is not able to find the basic block info for the new_insn (the one I inserted). Can someone please help me with this? Am I forgetting to set any extra variable? Any help is greatly appreciated! Please feel free to ask me if you need additional clarification Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
Question about Register Class Allocation
Hello Everyone, I am currently working with Gcc 4.0.2 and I have a question regarding the register allocation. I saw that regclass() function determines which class of register the registers in the current units should be assigned to. The question I have is: Will this decision change in any other parts of the compiler? or is this this the final place where they fix the register class? So, if I add my own priority-based register-class assigner, can I just replace this function and add my own? Any help is very very much appreciated. Please feel free to contact me if you need any additional clarification. Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
Help with GCC RTL and Register Allocator
Hello Everyone, I have a question regarding GCC RTL. I am currently modifying the OpenRISC backend to partition the register files. Here is an example of my add function: (define_insn addsi3 [(set (match_operand:SI 0 register_operand =a,b,a,b) (plus:SI (match_operand:SI 1 register_operand %a,b,a,b) (match_operand:SI 2 nonmemory_operand a,b,I,I)))] @ l.add \t%0,%1,%2 l.add \t%0,%1,%2 l.addi \t%0,%1,%2 l.addi \t%0,%1,%2 [(set_attr type add,add,add,add) (set_attr length 1,1,1,1)]) TO explain my variables: a = Register number between 0-31 b = Register number between 32-63 I = Integer value The question I have is this: How can I tell the register allocator (more like convey the message from the scheduler) to schedule the instructions in a certain cluster of my choice? I have another data structure that indicates which register file the instruction must be scheduled in and I want the register allocator to read this and make the choice about the appropriate alternative, not pick the first one from the different alternatives. Any help is highly appreciated. Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
UNIQUE ID (INSN UID) Question
Hello Everyone, I have a quick question regarding instruction unique ID in the RTL. Is this number unique for the function? or is it unique for the entire program that it is compiling? I would like to mark instructions and identify them, so can I use this value as a unique identifier for program level? Any help or suggestion is highly appreciated. Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
Segmented Register file Implementation
Hello Everyone, I am currently working on dividing the register file into two different processing element. In the first processing element (PE) I want to have certain operations (add, sub, mult, div, branch, jumps..etc) in first PE and loads and stores should be in the 2nd Processing Element. A couple specialized instructions were created to copy data between PEs. Also, both the processing elements are able to process add instructions. I want to put Registers 0-15 to PE#1 and 16-31 to PE#2. I am currently using OpenRISC Port of GCC (4.0.2). I have modified the machine description and assigned the PE#1 operations to register class a and the operations for PE#2 to register class b. Also I have set these letters appropriately in the or32.h file. Now, my question is this: How can I make the register allocator allocate correctly based on the restrictions I have set? Secondly, let's say I want to go through the instruction list (mostly in the machine_dependent_reorg function) and want certain ADDs to be put in a specific PE. This is mainly done to reduce the number of inter-PE copies. Is there a way I can set a certain flag (or create a certain FLAG) on the instruction (I know instruction is an RTX structure) so that the register allocator can recognize this? Any help is greatly appreciated. Yours Sincerely, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.
RE: Help with another constraint
Hi Rask,
First, Thank you very much for all help you have provided me. It
really help me finish my project.
This is what I did:
I capture all the moves regardless of the operand and then to move an
immediate into a regiser, I force a register:
here is the code for this:
if (!no_new_pseudos)
{
/* taking care of moving constant integers */
if (GET_CODE (operands[1]) == CONST_INT)
{
rtx reg = gen_reg_rtx (SImode);
emit_insn (gen_movsi (reg, operands[1]));
operands[1] = gen_lowpart (QImode, reg);
}
/* moving memory operands */
if (GET_CODE (operands[1]) == MEM)
{
rtx reg = gen_reg_rtx (SImode);
emit_insn (gen_rtx_SET (SImode, reg,
gen_rtx_ZERO_EXTEND (SImode,
operands[1])));
operands[1] = gen_lowpart (QImode, reg);
}
/* moving register operands */
if (GET_CODE (operands[0]) != REG)
operands[1] = force_reg (QImode, operands[1]);
}
I hope this helps.
-Balaji V. Iyer.
--
Balaji V. Iyer
PhD Student,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
-Original Message-
From: Rask Ingemann Lambertsen [mailto:[EMAIL PROTECTED]
Sent: Monday, December 17, 2007 1:33 PM
To: Balaji V. Iyer
Cc: gcc@gcc.gnu.org; [EMAIL PROTECTED]
Subject: Re: Help with another constraint
On Wed, Dec 12, 2007 at 03:35:09PM +0100, 'Rask Ingemann Lambertsen'
wrote:
The movxx patterns are special and you'll need to hold the
compiler's hands a little. Since your target can't move immediates
directly to memory, you have to ask for a secondary reload to an
intermediate register. Use the target hook TARGET_SECONDARY_RELOAD.
Actually, how do you do that? I can't see any place in the
documentation that says how TARGET_SECONDARY_RELOAD can be used for that
purpose.
--
Rask Ingemann Lambertsen
Danish law requires addresses in e-mail to be logged and stored for a
year
RE: Help with another constraint
Hi Revital1, Thank you very much for your help. The ISA I am using (OpenRISC) does not provide an alternative for moving a constant into memory. The only way of doing this is to move the constant into a register (which i am doing) and then move that register value into memory. So what can I do in that case? Thanks, Baljai V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Revital1 Eres [mailto:[EMAIL PROTECTED] Sent: Wednesday, December 12, 2007 7:14 AM To: Balaji V. Iyer Cc: gcc@gcc.gnu.org; [EMAIL PROTECTED]; 'Rask Ingemann Lambertsen' Subject: RE: Help with another constraint Hello, I think you should add the pair of constraints m and I respectively to the description of the instruction in your md file (and a relevant case 8 to handle such instruction), i.e.: (define_insn movqi - [(set (match_operand:QI 0 nonimmediate_operand =p,q,m,m,p,q,p,q) -(match_operand:QI 1 general_operand m,m,p,q,p,q,I,I))] + [(set (match_operand:QI 0 nonimmediate_operand =p,q,m,m,p,q,p,q,m) +(match_operand:QI 1 general_operand m,m,p,q,p,q,I,I,I))] * switch(which_alternative) @@ -17,6 +17,8 @@ case 6: case 7: return \l.addi \\t%0,r0,%1\\t # move immediate\;, + case 8: + return ...; default: return \invalid alternative\; } It seems that the pair m and I is missing (which indicate the memory = constant instruction). You could look for which_alternative variable in GCC internals for more details on this. Revital
RE: Help with another constraint
Hello Everyone,
I got past that negdi2 and some errors..now I am trying to compile
some linux module, and it says I am not able to find this constraint:
init/main.c: In function 'start_kernel':
init/main.c:441: error: insn does not satisfy its constraints:
(insn 112 110 478 12 (set (mem:QI (reg/v/f:SI 16 r16 [orig:72 line.183 ]
[72]) [0 S1 A8])
(const_int 0 [0x0])) 16 {movqi} (nil)
(nil))
init/main.c:441: internal compiler error: in
reload_cse_simplify_operands, at postreload.c:391
Please submit a full bug report,
Here is what I have for movqi:
(define_insn movqi
[(set (match_operand:QI 0 nonimmediate_operand =p,q,m,m,p,q,p,q)
(match_operand:QI 1 general_operand m,m,p,q,p,q,I,I))]
*
switch(which_alternative)
{
case 0:
case 1:
return \l.lbz \\t%0,%1\;
case 2:
case 3:
return \l.sb\\t%0,%1\;
case 4:
case 5:
return \l.ori \\t%0,%1,0\\t # move reg to reg\;
case 6:
case 7:
return \l.addi \\t%0,r0,%1\\t # move immediate\;
default:
return \invalid alternative\;
}
To give a quick explanation:
p = register numbers between 0-31 (inclusive)
q = register numbers between 32-63 (inclusive)
I = constant int value: ((VALUE) =-32768 (VALUE) =32767)
So, what am I missing?
Any help is highly appreciated!
Thanking You,
Yours Sincerely,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Student,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
-Original Message-
From: 'Rask Ingemann Lambertsen' [mailto:[EMAIL PROTECTED]
Sent: Monday, December 10, 2007 12:16 PM
To: Balaji V. Iyer
Cc: gcc@gcc.gnu.org; [EMAIL PROTECTED]
Subject: Re: Help with another constraint
On Sun, Dec 09, 2007 at 11:35:32AM -0500, Balaji V. Iyer wrote:
Hello Rask,
I am not understanding your response, can you clarify it for me?
As per the question about the error message above?
../../gcc-4.0.2/gcc/libgcc2.c -o libgcc/./_negdi2.o
../../gcc-4.0.2/gcc/libgcc2.c: In function '__negdi2':
../../gcc-4.0.2/gcc/libgcc2.c:72: error: insn does not satisfy its
constraints:
I think this is misleading you. It seems likely that the problem is
with the predicate and not the constraint.
(insn 15 13 16 (set (mem:SI (plus:SI (reg/f:SI 2 r2)
^^^
This has to be a register, doesn't it? If so, use -fdump-rtl-all and
look at the dump files to see where it goes wrong.
(const_int -28 [0xffe4])) [0 D.1256+0 S4 A32])
(neg:SI (reg:SI 3 r3 [orig:80 D.1255 ] [80]))) 38 {negsi2}
(nil)
(nil))
Please also post your negsi2 pattern.
--
Rask Ingemann Lambertsen
Danish law requires addresses in e-mail to be logged and stored for a
year
RE: Help with another constraint
Hello Rask,
I am not understanding your response, can you clarify it for me?
As per the question about the error message above?
../../gcc-4.0.2/gcc/libgcc2.c -o libgcc/./_negdi2.o
../../gcc-4.0.2/gcc/libgcc2.c: In function '__negdi2':
../../gcc-4.0.2/gcc/libgcc2.c:72: error: insn does not satisfy its
constraints:
(insn 15 13 16 (set (mem:SI (plus:SI (reg/f:SI 2 r2)
(const_int -28 [0xffe4])) [0 D.1256+0 S4 A32])
(neg:SI (reg:SI 3 r3 [orig:80 D.1255 ] [80]))) 38 {negsi2} (nil)
(nil))
../../gcc-4.0.2/gcc/libgcc2.c:72: internal compiler error: in
final_scan_insn, at final.c:2439
Please submit a full bug report,
with preprocessed source if appropriate.
See URL:http://gcc.gnu.org/bugs.html for instructions.
make[2]: *** [libgcc/./_negdi2.o] Error 1
make[2]: Leaving directory
-Balaji V. Iyer.
--
Balaji V. Iyer
PhD Student,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
-Original Message-
From: Rask Ingemann Lambertsen [mailto:[EMAIL PROTECTED]
Sent: Sunday, December 09, 2007 8:08 AM
To: Balaji V. Iyer
Cc: gcc@gcc.gnu.org; [EMAIL PROTECTED]
Subject: Re: Help with another constraint
On Sun, Dec 09, 2007 at 03:55:36AM -0500, Balaji V. Iyer wrote:
Hello Everyone,
I am trying to partition register files in GCC port of Opencores
(OPENRISC 1000). It is currently failing the following constraint in
negdi2
(insn 15 13 16 (set (mem:SI (plus:SI (reg/f:SI 2 r2)
^^^
(const_int -28 [0xffe4])) [0 D.1256+0 S4 A32])
(neg:SI (reg:SI 3 r3 [orig:80 D.1255 ] [80]))) 38 {negsi2}
(nil)
(nil))
../../gcc-4.0.2/gcc/libgcc2.c:72: internal compiler error: in
final_scan_insn, at final.c:2439 Please submit a full bug report,
+(define_insn negsi2
+ [(set (match_operand:SI 0 register_operand =r)
+ (neg:SI (match_operand:SI 1 register_operand r)))]
+ l.sub \t%0,r0,%1
+ [(set_attr type add)
+ (set_attr length 1)])
How did that happen? Look at the dump files. Btw, what is the error
message above the insn dump?
--
Rask Ingemann Lambertsen
Danish law requires addresses in e-mail to be logged and stored for a
year
Help with the Machine Description
Hello Everyone,
I am trying to modify the OpenRISC GCC to modify the existing
instructions and add more instructions into the system. I had to rewrite
most of the or32.md. When I am trying to compile something, it says the
following constaint is not found. Can someone please help me with
reading this contraint correctly?
(insn 112 110 478 12 (set (mem:QI (reg/v/f:SI 16 r16 [orig:72 line.183 ]
[72]) [0 S1 A8])
(const_int 0 [0x0])) 16 {movqi} (nil)
(nil))
From what I see, it is just a that we are trying to set 1 byte of a
memory location with the value in register #16 (r16) with an offset of
0which I have handled already in my machine description...so what
can this be?
Any help is highly appreciated.
Thanking You,
Yours Sincerely,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Student,
Center for Efficient, Scalable and Reliable Computing,
Department of Electrical and Computer Engineering,
North Carolina State University.
Register Numbers during machine dependent reorg?
Hello Everyone, I am currently working with MIPS port of gcc-4.0.2 by using segmented register files (like a multi-core approach). This is what i would like to do: I would like to assign instructions whose destination registers are between 0 to 7 to core 1, 8-15 to core 2 and so forth. I would like some advice about doing this efficiently in GCC? Can I do this in machine dependent reorganization phase? When the compiler reaches this phase, does it know the register numbers already? I am OK with modifying the main-stream GCC files, the whole change doesn't have to be in the files of config/mips directory. Any help is highly appreciated. Thanking You, Yours Sincerely, Balaji V. Iyer. PS. Please CC me in your response since I am not a subscriber of this mailing list. Balaji V. Iyer PhD Student, Center for Efficient, Secure and Reliable Computing Department of Electrical and Computer Engineering North Carolina State University.
RE: Vectorizer in GCC 4.0
Thank you very much Mr. Naishlos. -Balaji V. Iyer. -Original Message- From: Dorit Naishlos [mailto:[EMAIL PROTECTED] Sent: Monday, November 21, 2005 3:47 PM To: Balaji V. Iyer Cc: gcc@gcc.gnu.org Subject: Re: Vectorizer in GCC 4.0 Hello Everyone, I am interested in knowing more about the vectorizer in GCC. Does anyone have or know of any statistics about the percentage of loops that can be vectorized in some benchmarks like MediaBench, SPEC2K and so forth? I have some old Spec2000 statistics, from around June, using autovect-branch: 226 loops where vectorized on powerpc970 out of 4506 inner-most single-entry/exit single-bb countable loops. (note that on powerpc970 only single-precision fp benchmarks can be vectorized, and most of Spec-fp operates on doubles). The more interesting question is whether we get any performance impact with vectorization. There's one Spec-int benchmark for which vectorization actually has an impact on the performance of the entire application - gzip is improved by 8% due to vectorization. Haven't tried MediaBench yet; I'd be curious to see the results if anyone tries it out. We vectorize 4 loops in linpack, getting ~36% improvement on the entire benchmark. Additional numbers on other benchmarks will be available in the near future. Also see: - Vectorizing Hilaram: http://gcc.gnu.org/ml/gcc/2005-10/msg01044.html - Vectorizing libgfortran: http://gcc.gnu.org/ml/gcc-bugs/2005-11/msg01722.html dorit Thanking You, Yours Sincerely, Balaji V. Iyer.
Vectorizer in GCC 4.0
Hello Everyone, I am interested in knowing more about the vectorizer in GCC. Does anyone have or know of any statistics about the percentage of loops that can be vectorized in some benchmarks like MediaBench, SPEC2K and so forth? Thanking You, Yours Sincerely, Balaji V. Iyer.
Extracting destination register from an instruction
Hello Everyone, I have a question about finding register names from the instruction. I am porting GCC for a propriatery architecture and the thing is that, I want to group instructions whose destination registers are between 0-15 into one cluster and 16-31 in another. Firstly, I was under the impression that the only way I can do this is in the machine_dependent reorganization phase? Is there another way to do this? Also, how can I extract destination register information from the instruction? Any help is highly appreciated. Thanking You, Yours Sincerely, Balaji V. Iyer. PS. Please CC me while responding since I am not a subscribing member of this list.
Explicit NOPs for a VLIW Machine
Hi Everyone, I am porting GCC 4.0.0 to a proprietary VLIW machine, and I want to insert NOPs explicitly wherever there is an Output/Flow/Anti dependencies. I am currently doing this insertion in the machine dependent reorganization phase. Is there a way to do this in machine description file (or during scheduling phase) itself (or a better way to do this)? Thanks, Balaji V. Iyer.
Question about Machine Description
Hi all,
I am currently developing a GCC port for my own generic 32 bit
processor. I have this following error when I tried to compile a
benchmark.
(insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (reg:SI 12 r12)
(const_int 0 [0x0]))) 0 {*cmpsi_normal}
(insn_list:REG_DEP_TRUE 86 (
nil))
(nil))
convolve.c:236: internal compiler error: in reload_cse_simplify_operands,
at postreload.c:391
Please submit a full bug report,
with preprocessed source if appropriate.
See URL:http://gcc.gnu.org/bugs.html for instructions.
make: *** [convolve.o] Error 1
My question is that..what is the constaint/instruction I am missing? If
you could give me an assembly example tto illustrate an instrction that I
hvaent implemented, it would be nice too.
Any Help is highly appreciated.
Thanking You,
Yours Sincerely,
Balaji V. Iyer.
PS. Please CC me since I am not a subscribed member of this list.
Re: Question about Machine Description
Thank you very much Ian and Shreyas for your quick response. So I guess,
my question now would be, what would be an exmple that matches this
constraint below?
((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (reg:SI 12 r12)
(const_int 0 [0x0]))) 0 {*cmpsi_normal}
(insn_list:REG_DEP_TRUE 86 (
nil))
(nil))
The reason I ask is that, from my understanding it needs an instruction
that does the following:
if (r12 = 0) then
(r2+ -137) = 1
else
(r2+ -137) = 0
Is this correct?
Thanks,
Balaji V. Iyer.
PS. I am sorry for posting in both the mailing list.
Ian Lance Taylor wrote:
Balaji V. Iyer [EMAIL PROTECTED] writes:
No need to send to both gcc@gcc.gnu.org and [EMAIL PROTECTED] I
removed gcc-help in this reply. Thanks.
I am currently developing a GCC port for my own generic 32 bit
processor. I have this following error when I tried to compile a
benchmark.
(insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (reg:SI 12 r12)
(const_int 0 [0x0]))) 0 {*cmpsi_normal}
(insn_list:REG_DEP_TRUE 86 (
nil))
(nil))
convolve.c:236: internal compiler error: in
reload_cse_simplify_operands,
at postreload.c:391
Please submit a full bug report,
with preprocessed source if appropriate.
See URL:http://gcc.gnu.org/bugs.html for instructions.
make: *** [convolve.o] Error 1
My question is that..what is the constaint/instruction I am missing? If
you could give me an assembly example tto illustrate an instrction that
I
hvaent implemented, it would be nice too.
This kind of error generally means that the operand predicate accepts
an operand which no constraint matches. If the predicate (e.g.,
register_operand) accepts an operand, then there must be a constraint
that matches it. Otherwise you will get an error in
constrain_operands, such as the above.
Ian
Help with GCC
Hello Everyone, Greetings! I apologize ahead for asking an non-specific question. I have a question about the liveness analysis. This is what I wanted to do. I want to check to see if an instruction is live after a certain number of stage. (eg. 3 cycles) if (INSN is not live for more than 3 cycles) Mark it as not_live (NOT the same place as dead code marking) else Mark it as live Pass this live/not-live flag to the register allocation process so that it can output instruction in such a way (please see example below) (I want this information to be passed into .md stage) if (live) print add.live r1,r2,r3 else print add.notlive r1,r2,r3 I would also like to do it on the OpenRISC processor. Also, would like to NOT change the GCC sources as much as I can. I would appreciate if anyone could point me in the right direction to go about doing this. Thanking You, Yours Sincerely, Balaji V. Iyer. PS. CC's greatly appreciated.
DFA recognizer
Hi Everyone, I am adding a DFA scheduler for OpenRISC Processor in GCC. (I have not changed anything else). I don't see a difference in assembly at all. I would like to know how to make it recognize that there is a DFA scheduler. I have already did the following line (include OpenRISC_DFA) I know it is including it and compiling it with the rest of hte GCC Source code. Any help is highly appreciated. Thanking You, Yours Sincerely, Balaji V. Iyer. PS. CC's appreciated.
