gEDA-user: board's setup and output

2008-10-29 Thread Eduardo Santana
Hello guys,

I've finished a board I've been working on, though I have a question about 
both, it's proper setup and output.

Since I'm doing a one side board, I've just left the solder layer (where my 
routes live), and the ground layer, which is where I have the ground plane, 
both of them on the same group (layout's solder side).

Then, I haven't got nothing on the component side (not even a compoment layer 
as such), still I can see the layout as I guess I should by using the tab key 
(the solder and ground plane in one, and just the components' silkscreen on the 
other).

And so at output time I'd expect to see a mirrored solder layer (one side), and 
the mirrored component layer (just the silkscreen) but I never get to see the 
mirrored silkscreen on my ps output so tonner transfer would leave things as 
I'd like to.

While I can achieve this by tweaking ps output options, I'd appreciate if 
someone could tell me what I'm doing wrong, or missunderstanding in here.

I used to have the compoment layer, but since it was empty I just deleted it. 
Now in the layers' group window I have solder and ground on group one (solder 
side), and nothing on group two (component side).

Many thanks.

Eduardo,




  



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Re: gEDA-user: board's setup and output

2008-10-29 Thread DJ Delorie

 I used to have the compoment layer, but since it was empty I just
 deleted it. Now in the layers' group window I have solder and ground
 on group one (solder side), and nothing on group two (component
 side).

It's usually better to leave the component layer there, but just
disable (not delete) it if you need to use the autorouter.  Your
physical board *has* a component side, you just don't put copper on
it.


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Re: gEDA-user: pcb, howto partition power planes?

2008-10-29 Thread Steve Meier
On Tue, 2008-10-28 at 20:47 -0400, DJ Delorie wrote:
 Joerg [EMAIL PROTECTED] writes:
  By now I'd say Prehistoric Digital Assistant. The only guy I know
  who actually still uses one is our pastor.
 
 I have one I use every day, but it's in my watch.
 

So that watch isn't on a wrist band it is on an adjustable crane hook. 



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Re: gEDA-user: pcb, howto partition power planes?

2008-10-29 Thread DJ Delorie

  I have one I use every day, but it's in my watch.
 
 So that watch isn't on a wrist band it is on an adjustable crane hook. 

Heh, I suppose.

FYI it's a Timex Ironman USB.  Very useful watch.


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Re: gEDA-user: pcb, howto partition power planes?

2008-10-29 Thread Eric Brombaugh
DJ Delorie wrote:
 I have one I use every day, but it's in my watch.
 So that watch isn't on a wrist band it is on an adjustable crane hook. 
 
 Heh, I suppose.
 
 FYI it's a Timex Ironman USB.  Very useful watch.

But can you talk to it with Linux?

Eric (who still uses a VR3 - mostly to play DJ's Ace of Penguins Freecell)


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Re: gEDA-user: pcb, howto partition power planes?

2008-10-29 Thread DJ Delorie

 But can you talk to it with Linux?

I don't, but I think you can.  There's an SDK and emulator from the
timex yahoo group folks.


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gEDA-user: Size of symbols

2008-10-29 Thread Peter Carlsson
Hello!

I have created some symbols with the djboxsym tool and everything
seems fine except that when I add the symbols to a schematic their
size relative the title-B.sym is way too big.

Should I adjust the size of the symbols or the size of title-B.sym?
What is the correct way and how do I do that?

Best regards,
Peter Carlsson


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Re: gEDA-user: Size of symbols

2008-10-29 Thread John Luciani
On Wed, Oct 29, 2008 at 4:56 PM, Peter Carlsson [EMAIL PROTECTED] wrote:

 Should I adjust the size of the symbols or the size of title-B.sym?
 What is the correct way and how do I do that?

I would adjust the size of the symbols. The standard symbols seem a bit too big
for me as well.

(* jcl *)



-- 
http://www.luciani.org


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Re: gEDA-user: Size of symbols

2008-10-29 Thread Dave McGuire
On Oct 29, 2008, at 5:02 PM, John Luciani wrote:
 Should I adjust the size of the symbols or the size of title-B.sym?
 What is the correct way and how do I do that?

 I would adjust the size of the symbols. The standard symbols seem a  
 bit too big
 for me as well.

   Same here.  Is there any way to do this en masse?

   -Dave

-- 
Dave McGuire
Port Charlotte, FL




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Re: gEDA-user: Size of symbols

2008-10-29 Thread DJ Delorie

 I have created some symbols with the djboxsym tool and everything
 seems fine except that when I add the symbols to a schematic their
 size relative the title-B.sym is way too big.

Sometimes, grouping pins into busses in djboxsym helps (don't put
blank lines between them, and put .bus on a line before the group).

Sometimes you need more compact symbols, though.  It depends on the
symbols.

See also: http://www.delorie.com/pcb/cs8900a.html


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Re: gEDA-user: Size of symbols

2008-10-29 Thread John Doty

On Oct 29, 2008, at 3:04 PM, Dave McGuire wrote:

 On Oct 29, 2008, at 5:02 PM, John Luciani wrote:
 Should I adjust the size of the symbols or the size of title-B.sym?
 What is the correct way and how do I do that?

 I would adjust the size of the symbols. The standard symbols seem a
 bit too big
 for me as well.



That's not the paradigm. The way gEDA works is that you keep the  
symbol size constant in gEDA's arbitrary units, and make the extent  
of your page what you want to shrink them to the size you want.

I personally find title-B about right for letter or A4 paper with the  
existing symbols. I like modules I can comprehend, not spaghetti  
going all over the place. I also don't want to give the bifocals too  
much of a workout ;-)

Note that you don't have to use a titleblock at all. Some of my  
collaborators just put in cvstitleblock-1.sym with no frame, so the  
schematic just fills whatever page it's printed on.

John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
[EMAIL PROTECTED]




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Re: gEDA-user: Size of symbols

2008-10-29 Thread DJ Delorie

 I personally find title-B about right for letter or A4 paper with the  
 existing symbols.

I have a set of my own titleblocks that are multiples of letter size,
designed for extents without margins prints.


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Re: gEDA-user: pcb, howto partition power planes?

2008-10-29 Thread Steve Meier
I went looking to see if the Analog Device book was available
electronically. Here are the links.


Steve Meier


High Speed System Applications Table of Contents



High Speed System Applications Section 1: High Speed Data Conversion
Overview



High Speed System Applications Section 2: Optimizing Data Converter
Interfaces



High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock
Distribution




High Speed System Applications Section 4: PC Board Layout and Design
Tools



On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote:
 I won't argue this point. I will refer every one to an Analog Device
 publication High Speed System Applications copyright 2006 ISBN-10:
 1-56619-909-3  or ISBN-13: 978-1-56619-909-4
 
 In particular if you get a copy of this book (and they gave me mine)
 look at pages 4.15 and 4.16
 
 There AD recommends connecting both of the A/D grounds digital and
 analog to the analog ground plane this is because it causes less
 problems for the relatively small amount of digital return current to be
 returned through the analog ground than it would to connect the
 converter to the much noisy digital ground.
 
 There is a lot more talked about then just that one blurb.
 
 Steve Meier
 
 
 
 On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote:
  Stefan Salewski wrote:
   Sometimes it is necessary/recommended to partition (separate) power or
   ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in
   
   http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf
   
   We can do this in pcb program with (adjoining) polygons.
   Disadvantage is, that if we change the size of one of the polygons we
   have to manually adjust the other sizes. A other method may be so divide
   a large polygon by copper clearing traces (with trace width zero). 
   
   This is related to my question from
   
   http://archives.seul.org/geda/user/Sep-2008/msg00387.html
   
   but not identical.
   
   What is the best way to handle this?
   
  
  I can't speak to that but just one word of caution: In my 20+ years in 
  engineering I have yet to see one case where splitting a ground plane 
  under high-speed ADCs has worked. Regardless of what application notes 
  say. Usually it didn't work, lots of noise. Or it kind of worked but 
  fell apart the instant somebody whipped out a GSM cell phone or BlackBerry.
  
  Myself, I never spilt a ground place. OTOH the industry practice of 
  splitting planes is providing part of my income :-)
  
  The only time I split is where required for safety, for example patient 
  isolation per 60601 (ECG, ultrasound etc.).
  
 
 
 
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Re: gEDA-user: Size of symbols

2008-10-29 Thread Dave McGuire
On Oct 29, 2008, at 5:33 PM, John Doty wrote:
 Should I adjust the size of the symbols or the size of title-B.sym?
 What is the correct way and how do I do that?

 I would adjust the size of the symbols. The standard symbols seem a
 bit too big
 for me as well.

 That's not the paradigm. The way gEDA works is that you keep the
 symbol size constant in gEDA's arbitrary units, and make the extent
 of your page what you want to shrink them to the size you want.

 I personally find title-B about right for letter or A4 paper with the
 existing symbols. I like modules I can comprehend, not spaghetti
 going all over the place. I also don't want to give the bifocals too
 much of a workout ;-)

 Note that you don't have to use a titleblock at all. Some of my
 collaborators just put in cvstitleblock-1.sym with no frame, so the
 schematic just fills whatever page it's printed on.

   I rather despise the new-fangled plop a component down and attach  
netnames to each of the pins, with no lines going anywhere  
methodology, if that's what you meant by your spaghetti reference. ;)

   What I like to do is have large schematics with small symbols,  
with a title block, and I print them usually at 11x17.  Would it be  
reasonable to simply use a LARGE title block (say, E size) and scale  
it to fit the page on the way out to the printer?

-Dave

-- 
Dave McGuire
Port Charlotte, FL




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Re: gEDA-user: Size of symbols

2008-10-29 Thread John Doty

On Oct 29, 2008, at 4:22 PM, Dave McGuire wrote:

 On Oct 29, 2008, at 5:33 PM, John Doty wrote:
 Should I adjust the size of the symbols or the size of title- 
 B.sym?
 What is the correct way and how do I do that?

 I would adjust the size of the symbols. The standard symbols seem a
 bit too big
 for me as well.

 That's not the paradigm. The way gEDA works is that you keep the
 symbol size constant in gEDA's arbitrary units, and make the extent
 of your page what you want to shrink them to the size you want.

 I personally find title-B about right for letter or A4 paper with the
 existing symbols. I like modules I can comprehend, not spaghetti
 going all over the place. I also don't want to give the bifocals too
 much of a workout ;-)

 Note that you don't have to use a titleblock at all. Some of my
 collaborators just put in cvstitleblock-1.sym with no frame, so the
 schematic just fills whatever page it's printed on.

I rather despise the new-fangled plop a component down and attach
 netnames to each of the pins, with no lines going anywhere
 methodology, if that's what you meant by your spaghetti reference. ;)

No, I meant the opposite, where you have hundreds of long lines on  
the page, requiring extremely careful tracing to figure out where the  
one you're interested goes. I like named nets.

For the CCD focal plane electronics on the Suzaku satellite, I  
dispensed with drawings for the backplane altogether. I just had a  
database of net-connector pin associations and ground it into the  
netlist form the layout software wanted with an AWK script. Very easy  
to understand and edit. But then I turned it over real engineers (I'm  
just a physicist faking it), and they just *had* to have a drawing.  
To my eyes, it's incomprehensible...

But to each his own.


What I like to do is have large schematics with small symbols,
 with a title block, and I print them usually at 11x17.  Would it be
 reasonable to simply use a LARGE title block (say, E size) and scale
 it to fit the page on the way out to the printer?

Yes. That's the approach gschem supports: the paper size you give in  
the print dialog determines the scale of the PS output. I typically  
print a B titleblock on A paper. Some prefer C (screen) to  
A (paper). The only unreasonable thing here is that I suspect  
you'll find that people will need a magnifier to read E to B. But  
maybe your readers' eyes are better than mine.

John Doty  Noqsi Aerospace, Ltd.
http://www.noqsi.com/
[EMAIL PROTECTED]




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Re: gEDA-user: Size of symbols

2008-10-29 Thread Steve Meier
I like a hierarchical schematic where I have a top.sch which has symbols
for each of the major subsections and I use buses for most digital
signal paths and nets for the analog paths to interconnect these
symbols.

When you have designs with a thousand components on it I don't care how
small your symbols are or how big your printer is it ain't readable.

Steve Meier



On Wed, 2008-10-29 at 18:22 -0400, Dave McGuire wrote:
 On Oct 29, 2008, at 5:33 PM, John Doty wrote:
  Should I adjust the size of the symbols or the size of title-B.sym?
  What is the correct way and how do I do that?
 
  I would adjust the size of the symbols. The standard symbols seem a
  bit too big
  for me as well.
 
  That's not the paradigm. The way gEDA works is that you keep the
  symbol size constant in gEDA's arbitrary units, and make the extent
  of your page what you want to shrink them to the size you want.
 
  I personally find title-B about right for letter or A4 paper with the
  existing symbols. I like modules I can comprehend, not spaghetti
  going all over the place. I also don't want to give the bifocals too
  much of a workout ;-)
 
  Note that you don't have to use a titleblock at all. Some of my
  collaborators just put in cvstitleblock-1.sym with no frame, so the
  schematic just fills whatever page it's printed on.
 
I rather despise the new-fangled plop a component down and attach  
 netnames to each of the pins, with no lines going anywhere  
 methodology, if that's what you meant by your spaghetti reference. ;)
 
What I like to do is have large schematics with small symbols,  
 with a title block, and I print them usually at 11x17.  Would it be  
 reasonable to simply use a LARGE title block (say, E size) and scale  
 it to fit the page on the way out to the printer?
 
 -Dave
 



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