Re: gEDA-user: OFF: capacitors for RF power amplifier
If you are going to model the PA - particularly to look at resonance effects - then you should include reasonably accurate models for the inductors and capacitors which include their major parasitic components. The Murata Chip S-Parameter Impedance Library is a handy tool for looking at their ceramic capacitor and inductor behaviour. http://www.murata.com/products/design_support/mcsil/index.html or there's an online version: http://ds.murata.com/software/simsurfing/en-us/index.html Andy. signality.co.uk On 12 April 2011 23:57, Wojciech Kazubski w...@o2.pl wrote: I'm currently designing a power amplifier for the HF (3-30MHz) radio band. I am selecting capacitors for the low pass harmonic filter bank at the output. My question is what kind of capacitors should I use? I apply not more then 100V of say 30MHz maximum. My best bet is to use X7R capacitors with as much DC voltage rating as I can get. I don't know if there's any connection between the DC and AC losses. Thanks, Levente The biggest problem can be the current handling capacity. Very few capacitor makers specify this. Usually if a capacitor is rated for 100V this means 100V DC wthout any current. Only special purpose capacitors for RF power applications have HF current ratings, see Anerican Technical Ceramics for example: http://www.atceramics.com For RF do not use X5R/X7R (good only for supply bypassing), use NP0/C0G or similar low loss ones. Their maximum capacitance is limited to few nanofarads in 1210 case, so it may be necessary to connect few in parallel to get desired value. Also if you do not have capacitors with high current ratings, connect several smaller ones in parallell instead of one big. Foil type capacitors are suitable for lowest frequencies (LW/MW) and have to be low loss. Polipropylene or teflon ones are low loss and usable, while poliester ones are too lossy. Parasitic inductance can also be a problem. Check your PA circuits with circuit simulator for resonance effects. In this case currents and voltages can be much higher. Wojciech Kazubski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
On Wed, Apr 13, 2011 at 1:31 AM, Andy Fierman andyfier...@signality.co.uk wrote: If you are going to model the PA - particularly to look at resonance effects - then you should include reasonably accurate models for the inductors and capacitors which include their major parasitic components. The Murata Chip S-Parameter Impedance Library is a handy tool for looking at their ceramic capacitor and inductor behaviour. http://www.murata.com/products/design_support/mcsil/index.html or there's an online version: http://ds.murata.com/software/simsurfing/en-us/index.html Hmm...it seems to be an .exe. Do they have a table or something? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: RFC using SVG with semantic markup as an EDA format
If anybody's interested there's a lot of info on previous attempts to produce standards based EDA formats here; http://xml.coverpages.org/xmlAndEDA.html this is probably old hat to many of you! My assessment is; 1. They tried to cover way too much in one go with edaXML, PCB's, MCM, fat symbols, basically trying to encapsulate all possible EDA data in one description and thus produced a complex format that was difficult to implement and poorly adopted. 2. Saying something is standards based as it's XML is a bit of a joke, as far as I know no open tools to read the format were ever produced. 3. I think it was a good idea that was before it's time, most EE's still were not that internet savvy back in 2000. Anyway it's looking dead easy to have gschem symbols - SVG . Should have something on Github shortly. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
On Wed, Apr 13, 2011 at 09:31:24AM +0100, Andy Fierman wrote: If you are going to model the PA - particularly to look at resonance effects - then you should include reasonably accurate models for the inductors and capacitors which include their major parasitic components. The Murata Chip S-Parameter Impedance Library is a handy tool for looking at their ceramic capacitor and inductor behaviour. http://www.murata.com/products/design_support/mcsil/index.html or there's an online version: http://ds.murata.com/software/simsurfing/en-us/index.html Andy. signality.co.uk On 12 April 2011 23:57, Wojciech Kazubski w...@o2.pl wrote: I'm currently designing a power amplifier for the HF (3-30MHz) radio band. I am selecting capacitors for the low pass harmonic filter bank at the output. My question is what kind of capacitors should I use? I apply not more then 100V of say 30MHz maximum. My best bet is to use X7R capacitors with as much DC voltage rating as I can get. I don't know if there's any connection between the DC and AC losses. Thanks, Levente The biggest problem can be the current handling capacity. Very few capacitor makers specify this. Usually if a capacitor is rated for 100V this means 100V DC wthout any current. Only special purpose capacitors for RF power applications have HF current ratings, see Anerican Technical Ceramics for example: http://www.atceramics.com Another manufacturer is Dielectric Labs: http://www.dilabs.com but they are not cheap, especially the porcelain ones. However, they have very good temperature characteristics and high to very high voltage ratings. Dilabs basically only manufactures capacitors for high frequency applications. For RF do not use X5R/X7R (good only for supply bypassing), use NP0/C0G or similar low loss ones. Agreed, well X5R/X7R can be used for loop filters in PLL and servo applications, when the bandwidth is not too critical, as long as you meet the stability criteria (but I use 25 or even 50V rated capacitors when the voltage on the capacitor never exceeds 3.3V). The problem is that you can't use anything else when you have size constraints and need capacitors in the 0.1 to 10 microfarad range: very low loop bandwidths for either crystal (VCXO) oscillators and even much lower for thermal stabilization loops. On the other hand, class Y and Z dielectrics should not even be allowed; a look at temperature and voltage dependence graphs should suffice to convince any circuit designer. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Spam Email to This List
I use a separate email address for this list and that address received a spam email. It doesn't look like that email came through this list, but rather the list was somehow harvested for email addresses and the message sent directly. Did anyone else get an email from s...@jxtpcb.com with the name Chinry? He is hawking PWB manufacturing. I've gotten messages from this same guy at other addresses, but this email address isn't used anywhere else at any time. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Spam Email to This List
Yes I got this. OT: I'm new hear so please feel free to ignore this comment, but might it be worth switching to google groups or similar? The interface is nice and you can use it like a traditional mailing list if desired. On Wed, Apr 13, 2011 at 12:51 PM, rickman gnuarm.g...@arius.com wrote: I use a separate email address for this list and that address received a spam email. It doesn't look like that email came through this list, but rather the list was somehow harvested for email addresses and the message sent directly. Did anyone else get an email from s...@jxtpcb.com with the name Chinry? He is hawking PWB manufacturing. I've gotten messages from this same guy at other addresses, but this email address isn't used anywhere else at any time. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Spam Email to This List
I got mail too. I deleted it. On 13 April 2011 12:51, rickman [1]gnuarm.g...@arius.com wrote: I use a separate email address for this list and that address received a spam email. It doesn't look like that email came through this list, but rather the list was somehow harvested for email addresses and the message sent directly. Did anyone else get an email from [2]s...@jxtpcb.com with the name Chinry? He is hawking PWB manufacturing. I've gotten messages from this same guy at other addresses, but this email address isn't used anywhere else at any time. Rick ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:gnuarm.g...@arius.com 2. mailto:s...@jxtpcb.com 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Spam Email to This List
Yes, a while back IIRC. -Original Message- From: geda-user-boun...@moria.seul.org [mailto:geda-user-boun...@moria.seul.org] On Behalf Of rickman Sent: Wednesday, April 13, 2011 7:52 AM To: gEDA user mailing list Subject: gEDA-user: Spam Email to This List I use a separate email address for this list and that address received a spam email. It doesn't look like that email came through this list, but rather the list was somehow harvested for email addresses and the message sent directly. Did anyone else get an email from s...@jxtpcb.com with the name Chinry? He is hawking PWB manufacturing. I've gotten messages from this same guy at other addresses, but this email address isn't used anywhere else at any time. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Where is pcb-20100929 for Win32 ?
Hello all, I don't want to disturb you too much. But can I get version 20100929 of PCB for Windows ? I still use pcb-2009 but I am getting tired of Request for bounding box of unsupported type 1024 bug. I found that the problem is fixed in the pcb-2010 version. Thank you in advance, Vaclav ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB Panelisation and outline layers
Hi all, First I'd like to say thanks to all the gEDA devs for creating such a great EDA package. After the initial learning curve and time spent learning all the little quirks and file formats, I much prefer gEDA over the commercial packages I've had to use. I've just started panelising some designs in PCB and while I've managed to create panels for manufacture, my process seems like a bit of a kludge. My current workflow goes like this: -Create individual boards in PCB (say board1.pcb and board2.pcb) -Run python script to generate the panel .pcb file (create pcb file of proper size, v-cuts, internal routes for punchout, mouse-bites, measurements, etc) -Run python script to generate pcb action script (Commands load board1/2.pcb into past buffer and paste in tiled pattern) -Load panel .pcb file in PCB -Execute command file in PCB -Place fiducials, thieving patterns, text, whatever in panel .pcb file -Export to Gerber I'd be interested to know if there's a better way to do this. I'm also a bit confused about how the panel outline and mechanical layers should work in this situation: I initially created the panel .pcb file with the exact dimensions of the panel I wished to create. When I sent out the Gerbers for quotes I had both fab houses come back to me saying they couldn't determine the panel's dimensions, in the end I had to create the panel .pcb file with arbitrarily larger dimensions and draw a panel sized rectangle so that they could determine the panel's size. Is this how it's normally done, it seems to defeat the whole purpose of specifying the dimensions in the .pcb file? I've never run into this problem when when manufacturing individual boards from PCB's gerber exports. My current layer stack is : Layer(1 component) Layer(2 solder) Layer(3 GND) Layer(4 power) Layer(5 signal1) Layer(6 signal2) Layer(7 signal3) Layer(8 signal4) Layer(9 route) - internal routing so that boards can be punched out in strips Layer(10 vgroove) Layer(11 outline) - contains board outline and dimensions of all panel sub-sets (individual board dimensions, route-line widths, margins etc) Layer(12 silk) Layer(13 silk) When I export to Gerber I end up with a .outline file containing just the panel outline and no internal routing. I also get a .fab file in which the vgroove lines don't appear, route layer lines are visible but are not as thick as the lines that appear on the PCB route layer (and have no associated drill-size). If I export all layer groups I end up with the v-grooves and routing in separate Gerbers as they should appear (along with every via/pin for some reason). What I'd really like is to be able to export different combinations of these mechanical layers (minus the drill holes) eg. one containing just the panel outline, one containing only lines for routing(the panel outline + internal routes), one with just the v-grooves, one marking the outline of the individual boards (ie the panel outline + v-grooves + internal routes) or other combinations as needed. Is there any way to generate these type of Gerbers from within PCB? If what I want to do isn't possible, are the any suggestions as to the best way to add this feature? Regards, Tom Pope ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Spam Email to This List
On Wed, Apr 13, 2011 at 01:02:40PM +0100, Andrew Seddon wrote: Yes I got this. OT: I'm new hear so please feel free to ignore this comment, but might it be worth switching to google groups or similar? The interface is nice and you can use it like a traditional mailing list if desired. Last year we tried that for challenge24 to remove some load from our servers during the contest. It works fine as long as you are using web and especially if you have google account, but for a plain, non-google user with email only it wasn't that good. I can not recall what exactly went wrong, but I remember we had to switch back to mailman running on our own server. I personally would be more happy to keep the mailing list private - of course I am not the one who contributes hosting, bandwidth or admin time. Regards, Tibor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Spam Email to This List
On 4/13/2011 8:56 AM, ge...@igor2.repo.hu wrote: On Wed, Apr 13, 2011 at 01:02:40PM +0100, Andrew Seddon wrote: Yes I got this. OT: I'm new hear so please feel free to ignore this comment, but might it be worth switching to google groups or similar? The interface is nice and you can use it like a traditional mailing list if desired. Last year we tried that for challenge24 to remove some load from our servers during the contest. It works fine as long as you are using web and especially if you have google account, but for a plain, non-google user with email only it wasn't that good. I can not recall what exactly went wrong, but I remember we had to switch back to mailman running on our own server. I personally would be more happy to keep the mailing list private - of course I am not the one who contributes hosting, bandwidth or admin time. I hope this thread doesn't go on too long. I had received email from this guy at another address so I wasn't sure if the problem had something to do with my security or if he had harvested from this group. I guess it was the latter. I think there is a lot of private email sent as a result of things discussed on this list. So making the list private might not be the best way to handle the spam. In fact, I've only gotten one spam email from this list that I can remember so clearly the problem isn't very bad. That isn't why I posted about this. I respond to business related spam by asking them to call me. If they are lucky they get the answering machine. If they get me, I ask them a million questions about how they got my email address. That always seems to piss them off measurably. If everyone did this, they would soon change their thinking about sending spam for business purposes. Rick ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Hmm... I used to get that error on Linux, but it never bothered me (I used PCB fine.) Just leave the message log open in the background and it won't bother you. On 13 April 2011 13:19, Vaclav Peroutka [1]vacla...@seznam.cz wrote: Hello all, I don't want to disturb you too much. But can I get version 20100929 of PCB for Windows ? I still use pcb-2009 but I am getting tired of Request for bounding box of unsupported type 1024 bug. I found that the problem is fixed in the pcb-2010 version. Thank you in advance, Vaclav ___ geda-user mailing list [2]geda-user@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:vacla...@seznam.cz 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
Hmm... I used to get that error on Linux, but it never bothered me (I used PCB fine.) Just leave the message log open in the background and it won't bother you. I have the message log open but GUI freezes. I have to close PCB and restart it again. Sometimes I can work 20 minutes but sometimes I am getting into this problem each mouse-wheel movement. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
I don't want to disturb you too much. But can I get version 20100929 of PCB for Windows ? I still use pcb-2009 but I am getting tired of Request for bounding box of unsupported type 1024 bug. I found that the problem is fixed in the pcb-2010 version. I wasn't able to build the win32 version of 20100929 when I released it. I still try every once in a while to get it working; the problem is mostly on my end (getting a build environment set up seems more problematic than I expected). If anyone wants to help make the process more robust, feel free :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Panelisation and outline layers
DJ's Panelization Scripts: http://www.gedasymbols.org/user/dj_delorie/ pcb2panel - combines boards into a panel board (outline for each board as an element) for easy editing). panel2pcb - reads panel board and input pcb's, produces a composite panel pcb. Although I've never done so, I assume the panel board could be easily generated from a script, allowing you to automate gridded panels. I just a few days ago added an outline layer to PCB's default stackup, and magic code to insert a rectangular boundary if it's otherwise empty. I'm not sure how it will interact with the panelization script, or how it *should* interact - do you want the outline gerber to have the overall outline, or the outlines of the individual boards? PCB's board dimensions are actually the dimensions of the work area. In the absence of an outline layer, it assumes that's the board area. It should produce a fab drawing with an outline on it; if you have no other outline, send them the fab drawing. Also: note that naming a layer route is a synonym for outline - don't use that to mean something else. vgroove is not a special name; pcb assumes it's yet another copper layer. As for arbitrarily combining layers, I suggest scripting something that changes the Groups() line in the .pcb (to a temp file, of course), a running pcb -x gerber ... to plot the various combinations. Sadly, we don't have the ability to export arbitrary cam jobs like the Big Boys. Another option is to look at gerbv and see if it has merging capabilities. I know PCB is careful to use a consistent set of apertures across gerbers; a perl script should be able to merge gerbers from pcb without too much work. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Panelisation and outline layers
On Wed, Apr 13, 2011 at 10:38:05AM -0400, DJ Delorie wrote: Another option is to look at gerbv and see if it has merging capabilities. I know PCB is careful to use a consistent set of apertures across gerbers; Yes, and thank you very much for that feature... I've used it to merge layers (mostly manually, it's not even difficult), obvisouly checking the result with gerbv before sending to the fab. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
is mostly on my end (getting a build environment set up seems more problematic than I expected). Using the minipack build environment has been working for building the Windows version. If anyone wants to help make the process more robust, feel free :-) If the steps for creating the release are written down, Wiki would be fine, I'll take care of making a regular build of the Windows version. In discussing this with Dan a couple of years ago it was issues like tracking down the licenses to be shown by the installer etc. that were more problematic than the actual building of the code to do a release. I started once and gave up when I could not find the zlib license, then I understood what Dan meant. I'll do the steps needed, but need to have the staircase documented first. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tragesym template problem.
Hi Daniel, On Samstag, 19. März 2011, Daniel Ross wrote: Hello, I am trying to fill out the Tragesym template for an ATmega128RFA1, but the script gives me an error when I pass it the CSV file (renamed to a .sch file): error: version attribut missing In the template, I had changed the example version number to 20110319 1, following the format of the template version number. I verified that the CSV file contains a version line. Has anyone out there found a solution to this problem? I am following the tutorial at http://geda.seul.org/wiki/geda:tragesym_tutorial;, using the OpenOffice template. Thanks, Dan. Can you show me the first few lines of the input file? ... and the command you've used. Regards Werner ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Spam Email to This List
On Wed, Apr 13, 2011 at 09:36:20AM -0400, rickman wrote: On 4/13/2011 8:56 AM, ge...@igor2.repo.hu wrote: On Wed, Apr 13, 2011 at 01:02:40PM +0100, Andrew Seddon wrote: Yes I got this. OT: I'm new hear so please feel free to ignore this comment, but might it be worth switching to google groups or similar? The interface is nice and you can use it like a traditional mailing list if desired. Last year we tried that for challenge24 to remove some load from our servers during the contest. It works fine as long as you are using web and especially if you have google account, but for a plain, non-google user with email only it wasn't that good. I can not recall what exactly went wrong, but I remember we had to switch back to mailman running on our own server. I personally would be more happy to keep the mailing list private - of course I am not the one who contributes hosting, bandwidth or admin time. I hope this thread doesn't go on too long. I had received email from this guy at another address so I wasn't sure if the problem had something to do with my security or if he had harvested from this group. I guess it was the latter. I think there is a lot of private email sent as a result of things discussed on this list. So making the list private might not be the best way to handle the spam. In fact, I've only gotten one spam email from this list that I can remember so clearly the problem isn't very bad. That isn't why I posted about this. Sorry, missunderstanding. By private I meant hosted privately instead of hosted by some 3rd company like google. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
On Tue, Apr 12, 2011 at 04:31:03PM +0100, Peter Clifton wrote: This is a really neat idea.. P pin number :1 doesn't really matter, it is just a way of referring to a particular pin. If we could reference by other means, that would also be cool. I'm thinking of some kind of id=... attribute like CSS / HTML / SVG would use to refer to other elements. As someone who's just ranted against lots of magic special cases.. how would people feel to a primitive id=... attribute which is handled by API to look up and element's ID. We could make the code DEFAULT to looking up pinnumber= or pinseq= for pins (if an id=... doesn't exist), so the new syntax could key off id=, not pinnumber= or So we are more or less looking at a simplified hierarchical path syntax, where elements without explicit id= provide default id based on the type and other attributes? Examples: U1.1.net=Vcc (global attribute, pinnumber assumed for 1) 1.net=Vcc (attribute attached to U1) D1.A.net=Vcc (global, pinlabel assumed for A) Same could be specified in hierarchical design and would possibly solve the problem of different values in different instances of subcircuits. We'd have to work a bit on the syntax, precedence, resolution rules and how to refer to target attribute (in the above examples net would need to be a keyword). From that there's only a small step towards referring to arbitrary values in expressions (to specify component values etc). -- Krzysztof Kościuszkiewicz Simplicity is the ultimate sophistication -- Leonardo da Vinci ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
We'd have to work a bit on the syntax, precedence, resolution rules and how to For PCB attributes, we're going with foo:bar for heirarchy (or at least grouping), so U3:14.net=+5v ? (: for heirarchy, . for attributes ?) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
I thought we used / for netlist hierarchy. At least - that is what I
coded for the netlist viewer in PCB.
I suggested Attributes use : to assign attributes to owners, to
avoid conflict.
Like PCB:background-color=yellow
The syntax for what the owner owns can be different.
PCB:drc.silk.minimum=5mil
I'd put a preference for similarity to CSS syntax if we can use that.
CSS uses spaces for heirarchy:
P EM { background: yellow; }
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gEDA-user: Parallel Installation of Stable and Unstable gEDA Version
Hello, currently I am using gEDA 1.6.2 on a Ubuntu Linux System in a VirtualBox - this runs very good. For test reasons, I would like also to install the 1.7.x version of gEDA. I can do it at a different place - that's no problem. But what I am looking for is a good way to switch between the stable and the unstable version? What is your way of doing that? Thanks a lot for you help ... Markus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
On Wed, 2011-04-13 at 22:16 +0200, Krzysztof Kościuszkiewicz wrote:
So we are more or less looking at a simplified hierarchical path syntax, where
elements without explicit id= provide default id based on the type and other
attributes?
Examples:
U1.1.net=Vcc (global attribute, pinnumber assumed for 1)
D1.A.net=Vcc (global, pinlabel assumed for A)
You would need to be explicit about what attribute you're keying off, as
pinnumber=A is completely vaild in gEDA. Think BGAs (A1 etc..), or
transistors where the footprint is lettered.
I propose we look closely at CSS:
http://www.w3.org/TR/2009/PR-css3-selectors-20091215/#attribute-selectors
pin[pinnumber=1] {
pinnumber=99;
}
complex[device=RESISTOR] {
footprint=0603;
}
pin#blah {
pinnumber=2;
}
(Shorthand for a match against a pin with id=blah)
#X1 # X2 #R1 {
value=100R;
}
Override X1/X2/R1 value attribute to 100R#
(Where X1, X2, R1 are id names. These might default from refdes=
attributes where they are unique, and belong to a complex).
Note that id attributes in CSS are explicitly unique, whereas our
refdes= attributes historically are not required to be.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
On Wed, 2011-04-13 at 16:58 -0400, DJ Delorie wrote:
I thought we used / for netlist hierarchy. At least - that is what I
coded for the netlist viewer in PCB.
I suggested Attributes use : to assign attributes to owners, to
avoid conflict.
That is a good separator prefix for namespacing, yes. Or :: even, like C
++.
Like PCB:background-color=yellow
The syntax for what the owner owns can be different.
PCB:drc.silk.minimum=5mil
I'd put a preference for similarity to CSS syntax if we can use that.
CSS uses spaces for heirarchy:
P EM { background: yellow; }
That is ancestory. It would also match P/foo/bar/EM/
If you want just P/EM, you need:
P EM { background: yellow; }
or
PEM { background: yellow; }
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
That is ancestory. I'm a big fan of backwards compatibility :-) But it does point out that no one style seems to have a clear majority of the mindset :-P ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
On Wed, 2011-04-13 at 22:26 +0100, Peter Clifton wrote:
pin[pinnumber=1] {
pinnumber=99;
}
And regarding stuff like the above - where we key off one attribute and
change it in the rule, IF that is ever legal - we should do it like a
PLC executes its processing cycles.
Freeze a view of the attributes as exist before, run the rules on
those frozen attributes, then bulk update. That would enable a pin-swap
with syntax such as:
pin[pinnumber=1] {pinnumber=2;}
pin[pinnumber=2] {pinnumber=1;}
I've long seen this to be the most sane way of managing back-annotation
into a hierarchy. I would go as far to say refdes should be
back-annotated as such:
#X1 #X1 #R1 {refdes = R99;}
#X1 #X2 #R1 {refdes = R123;}
#X1 #X3 #R1 {refdes = R3;}
Could be included in some back-annotation file from the PCB which
operates live on the design data at net-list generation stage.
I'm not sure if the schematic hierarchy would use id=R1, id=X3 etc..
refdes=R1, refdes=X3 but to be honest, it doesn't really matter.
The only thing which is important is the processing order of each block
of attribute annotations.
Whether the attribute annotations should be a separate file, or reside
within an attribute (also over-ridable for extra CS recursive
elegance? ;)) is not something I've thougth about much yet. Either has
its charm - perhaps we could use both.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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Re: gEDA-user: Spam Email to This List
Got it, deleted it. ~Abhijit On Wed, Apr 13, 2011 at 17:21, rickman [1]gnuarm.g...@arius.com wrote: I use a separate email address for this list and that address received a spam email. � It doesn't look like that email came through this list, but rather the list was somehow harvested for email addresses and the message sent directly. � Did anyone else get an email from [2]s...@jxtpcb.com with the name Chinry? � He is hawking PWB manufacturing. � I've gotten messages from this same guy at other addresses, but this email address isn't used anywhere else at any time. Rick ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:gnuarm.g...@arius.com 2. mailto:s...@jxtpcb.com 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Where is pcb-20100929 for Win32 ?
I don't want to disturb you too much. But can I get version 20100929
of PCB for Windows ? I still use pcb-2009 but I am getting tired
of Request for bounding box of unsupported type 1024 bug. I found
that the problem is fixed in the pcb-2010 version.
I wasn't able to build the win32 version of 20100929 when I released
it. I still try every once in a while to get it working; the problem
is mostly on my end (getting a build environment set up seems more
problematic than I expected).
If anyone wants to help make the process more robust, feel free :-)
Hello, I tried to compile PCB by myself, I slightly edited the build_pcb script
and run it in minsys environment with win32/build_pcb command. But it ends
with the strange message in the Makefile. See last lines of log below. The
problem is following:
DIST_COMMON = README $(am__configure_deps) $(srcdir)/Makefile.am \
$(srcdir)/Makefile.in $(srcdir)/config.h.in \
$(top_srcdir)/configure $(top_srcdir)/intl/Makefile.in \
ABOUT-NLS AUTHORS COPYING ChangeLog INSTALL NEWS compile \
config.guess config.rpath config.sub depcomp install-sh \
missing mkinstalldirs ylwrap
My system puts white space after backslash. Therefore the second line is
recognized as a command. Or is it the problem of ./configure script ? I will
try to edit Makefile manually. But better way is to generate proper Makefile.
Does anybody have similar problem ?
** Configuration summary for pcb 20100929:
GUI: gtk
Printer: lpr
Exporters:bom gcode gerber nelma png ps
Source tree distribution: tarball
Build documentation: yes
Build toporouter: yes
Enable toporouter output: no
xdg data directory: /d/V/temp/pcb-20100929/pcb_inst/share
KDE data directory: /d/V/temp/pcb-20100929/pcb_inst/share
dmalloc debugging:no
ElectricFence debugging: no
Cross Compiling: no
CC: gcc -std=gnu99
CPPFLAGS: -mms-bitfields -mwindows
-DPREFIXDIR=\${prefix}\ -DBINDIR=\${bindir}\ -DHOST= \${host}\
-DPCBLIBDIR=\/d/V/temp/pcb-20100929/pcb_inst/share/pcb\
-DPCBTREEDIR=\/d/V/temp/pcb-20100929/pcb_in st/share/pcb/newlib\
-DPCBTREEPATH=\/d/V/temp/pcb-20100929/pcb_inst/share/pcb/newlib:/d/V/temp/pcb-20100929/pcb_
inst/share/pcb/pcblib-newlib\
CFLAGS: -Id:\V\temp\gdwin32/include -mms-bitfields
-mwindows -mms-bitfields -Id:/V/temp/ gtk_win32/include/glib-2.0
-Id:/V/temp/gtk_win32/lib/glib-2.0/include -Wall
-Wdeclaration-after-statement
LIBS: -lm -Ld:/V/temp/gtk_win32/lib -lglib-2.0
-lintl -lbgd
PCB: ${top_builddir}/src/pcb
Cleaning
Makefile:38: *** commands commence before first target. Stop.
ERROR Clean failed. See log in clean.log
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Re: gEDA-user: Where is pcb-20100929 for Win32 ?
I built pcb-20100929 last night using the minipack environment in a virtualbox VM with a fresh Ubuntu 10.10 install. Process was nearly painles: I had to find alternative sources to the ones given in the pixman and gd recipes(it seems like libgd.org has been down for a long time), but that was the only hiccup . I remember ages ago when I was doing a bit of coding for the N900, Nokia actually release a VM image containing a fully set-up Maemo linux development environment. It saved me alot of time compared to navigating a sea of dependencies and manually setting up the cross-compiler and emulator environments. Is there any interest in something like this for PCB/Minipack? I'd be happy to slap one together but don't have the resources to host it. -Tom Pope On Wed, Apr 13, 2011 at 11:21 PM, Bob Paddock graceindustr...@gmail.com wrote: is mostly on my end (getting a build environment set up seems more problematic than I expected). Using the minipack build environment has been working for building the Windows version. If anyone wants to help make the process more robust, feel free :-) If the steps for creating the release are written down, Wiki would be fine, I'll take care of making a regular build of the Windows version. In discussing this with Dan a couple of years ago it was issues like tracking down the licenses to be shown by the installer etc. that were more problematic than the actual building of the code to do a release. I started once and gave up when I could not find the zlib license, then I understood what Dan meant. I'll do the steps needed, but need to have the staircase documented first. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
