Re: gEDA-user: Fwd: Re: [OH Updates] How can you help solve the proprietary tool problem?
- back-annotation to schematic from the PCB editor. An example of where this is essential is if impedance controlled nets end up having to cross plane breaks and extra capacitors have to be added to couple the ground return paths between the planes. A net in the schematic may have an impedance constraint on it. When it is passed into layout, the net then ends up having to cross from over a ground plane to over a power plane. Capacitors may have to be added to bring the ground return path close to the plane crossing point. Other than by adding a number of redundant capacitors to the schematic, there is no way the need for these extra capacitors can be predicted from the schematic so they have to be added to the layout and then back-annotated into the schematic. I know this is bad practice but there are often situations where physical constraints on layer count such as dimensions or costs mean that the layout is limited to a certain number of layers. Cheers, Andy. signality.co.uk 2011/9/3 Steven Michalske smichal...@gmail.com: On Sep 2, 2011, at 12:45 PM, Colin D Bennett co...@gibibit.com wrote: On Fri, 02 Sep 2011 10:18:20 -0500 John Griessen j...@ecosensory.com wrote: Does the category low end bother you? Well, I think low-end is not very specific in reality. Does gEDA really belong in the category of EAGLE, or is it much more powerful? Maybe the “low-end” attitude toward gEDA is based on the fact that pcb doesn't support important features for large and complex boards such as - trace length matching, Important in high speed. I recall a serpentine plugin for pcb. +1 to bundling plugins with pcb sources.. - constraints/routing styles defined at the net level, Important for high speed and power applications - pushing/pulling PCB traces and better support for moving parts with traces routed, Nifty, aids layout but often you can't shove those length matched sets anyhow. - ability to select a component on the PCB by clicking it in the schematic view, Novice feature Layout engineers have paper schematics with notes taken on them when they met with the EEs who drew the schematics. - back-annotation to schematic from the PCB editor. Again, back annotation comes from yelling at the EE and telling them that they can't break physics no mater how hard they try! On the other hand for FPGAs and other high pin count devices I suspect that this would be more welcome. Though I think that a tool that mapped the ports and I/Os an stored them in a table. With an option to render to graphical symbols would be better. Nets in schematic assigned to layout placement. Then layout is assisted by assignment tool, kinda like a reverse fanout tool. Then The table in the design is updated. Then graphics and pinmap file get generated. This would cut the iterative process from the desiring of large FPGA parts. Just a few things that sound important to me, a novice PCB designer. What is really missing is the support contracts from the high end tools. We need the equivalent of what RedHat is for Linux to be considered a high end tool. Regards, Colin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating bill of materials?
What is mfgs? Manufacturers? (Not sure why they'd be bothered to contribute symbols anyway. They do very few for commercial packages.) Andy. signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Off topic: request for a little help
Which browser and OS are you using ? Chrome (with default settings i.e. JS enabled) on WinXP Pro SP3 32 bit. Haven't tried it at home with FF on LMDE 64 bit. :) BTW; just submitted a couple of your pages to: http://validator.w3.org/ Quite a few errors. H. :( Andy ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Off topic: request for a little help
Hi Stephen, FWIW, It's not clear to me if the prices shown are in $AU or $US and the option to select one or the other doesn't appear to change the prices shown on the products or in the cart. I'm in the UK on a fairly throttled broadband connection and the pictures took some seconds to load. How big are the pictures? Can they be shrunk and still be clear enough not to look silly? That would speed up page loading. There's nothing to say what SOI is all about. Some sort of About page would give the customer a bit more of a feel for what SOI is offering, what makes it special, different from any other place. All the usual business speak about Unique Selling Point etc. I'm a customer: talk to me; give me a reason to walk in your shop, poke about your shelves and buy your stuff. The Conditions of use page maybe should be renamed Terms and Conditions to make it clear that that is what they are as opposed to some conditions of use of the website, which they are not. Are you legally obliged to put any information on the site about company registration, VAT numbering or whatever? . Cheers, Andy. signality.co.uk On 17 August 2011 07:57, Stephen Ecob silicon.on.inspirat...@gmail.com wrote: Thanks to all who have replied, I've received some really useful feedback. The most commonly repeated comment was that the animated price tags are just plain irritating. I'll put their removal on the slate for the first refresh of the web site ;-) Thanks and best regards, Stephen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating bill of materials?
Hi John, Sounds like you've not yet found this: http://geda.seul.org/wiki/geda:faq-gnetlist I know, netlist isn't necessarily the first search term that comes to mind when looking for info on how to generate a BoM ... See also: http://geda.seul.org/wiki/geda:faq-attribs Cheers, Andy. signality.co.uk On 17 August 2011 13:24, John Hudak jjhu...@gmail.com wrote: Perhaps I have not progress through the development cycle far enough, but, it there a way generate a bill of materials (BoM) from gschem and/or PCB? In my readings I have not come across reference to BoMs. I am thinking that one could be made by specifying the BoM headings of interest (which would be the desired attributes from gschem) in a BoM template file, have a program comb through the components in gschem and create a csv file suitable for Excel to use. Along these lines, are there program provisions in gschem and/or pcb that allows one to create user define attributes for a component? (e.g. component supplier, pointer to relevant documentation such as an app note, or even a note attribute). Again, thank you for your feedback John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating bill of materials?
What version of gattrib are you using? I opened a bug report on SourceForge about what seems to be the same problem back in 2009: Bugs item #2793743, was opened at 2009-05-19 11:18 The version of gattrib I was using then was 1.4.0.20080127 from the Debian lenny repos. I don't know if that bug report can still be accessed since the SourceForge Tracker had been disabled: https://sourceforge.net/tracker/?func=detailatid=818426aid=2793743group_id=161080 Sorry, knowledge buffer now empty. Andy. signality.co.uk On 17 August 2011 15:40, John Hudak jjhu...@gmail.com wrote: Very cool, thank you! So, I tried itand it produced output that was not expected, and I would go so far as to say that it is wrong. Attached is a jpg file of how the original attribute-component matrix looks like. Then I do an Add attribute column and I get the result shown in modified attribute pic... Ummm, I expected to see a blank column with my designated heading appended to the right of the existing column. What I got was my new column PREPENDED before the last column, and populated with the contents of the original last column. So what did I do wrong?!? John On Wed, Aug 17, 2011 at 9:43 AM, Andy Fierman [1]andyfier...@signality.co.uk wrote: Hi John, Sounds like you've not yet found this: [2]http://geda.seul.org/wiki/geda:faq-gnetlist I know, netlist isn't necessarily the first search term that comes to mind when looking for info on how to generate a BoM ... See also: [3]http://geda.seul.org/wiki/geda:faq-attribs Cheers, Andy. [4]signality.co.uk On 17 August 2011 13:24, John Hudak [5]jjhu...@gmail.com wrote: Perhaps I have not progress through the development cycle far enough, but, it there a way generate a bill of materials (BoM) from gschem and/or PCB? In my readings I have not come across reference to BoMs. I am thinking that one could be made by specifying the BoM headings of interest (which would be the desired attributes from gschem) in a BoM template file, have a program comb through the components in gschem and create a csv file suitable for Excel to use. Along these lines, are there program provisions in gschem and/or pcb that allows one to create user define attributes for a component? (e.g. component supplier, pointer to relevant documentation such as an app note, or even a note attribute). Again, thank you for your feedback John ___ geda-user mailing list [6]geda-user@moria.seul.org [7]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [8]geda-user@moria.seul.org [9]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:andyfier...@signality.co.uk 2. http://geda.seul.org/wiki/geda:faq-gnetlist 3. http://geda.seul.org/wiki/geda:faq-attribs 4. http://signality.co.uk/ 5. mailto:jjhu...@gmail.com 6. mailto:geda-user@moria.seul.org 7. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 8. mailto:geda-user@moria.seul.org 9. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Linux Desktop für gEDA
Drifting off topic ... but going with the flow somewhat: I've been running Linux Mint Debian Edition 64bit since about February this year. Very impressed. I like the rolling distro idea. So far nothing serious has broken and have not had to be too techy with it. There are some good ideas coming later in the summer to make it easier to update too. The standard Mint Gnome desktop is dull but does me fine. I can't be bothered to change it. I also have Linux Mint Debian Edition 32bit XFCE running on an EEE PC 701 which seems to run OK (it doesn't play too well with hibernate but that's not surprising as it has no swap partition). Cheers, Andy. signality.co.uk 2011/8/4 David Griffith dgri...@cs.csubak.edu: On Thu, 4 Aug 2011, Павел Таранов wrote: I'm currently using Ubuntu 11.04 with classic Gnome (you can switch on GDM prompt). But Ubuntu team promice to remove this feature on next realeses... Nonsense like that is why I ditched Ubuntu for straight Debian. Now, seeing the writing on the wall, I'm trying to acclimate myself to XFCE. So far so good. There are some nits I'm working out. -- David Griffith dgri...@cs.csubak.edu ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Design Nark
Is it just me being a Grumpy Old Man or does anyone else take issue with RS over their advertising for their Design Spark EDA tool? In particular the statement at the end of the last paragraph in: http://www.designspark.com/content/designspark-pcb-version-2-takes-pcb-design-another-dimension that With the release of DesignSpark PCB Version 2, RS has reaffirmed its commitment to delivering the best open source experience to its engineering community. To the best of my knowledge, no source code for Design Spark has been released. I have had conversations with people presenting Design Spark at RS sponsored events about making Design Spark open source and have been told categorically that they have no intention of releasing the source code. I suppose RS do only claim to be delivering whatever it is that they are delivering, to its engineering community., i.e. not to anyone else's. To a lesser extent I find the statement here: http://www.designspark.com/theme/designspark-pcb that DesignSpark PCB is the world's most powerful free of charge PCB design tool. a bit presumptuous too. Bah. Humbug! Andy. signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT - non-contact digital current loop sniffer
As long as you have access to a single wire and not the return path! :) Andy. signality.co.uk On 13 July 2011 22:48, Stephen Ecob silicon.on.inspirat...@gmail.com wrote: On Thu, Jul 14, 2011 at 1:18 AM, David C. Kerber dker...@warrenrogersassociates.com wrote: Hi, electronics gurus - We have an application where we need to passively monitor a digital current loop (no data sending by us), with a data rate of 9600 baud. We already have solutions for tapping into the circuit, but in some of our customers' cases the circuits don't have enough drive capability to add another load to it. So we're looking for a non-loading, and preferably non-contact solution, such as a inductive pickup or hall-effect pickup, that hopefully wouldn't require us to break into the circuit. Does anybody know of such an animal? If not, it's also possible that we might contract to have one designed, but that's not decided for sure yet. It's a fairly electrically noise environment, but not extreme, and the sensor itself would likely be installed inside an already-existing box on the wall. The circuit runs at 45mA for the high signal, and the low is 2mA. Is the current flowing through a length of accessible wire at some point, or is it only accessible in a PCB trace ? If it flows through a length of wire then running it through a current transformer could work well. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Good point Rick, I should have explained that even though the larger inductance reduces the rms current in the primary significantly, the positive and negative peak currents are highly asymmetric. Simulating with a sinewave input, the positive peak current is about 110mA whilst the negative is about -390mA. Hence the transformer has to have a considerably higher peak current rating than the rms values might suggest. Robert originally said his input is bandlimited 15KHz to 28KHz but all his circuits include some form of discrete bandpass filtering. I suspect what Robert intends is that C1 and some combination of the transformer primary - as in his later posting - or a single inductance to ground or an additional series inductance - as in the original circuit posted - forms a bandpass filter centred on about 23kHz. In any case it is difficult to see how C1 can be removed without adding some sort of active buffer stage between the rectifiers and the filter, which then requires some sort of bootstrap supply to bring up the buffer to drive the rectifiers. Andy. signality.co.uk On 29 June 2011 23:54, rickman gnuarm.g...@arius.com wrote: The transformer allows a DC path to exist on the secondary side, but you still have the capacitor on the primary side of the circuit. If the positive and negative pulse currents are not equal, you will still have a problem on the primary side. You need to remove the cap C1. I still can't tell exactly what is going on in your circuit because you don't provide any labels on the o'scope diagrams. It would also be useful to see current waveforms from the simulations and waveforms from the loads. As was asked for previously, we still have not seen your requirements so I can't tell exactly what you are trying to do with this circuit. How large is the DC offset in the source? Why don't you include that in your simulation model? What voltage do you need out of this supply? I really can't tell what is needed in your design and what is just wrong. Rick On 6/24/2011 7:10 AM, myken wrote: This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? On 22/06/11 22:39, Andy Fierman wrote: Sorry Robert, Both Wojciech and I are wrong. His suggestion about adding a choke is basically the same as mine of using a transformer. The idea of both is to add a dc path to ground at the rectifier inputs. The difference is that the transformer adds DC isolation - which if you include your bandpass filter - you do not need. Sounds like the thing to do but sadly, the simulations show the reality! A choke does not do what you want and neither does a simple 1:1 transformer. However, if you use a 1:1:1 transformer then it all comes together. You can use a transformer with a 1:2 turns ratio, centre tapped and keep to the original half wave rectifier scheme. If you use a three winding transformer of 1:1:1 then you can use two bridge rectifiers. Using bridge rectifiers doubles the ripple frequency so allows lower smoothing C for the same ripple voltage. The attached (not very good quality) pdf shows the non-working choke and 1:1 transformer ideas and the working 1:1:1 transformer versions. Note the 1u smoothing capacitor values. These were reduced to make the simulation reach a steady state sooner than with the original 100uF values. Andy. signality.co.uk On 22 June 2011 01:12, Wojciech Kazubski [1][1]w...@o2.pl wrote: Hello all, I would appreciate some expert advice. I have a system which rectifies a sine wave input signal of 20Khz after a LC filter (see Rectifier_sim.jpeg) Everything works fine if LOAD_1 and LOAD_2 are equal. Vx is then (almost) the same as Vin. And Vcc and Vss are equal to the positive or negative part of the sine wave (less the DC losses) (Vss = -Vin_top and Vcc = Vin_top). BUT if LOAD_1 and LOAD_2 are not equal (like in Rectifier_sim.jpeg) it seems that Vx is lifted (DC component added) and Vss moves to the 0V and Vcc is lifted to twice the value I would expect (Vss = 0 and Vcc = Vin_toptop) (see rectifiersmp.eps). Our real life prototype shows the same behaviour as the simulation. I need this set-up for my system to work and I can not guarantee that the two loads always will be equal. Vin can be anything between 10Vtt and 90Vtt. I have tried adding a resistor from Vx to ground and that seems to help but increases the current drawn from the source (V1) to a unacceptable level. It should be a low power solution. If I short-circuit C1 everything works fine again (V1 has a low resistance output) but of course
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
The most recent circuit you posted is not the same as your original and as Gene pointed out, you have now made a series resonant circuit between the 220nF cap and the 200uH primary inductance. In the simulation, the source resistance is zero, the ESR of the cap is zero and there is only 0.25R series R and a bit over 500R parallel R (admittedly highly nonlinear) to damp the resonance. This is why the output voltage is so high. The value of output voltages you see in simulation may depend somewhat on exactly how the simulator is set up (and which simulator you use). Gnucap, LTspice and QUCS show rectified output voltages of around 180V for the 500k side output and 153V for the 500R side. I haven't run this in ngspice. A real transformer would have a K 1 but for this level of simulation setting K to 1 instead of 0.999 will significantly speed up the simulation with negligible effect on the output. Setting K to 1 introduces some leakage inductance but at 0.999 this is very small so it has a high resonant frequency with the 220nF input cap. The nonlinearity of the load switching between 500R and 500k through the diodes kicks this into ringing so the simulator spends ages calculating each ring. As Wojciech suggested, if you use an inductor with a much higher value then the resonance drops to well below your band of interest and the output voltages are about where you'd expect. The primary currents also fall dramatically. In your circuit, with an ideal inductor they are about 4.1A rms. Your little pulse transformer probably saturates some way below that current. With a 2mH primary inductance this falls to about 108mA rms. Of course, you then lose the bandpass filter effect of the resonance at 23kHz. The same general discussion applies to if you use a single inductor instead of a 1:1 transformer except of course there is no leakage inductance to worry about. What were the scales on the scope traces you sent? Cheers, Andy. signality.co.uk On 27 June 2011 01:27, Wojciech Kazubski w...@o2.pl wrote: Dnia piątek 24 czerwca 2011 o 13:10:35 myken napisał(a): This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? Probably the transformer has too low inductance for that frequency, it should be in mH range. Magnetizing current I=Uin/(2*pi*f*L) is high and saturates the core so waveforms are not sinusoidal. Wojciech Kazubski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Ooops, Just missed the Undo Send window ... Typo in (i): if the source has a peak to peak swing of x volts but a dc offset of y then (neglecting the diode drops) vcc = x/2+y and vss = x/2-y. :) Andy On 19 June 2011 11:01, Andy Fierman andyfier...@signality.co.uk wrote: Rick is spot on. However, there are more things you need to consider: i) Does your signal source have a mean DC level of zero? Without C1, if the source has a peak to peak swing of x volts but a dc offset of y then (neglecting the diode drops) vcc = x+y and vss = x-y. If you have to remove a DC offset then you'll have to put a transformer between C1 and the recirfiers. Then C1 keeps DC out of the transformer primary and the transformer secondary provides the necessary dc path for the rectifiers to work as required. ii) I note that C1 and L1 form a series resonant circuit with a centre frequency at about 22.9kHz. So is your source really bandlimited 15kHz - 28kHz by the time it gets to your circuit or are you trying to do the bandpass filtering as part of your circuit? If the latter then you will have to keep C1, L1 but add the transformer as described in (i) above. The you will have to model that transformer to include at least the leakage inductance to get the bandpass response right. Such transformers are not difficult to design and source. iii) What is the source impedance? Does the 8 ohms represent all of your source impedance or is there more hidden in the source itself? You will need to allow for all of it to see how the rectified outputs drop and ripple increases with load current. iv) Don't forget that a SMPS represents a constant power or negative resistance load. As the input voltage drops the current it draws from the source increases. The actual behaviour of a real SMPS is complicated by any input undervoltage lockout and soft start features. This may or may not play well with your source. I'd like to make a general point here. This isn't a criticism but an important observation: when asking a question about how to do something, it saves everyone a lot of time, guesswork and blind alleys if the problem that is to be solved is clearly stated alongside whatever attempt at a solution that the specific question may be about. Essentially, include the design specification in the original question otherwise no-one knows the whole story so the question doesn't get a proper answer in a timely manner. Clearly in some instances the design spec may not be something that can be given openly but usually the part relevant to a question can be reframed so as to not give away too much. However, there has to be enough information so that the boundaries of the problem in question can be understood. This question is a classic example. Several people have discussed removing a part of the circuit that I now strongly suspect (C1 and L1) is an essential (if inappropriately implemented) part of the circuit because it wasn't clear what the overall function or scope of the circuit was. Cheers, Andy. signality.co.uk On 18 June 2011 21:19, rickman gnuarm.g...@arius.com wrote: What is the purpose of C1 and L1? If you want to filter anything, it should be AFTER you rectify the signal to DC. A series cap is going to remove low frequencies... like DC which is attenuated very highly. So much in fact that you can't draw a DC signal through a capacitor. That is why your circuit is not working. If you remove C1 and L1 the circuit will work the way you want it to I believe. Also, with an input frequency of 15 kHz or higher, you won't be needing 100 uF output filter capacitors for a light load. How many mA is your load? How much ripple can you allow? Use those two values to calculate the value of output filter capacitor you need. Once I fix your circuit by removing the input filter I measure 19.14 volts out and 38.2 mA of current into a 500 ohm load. Is that what you are shooting for? The 100 uF cap gives around 10 mV of ripple. With lighter loads or more ripple the cap can be smaller. Rick On 6/17/2011 4:44 AM, myken wrote: Yeap, it should be a very low power power supply. Vx is not important Vcc and Vss are. Vin can be anything from 15Khz to 28Khz so a transformer is not the most desired option. I have designed two SMPS for Vcc and Vss but there load to the rectifier are not the same, with the described result. I will try the options suggested in this list today. Robert. On 17/06/11 04:13, gene glick wrote: On 06/16/2011 02:30 PM, myken wrote: Hello all, I would appreciate some expert advice. Are you trying to make a low current power supply? I agree with DJ - the unequal loading on + and - cycle will average to something other than zero (unequal capacitors, unequal diodes, etc) If Vx must always be average zero - you'll need to do something else. If you can handle a little voltage drop, don't care what happens
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Simply reproducing the filter twice, one for each polarity of rectifier will not work. If you can float the load or the source then splitting the circuit into two and using a bridge rectifier in each will work OK. The attached shows what I mean. Cheers, Andy. www.signality.co.uk On 16 June 2011 23:05, myken my...@iae.nl wrote: Thanks DJ, I had the same thought that Vx was floating somewhere unwanted, that's why I added the resistor (which didn't work). Gazing at this problem for a couple of days make me miss the obvious, just split the filter. Brilliant. I'll give it a try. Robert. On 16/06/11 20:48, DJ Delorie wrote: When you put two capacitors in series, there's no way to know what the voltage between them will be. You have three with a common central connection Vx. V1 acts to charge the node, the loads act to discharge it, so an unequal load means unequal discharging and thus nonzero average node voltage. Since D1 and D2 may have different average currents through them, Vx will adjust until the average current through R2 is the same as the net current throuth the two diodes. Can you split the filter into two filters, one for each load? or at least move C1 to the Vx side of the filter, and split it into two capacitors? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user rects_01.pdf Description: Adobe PDF document ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Darter - SPICE based IBIS modelling tool
Oh, yes. We like this! Cheers, Andy. signality.co.uk On 31 May 2011 07:11, Russell Dill russ.d...@asu.edu wrote: As edge rates increase, signal intergrity (SI) becomes more and more important, even for the hobbyist. Unfortunately, the models provided by semiconductor vendors typically come in only 2 forms, encrypted HSPICE and IBIS. No open tools exist for handling either. An open HSPICE decryption utility would only either encourage encryption changes or take-down notices. Enter Darter, a tool for creating SPICE models based on IBIS models. The basic idea is to create a SPICE subcircuit for each IBIS model within an IBIS file. Each subcircuit is then wrapped in one of several different subcircuits depending on component and pin (or signal name). This gives subcircuit names like (note that spaces in the model name get converted to underscores): DQ_FULL_ODT50_800 for bare buffers and: MT47H128M16U69A_DQ_FULL_ODT50_800_DQ14 for a buffer with parasitics. The buffers can then be connected with transmission lines for simulating SI problems. https://gitorious.org/darter http://www.gedasymbols.org/user/russell_dill/darter.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: This morning's treat
Well done that man. Cheers, Andy. On 23 May 2011 05:18, Steven Michalske smichal...@gmail.com wrote: Cool, Got photos? Steve On May 22, 2011, at 6:57 PM, John Doty j...@noqsi.com wrote: Well, here I am in Osaka. It's Monday morning, and I just saw the prototype Soft X-ray Imager (SXI) for the ASTRO-H space mission under test. Much of the electronics, a large, complex circuit board and some mixed-signal ASICs, is of my design, using gEDA. I've been working on this for six years, now, and it's wonderful to see it all built and plugged together. So, thank you to all who made this possible. It's a beautiful morning. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: zener diode modeling
By component sizes do you mean the parameters in the model? It might be instructive to compare the parameters in a normal diode model with those in your zener model to see if there are any you could add to see if they improve the behaviour. The idea of using a V source with a series diode and an anti-parallel diode across the lot might work best: V1 intk a 5 D1 k intk D D2 a k D .model D D This would give a zener voltage of about 5.6V. An alternative which could be fun to try is a B voltage source in series with a 0V source acting as a current monitor: .param Vz=5.6 Vfwd=0.6 epsilon=1k B1 intk anode V=(Vz+Vfwd)*tanh( Vfwd/(Vz+Vfwd)*exp(I(Vmon)*epsilon) )-Vfwd Vmon kathode intk 0 This gives very well defined zener and forward drop voltages (defined by the Vz and Vfwd parameters respectively). The epsilon parameter determines the sharpness of the forward and reverse conduction knees. The model is not quite right in that if the diode is placed in series with a resistor, as you would use with a zener, it does not produce exactly 0V across - i.e. 0A through - the diode for 0V applied to the overall series circuit of the diode and resistor. With a 1k resistor in series with the diode and Vz = 2.7, Vfwd = 0.6 and epsilon = 1k, the offset is around -4.1mV. The offset reduces for higher Vz and epsilon values. I haven't had time to work out what I've missed in the B source expression that makes the offset non-zero but for your application it may be good enough. You can always tweak the voltage of Vmon to take out the residual offset for a given set of Vz, Vfwd and epsilon. It is also possible to define the same function using a B current source - which may converge better than a B voltage source - but I can't see the wood for the trees on that version at present. I'd be interested to hear how you get on if you - or anyone else - do try it. :) Andy. signality.co.uk On 18 April 2011 23:27, yamazakir2 yamazak...@gmail.com wrote: I have not used a parallel gig ohm resistor or series inductor, but I have tried tweaking component sizes and it is extremely hard to get zeners to not gag in the middle of a transient sim I was looking for a very generic all purpose model that won't yak. It doesn't haven't to be accurate, just work. On Mon, Apr 18, 2011 at 1:38 PM, Andy Fierman andyfier...@signality.co.uk wrote: Hmmm. Tricky things zener, schottky and soft recovery diode models ... Try a different vendors model (check to see if it is actually a different model)? You could try using a V (voltage) source in series with an ordinary diode plus a second diode in anti-parallel with the series V and diode. This will give you a high reverse drop and a forward drop of a normal diode. The V source is set to the zener voltage minus one diode drop. So if you wanted a 5.6V zener, you set V to about 4.9V and assume about a 0,7V forward drop in the diode. You can play about with the value of V to set the overall drop to where you want it because you don't know exactly what the diode drop will be as it will depend on the diode model and of course the forward current. Or you can start with your existing zener model and play about with the parameters to see if you can make it work. If you make yourself a simple test circuit such as a pulse source with some series R driving the zener with maybe some C in parallel with the diode you can run transient tests on it to make sure you've not set up silly capacitance or transit times or messed up the forward or breakdown voltage to much whilst still giving you something that behaves like the diode you might expect. Beware stripping the model down too far though. If you take out too much of the realistic diode, you may end up with an idealised device that has inherent 2nd or even first order discontinuities that will make your convergence problems even worse. Silly question though: have you tried putting a 1G resistor in parallel with it? Or adding a few nH in series to model some lead inductance? Often the more realistic the circuit is the better it converges. Cheers, Andy. signality.co.uk On 18 April 2011 18:02, yamazakir2 yamazak...@gmail.com wrote: Does anybody have a nice and simple zener diode model they would like to share? The model that I am using has trouble with convergence in context of a complicated switching circuit with ngspice. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org
Re: gEDA-user: zener diode modeling
Hmmm. Tricky things zener, schottky and soft recovery diode models ... Try a different vendors model (check to see if it is actually a different model)? You could try using a V (voltage) source in series with an ordinary diode plus a second diode in anti-parallel with the series V and diode. This will give you a high reverse drop and a forward drop of a normal diode. The V source is set to the zener voltage minus one diode drop. So if you wanted a 5.6V zener, you set V to about 4.9V and assume about a 0,7V forward drop in the diode. You can play about with the value of V to set the overall drop to where you want it because you don't know exactly what the diode drop will be as it will depend on the diode model and of course the forward current. Or you can start with your existing zener model and play about with the parameters to see if you can make it work. If you make yourself a simple test circuit such as a pulse source with some series R driving the zener with maybe some C in parallel with the diode you can run transient tests on it to make sure you've not set up silly capacitance or transit times or messed up the forward or breakdown voltage to much whilst still giving you something that behaves like the diode you might expect. Beware stripping the model down too far though. If you take out too much of the realistic diode, you may end up with an idealised device that has inherent 2nd or even first order discontinuities that will make your convergence problems even worse. Silly question though: have you tried putting a 1G resistor in parallel with it? Or adding a few nH in series to model some lead inductance? Often the more realistic the circuit is the better it converges. Cheers, Andy. signality.co.uk On 18 April 2011 18:02, yamazakir2 yamazak...@gmail.com wrote: Does anybody have a nice and simple zener diode model they would like to share? The model that I am using has trouble with convergence in context of a complicated switching circuit with ngspice. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
If you are going to model the PA - particularly to look at resonance effects - then you should include reasonably accurate models for the inductors and capacitors which include their major parasitic components. The Murata Chip S-Parameter Impedance Library is a handy tool for looking at their ceramic capacitor and inductor behaviour. http://www.murata.com/products/design_support/mcsil/index.html or there's an online version: http://ds.murata.com/software/simsurfing/en-us/index.html Andy. signality.co.uk On 12 April 2011 23:57, Wojciech Kazubski w...@o2.pl wrote: I'm currently designing a power amplifier for the HF (3-30MHz) radio band. I am selecting capacitors for the low pass harmonic filter bank at the output. My question is what kind of capacitors should I use? I apply not more then 100V of say 30MHz maximum. My best bet is to use X7R capacitors with as much DC voltage rating as I can get. I don't know if there's any connection between the DC and AC losses. Thanks, Levente The biggest problem can be the current handling capacity. Very few capacitor makers specify this. Usually if a capacitor is rated for 100V this means 100V DC wthout any current. Only special purpose capacitors for RF power applications have HF current ratings, see Anerican Technical Ceramics for example: http://www.atceramics.com For RF do not use X5R/X7R (good only for supply bypassing), use NP0/C0G or similar low loss ones. Their maximum capacitance is limited to few nanofarads in 1210 case, so it may be necessary to connect few in parallel to get desired value. Also if you do not have capacitors with high current ratings, connect several smaller ones in parallell instead of one big. Foil type capacitors are suitable for lowest frequencies (LW/MW) and have to be low loss. Polipropylene or teflon ones are low loss and usable, while poliester ones are too lossy. Parasitic inductance can also be a problem. Check your PA circuits with circuit simulator for resonance effects. In this case currents and voltages can be much higher. Wojciech Kazubski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
Uwe is spot on. The capacitance vs. voltage of the X7R dielectric is not very good. NP0/COG are usually specified for precision timing and filter applications. NP0/COG also have a much lower temperature coefficient. Andy. On 11 April 2011 15:58, Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de wrote: Kovacs == Kovacs Levente leventel...@gmail.com writes: Kovacs I'm currently designing a power amplifier for the HF (3-30MHz) Kovacs radio band. Kovacs I am selecting capacitors for the low pass harmonic filter bank Kovacs at the output. My question is what kind of capacitors should I Kovacs use? I apply not more then 100V of say 30MHz maximum. Kovacs My best bet is to use X7R capacitors with as much DC voltage Kovacs rating as I can get. I don't know if there's any connection Kovacs between the DC and AC losses. What value do you need? Try NP0/COG type, even if substantial more expensive. I guess the X ceramic will introduce more harmonics than it will filter out... -- Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt - Tel. 06151 162516 Fax. 06151 164321 -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for spice models that work with ngspice
Fairchild no longer make the 2N3416 so there is no longer a direct link to it. However, after a bit of educated guesswork it turns out that you can still get their model. Follow this link then fill in the form. http://www.fairchildsemi.com/cgi-bin/email_model.cgi?file=2N3416.mod Andy. www.signality.co.uk On 2 March 2011 18:50, Daniel B. Thurman d...@cdkkt.com wrote: On 03/02/2011 10:33 AM, yamazakir2 wrote: unless you need some kind of precision accuracy just use any standard npn model, adjust parasitics and beta based on datasheet On Wed, Mar 2, 2011 at 10:26 AM, Daniel B. Thurman d...@cdkkt.com wrote: On 03/02/2011 10:03 AM, yamazakir2 wrote: regular spice models work for ngspice On Wed, Mar 2, 2011 at 9:55 AM, Daniel B. Thurman d...@cdkkt.com wrote: I am looking for a 2N3416 spice model for ngspice. In any case, where can I look for comprehensive ngspice models? Thanks- Dan Ok... but 2N3416 does not exist in the ngspice library - so where can one get it? Ok, thanks. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another free schematic/PCB tool
:) Andy. www.signality.co.uk On 4 February 2011 21:27, Peter Clifton pc...@cam.ac.uk wrote: On Fri, 2011-02-04 at 13:07 +, Andy Fierman wrote: * Sorry, I can't remember who. John Luciani. I think.. http://www.luciani.org/index.html He has a lot of nice footprints available there. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: MultiSim, Analog Devices Edition
I downloaded a copy something over a year ago. I gave up on it very quickly because (if I remember correctly) it's very limited in terms of circuit size and model and symbol creation/editing. Andy. www.signality.co.uk On 4 February 2011 07:05, Gareth Edwards gar...@edwardsfamily.org.uk wrote: More competition from the free-as-in-beer sector for circuit simulation: http://www.elektor.com/news/free-downloadable-spice-simulator-for-analog.1699331.lynkx Not sure how closely it's 'tailored' towards ADI though. /GDE ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another free schematic/PCB tool
Sorry if I seem a bit scathing but it seems less an interesting article, more a very wordy advert. And I'm struggling with the Open Source part of the title. Free, yes. FOSS; no. As a schematic capture and pcb layout package it looks nice. As an EDA tool it looks a bit thin. And as for: DesignSpark PCB is the world's most powerful free of charge PCB design tool. Ahem, I think there are some folk who would beg to differ. :) Andy. www.signality.co.uk On 4 February 2011 07:17, Gareth Edwards gar...@edwardsfamily.org.uk wrote: Some recent coverage on DesignSpark (written by the TME for the product) in the RS house rag here (p24): http://www.easyflip.co.uk/takeiteasy/rscomponents/eTech_-_Issue_5_UK/enter.html The section Open Source Design Tools in the middle of p25 is worth reading if you can put up with the Flash document reader for long enough to get there. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Another free schematic/PCB tool
Hi Gareth, I understand the connection between RS and the tool and hence why the article reads like an advert. My point is that precisely because it is written by the supplier, the article gives very little useful information about Design Spark PCB or other genuinely FOSS tools that it is actually in competition with. Sure FOSS tools are mentioned but without even a link to give the reader a starting point for a comparison. It is great to see free, unlimited, unclobbered tools being made available but the people behind Design Spark have missed the point of the open source philosophy. Someone* on this list has a tagline along the lines of: You can't design open hardware using closed source tools. Andy. www.signality.co.uk * Sorry, I can't remember who. On 4 February 2011 09:54, Gareth Edwards gar...@edwardsfamily.org.uk wrote: On 4 February 2011 09:28, Andy Fierman andyfier...@signality.co.uk wrote: Sorry if I seem a bit scathing but it seems less an interesting article, more a very wordy advert. It's a house mag, I wouldn't expect any different. My company does one too. If you pay for publishing it, you get to decide what goes in it. And I'm struggling with the Open Source part of the title. Free, yes. FOSS; no. Agreed. Gareth ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Chortle: A Technology Mapping Program for LookupTable-Based Field Programmable Gate Arrays
I reached much the same place ... Is this it? Chortle-Technology Mapping for Lookup Tables (ZIP File) on this page: http://www.eecg.toronto.edu/~jayar/software/software.html Otherwise try contacting Jonathan Rose directly. Andy signality.co.uk On 13 July 2010 15:27, John McCaskill jhmccask...@fastertechnology.com wrote: Here is a web page for one of the papers authors: http://www.eecg.toronto.edu/~jayar/Welcome.html I saw Chortle mention on his pages, but not the source code for it. He did have source code for other projects he is working on, so maybe he can get you a copy. Regards, John McCaskill Faster Technology LLC Xilinx Authorized Training Provider and Alliance partner 1812 Avenue D, Suite 202, Katy, TX 77493 USA Tel: (281) 391-5482, Fax: (281) 391-9384 Email: jhmccask...@fastertechnology.com Web: http://www.fastertechnology.com -Original Message- From: geda-user-boun...@moria.seul.org [mailto:geda-user- boun...@moria.seul.org] On Behalf Of Ronald Mathias Sent: Monday, July 12, 2010 11:15 PM To: geda-user@moria.seul.org Subject: gEDA-user: Chortle: A Technology Mapping Program for LookupTable- Based Field Programmable Gate Arrays Hi, Could any one tell me from where I can download the source code for Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays program. I have tried searching for it on google. I only get the pdf file that describes the program but I am unable to find its source cde. Regards, Ronald ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to use Transformer in gschem
Hi Hari,
If you want to simply model the bidirectional behaviour of a
transformer to see - very roughly - what the input to the transformer
looks like but are not too worried about the ac behaviour then an
ideal transformer like this will do the job.
**
* This is the driving source
**
V1 N002 0 PULSE(0 1 0 10n 10n 5u 10u)
R1 N003 N002 1
**
* Turns ratio
**
.param N=10
**
* This is the transformer.
* Note that R2 provides
* the dc ground return
* path that SPICE
* requires because
* current sources are
* effectively infinite
* impedance.
**
G1 0 N001 N003 0 1
G2 0 N001 N004 0 {1/N}
G3 N003 0 N001 0 1
G4 N004 0 N001 0 {1/N}
R2 N001 0 1G
**
* This is the load
**
R3 N004 0 100
**
* Simulation command
**
.tran 100u
*
It represents an ideal transformer (it works down to DC!) with two
windings. N is the turns ratio.
Although probably not an issue in your application, this tends to run
faster than the K coupled inductor model in switching circuits.
For some more insight into basic transformer modelling including
adding primary and leakage inductances to this ideal DC model, this
page may help:
http://ltwiki.org/index.php5?title=Transformers
Although it is written around LTspice, I think the information on the
ideal transformer with the added elements is valid for - and the
example netlist will run in - Ngspice.
(Note that in this example, the 1G resistor to ground is no longer
needed because the primary inductance Lm provide the DC path.)
The exceptions will be that:
i) Ngspice supports the expression defined behavioural inductor model
(ngspice user manual sect 3.2.10 - 3.2.12) but that is not quite the
same as the LTspice flux defined model;
ii) Ngspice does not have the the same implementation of the Chan
inductor model. However, it does have inductive coupling and core
models (Ngspice manual 13.2.16, 13.2.17).
Non-linear transformer modelling quickly gets to be a full time job
all on its own ...
The Ngspice manual is here:
http://ngspice.sourceforge.net/docs/ngspice21-manual.pdf
:)
Andy.
www.signality.co.uk
On 1 July 2010 18:32, John Doty j...@noqsi.com wrote:
On Jul 1, 2010, at 8:41 AM, hari venkatesh wrote:
I want to simulate a rectifier circuit in gEDA, while i am generating
the netlist for the circuit.
i have given the refdes as T1, during netlist generation it is giving
error, refdes=T1 not found
Could u please mail me the list attributes that should be attached for
the transformer
Eg: refdes, value, model, footprint etc
Modeling transformers in SPICE requires some specialized knowledge. SPICE
represents a transformer as inductors (Lelements) with mutual inductance
coupling (K elements). The catalog specs typically do not include the
necessary information to formulate such a model, so measurement or informed
guesswork is required.
Probably the easiest solution is to use a AC independent source (vac-1.sym in
gschem) to drive the rectifier, and forget about modeling the transformer.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
j...@noqsi.com
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Audio processing
Another problem is that the ear is very sensitive to the delay between the note being struck and the actual sound being produced. The processing delay has to be in the order of a few milliseconds or life gets very confusing for the player and any other listeners. The guitars Roland built for their guitar synthesisers around the 1980's used seperate pickups for each string. http://www.synthmuseum.com/roland/rolgr30001.html There's info floating about the web on how they worked and how they fed signals back to each string through a drive head to turn the strings into oscillators and so get infinite sustain. The early versions struggled to keep up with playing faster riffs etc. The later ones were better but even they struggled with the virtuoso players. The SynthAxe went to the extreme of only having the strings as a mechanism to connect to the frets to determine pitch with some sort of strain gauge to define pitch bend per string. It used 2 sets of strings, one on the neck for pitch and a second short set for triggering and envelope generation: start, decay and amplitude of notes etc. http://en.wikipedia.org/wiki/SynthAxe An amazing performance machine but so expensive. Cheers, Andy. On 14 April 2010 23:59, Dave McGuire mcgu...@neurotica.com wrote: On 4/14/10 6:44 PM, John Doty wrote: Why is disentangling the chords any more difficult than looking at the frequency spectrum and picking out the peaks? Because a note isn't a pure tone. If you see 1319 Hz, is that E6 or the third harmonic of A4? The spectrum will contain many more peaks than there are notes. Then, you might have half a dozen instruments, some (guitar, piano, ...) emitting multiple notes. So, what chord is the guitar player playing? A I see, ok. I suppose they're nowhere near sinusoidal. I was thinking in those terms. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
Could be interesting. Thanks for that! Cheers, Andy. Signality Solutions York, UK t: +44 (0) 5601 720 580 m: +44 (0) 7796 538 192 skype: andyfierman www.signality.co.uk On 24 February 2010 15:12, Kai-Martin Knaak k...@familieknaak.de wrote: I just got aware of the open source mechanical CAD project freecad. It hit the debian repository a month ago. Although it is still lacking important features, much of the basic infrastructure is already up and running. http://en.wikipedia.org/wiki/FreeCAD_(Juergen_Riegel) ---(kaimartin) -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Getting new linux, which distribution?
Larry, Are you thinking of this: http://www.liquidpcb.org/index.html ? Cheers, Andy. Signality Solutions t: +44 (0) 5601 720 580 m: +44 (0) 7796 538 192 skype: andyfierman www.signality.co.uk On 21 February 2010 03:20, Larry Battraw lbatt...@gmail.com wrote: I had a quick question. I know there are several sparsely-documented plugins for PCB but I am trying to locate the one that makes the traces on the board look like they were laid out by hand the old-fashioned way with tape, resulting in curving, contoured traces instead of the standard auto-routed straight X/Y traces generated by default. As I recall you would route your board and then run this plugin as the final step since editing it afterwards was virtually impossible. Am I thinking of a different pcb layout program or does this plugin exist somewhere? Thanks- Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TL431
Hi Gene, As has already been mentioned, the problem will be what happens as the supply turns on. In theory, as VCC ramps up, the 431 will start to regulate and so limit its own cathode voltage. However, there may be a delay before this starts to happen (due to the devices internal startup and any external capacitances). If VCC exceeds 36V before the 431 has started drawing current then all bets are off. Crude but you could try putting a zener in series with R3/NPN_B and 431 cathode to drop the excess voltage so that VCC - Vzen 36V. Another caution with 431's: check the specs of them carefully as they vary a lot from one manufacturers to another. And another: they are notoriously unstable (and the spice models don't always show it) with certain cathode loads. I think it's either National or TI that if you look closely at the curves on the datasheet and some of the small print notes it hints that this happens but is unclear about where and how. That said, I have used them to make an adjustable 75V - 35V series regulator running from 80V. If you use an NPN cascode like this you can limit the max cathode voltage by setting Vref 36V + Vbe where Vbe is the base emitter drop of the NPN cascode. (npn) VCC -- C E -- | \ /| / -/ R3 \| B\ /| / R1 || \ | / | | |/ C | Vref--| NPN | |\ E | | | | | --/ | / / \ | TL431 / \- -| | / | \ R2 | / | | | | | / / / Vref can be derived from a resistive divider or a zener reference. This can be made to work but is tricky to compensate (see above). Even though it should be OK as drawn, in practice, it will probably need a resistor in series with the cascode emitter and a cap from the 431 cathode to its adjustment pin. All in all, may be more trouble than it's worth. Cheers, Andy. Signality Solutions t: +44 (0) 5601 720 580 m: +44 (0) 7796 538 192 skype: andyfierman www.signality.co.uk On 21 February 2010 01:54, gene glick carzr...@optonline.net wrote: Wojciech Kazubski wrote: - Anyone use these shunt regulators? I'm wondering about the max voltage. Or set up your mailer to use a fixed-width font.. Yes, that was it - thanks. I suspect this TL431 isn't a good device for my app. I have an LM317 to give me around +12V for bootstap voltage to a high-side mosfet driver. The average current is very low, but the peaks can get pretty high. The LM317 circuit is solid, just uses a lot of parts. I was trying to replace the LM317 with TL431 - but simulation does not look promising. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new components
Hi Chris, Welcome to the free world! If you've not already found it, a good place to start is here: http://geda.seul.org/wiki/geda:gsch2pcb_tutorial then have a good read of: http://geda.seul.org/wiki/geda:gschem_symbol_creation and http://geda.seul.org/wiki/geda:transistor_guide Then have a look at this bit of the FAQ here: http://geda.seul.org/wiki/geda:faq-gschem#gschem_symbols I only suggest doing it that way round because otherwise you may get distracted by the rest of the FAQ ... and when it comes to PCB footprints, I'd recommend you read this first: http://www.brorson.com/gEDA/land_patterns_20070818.odf or http://www.brorson.com/gEDA/land_patterns_20070818.pdf from: http://www.brorson.com/gEDA/ and then go back to: FAQs Quick Reference http://geda.seul.org/wiki/ :) Cheers, Andy. Signality Solutions t: +44 (0) 5601 720 580 m: +44 (0) 7796 538 192 skype: andyfierman www.signality.co.uk On 2 February 2010 13:32, Chris Cole cle...@gmail.com wrote: Hey all, I'm new to the gEDA community (and fairly new to electronics in general), and I have a pretty simple question for the gurus. I was working on converting a PIC project schematic into gschem when I realized that none of the Microchip IC's I was using were in the component library. What's the standard procedure for this? Is it easier to mooch off an existing part or to create your own? Thanks, Chris ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT diode reverse saturation current
Hi Gene, The usually quoted formula is: IS = A*exp(-Eg/(k*T) Where IS = saturation current, A is nearly constant independent of temperature and dependent on diffusion coefficients of electrons and holes. k is the Boltzmann constant. ν is a constant; 1 for germanium and 2 for silicon; and T is the absolute temperature (deg Kelvin). Eg is the band gap of the semiconductor. The band gap of silicon is 1.12eV and that of germanium 0.66eV. According to this formula, IS doubles for approx 5degC rise in temperature for silicon and 8degC for germanium. However, the reality is somewhat different and a better approximation(i) is this: IS = A*T^m*exp(-Eg/(n*k*T)) Where IS = saturation current, A is a constant independent of temperature and dependent on diffusion coefficients of electrons and holes. k is the Boltzmann constant. T is the absolute temperature (deg Kelvin). m is a constant; 1.5 for silicon and 2 for germanium. n is a constant; 1 for germanium and 2 for silicon Eg is the band gap of the semiconductor. The band gap of silicon is 1.12eV and that of germanium 0.66eV. I think the formula holds for GaAs and other semiconductor junction diodes but the various constant will be different. I'm not sure how IS varies for schottky (metal-semiconductor junction) diodes. This also assumes that the reverse bias is not high enough to cause any zener or avalanche breakdown effects that contribute to the reverse leakage current. Cheers, Andy. www.signality.co.uk (i) Integrated Electronics. Millman and Halkias (International Student Edition) 1972 Lib Cong Cat Card # 79-172657 p752 sect 19.11 2009/12/1 gene glick carzr...@optonline.net: I'm trying to find some info on the temperature variation of the reverse saturation current of a diode. Anyone know about this? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Analog books
Now don't open your presents all at once! Save some to read for the rest of those long dark winter nights . :) Cheers, Andy. www.signality.co.uk 2009/11/24 Karl Hammar k...@aspodata.se: A lot of people responding: On Tue, Nov 24, 2009 at 9:34 AM, Karl Hammar k...@aspodata.se wrote: Can anyone recommend some good books on analog circuit design for audio, precision/low noise op.amp., emc, active filters and similar ? ... Thank you all, this is like Christmas... Regards, /Karl --- Karl Hammar Aspö Data k...@aspodata.se Lilla Aspö 148 Networks S-742 94 Östhammar +46 173 140 57 Computers Sweden +46 70 511 97 84 Consulting --- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Books about PCB design
Hi Torsten, Have a wander round: http://www.cherryclough.com/Pages/Publications%20and%20downloads.htm and http://www.signalintegrity.com/ After all, push your signal fast enough and you can no longer treat the PCB and the schematic as separate entities. Cheers, Andy. www.signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Analog books
Hi Karl, It's worth having a look around Doug Self's site: http://www.dself.dsl.pipex.com/ampins/ampins.htm A lot of the info has been removed in advance of his publishing a new book but there's a lot of other stuff there and pointers to more. Andy. www.signality.co.uk 2009/11/24 John Luciani jluci...@gmail.com: On Tue, Nov 24, 2009 at 9:34 AM, Karl Hammar [1]k...@aspodata.se wrote: Can anyone recommend some good books on analog circuit design for audio, precision/low noise op.amp., emc, active filters and similar ? National Semiconductor use to publish the Audio/Radio Handbook. IIRC a third party is now publishing it. Precision Monolithics (PMI) also had an audio handbook. Not as much detail as the National book. You may want to post on the synth-diy list as well. (* jcl *) -- You can't create open hardware with closed EDA tools. twitter: [2]http://twitter.com/jluciani blog: [3]http://www.luciani.org References 1. mailto:k...@aspodata.se 2. http://twitter.com/jluciani 3. http://www.luciani.org/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: opamp slew rate limiting
Hi Gene, Some more things to think about as sanity checks. Following on from Peter's question, what is the gain of your amplifier (including any effects of the source resistance if it's an inverting amplifier configuration)? You say that The gain is sufficiently large that the opamp is driven into saturation by the sine wave but by how much is it driven into saturation? Just near the peaks and troughs or very close to the zero crossings? As has been alluded to already, the slew rate of the opamp is usually specified for the device operating in the linear region. If it is being driven hard into saturation then there will be some recovery time before the output can drag itself. out of saturation as the signal changes direction. Don't be misled by the Large signal step response diagram in the TI datasheet (top right p6 June 2004). The output is only swinging +/-10V from a +/-15V supply so it is not in saturation. Another potential gotcha is how much stray capacitance is there between the output and the inverting input of the device? Have you got an accidental integrator? Cheers, Andy. http://signality.co.uk 2009/11/10 Peter TB Brett pe...@peter-b.co.uk: On Tue, 10 Nov 2009 01:58:26 + (GMT), carzr...@optonline.net wrote: I have a problem with an opamp at work and was hoping someone may have some insight. This particular opamp is opa2132 from TI, and has slew rate of about 20 V/us. It's driven by a sine wave at 5 kHz. The gain is sufficiently large that the opamp is driven into saturation by the sine wave and the slew rate limited edges are very obvious. The rails are +/- 7.5V and it is able to drive to about +/- 6V. It is connected to an old CD40106 schmitt trigger inverter. Here's the rub. The opa2132 doesn't run anywhere near the advertised 20V/uS spec. I see, at best, around 15V / 12 uS, or about 1 or 2 V/ uS. Not even close to spec. I am fairly certain that the schmitt trigger responds poorly to the very slow edges from the opamp. I happen to use 2 channels of this, and the phase relationship is very important - but it gets destroyed through the schmitt trigger. I've gone as far as removing all loads from the opa2132, and it doesn't change the slew rate. The data sheet has a drawing with 'large signal step response', and it shows the part slewing around 15 or 20V in 1 uS. Not bad. So what have I done wrong? They do claim it's with a gain of -1, but I don't see how that has anything to do with it. What's the op-amp's gain-bandwidth product? Peter -- Peter Brett pe...@peter-b.co.uk Remote Sensing Research Group Surrey Space Centre ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: opamp slew rate limiting
For the opa2132, it's not clear what the slew rate would do as it comes out of saturation but it may well only really add some delay rather than reduce the slew rate. Using opamps as comparators can be tricky. Alan's suggestion of using something from the LM339 / LM2907 / LM3302 comparator family might be a better idea. Then you don't have to worry so much about common mode or differential voltage ranges as you do with an opamp. Anyway, hopefully we've set you on the right track. :) Andy. http://signality.co.uk 2009/11/10 gene glick carzr...@optonline.net: The gain is set at -10. The prior stage has gain, and off-hand I don't recall how large the signal is, I'll check. GBW for the part is 8MHz, I run it at 5kHz*10= 50 kHz GBW - plenty of headroom there. SR definition is SR = 2 * pi * f * Vpk So I need SR 6.28 * 5000 cycles/sec * 15 Volts, or 471,000 Volts/Second. If my math is right, that works out to 0.471 V/uS. Lots of margin there too, the part can do 20. I agree about the linear/saturation description, but couldn't find any hard literature on the subject. I removed all external capacitance, so all that remains is stray - hopefully small. You say that The gain is sufficiently large that the opamp is driven into saturation by the sine wave but by how much is it driven into saturation? Just near the peaks and troughs or very close to the zero crossings? great point. Maybe I should increase the gain to force the saturation earlier into the cycle. I was trying just the opposite. Ozzy Lash wrote: Are you sure your not just tracking the slow edge of the sine wave? Your 12 microseconds is about 20 degrees for your 5 kHz sinusoid. If you increase the frequency does the edge steepen? Does the slew rate go up and down as you increase and decrease the amplitude of the sinusoid? If so, I think that is your problem Bill Yeah, I now think this is the case. As has been alluded to already, the slew rate of the opamp is usually specified for the device operating in the linear region. If it is being driven hard into saturation then there will be some recovery time before the output can drag itself. out of saturation as the signal changes direction. Yeah, I thought the same thing. Wouldn't that just add delay, but not change the slew rate once it comes out of saturation? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
There are some nice little tools to show the behaviour of multilayer chip ceramics (and some of Murata's inductors) Although they don't include their single layer microwave caps in the database, the Murata Chip Capacitor and Inductor S-Parameter Impedance Library program from here: http://www.murata.com/products/design_support/mcsil/exe/mcsil-setup.exe (This one runs OK on Linux too using WINE: http://appdb.winehq.org/objectManager.php?sClass=versioniId=18139) And as similar tool from Cap Cal from here: http://www.dilabs.com/UserFiles/File/CapCadv302.exe Fun to play with and give a good feel for how the caps and their parasitics behave. Single layer uwave caps may have a lower series L than MLCC parts but it's not clear from many of the manufacturers data. By their nature they are only available in relatively low capacitances (up to a couple of nF). As Neil Hendin explained, using supply traces rather than planes can lead to resonance problems which may then need extra decouplers to, in effect, tune these resonances out of you working frequency range. For RF and microwave stuff that is fine but for the more broadband and digital circuitry this is a real challenge. At high enough frequencies you may be able to use the supply trace skin effect resistance to help damp any resonances. A further complication is that when you put several decouplers of different values in parallel, you get unwanted resonances between the series inductance of one cap and capacitance of another. This can introduce some very wild parallel resonances where the supply suddenly becomes high impedance to ground. Other series resonances from each cap can form between the parallel ones to make a highly complex (!) supply impedance. These resonances aren't well behaved because the parasitics they are caused by are not specified in the device datasheets so they should not be relied on to do things like null out clock noise on Vcc rails. As Gene's commented, very careful attention must be given to how any decoupling cap is physically connected: the series L of MLCC's is so small it can easily be swamped by the external PCB trace used to connect it to the device and to ground. If you have the component side signal layer over a ground plane then using a small supply plane (via'd to the internal supply plane or tracked to the nearest Vcc) directly under a chip with the decouplers connected off that can create a very effective decoupling scheme. The plane reduces the Vcc supply inductance at the device pins and provides a very small but reasonably high quality decoupling C directly at the device pins. The larger lower frequency decoupling can then be located a little further away. There's a very nice apps note showing that here: http://www94.web.cern.ch/HSI/s-link/devices/g-ldc/decouple.pdf It was originally from Cypress but seems to have disappeared from their website. Andy. www.signality.co.uk 2009/10/20 Gabriel Paubert paub...@iram.es: On Mon, Oct 19, 2009 at 06:43:42PM -0500, Darrell Harmon wrote: On Mon, Oct 19, 2009 at 5:27 PM, Dan McMahill d...@mcmahill.net wrote: my recent experiences are more in line with Larry's. Most C for a given package and voltage seems to be the best meaning that above resonance it is no worse than smaller capacitance value devices and below resonance it is better. And yes, this seems to fly in the face of what has been recommended in the past. I've not done any careful measurements of older technology bypass caps but I wonder if this is one of those rules which became obsolete 15-20 years ago and no one noticed... -Dan I have done some testing of various passives (mostly 0402) and came to the conclusion. I tested both shunt and series capacitors on a 50 ohm transmission line with a VNA. What was most interesting to me was that the large value capacitors performed better as series coupling caps than the small ones. The single layer caps in the 1 to 100 pF range frequently had parallel resonances in the 10 to 30 GHz range. Most of the multilayer caps (10 nF to 1 uF) performed well to at least 30 GHz. And for the shunt case? Some manufacturers (ATC, Dielectric Labs) also offer specific broadband coupling capacitors, did you try them? Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eliminate separate Vcc planes?
So your consultant thinks it's a bad idea to have a Vcc plane because it takes up space that you could use for additional ground planes and that you might need to run traces ... ... and then urges you to run power traces where? In the - now empty - Vcc plane layer? Or in the same layer as your already (according to your consultant) full signal layers, leaving you a whole layer to put a shiny new ground plane into? Hmmm. Suppose you have a 6 layer PCB with one continuous ground pane and one continuous Vcc plane (dream on ...). It's not ideal but not everyone wants to pay the extra for 8 layers. layer 1 = signal (set up for 50R trace impedance w.r.t. ground plane) : small spacing : layer 2 = ground plane : small spacing : layer 3 = signal (set up for 50R trace impedance w.r.t. ground plane) : big spacing! (to minimise Xtalk between layers 3 to 4) : layer 4 = signal (set up for 50R trace impedance w.r.t. Vcc plane) : small spacing : layer 5 = power plane : small spacing (set up for 50R trace impedance w.r.t. Vcc plane) : layer 6 = signal All the return currents for signals on layers 4 6 run over the power plane until they get decoupled to layer 2 ground plane. Not ideal but if the Vcc plane is properly decoupled to the ground plane with good ceramic decouplers adjacent to all signal sources and destinations (some of which may be dedicated and some shared Vcc decouplers anyway) then that is OK. (Note that with 6 layers you cannot gain much from the capacitance between the ground and Vcc planes because you have two signal layers sandwiched between them and so must keep those traces far enough apart to keep the crosstalk between them negligible.) And then you remove the plane from layer 5 .. The return currents for layers 4 6 now run in layer 2 ground but the trace impedances have skyrocketed because their image plane is now many times further away. Crosstalk between signals on layer 4 and on layer 6 is now huge because it is proportional to 1/(1+(D/H)^2) where D is the spacing between the adjacent traces on a layer and H is the height above the image (ground) plane. Crosstalk between signals on layer 6, 4 and 3 is now also huge because they are no longer screened or effectively separated from each other. Oh and you might be putting signals on layer 5 too? The reduction of the total copper available to supply current to the devices is slashed because it's only through individual traces. Voltage drops increase due to the DC resistive losses. Dynamic voltage drops increase due to the residual switching currents that the discrete decoupling cannot remove being drawn through the increased inductance and skin effect resistance of the supply traces rather than a low inductance Vcc plane. If you replace the Vcc plane with a ground plane then that would be nearly ideal (assuming you properly via the two ground planes together to keep the return path currents close to any signal vias that transfer signals on traces referred to one ground plane to traces referred to the other). But if you could do that then wouldn't you have done it to start with? As for the assumption that you put signal traces into a Vcc plane layer. There are cases where you might have to but if you are so worried about running out of routing space and can afford to replace the power plane with a ground plane then you should not be putting traces into that Vcc plane in the first place. As you say, if your running stuff around in the GHz region then this is just a nonsense. Even the very best ceramic caps still look inductive much above 1GHz so they are still far from the ideal parts you'd like to be able to sprinkle like fairy dust over all your noisy parts and for you return paths. As you mention; if you have a multi-rail system then you either have a power plane layer that looks like the classic Patchwork fields of England with lots of plane breaks (in which case you may have a problem waiting to catch you out) or you already have a PCB with extra layers in it to accommodate all these planes. I can't see this advice catching on in many of those well known whizzy processor motherboards. Sorry if this seems like a bit of a rant or if you feel I have offended your Grandmothers legendary egg sucking abilities but ... Hopefully you can gently persuade your boss that this is not quite what the very expensive consultant meant to say. And I'll just go and calm down now. Cheers, Andy. www.signality.co.uk 2009/10/19 Bob Paddock graceindustr...@gmail.com: Boss just sent around something he got from a consultant on doing proper EMI design (which I've been doing for years already, I thought until consultant came up with this): Eliminate separate Vcc planes. This ancient practice is long overdue for an overhaul. Years ago, the leaded capacitors were not able to provide a good enough short at VHF and above, so the reasoning was that the parallel plates of Vcc and ground made a
Re: gEDA-user: TI CC2480 ZigBee (off-topic)
Please excuse me if if I haven't understood your question correctly but if your question is about making a PCB element then would this help? http://www.geda.seul.org/wiki/geda:pcb_tips and in particular, http://brorson.com/gEDA/land_patterns_20070818.pdf Andy. 2009/9/10 Goran Mekić m...@ns-linux.org: Is there a document on how to make an element with multiple slots (2 for start)? Thanx! -- FreeB(eer)S(ex)D(rugs) are the real daemons ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: Is it possible to draw a thicker net?
Hi Robert, I think if you look for the system-gschemrc file (probably in /etc/gEDA/) then you'll find a section in there ; net-style string ; ; Set to thin if you want thin nets. ; Set to thick if you want thick nets. ; This mode also determines what net style gets printed ; ;(net-style thin) (net-style thick) (there are similar sections below that for bus, pin and line styles) If you net style edit this file (as root) then you'll alter the net style for all new schematics (after a quick check: it seems to apply to all schematics as they are opened). Now, if you read through this: http://geda.seul.org/wiki/geda:gsch2pcb_tutorial and look carefully at the section on Setup you'll see that you can put a gschemrc file into ~/.gEDA that will allow you to set any preferred net style for all your projects. I think it is possible to put a gschemrc file in each project that will apply just to that project but I haven't managed to make that work in a quick play. I'm sure there are people with more experience who can tell you about some of the other ways that you can customise gEDA but I hope this gets you off in the right direction. Cheers, Andy. http://signality.co.uk 2009/9/3 myken my...@iae.nl: Hallo all, I'm new to this mailinglist so please be gentle. My question: Is it possible to make a net thicker in gschem (not a line but a net). I want to indicate in my schematic than the net is a high current power net. Thanks for your answers. Best regards, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Multivibrator Simulation
Hi Micheal, Sorry about that, Al Davis is right, OFF doesn't seem to help. Here are two ways to fix the problem. 1) As has already been described, if you start the simulation with the supply voltage at 9V but apply an initial condition of 0V to one of the transistor bases - using the .IC spice directive - then oscillation should start. The initial condition forces one transistor off while the other is on and then lets it go. This then starts the first cycle at time zero. Here's a netlist that does that: --- V1 V1_P 0 9 R1 V1_P R1_N 15k R2 V1_P R2_N 15k R3 V1_P R3_N 1K R4 V1_P R4_N 1K .IC V(R2_N)=0 ; this is the initial condition Q1 R3_N R2_N 0 0 Q2N3904 Q2 R4_N R1_N 0 0 Q2N3904 C1 R1_N R3_N 10u C2 R4_N R2_N 10u --- 2) Alternatively, if you do two things, it will start oscillating. i) make the 9V supply ramp up from zero at the start of the simulation. A short rise time of about 100n should be OK. ii) make one of the base resistors slightly different from the other. A difference of even 1 Ohm will do it. This adds a slight imbalance to an otherwise perfectly balanced circuit. The supply ramp up than acts to turn one transistor on slightly before the other setting up the initial conditions for the first cycle just after time zero. And here's a netlist that does that: --- V1 V1_P 0 Pulse(0 9 0 100n 100n) ; this is the supply ramp R1 V1_P R1_N 15k R2 V1_P R2_N 15.001k ; this is the base resistor imbalance. R3 V1_P R3_N 1K R4 V1_P R4_N 1K Q1 R3_N R2_N 0 0 Q2N3904 Q2 R4_N R1_N 0 0 Q2N3904 C1 R1_N R3_N 10u C2 R4_N R2_N 10u --- Try running them for about 500ms to see how the oscillations start up. I've not used gnucap or ngspice yet so I'm not familiar with how you drive them. You may need to add the transistor models to my netlists. --- .model Q2N3904 npn ( IS=2.48E-13 VAF=101.7 BF=400 IKF=0.0334 NE=1.5243 +ISE=2.113E-12 IKR=0.02 ISC=5.00E-12 NC=1.1 NR=1 BR=10 RC=0.5 CJC=3.50E-12 +FC=0.5 MJC=0.25 VJC=0.7 CJE=4.50E-12 MJE=0.33 VJE=0.75 TF=2.80E-10 +ITF=0.4 VTF=2 XTF=10 RE=1 TR=8.00E-07) *From NS Discrete 1978, Motorola DL126/D rev 4 - Process 66 * Base resistance not modelled - no info. --- Cheers, Andy. http://signality.co.uk 2009/6/23 al davis ad...@freeelectron.net: On Tuesday 23 June 2009, Michael B Allen wrote: *== Begin SPICE netlist of main design Q2 output 2 0 2N3904 .MODEL 2N3904 NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734 Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb) This syntax is incorrect .. Rb) ??? V1 4 0 DC 9V R4 output 4 0.999K Q1 1 3 0 2N3904 .MODEL 2N3904 NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734 Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10) syntax correct this time, but there should be only one .model statement. R3 1 4 1.001K R2 3 4 15K R1 2 4 15K C2 output 3 10uF C1 1 2 10uF .end You need to explicitly start the oscillator. I'm not having any luck with this. It seems the syntax of netlist vs. interpreter mode commands vs. gspiceui fields is different enough that it's totally unclear as to how to achieve non-trival things. Why I don't like the GUI .. There are hundreds of things you can do. The GUI gives you about three of them. First, do I want to use GNU-Cap or NG-Spice? Gnucap, if you want my help. If you are really into it, try both and you will see that some things work better in one, some in the other. Also, what timing do I want? I was thinking something like 50ms - 100ms in 1ms increments reasoning that it will take time for the oscillation to start. It depends on your circuit. What frequency did you design it for. You need to run it a while to start up. See the example I referenced in the other mail. Regarding simulating power on, I don't recognize the format on the page cited: Vcc (vcc 0) pulse(iv=0 pv=12 rise=.01) My netlist above does not have parenthesis. Parenthesis are optional, but make it easier to read. And it seems gspiceui overrules the voltage source properties anyway? I think you put the whole string pulse ( ...) as the value in the schematic. With Spice, you list a bunch of numbers in a particular order. Gnucap accepts that too, but I can never remember what order they go in, so the labels are a better way to do it. That statement says the initial value (iv) is 0, pulsed (final) value (pv) is 12, and the rise time is .01 seconds. Look up the pulse http://gnucap.org/gnucap-man-html/gnucap-man094.html Similarly I'm not sure where the OFF
Re: gEDA-user: Multivibrator Simulation
Hi Michael, Another way to do this is to use the OFF option in the bipolar transistor model to force one of the transistors into a known initial state. I'm not sure how you introduce this parameter into you particular simulation schematic, you may have to just hand edit the device model in your spice netlist. Here's an example of the model options similar to what you'll find in most generic Spice device documentation. - Q collector base emitter [substrate] modelname [area] [OFF] [IC=vbe,vce] [TEMP=local_temp] [M=mult] [DTEMP=dtemp] collector Collector node name baseBase node name emitter Emitter node name substrate Substrate node name modelname Name of model. Must begin with a letter but can contain any character except whitespace and ' . ' . areaArea multiplying factor. Area scales up the device. E.g. an area of 3 would make the device behave like 3 transistors in parallel. Default is 1. OFF Instructs the simulator to calculate operating point analysis with the device initially off. This is used in latching circuits such as thyristors and bistables to induce a particular state. - Notes about ‘OFF’ Parameters: Some semiconductor devices such as diodes, bipolar and MOSFET transistors feature the device parameter OFF. If there are devices in the circuit which specify this parameter, the bias point solution is found in two stages. In the first stage, the devices with OFF specified are treated as if their output terminals are open circuit and the operating point algorithm completes to convergence. In the second stage, the OFF state is then released and the solution restarted but initialised with the results of the first stage. The result of this procedure is that OFF devices that are part of latching circuits are induced to be in the OFF state. Note that the OFF parameter only affects circuits that have more than one possible DC solution such as bistables. Specifying the OFF parameter in a non-latching circuit such as an amplifier which will generally have a unique solution, will work OK but may slow down arrival at the correct final state. the same. It will just take a little longer to arrive at it. Other ways already mentioned in this thread that will usually start up circuits in unstable equilibrium are to introduce a ramp or small step in the power supply voltage . Cheers, Andy. http://signality.co.uk 2009/6/23 John Doty j...@noqsi.com: On Jun 23, 2009, at 9:45 AM, Michael B Allen wrote: I'm trying to run a simple multivibrator simulation but both SPICE and GNU-Cap do not yield anything that even oscillates. Here is the circuit: http://207.192.69.113/~miallen/mv_1.pdf Is there anything wrong with this? Is there any trick to getting something like this to work? You've created a simulation of a pencil perfectly balanced on its point. Break the symmetry somehow. Lots of ways to do it: Change one of your resistor values a skosh. They won't be perfectly equal in reality anyway. Or use different transistor models. Or force one of the node voltages away from equilibrium with a .IC command and specify UIC in your .TRAN command. Or force the charge on your capacitors away from equilibrium with IC=, and UIC as above. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprints with mounting holes
Add the pins to the symbol, name them as already suggested and then in schematic add one of the not connected symbols (nc-bottom/left/right/top-1.sym in the Misc unsorted symbols library) to each pin. That should ensure that all the pins in the symbol and the footprint then match but the nc symbols stop them all being connected together. Of course, you may want them all connected to ground or some other rail but if the pins are there, you can connect them as you like. Andy. www.signality.co.uk 2009/6/13 DJ Delorie d...@delorie.com: I usually name those pins like M1 M2 etc. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Footprints with mounting holes
I think I put that badly. The nc symbols are purely for visual purposes. They don't of themselves stop nets or pins being connected together. However, if they are placed directly on any pin that is to be left unconnected then it is made clear that there is no net connected to those pins. Playing with PCB just now it seems that if pins are left just with dangling nets (a pin with a single connection to a net that goes nowhere else), as long as the nets have unique names then even if the pins on the symbol have the same pinlabel and pinnumber attributes and the pin numbers on the footprint are the same, they do not show up as being connected together in PCB. After going through the steps of gsch2pcb, the rats nest shows no connection between unconnected pins. Not sure if that makes it any clearer though. :) Andy. http://signality.co.uk 2009/6/15 Stefan Salewski m...@ssalewski.de: On Mon, 2009-06-15 at 10:27 +0100, Andy Fierman wrote: Add the pins to the symbol, name them as already suggested and then in schematic add one of the not connected symbols (nc-bottom/left/right/top-1.sym in the Misc unsorted symbols library) to each pin. That should ensure that all the pins in the symbol and the footprint then match but the nc symbols stop them all being connected together. Of course, you may want them all connected to ground or some other rail but if the pins are there, you can connect them as you like. Andy. This info about the nc symbols is new for me -- I was thinking that they are only for visual purposes. Are they magic? I think pins or pads of a footprint with the same name are always electrically connected in PCB. Pins or Pads for which there is no identical pinname in a gschem schematic symbols remain unconnected to other copper. (Additional there are the unplated holes, which have no copper and can not connect to something.) If the nc symbols really have any magic -- is there a description about this in the wiki? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Question about gschem DRC errors when using separate power pin symbols.
Hi, I'm puzzled by a couple of gschem DRC errors I'm getting. I'm using Stefan Salewski's quad comparator symbol with the separate power pins symbol. I have four comparators plus the power pin symbol all with the refdes of U1. All symbols are given an SO14.fp footprint. When I run: gnetlist -g drc2 hv-psu_090608.sch -o drc_output.txt I get errors. Here's the message: --- gEDA/gnetlist version 1.4.0.20080127 gEDA/gnetlist comes with ABSOLUTELY NO WARRANTY; see COPYING for more details. This is free software, and you are welcome to redistribute it under certain conditions; please see the COPYING file for more details. Remember to check that your schematic has no errors using the drc2 backend. You can do it running 'gnetlist -g drc2 your_schematic.sch -o drc_output.txt' and seeing the contents of the file drc_output.txt. Loading schematic [/home/andyfierman/gaf/projects/hv-psu/RC1/hv-psu_090608.sch] DRC errors found. See output file. --- and when I check the output file (drc_output.txt), I can see that the errors are due to the duplicate reference to U1. --- Checking non-numbered parts... Checking duplicated references... ERROR: Duplicated reference U1. Checking nets with only one connection... Checking pins without the 'pintype' attribute... Checking type of pins connected to a net... Checking unconnected pins... Checking slots... Checking duplicated slots... ERROR: duplicated slot 1 of uref U1 Checking unused slots... No warnings found. Found 2 errors. --- Running this schematic through gsch2pcb works OK: I get no problems in PCB and all the pins on U1 are connected correctly. Reading the FAQ at: http://geda.seul.org/wiki/geda:faq-gschem#what_should_i_do_about_power_pins_on_my_symbolsmake_them_visible_explicit_or_invisible_implicit tells me: --- That said, it may still be useful to detach the power pins from the functional part of the symbol. To do so, define a seperate power symbol and give it the same refdes as the functional part. A run of gsch2pcb will treat the siblings properly as one single component. As neither gschem nor gsch2pcb explicitely know that the component is only complete with both symbols defined, you have to check yourself. With this workaround, you can draw all power related circuitry in one corner of the schematic where it does not interfere with the signal nets. In many cases this is advantageous with analog circuits. --- ** Therefore, my question is this: are the gschem DRC errors for such symbols to be expected? Any insight on this would be gratefully received. Thanks, Andy http://signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Question about gschem DRC errors when using separate power pin symbols.
Hi John, The comparator symbol has a numslots and slotdef attributes and I have edited the slot attribute for each. The power pin symbol does not have a numslots or any slotdef attributes. I've got the right pinout for each of the four comparator symbols in gschem and as I say, the connectivity is right in PCB. For info, the symbols I'm using come from here: http://www.gedasymbols.org/scripts/search.cgi?key=lm339 Andy. http://signality.co.uk 2009/6/11 John Luciani jluci...@gmail.com: Did you change the slot attribute for each of the comparators? (* jcl *) -- You can't create open hardware with closed EDA tools. http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Question about gschem DRC errors when using separate power pin symbols.
Perhaps I should ask a different question then Is there a better tool to use for gschem DRC? In the meanwhile, I think I may add a comment to the pwr pins symbol to remind me that it will show up a refdes and slot error. :) I think that answers my question Thanks, Andy. http://signality.co.uk 2009/6/11 John Doty j...@noqsi.com: drc2 has a very narrow view of how the world works. If you are doing a pure digital design using a single logic family using hidden power pins, it's not *too* bad. But generally, it hides real errors behind a flood of messages about things that aren't errors at all. gEDA is much more flexible than drc2 understands. It's generally only useful if you've learned to find the few real issues in the flood. DEVELOPERS: WHY DO WE RECOMMEND THIS FLAWED, NARROW, EXPERT TOOL, REPEATEDLY AND OBNOXIOUSLY, TO ALL WHO USE GNETLIST, EVERY TIME THEY USE IT? On Jun 11, 2009, at 10:28 AM, Andy Fierman wrote: Hi, I'm puzzled by a couple of gschem DRC errors I'm getting. I'm using Stefan Salewski's quad comparator symbol with the separate power pins symbol. I have four comparators plus the power pin symbol all with the refdes of U1. All symbols are given an SO14.fp footprint. When I run: gnetlist -g drc2 hv-psu_090608.sch -o drc_output.txt I get errors. Here's the message: --- gEDA/gnetlist version 1.4.0.20080127 gEDA/gnetlist comes with ABSOLUTELY NO WARRANTY; see COPYING for more details. This is free software, and you are welcome to redistribute it under certain conditions; please see the COPYING file for more details. Remember to check that your schematic has no errors using the drc2 backend. You can do it running 'gnetlist -g drc2 your_schematic.sch -o drc_output.txt' and seeing the contents of the file drc_output.txt. Loading schematic [/home/andyfierman/gaf/projects/hv-psu/RC1/hv- psu_090608.sch] DRC errors found. See output file. --- and when I check the output file (drc_output.txt), I can see that the errors are due to the duplicate reference to U1. --- Checking non-numbered parts... Checking duplicated references... ERROR: Duplicated reference U1. Checking nets with only one connection... Checking pins without the 'pintype' attribute... Checking type of pins connected to a net... Checking unconnected pins... Checking slots... Checking duplicated slots... ERROR: duplicated slot 1 of uref U1 Checking unused slots... No warnings found. Found 2 errors. --- Running this schematic through gsch2pcb works OK: I get no problems in PCB and all the pins on U1 are connected correctly. Reading the FAQ at: http://geda.seul.org/wiki/geda:faq- gschem#what_should_i_do_about_power_pins_on_my_symbolsmake_them_visibl e_explicit_or_invisible_implicit tells me: --- That said, it may still be useful to detach the power pins from the functional part of the symbol. To do so, define a seperate power symbol and give it the same refdes as the functional part. A run of gsch2pcb will treat the siblings properly as one single component. As neither gschem nor gsch2pcb explicitely know that the component is only complete with both symbols defined, you have to check yourself. With this workaround, you can draw all power related circuitry in one corner of the schematic where it does not interfere with the signal nets. In many cases this is advantageous with analog circuits. --- ** Therefore, my question is this: are the gschem DRC errors for such symbols to be expected? Any insight on this would be gratefully received. Thanks, Andy http://signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Question about gschem DRC errors when using separate power pin symbols.
Stefan, I should have said that I am using your latest symbols after all it was me that found the slotting bug. I've not tried Kai-Martin's symbols yet. :) Andy. http://.signality.co.uk 2009/6/11 Stefan Salewski m...@ssalewski.de: On Thu, 2009-06-11 at 17:28 +0100, Andy Fierman wrote: Hi, I'm puzzled by a couple of gschem DRC errors I'm getting. I'm using Stefan Salewski's quad comparator symbol with the separate power pins symbol. Please ensure that you are using a recent version from gedasymbols -- some months ago I was pointed to a bug in two of my slotted symbols. Indeed I am not using the quad comparator myself currently. I use only dual one and my multislot 74HCxx symbols. You may also use the comparator symbols of Kai-Martin. I will try to check if I can see what may be wrong with my quad comparator... Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gattrib: Adding new attribute columns
Bug report posted . ID: 2793743 :) BTW the version I'm using pops up various messages about things not being implemented yet such as opening a file, finding or searching for attributes. Is that what you'd expect from this version? Thanks, Andy ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gattrib: Adding new attribute columns
The version of gattrib I'm using (1.4.0.20080127 from the Debian lenny repos) has the option to add a new attribute column (Edit Add new attribute column). Having read the gattrib readme I'm confused by how this function behaves. Say I have attributes A, B , and D in my schematic and I want to add a new attribute C to all the components. All my components have attribute information already entered for each of A, B and D. When I run gattrib, I get a table with column headings A, B and D with data under each of the relevant columns. If I add now a new column C then a new column heading for C is inserted between columns B and D and the existing column D heading is shifted one column to the right. However, the existing column contents do not. So, the column contents that were originally under column heading D are now under column heading C whilst the column under heading D is empty. If I save this then of course all the component attribute values that were originally named D are now named C. If instead, before I run gattrib, I add the new attribute to at least one instance of a component in the schematic then of course when gattrib is run the table has all four column headings A, B, C and D with the attribute data in the right columns. Is that the expected behaviour of this version of gattrib? I ask because the current gattrib readme implies it is no longer necessary to add the new attribute to at least one instance of a component in the schematic. Could somebody clarify this for me? Thanks, Andy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gattrib: Adding new attribute columns
Hi Stuart, Should I file a bug report? Should have said: I'm running the 64bit debs from the Mepis 8 repos on a dual core Athlon machine. 2009/5/18 Stuart Brorson s...@cloud9.net: Hi -- Say I have attributes A, B , and D in my schematic and I want to add a new attribute C to all the components. All my components have attribute information already entered for each of A, B and D. When I run gattrib, I get a table with column headings A, B and D with data under each of the relevant columns. If I add now a new column C then a new column heading for C is inserted between columns B and D and the existing column D heading is shifted one column to the right. However, the existing column contents do not. So, the column contents that were originally under column heading D are now under column heading C whilst the column under heading D is empty. If I save this then of course all the component attribute values that were originally named D are now named C. Sound like a bug. If instead, before I run gattrib, I add the new attribute to at least one instance of a component in the schematic then of course when gattrib is run the table has all four column headings A, B, C and D with the attribute data in the right columns. Sounds correct. Is that the expected behaviour of this version of gattrib? No, you have a bug. I don't recall it behaving this way long ago, but it's been quite a while since I last hacked or used gattrib. I ask because the current gattrib readme implies it is no longer necessary to add the new attribute to at least one instance of a component in the schematic. The README is probably older than the insert column feature. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Cheers, Andy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Signal Source Setup for Electric Guitar?
Quick tip on your schematic: it's a good idea to offset 4 wire junctions (C1, R1, R2 Q1b) so that they appear as two pairs of 3 wire junctions. That way even if the junction dot disappears in a .png or .pdf or whatever, it is obvious that the 4 wires are all joined and it's not just 2 wires crossing. The reason you're seeing such distortion with your first attempt is that the R1, R2 base bias potential divider feeds current into Q1b so this node sits at between about 0.55V and 0.7V above ground (let's say it's 0.6V and call this Q1vbe). Your 1V ac source (V2) is driving 1V pk, i.e. 2V pk - pk directly into C1. It is a pure (zero R) voltage source so R5 has no effect at all. The signal swing at Q1b is then offset by Q1vbe so whenever V2 drops below -0.6V, Q1 is cut off. If you look closely at what happens to Voutput when V2 swings through -0.6V, you'll also see that Voutput is increasingly distorted. This is a long way of saying that you are right: you need to use a much smaller input voltage swing. And yes, you can probably get away with using some sort of high impedance buffer in front of a sound card or even your on board sound but for it to be of much use, the buffer has to be very linear, have a suitably wide input voltage and frequency range and you'll need some sort of reasonably calibrated signal source with which to calibrate what you can see on any waveform display. If you don't have those things then you can't relate what you see on the display with what is actually happening at the point you are trying to measure. By the time you've sorted all that out you may find it easier and cheaper to get a reasonable quality PC scope card or even a 2nd hand scope. Don't forget that you need to allow for the effect of the connection you make into your circuit at the point you are trying to measure it too. Connecting a 1Meg // 50pF scope input across a 10Meg buffer input is not very helpful! Even x10 probes (notionally 10Meg//5pF) are not that much use. (You can reconcile the scope and simulator displays if you model the effect of the scope probe in the schematic too but that is getting a bit esoteric.) Whatever, Spice is a good tool for learning about electronics. With gEDA/gaf the tools and all the components are free and you can't even blow anything up! That said you do need to sanity check simulations for things like silly voltages or currents and power dissipations that would have destroyed real devices. : ) 2009/5/13 Gareth Edwards gar...@edwardsfamily.org.uk: 2009/5/12 Joerg joerg...@analogconsultants.com For guitar pickup modelling, you might like to do a bit of Googling on spice model guitar pickup or similar. Yes, that is a very interesting page. This is precisely the kind of thing I'm interested in. I had no idea the capacitance of the cable was so significant. Anyway it looks like their AC generator is using 2mV. So the 20mV value I used to get a good output SIN looks closer to reality which means my model is probably ok. I wish I had a real oscilloscope to find out what my guitar is really putting out but xoscope doesn't seem to produce voltages (but I'm not surprised since the sound card is probably oblivious to such things). Maybe I'll have to get one of those PC oscilloscopes. Unless you are building a pickup, don't get too hung up on modelling it - it's a complex and changing impedance across frequency (stray and interwinding capacitance, leakage inductance, DC resistance etc) and the unit-to-unit variation in impedance and output voltage is large. You've already spotted that cable capacitance plays a part - the tone and volume controls loading the pickup are probably just as important. The trick is to use a high impedance amp front end that isolates the pickup from the rest of the circuit (JFET or, my personal preference/prejudice, a valve triode stage); then you can simplify the pickup model to a simple generator without worrying too much. In my amp work, I use a 100mV pk nominal signal - this is recommended by Kevin O'Conner in his excellent Ultimate Tone series of books: http://www.londonpower.com/catalog/index.php?cPath=3 However, modelling can only get you in the ballpark of gain staging and frequency response - eventually you have to evaluate with your ears, not with SPICE! If you want to display the waveforms or an FFT spectrum on the PC cheaply you could use an emitter follower as a buffer so the voltage gets transferred 1:1. Then a high input impedance is provided to the guitar even if you connect a sound card. Agreed, guitar into soundcard is sonic disappointment but JFET source follower would be much better. Here's a good one (not mine, but derived from a Win Hill circuit he posted on Usenet): http://www.ciphersbyritter.com/RADELECT/PREJFET/JFETPRE.HTM Cheers Gareth ___ geda-user mailing list geda-user@moria.seul.org
Re: gEDA-user: A not too serious PCB question
Interesting idea. Looks like it's a single (maybe double) sided through hole PCB. Probably only a low frequency board. I can see this may have some advantages for high current and therefore maybe switch mode PSU's but it may only have limited use for the following reasons: i) All tracks have the same gap between them. This may have adverse implications for crosstalk. ii) Track dimensions are very irregular. This makes it almost impossible to provide a controlled impedance. Therefore limited to only low frequency / slow edge applications. Could open a whole new topological discussion on auto routers though :) 2009/5/13 Stefan Salewski m...@ssalewski.de: Someone asked how one can build PCB boards like this: http://www.mikrocontroller.net/topic/137821#new (Click on the picture too enlarge) This layout may have advantages if PCB is made mechanical, i.e. by milling machines. So I asked myself is current PCB can do it -- I guess not, but I may be wrong. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Cheers, Andy. Signality Solutions tel: +44 (0) 5601 720 580 skype: andyfierman www.signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Signal Source Setup for Electric Guitar?
As Anthony has already asked, where is a copy of the schematic? I followed your link but haven't found one from there yet. For guitar pickup modelling, you might like to do a bit of Googling on spice model guitar pickup or similar. The first one I found was this http://terrydownsmusic.com/technotes/guitarcables/guitarcables.htm Looks quite useful as a starting place. -- Cheers, Andy. http://signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Adding attributes to gschem symbols
Hi,
I am new to gEDA and have a question about how to make gschem
attributes invisible in the schematic.
I think I understand the basics of how to create and edit symbols with
their associated attributes and text etc.
* This is what I want to do:
Add a set of attributes to every symbol I create in my local library
that will simplify my bill of material creation and general
understability of my schematics. To do this where possible I am taking
existing symbols or creating new ones and as well as the default set
of gschem attributes such as device, refdes, value, footprint, I want
to add an extra set of attributes of my own.
I don't want all the extra attributes to be visible when I place an
instance of the symbol on a schematic because it makes the schematic
too cluttered. However, I do want to be able to edit their values in a
schematic instance when I select it and either right click on Edit
... or double click on the instance to open the Edit Attributes
window. So, in the symbol I set the visibility to 0 (invisible) and
show_name_value to 1 (value only).
Following the rules in http://geda.seul.org/wiki/geda:file_format_spec
I can do that in the symbol fine, no problem.
* The problem I have is this:
When I place one of my components on the schematic it shows me the
attributes I want and hides those I have set to be invisible. However,
when I open the Edit Attributes window none of the attributes I have
made invisible appear in the list of attributes in the top section of
the window. They also do not appear in the drop down list for the Add
attribute, Name text box.
The only way I have found to get them to show up in the top section of
the Edit Attributes window is if I make them visible in the symbol
before I save it to the library.
At first I thought this was a feature of the attributes being my own
extra ones but more tinkering showed me that if I chose some of the
gschem standard attributes such as model or model-name, then it
all gets a bit strange.
If I make both model and model-name invisible in the symbol, then
model is not in the top section of the window at all but
model-name is shown there with the relevant 3 boxes; Vis (blank), N
(blank) and V (ticked). Both attributes of course show in the drop
down list for the Add attribute, Name text box, I assume because
they are gschem default attributes.
* What I'd like from people on this list:
Is there a way to do what I want?
Is there something I am doing wrong or have misunderstood or is this a bug?
At the bottom of the post is a copy of the file of one of my symbols
(a mosfet with a parasitic diode and a circle round it). The
attributes I have added of my own are:
manufacturer
manufacturer_p/n
supplier
supplier_p/n
inhouse_p/n
I'm running gEDA 1.4.0.20080127 (straight out of the repos) on Mepis
Linux 8 64bit. Athlon dual core, 8Gbyte RAM.
Any help much appreciated.
Thanks,
Andy
http://signality.co.uk
v 20080127 1
P 600 1000 600 800 1 0 0
{
T 500 850 5 6 1 1 0 0 1
pinnumber=D
T 500 850 5 6 0 0 0 0 1
pinseq=1
T 500 850 5 6 0 1 0 0 1
pinlabel=D
T 500 850 5 6 0 1 0 0 1
pintype=pas
}
P 600 200 600 0 1 0 1
{
T 500 50 5 6 1 1 0 0 1
pinnumber=S
T 500 50 5 6 0 0 0 0 1
pinseq=3
T 500 50 5 6 0 1 0 0 1
pinlabel=S
T 500 50 5 6 0 1 0 0 1
pintype=pas
}
V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 900 500 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
T 900 700 5 10 1 1 0 0 1
value=value or generic p/n
T 900 500 5 10 1 1 0 0 1
footprint=PCB footprint
T 900 300 5 10 1 1 0 0 1
manufacturer=manufacturer
T 900 100 5 10 1 1 0 0 1
manufacturer_p/n=manufacturer p/n
T 900 2000 5 10 0 1 0 0 1
supplier=supplier
T 900 1800 5 10 0 1 0 0 1
supplier_p/n=supplier p/n
T 900 1600 5 10 0 1 0 0 1
model=simulation model
T 900 1400 5 10 0 1 0 0 1
model-name=simulation model name
T 900 1200 5 10 1 1 0 0 1
inhouse_p/n=inhouse p/n
L 400 700 400 300 3 0 0 0 -1 -1
P 0 500 184 500 1 0 0
{
T 100 550 5 6 1 1 0 0 1
pinnumber=G
T 100 550 5 6 0 0 0 0 1
pinseq=2
T 100 550 5 6 0 1 0 0 1
pinlabel=G
T 100 550 5 6 0 1 0 0 1
pintype=pas
}
L 400 500 184 500 3 0 0 0 -1 -1
T 900 900 8 10 1 1 0 0 1
refdes=Q?
L 600 800 600 640 3 0 0 0 -1 -1
L 440 700 440 580 3 0 0 0 -1 -1
L 440 300 440 420 3 0 0 0 -1 -1
L 440 440 440 560 3 0 0 0 -1 -1
L 440 640 600 640 3 0 0 0 -1 -1
L 440 360 600 360 3 0 0 0 -1 -1
L 600 200 600 360 3 0 0 0 -1 -1
L 600 360 600 500 3 0 0 0 -1 -1
L 440 500 480 520 3 0 0 0 -1 -1
L 480 520 480 480 3 0 0 0 -1 -1
L 480 480 440 500 3 0 0 0 -1 -1
L 480 500 600 500 3 0 0 0 -1 -1
L 600 700 680 700 3 0 0 0 -1 -1
L 660 530 720 530 3 0 0 0 -1 -1
L 680 700 690 700 3 0 0 0 -1 -1
L 690 580 690 700 3 0 0 0 -1 -1
L 640 510 660 530 3 0 0 0 -1 -1
L 720 530 740 550 3 0 0 0 -1 -1
L 660 470 690 530 3 0 0 0 -1 -1
L 720 470 690 530 3 0 0 0 -1 -1
L 660 470 720 470 3 0 0 0 -1 -1
L 690 530 690 580 3 0 0 0 -1 -1
L 600 300 690 300 3 0 0 0 -1 -1
L 690 300 690 470 3 0 0 0 -1 -1
V 600 700 5 3 0 0 0 -1 -1 1 -1 -1 1 -1 1
V 600 360 5 3 0 0 0 -1 -1 1 -1 -1 1 -1 1
V
Re: gEDA-user: Adding attributes to gschem symbols
Duncan, That's exactly what I needed thanks! Andy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding attributes to gschem symbols
John, Thanks for that. I think I may have mislead a bit by saying that I wanted to edit my attributes in the schematic. Thinking a bit more and reading your comments of course I wouldn't want to edit much in a schematic for the reasons you describe. If I wanted to convert all the R's and all the C's from 0805 to 0603 then I'd want to do it at the symbol level and not directly in the schematic. I guess your comment about The problem with the local library is that its scope isn't a project. means that if I edit a symbol then the scope of that change is across all projects and not just one particular project. So if I changed a resistor footprint from 0805 to 0603 then all resistors in all projects using that symbol would change. On the other hand if I needed to edit a footprint say for a different PCB manufacturer's guidelines then that might be what I wanted . It hadn't dawned on me that I could make symbol libraries project specific. I need to think about it a bit more and perhaps look at what gattrib can do for me. Cheers, Andy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding attributes to gschem symbols
John,
Also, I was a bit sloppy in my library terminology. I didn't mean
local library as in /usr/share/gEDA/sym/local. I meant as in
${HOME}/gaf/gschem-sym.
I've had a quick play to prove to myself that I can set up a gafrc
file and libraries anywhere I want.
Andy.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding attributes to gschem symbols
H I now see more what John D was warning me about. I hadn't realised that once a component is placed in a schematic although the graphical stuff is loaded from the library at gschem startup, the texty bits such as footprint aren't. For instance if I place my mosfet with the footprint attribute in the symbol visible then save the schematic, close gschem and then edit the symbol on it's own to move the circle round the mosfet say off to the right and edit the footprint from SO8 to DIL8, save the changes, start gschem again using alt-F2 gschem (rather than from the schematic in a project folder) and then reopen the schematic: the circle round the mosfet has moved to the new position but footprint info has not changed, it still says SO8. That happens whether I add the (promote-invisible enabled) line to my gafrc file or not. * Is there a way to force gschem to reload all the parts (lines and attributes) of every symbol from whatever library you put that symbol into and then pointed gschem to, every time you run it? I'm assuming there is and that I haven't found the right search terms for it yet :) What I'm trying to do is make sure that the library part has all the right info before it's placed in a schematic (though I have a feeling this could tip over into the heavy vs. light symbol discussion if I'm not careful!) Andy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding attributes to gschem symbols
Hi Stefan, Sorry, forgot to set composer to plain text .. Edit / Update component has basically the same effect as closing and restarting gschem: it updates the graphical parts of a symbol but not the text attributes. If I enclose the text attributes in curly brackets in the symbol file (don't know how to do that via the GUI) then they do all get updated by ep but then they don't show up in the edit attribute window even if I put (promote-invisible enabled) in the gafrc file. Then the only way I can see the content is if I select the instance and then go down symbol and do en (en at the schematic is too cluttered). I suppose that's not too much of a problem provided attributes in curly brackets can (a) be seen in gattrib (don't know because I haven't tried this program yet) and (b) whatever program that's used to generate a bill of materials can detect the attribute names and extract the value information from the relevant attributes (again, don't know because I haven't tried this program yet). And of I'll have to put all these carefully set up and checked components in a library where the user (i.e. me on a dim day!) can't forget and accidentally edit the symbol in the schematic then save it back into the library So somewhere like /usr/share/gEDA/sym/local would be the place to put them. Andy. 2009/5/11 Stefan Salewski m...@ssalewski.de: mosfet has moved to the new position but footprint info has not changed, it still says SO8. Is Edit/Update Component what you are looking for? Please note: You send your text twice, I think one is HTML. Redundancy should be not necessary. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Cheers, Andy. Signality Solutions tel: +44 (0) 5601 720 580 skype: andyfierman www.signality.co.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
