Re: gEDA-user: verilog - gschem
Hi, (Sorry for the top post) No autorouter is needed... Just place the generated symbols on a grid, so they don't touch, and add wire stubs to each pin. Each wire should have a netname attribute attached. The netlister will connect all similarly named nets together. Any reason you can't just instantiate the verilog from the external sources directly? Or do you desire a flattened netlist for some reason? Thanks, Mike -Original Message- From: Ouabache Designworks z3qmt...@gmail.com Sender: geda-user-boun...@moria.seul.org Date: Fri, 8 Jul 2011 09:43:02 To: geda-user@moria.seul.org Reply-To: gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: verilog - gschem ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist verilog back end gnet-verilog.scm
John Griessen wrote: This is probably a Mike Jarabek question: Could be... Sorry for the delay, got swamped. I don't get usable hierarchic netlist output when I have placed schematics and use the gnet-verilog.scm back-end. It drops the module definitions and endmodule statements of the placed symbols that refer to schematics. This is the intended behaviour. The instantiations of the symbols on the page represent instantiations of sub-modules in the design. So, is that the normal behavior, and I need to not use hierarchy, and run gnetlist on every schematic, then cat them together? That could be one way of doing things, but that's not normally how I have seen it done with larger digital designs. (I count modest size FPGA designs too, anything more than a couple of modules.) There seems to be no existing gnetlist concatenate function. Would handling this in scheme be difficult? By this I mean taking all the files referred to by source= attribs and running gnet-verilog.scm on each in order, then putting that to the gnetlist output. gnet-verilog.scm is ready to create a one level netlist -- one module's worth of verilog. If you include a source attribute in your symbols, you will be able to descend into the underlying schematics in gschem, and so will gnetlist, if the heirarchy traversal is enabled. The cost here is that when gnetlist runs, it will flatten the netlist down to the lowest level where there are no source attributes. I don't think this is what you really want though, you will get a single module with duplicated code for every sub module, even if said module is identical to others. Using a makefile is the obvious thought. Make could just take a list or all .sch in a dir and run them and cat them together to a filename. Perhaps you are thinking in too much of a linear way. This is what you probably have to do with a spice deck, but with most Verilog simulators, there is usually a mechanism for a 'manifest' file. I certainly hope that the verilog-ams parser you are using is capable of reading such a file. In practice, this file is simply a list of other file names that make up the design. In a pinch you should be able to craft a master file that does a series of '' 'include filex.v '' reading this master file into the simulator should have the same effect as using cat. Some times the manifest files are automatically generated, you might be able to pull this one off using some make file variables, and some shell code to write out the file. Something along the lines of rm -f manifest ; for i in $(VERILOG_FILES) do echo $i manifest ; done (bash-isms aside) Handling it without make complexity separate from the back end chosen would be nice though, so I ask, Anyone seen existing scheme code that could use source=verilog_io.sch to trigger running it again on the referenced file then outputting that to the same place as usual? I don't see that you should have to do such things, but such a recursive invocation of gnetlist should be possible, at least in theory. Our scheme interpreter has a 'system' call right? Thanks, John Griessen -- Mike Jarabek FPGA/ASIC Designer http://www.sentex.ca/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: OT: Single sided PCB...
Hi All, DJ, it looks like it's time to add that single sided support to PCB: http://blog.makezine.com/archive/2009/02/mobius_circuit.html I just saw this, and could not resist sending it off. Not sure if the maker here is on our list or not... Mike Jarabek http://www.sentex.ca/~mjarabek ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist -g verilog questions
John Griessen wrote: I'm using Mike Jarabeck's gnetlist plugin and studying verilog ams with creating gnucap compatible netlists in mind. When I run: gnetlist -g verilog verilog_io.sch That would be the right way to run it. I get unknown in one slot... /* Package instantiations */ unknown X2 ( /* IO1 */ B, /* IO2 */ C ); What is that supposed tom come from? Module name? Interesting... The name is supposed to come from one of the attributes inside the symbol. It also looks like the symbol has the positional ports attribute set on there, I've found that isn't usually what you want to do. Given that each of those is an instantiation of the same symbol, all three should come up as an instantiation of the same sub-module. Can you post the 2-term-device.sym file? putting module_name=xxx didn't change the netlist result. That should change the name of the top-level module. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: I am having problems making and installing.
Kipton Moravec wrote: I have 1.4.0-20080127 installed. Installed it with synaptic manager with Ubuntu 8.04. I need to update convert_sym in the util package. I downloaded the latest version of convert_sym and made some changes. It will not let me compile because configure: error: libgeda detection error: Requested 'libgeda = 20080929' but version of libgeda is 20080127 So I decided to install 1.4.1.20080929 1. I downloaded all of the files into /home/backup/Work/gEDA 2. I checked and gtk+, guile, pkg-config, LibStroke are the right versions. 3. All of the files are untared. 4. The instructions say Set the prefix= variable in the make file. I do not understand what that means. Do I have to edit the makefile in my /home/backup/Work/gEDA? Or is prefix= part of the command with an argument? and what should it be if I want to overwrite my existing 1.4.0 version. Yes, that is the place to edit the variable. In order to replace the installed version with the version you are compiling, you will have to be root to install in the system shared directories. This is the trouble you ran into with the install step complaining that it can't write. You could try: sudo make install in the /home/backup/Work/gEDA directory. This will prompt you for your password, then it will be able to install in the system directories. If you do this, it will overwrite the installed version from the package manager, and you may end up with trouble later, if you try to use Synaptic package manager to delete it or a dependency. It would be best to remove the gEDA package from the system entirely, (to avoid library mismatches) and edit the prefix variable in the top level Makefile to point to your home directory, where you have write access. This will isntall gEDA outside of the package management system, and safely in your home directory. You may need to set the path and the LD_LIBRARY_PATH as the makefile instructs you. 5. So I just entered make and it looks like it set the variables. 6. Then I tried make install [EMAIL PROTECTED]:/home/backup/Work/gEDA $ make install ( cd geda-symbols-1.4.1; make install ) make[1]: Entering directory `/home/backup/Work/gEDA/geda-symbols-1.4.1' Making install in 4000 make[2]: Entering directory `/home/backup/Work/gEDA/geda-symbols-1.4.1/4000' make[3]: Entering directory `/home/backup/Work/gEDA/geda-symbols-1.4.1/4000' make[3]: Nothing to be done for `install-exec-am'. test -z /usr/local/share/gEDA/sym/4000 || /bin/mkdir -p /usr/local/share/gEDA/sym/4000 /bin/mkdir: cannot create directory `/usr/local/share/gEDA': Permission denied make[3]: *** [install-data4000DATA] Error 1 make[3]: Leaving directory `/home/backup/Work/gEDA/geda-symbols-1.4.1/4000' make[2]: *** [install-am] Error 2 make[2]: Leaving directory `/home/backup/Work/gEDA/geda-symbols-1.4.1/4000' make[1]: *** [install-recursive] Error 1 make[1]: Leaving directory `/home/backup/Work/gEDA/geda-symbols-1.4.1' make: *** [symbols_install] Error 2 so something is wrong. I am guessing it has to do with the Step #4 that I did not know what to do about. What do I do? Kip In that directory from the I typed make ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Documentation for convert_sym README file
Kipton Moravec wrote: Program name: convert_sym Written by: Mike Jarabek convert_sym takes ViewLogic Viewdraw schematic or symbol and outputs a gschem compatible file. This utility should be considered a work in progress. Be warned, this program has quite a few limitations. See the README file in the utils/ directory for more info. This program is written in C. There is also an awk version which is old and no longer supported, however it is included in the distribution as reference. The old Awk script was replaced with a C program some time ago, as you found out: SNIP There is only one file with the string convert_sym and that is the executable file. That's the right file. You can use this program on the Viewdraw schematics, and all symbol files, running it should give a brief command line synopsis. When you set up your geda project, I would recommend putting the schematics in one directory, and the symbols in another. Follow one of the tutorials to configure the geda config files for your project to look in the symbol directory for your converted symbols, and look for the schematics in the schematic directory you created. It's probably good to use the 'reset-component-library' command to flush the built in list of library searches in case one of your Viewdraw symbol names clash with one of the shipped symbol names. (Look on the wiki at http://geda.seul.org/wiki/geda:faq-gschem under Gschem configuration/customization for information on the configuration files. You will only need a few lines in each to accomplish what you need. If you set up your various conversion projects similarly, you can probably copy the config files from one project to another.) There is another utility included with the geda distribution called 'smash_megafile', which will break one of the Viewlogic '.lib' library files apart into the individual symbol files. You may need to do this on one or more Megafiles if you have used any of the stock components. Do this in a separate directory, as unpacking one of these can create many small symbol files. You will have to look at the gschem output log to see which files should be copied into your symbol directory. The process is somewhat manual, but can get the job done with some patience. Note that not all the Viewdraw attributes map into geda equivalents, so you may have to use gattrib on the resulting schematic to pound them into shape if you are planning to go to layout with PCB. It's been quite a while since I have played with these utilities, so please let us know how things work out. I do not know how to find the README. Can someone give me the full path to the README for convert_sym? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Laser diode operation?
Robert Butts wrote: Below is the link to the datasheet of a laser diode in using. It's not clear how I would wire this. Any suggestions on how to wire these? Digikey link: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=67-1500-ND Datasheet link: http://www.lumex.com/pdf/OED-LDP65001E.pdf http://www.lumex.com/pdf/OED-LDP65001E.pdfTG%20keenly These devices usually have a laser diode and a PIN diode facing the back facet of the main diode. The PIN diode is to sense the power output of the main diode, and can be used in a control loop to servo it. The data sheet shows the current through the PIN diode when the laser is operating at 5mW, this information can be used to design a control circuit. The terminals you are interested in for the main diode are the ones labled LD+ and LD-. The PIN diode is connected across the terminals labled PD+ and PD-. (The + is probably the anode and the - is the cathode.) The typical circuit to drive one of these things is a constant current source, I have seen circuits that have an op-amp that controls a FET with a series resistance on the ground side to measure the current, and feed it back to be compared to a reference control voltage. If you can get your hands on a dollar store laser pointer, you will probably find a simple circuit with a single transistor to limit the current, this will probably work fine but won't protect against the thing self-destructing. Either the sense resistor or the current from the PIN diode (or both) can be fed back to control the output power. You do have to be a bit careful with the voltage and current on one of these things, if the power gets to high they run away and self destruct. Don't exceed the operating voltage or current with your current source. Don't hook it up backwards, as this will also wreck it. You will also need some optics as the beam coming out of this device won't be colimated. Note too that the beam is quite oval shaped, 9 degrees in the horizontal and 35 degrees in the vertical. Hope this helps. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Laser diode operation?
Robert Butts wrote: Woe... I'm using ten of these and parallel. I WAS going to just use a 1 amp 5 vdc power supply with a 2.8 V zener diode to adjust the voltage to 2.2 V. I take it this is too simple. I didn't mean to scare you. You can probably get away with putting a bunch of simple current limiter circuits on the diodes, like the ones in the dollar store pointers. The circuit looks pretty simple, but I never traced it out. The main advantage to a current control circuit is that it will allow you to control the brightness as the diodes age, especially if you use the PIN diode for power feedback. I have even seen people drive these like an LED with a series ballast resistor, but this does not protect the diodes from destruction as they age, or protect them from over current. On Fri, Aug 29, 2008 at 10:46 PM, Mike Jarabek [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] wrote: Robert Butts wrote: Below is the link to the datasheet of a laser diode in using. It's not clear how I would wire this. Any suggestions on how to wire these? Digikey link: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=67-1500-ND Datasheet link: http://www.lumex.com/pdf/OED-LDP65001E.pdf http://www.lumex.com/pdf/OED-LDP65001E.pdfTG%20keenly These devices usually have a laser diode and a PIN diode facing the back facet of the main diode. The PIN diode is to sense the power output of the main diode, and can be used in a control loop to servo it. The data sheet shows the current through the PIN diode when the laser is operating at 5mW, this information can be used to design a control circuit. The terminals you are interested in for the main diode are the ones labled LD+ and LD-. The PIN diode is connected across the terminals labled PD+ and PD-. (The + is probably the anode and the - is the cathode.) The typical circuit to drive one of these things is a constant current source, I have seen circuits that have an op-amp that controls a FET with a series resistance on the ground side to measure the current, and feed it back to be compared to a reference control voltage. If you can get your hands on a dollar store laser pointer, you will probably find a simple circuit with a single transistor to limit the current, this will probably work fine but won't protect against the thing self-destructing. Either the sense resistor or the current from the PIN diode (or both) can be fed back to control the output power. You do have to be a bit careful with the voltage and current on one of these things, if the power gets to high they run away and self destruct. Don't exceed the operating voltage or current with your current source. Don't hook it up backwards, as this will also wreck it. You will also need some optics as the beam coming out of this device won't be colimated. Note too that the beam is quite oval shaped, 9 degrees in the horizontal and 35 degrees in the vertical. Hope this helps. ___ geda-user mailing list geda-user@moria.seul.org mailto:geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: (Vhdl help)
The code was designed for a CPLD, so perhaps there is a difference. In ISE, with the FPGA I'm putting down buffer symbols which tell it what kind of IO to use. If you could directly map the INOUT port to a pin on the chip (where 0 or Z output states would make sense), that works intuitively. What I couldn't do was take the inout lines, and connect them to the outside world via an IOBUF. Ahhh... This is where things went wrong. ISE is capable of inferring the IOBUF from the VHDL. The IOBUF is a primitive, that you can't connect to your 'internal' tri state bus. Best to connect the ports from the underlying module directly to 'inout' ports at the top level. I ran into this type of behaviour before when integrating IP blocks from various places, some of them assumed that the synthesis tool added the IOBUF in the netlist, while others did not. We had to edit the toplevels a bit to get them all on the same plan. One thing to watch out for with your I2C interface is that you really should sample the SDA line half way through the bit period, and that you should filter the inputs, as they have really slow rise times. Every I2C block I have seen from vendors have clocked internal logic directly from the SCL line, and this is dangerous. Sample and re-time the line with a high rate clock and sample the SDA line at the right time, with a delay generated by the master clock. In the past I have used a state machine to carry this out. Thanks, -Original Message- From: Peter Clifton [EMAIL PROTECTED] Date: Fri, 27 Jun 2008 00:02:30 To: gEDA user mailing listgeda-user@moria.seul.org Subject: Re: gEDA-user: OT: (Vhdl help) On Thu, 2008-06-26 at 15:22 -0700, Ben Jackson wrote: On Thu, Jun 26, 2008 at 11:07:49PM +0100, Peter Clifton wrote: This is similar to the code in the Xilinx I2C entity. When I try to assign from the input port of the IOBUF using similar code, I just end up getting this error. http://www.xilinx.com/support/answers/14264.htm Right, FPGAs don't really have internal tri-state (or wired-or) busses. If you had two I2C modules connected to the same pins, the I/O/T model allows you to combine them at one output. If the module just took 'SDA' and did the tri-stating internally then I would expect you to get that error when you connected another I2C module. Actually, its physical pins on the device I'm wanting to connect it to. The code was designed for a CPLD, so perhaps there is a difference. In ISE, with the FPGA I'm putting down buffer symbols which tell it what kind of IO to use. If you could directly map the INOUT port to a pin on the chip (where 0 or Z output states would make sense), that works intuitively. What I couldn't do was take the inout lines, and connect them to the outside world via an IOBUF. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tabs in text print wrong
Hi, The PS export code doesn't currently handle tabs. Except in the case where the text is rendered as vectors. If you look in the gschemrc files you will find the knob that controls this. The other option is to use two text items and line them up manually. --Original Message-- From: Matt Ettus Sender: To: gEDA user mailing list ReplyTo: gEDA user mailing list Subject: gEDA-user: Tabs in text print wrong Sent: Apr 10, 2008 1:25 PM I often use text on my schematic pages in the form of a table, so I use tabs to make columns. On the screen, these show up fine, but when printed, the tabs come out as capital Y's with umlauts on them. Is there some way to fix this? Thanks, Matt ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog: specify path for $readmemh?
Hi, You could try using a relative path, that is: Replace Romfile.txt with ../sim/Romfile.txt This might get you past the problem, at the expense of forcing the directory structure to always have the file in the 'sim' directory. I think the Xilinx tools can deal with the slashes. -Original Message- From: Günter Dannoritzer [EMAIL PROTECTED] Date: Fri, 21 Mar 2008 12:40:43 To:gEDA user mailing list geda-user@moria.seul.org Subject: gEDA-user: Icarus Verilog: specify path for $readmemh? Hi, I am using the system task $readmemh to init some ROM. Now my question is, can I specify for the simulation with Icarus somewhere the path to the file I am using with $readmemh? Here is my dilemma. My folder structure is as follows: + rtl/ + tb/ + sim/ + syn/ In rtl/ and tb/ I have my RTL implementation and in tb/ the test benches. In the sim/ folder I have a Makefile that does the compilation and simulation with Icarus Verilog. Now the $readmemh call is in some code in the rtl/ folder. The way I solved the path issue is that I moved the file that is read with the $readmemh call in the sim/ folder. Now the conflict happens with synthesis. In the syn/ folder I have a Makefile that calls synthesis with Xilinx webpack/ISE. It expects the file that is read in with the $readmemh call is in the rtl/ folder. I guess I could copy the ROM file in both locations or specify some macros and have two different $readmemh calls. Anyhow, is there a way to tell Icarus that the ROM file to be read with $readmemh is in another location than the folder the simulator (compiler) is called from? I did not find a command line switch that would apply to that issue. Thanks for the help. Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB crosshair tracks without focus (cygwin X?)
Hi, Using Cygwin-X at work, in rootless mode, I occasionally get behaviour like this from other X apps. For example Emacs help balloons sometimes pop up over top of other windows from underneath. I wouldn't necesarily blame PCB for this. Windows and X have quite different models of the world. -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- -Original Message- From: Ben Jackson [EMAIL PROTECTED] Date: Sun, 24 Jun 2007 22:39:16 To:gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: PCB crosshair tracks without focus (cygwin X?) On Mon, Jun 25, 2007 at 07:10:51AM +0200, Bert Timmerman wrote: Will check on my XP/Cygwin box later (tonight). I have one question: do you use the latest pcb cvs checkout and and your cygwin app is patched up to date ? The Pcb build is from CVS but it's running on a Unix box. The Cygwin binaries are fairly recent, but I don't know a lot about cygwin. Pcb draws the crosshair. Presumably it's getting pointer motion events all the time? It's been too long since I did X programming to remember if that's expected. -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: schematic symbol text size for printing
Hi, Besides the font anchor point, there's also a fudge-factor adjustment you can apply in the system-gschemrc. This sets a scaling factor between gschem's internal units and the font size. This is needed because not all fonts are created equal. If this does not do the trick for you, can you send me the postscipt output and the schematic/symbol that's causing you grief and I will look into it. Also, gschem supports overbars natively, and the PS code automatically makes them look nice. Just put a '_' where you want it to start and another '_' where you want it to end. -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- -Original Message- From: Ed Angie S. [EMAIL PROTECTED] Date: Mon, 4 Jun 2007 11:17:42 To:gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: schematic symbol text size for printing Ben, Thanks for the response. I may have more than one issue because I haven't addressed the anchor point issue at all. However, when I compare schematics printed out before and after the upgrade the text size (not just position) is significantly smaller for the post upgrade schematic page. The post upgrade text size in the print out is quite hard to read. I'm printing on A size sheets and before the upgrade my schematics were quite readable. The individual characters are smaller so it's not simply a proportional verses non proportional font issue either. It's possible that the screen font was slightly larger than the print font for the old gEDA version also but the difference must have been so slight as to not be noticeable. Note that the gEDA version I was using previously was a year or two old. Ed - Original Message - From: Ben Jackson [EMAIL PROTECTED] To: gEDA user mailing list geda-user@moria.seul.org Sent: Monday, June 04, 2007 9:43 AM Subject: Re: gEDA-user: schematic symbol text size for printing On Mon, Jun 04, 2007 at 09:50:24AM -0600, Ed Angie S. wrote: the text size for schematic symbols when printed is much smaller than before the upgrade. The problem is very evident for symbols which use a line above part of the signal name text to indicate negated because the line is no longer located in the correct place relative to the text. All symbol text looks fine on the screen; the problem is only with printed schematics. When text looks different when printed it's usually because the anchor point for the text is not where you want. I seem to recall a mention of an automatic anchor point moving feature, which is possibly affecting you. Since gschem does not print using its internal vector font, if the anchor point for your text is not toward the symbol, the smaller printed font means that the gap between the edge of the text and the symbol will increase. In the case of a hand-drawn overbar, you'd have to make the anchor top/center (in the default rotation) in order to have the bar stay in approximately the right place. It will still be too big for the printed text. If the bar is supposed to go over only one word of the text it's probably impossible to ensure it prints correctly. (and the print font has always been smaller since I started using gschem!) -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: howto : strap use in pcb
Hi, It has been suggested before that you can designate one copper layer for this purpose, and just use vias instead of a footprint. Wherever you want a strap, just draw a copper line. Print the layer seperately and you have a reference for your wires. Doing it this way will allow the DRC to pass and the rats nest will work too. -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- -Original Message- From: Ludovic SMADJA [EMAIL PROTECTED] Date: Tue, 15 May 2007 21:25:46 To:gEDA user mailing list geda-user@moria.seul.org Subject: gEDA-user: howto : strap use in pcb Hello, I would know how to put straps on my pcb in order to reduce vias. Is it possible and how ? -- Ludovic SMADJA Le hasard, c'est Dieu qui se prom�ne incognito - Albert Einstein HALTE AUX SPAMS : Cet email est sign�. Pourquoi signer un email ?? http://www.cacert.org/help.php?id=2lang=fr_FR#whyEmails Mes coordonn�es : Jabber ID : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] Cl� PGP : DD76063A sur pgp.mit.edu begin:vcard fn:Ludovic SMADJA n:SMADJA;Ludovic adr:Elancourt;;France email;internet:[EMAIL PROTECTED] note;quoted-printable:JID (jabber ID) : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] x-mozilla-html:TRUE url:http://Castor-et-herlie.homelinux.org version:2.1 end:vcard ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: photo-imagable supplies (was: dremel drill press)
Hi, When I did double sided photoresist boards I used a frame made from aluminum. The frame was made from a rectangular piece of aluminum sheet that had the same thickness as the board that we were using. There was a large cutout in the middle of the sheet to allow the board to sit in there. Imagine what a matte for a picture frame looks like. The two masks were then taped one on each sides of the frame and were aligned by looking through them. One side was not taped all the way around so that you could lift it up and place the board in between them. Two sheets of glass were then placed one on each side, and held there with hose clamps. The resulting sandwich was then placed unde UV poster lamps to expose. First on one side, then the other. If we had more lamps we would probably have built a frame to expose both sides at once. With this setup I made quite a few ISA plug in cards for PC's. The only real problem I ran into was that occasionally the print shop that did my photomasks would use a different piece of glass to hold down my original, this different glass ended up making about a 2% difference in the output size. Unfortunately for me they did this randomly, and I would end up with top and bottom that did not align. After I got burned a couple of times, I added a vernier scale to the output plot, and showed them the error, and made them do it again until they got it right. The eventually figured it out, and after that they made real nice plots for me. -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- -Original Message- From: John Griessen [EMAIL PROTECTED] Date: Mon, 16 Apr 2007 10:05:19 To:geda user mailing list geda-user@moria.seul.org Subject: gEDA-user: photo-imagable supplies (was: dremel drill press) DJ Delorie wrote: They seem to go where I want them. [jg]Great. I'll be trying some PCB carbide bits soon. The deviation of the bit itself is far less than the alignment accuracy of the two halves of the board. Off by 10 mil or so - this is my first try at double sided, I need to try a few techniques and see which is most accurate. I'm thinking of switching from toner transfer to photomask. Then, I can drill the board first and use the holes to line up the print. I've thought about that some, and also got a chance to do some film tests recently that were not acceptable -- it seems no easy photography supplier films are high enough contrast to get a good film for exposing photomask -- just dark grey instead of opaque black. Or black and grey if you expose it differently... So the supplies for making a pos from a neg or a reduction in size from a 2:1 print are hard to get. Agfa quit serving the US it seems -- I found one source that supplies super fine line chip/interconnect making film and didn't even bother to go through the hoops to get the price since they were dodging around the question so much. So, if you use toner on clear film and maybe stack two of them to get opacity, what's your source of photoimagable mask emulsions? I'd want some that are good with a red light instead of any total darkness processes. If you do photoimagable etch resist, you're all ready to go for soldermask also... and for masks to put on conductive inks too maybe... Conductive inks are now used in some lowest-cost-planet-wide circuit boards made in China so they have only one side etched, and the jumper layer is mostly ink on the same side, reducing holes to the minimum. You sometimes have to make conductive ink wide or use a copper wire jumper on the other side to get your desired conductance for a path, but leaving out drilling holes is best by me... John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Lab Equipment
To add my 0.02 CDN... I have a couple of NXP LPC2103 based boards that I have been using. They cost me $24.95 USD from www.futurlec.com. These are ARM based and I use GCC (with the patches from www.gnuarm.com, which you don't really need unless you want to mix ARM and Thumb code) to program them. They also have a built in ROM bootloader so you don't have to mess with JTAG to program them. NXP has plenty of example code to get you started, and I wrote a simple command line downloader for it that runs under FreeBSD, but should compile on Linux without any changes. . -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- -Original Message- From: Steven Michalske [EMAIL PROTECTED] Date: Tue, 3 Apr 2007 10:44:09 To:gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: Design Lab Equipment I second this motion! basic stamps have nice small simple boards, the drawback i have with them is I didn't want to learn another variant of basic. If you are familiar with C I'd suggest a microcontroller that is capable of being programmed in C, assembly can be tighter and cleaner, but that takes practice. I am fond of the Atmel AVR series, and the GCC tool chain that goes along with it, it is also convient for OS X and Linux users, as the basic stamps native environment is windows. yes they have compilers and such for linux, but the AVRs have better OS X support. With the GCC tool chain you have the ability to use both assembly and C I have seen DJ Delorie using the R8C from Renasas, and I see that they are also using a GCC tool chain. They look like a nice part as well. Happy researching Steve On Apr 3, 2007, at 7:49 AM, Dave McGuire wrote: On Apr 3, 2007, at 9:29 AM, Felipe Balbi wrote: Hmm... Nice... Actually, I'm Engineering studying... so.. that's my 4-year studying... But, I want to get it started now... Wanna understand how to design the correct interfaces... where to use capacitors, resistors, inductors, etc... How to interface a PIC or 8051 with an LCD... How to design a circuit to flash their memory... stuff like that... I think there should be some techniques to make things a little easier... :-p I will warn you, please listen...DO NOT expect to pick this up overnight, or even in a few weeks. There is a lot going on in those little components, and a lot of stuff to be aware of. I admire your desire to dive in and start doing things, but it's very important to be aware of one's own capabilities and select your projects accordingly. START SMALL...get a Basic Stamp and blink an LED, maybe make a low-frequency sine wave with a D/A converter, *then* move to a PIC or 8051 with an LCD. Seriously...you will be much less frustrated, and you'll destroy fewer components, if you start small. Move quickly, but start small. As others have suggested, Horowitz Hill's The Art of Electronics is absolutely fantastic. You can also check out http://www.allaboutcircuits.com/, it is very well-done and will get you off to a good start. Don't be tempted to skip over things like Ohm's Law, etc., because you'll use it every day and it's important to understand the underlying concepts. -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: 4-bit_12-LED.png (PNG Image, 1024x768 pixels)
Hi, From your picture it looks like you have used lines to connect your components. You need to use nets, put the mouse cursor over one of the red dots on the ends of the pins, and hit 'n'. Draw the nets between the pins like this to make electrical connections. When two nets cross without a connection, they will just intersect. When the end of one net touches another, a round red dot will automatically appear. Open ends on nets will have a square dot on them so you can see where the ends are not connecting. A common drawing style to help a reader of your shematic determine if two nets should be conected is to never connect four nets at the same point. Always stagger the nets apart so you get two round dots. Reserve the case where two nets just cross over each other for just that. (This is the situation that you used the arc to jump over your other net) Hope this helps. I think there is a getting started guide on the wiki for you. -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- -Original Message- From: william estrada [EMAIL PROTECTED] Date: Mon, 02 Apr 2007 15:03:08 To:geda-user@moria.seul.org Subject: gEDA-user: 4-bit_12-LED.png (PNG Image, 1024x768 pixels) Hi guys, I have made my first drawing using gEDA. I have some questions about using gEDA. In the drawing I used an 'arc' to jump over one of the 'traces'. Is the a better way to show that lines are not connected? http://64.124.13.3/PIC_Projects/4-bit_12-LED.png -- William Estrada [EMAIL PROTECTED] Mt-Umunhum-Wireless.net ( 64.124.13.3 ) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tabs print weird in schematics
Hi, On Tue, 2007-03-13 at 14:26 -0700, Matt Ettus wrote: If I put tabs in text in a schematic, it shows up fine on the screen. However, it prints funny -- the Tabs come out as Y's with 2 dots on top. Indeed, the position for 'Horizontal Tab' in the ISOLatin1Extended mapping table from the prolog generates '/Ydieresis'. Which is a 'Y' with dots on it. When I upgraded the PostScript output I did nothing special for tabs. As far as I know postscript itself has no notion of what a tab is. Is there a fix for this? Sort of, vector text should render correctly. For the nice postscript fonts, not currently, but I have two strategies that could fix it: 1) Add code into prolog.ps that traps tab characters and has the printer do the right thing. (con: reduces the number of international characters that can be used on a schematic. pro:overbars covering tabs will render automagically) 2) Add code into f_print_text() (and friends) that traps the tabs and makes one print command per tab separated section. (con: Overbars might be a bit of trouble to get working when they extend over a tab. pro: does not reduce the number of international characters.) I think that I favour #1, but I have to think carefully about what happens when someone actually wants to put a /Ydieresis in their schematic... -- -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gschem printing style chang (20060123 to 20060906)
Wojciech Kazubski [EMAIL PROTECTED] said: I have checked in a patch for this behaviour. Now, the default is to draw lines that have a '0' width as thick as the nets. This behaviour is configurable through the system-gschemrc. Look for the the 'line-style' rc command for the details. In gschemrc there are lines that control width of nets, pins and buses. Is another one to control width of lines in elements now? Yes, look for (line-style Thick) in the system-rc files. Postscript text on print is significantly smaller then the vector text on screen. Is it possible to add a scaling factor? Old postscript exporter created postscript text a bit bigger than vector text. That can be done, but I had believed that the text size was in 'points' from the data structures. The trouble is that the Helvetica font that is being used to print the schematics does not have the same font metrics as the stroked vector font. If you change the output font for another font, the scaling factor that we have chosen for the Helvetica is unlikely to be the 'right' scale factor for the new font. This probably needs to be a user tunable parameter too. Ales, can I go ahead and add this? At the same time, I will add a command that allows the name of the font to be changed. BTW. I found a bug in printing routine that under certain circumstances may cause a print to be miscentered. Can you elaborate? -- -- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: prolog.ps
Karel Kulhavy [EMAIL PROTECTED] said:
I found this in gschem.log:
Unable to open the prolog file `prolog.ps' for reading in f_print_header()
But why is it opening prolog.ps and not /usr/local/share/gEDA/prolog.ps?
When I insert prolog.ps behing the %%Beginprolog%% then the ps can be
displayed.
It's trying to open 'prolog.ps' because it does not know where to find the
actual prolog file. Your system-gafrc is missing the command to tell it
where to look.
Okay, this is what you are missing in your system-gafrc:
-
; postscript-prolog
;
; Sets the name of the postscript prolog file that will be
; pasted into the postscript output after the DSC comments, but
; before the main script.
(postscript-prolog ${GEDADATA}/prolog.ps)
-
This command will appear in your system-gafrc if you also download and
install the latest symbols tarball. This is where system-gafrc is shipped.
I added this in the system-gafrc because this is where the global paths are
set up, and it is the logical place to add it. Usually most people download
all the tarballs and install all the tools, instead of just one or two of
them. I think that the recommended proceedure for updating a gEDA
installation has been to always download and install all the parts. Note
that there are several other important paths set up in that file, so other
things may not work for you either, if they have changed since your last
install of the symbols package.
--
--
Mike Jarabek
FPGA/ASIC Designer
http://www.istop.com/~mjarabek
--
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Re: gEDA-user: Driving a constant RS-232 output directly from +12V
Tomaz Solc [EMAIL PROTECTED] said: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi So is there anything terribly bad/spec-violating/unsafe about driving an always-asserted RS-232 output directly from the +12V supply through a resistor, or is that perfectly OK? What should the resistor value be? Or should I use something more fancy like a PTC resistor acting as a resettable fuse protecting against external shorts? I currently have a circuit in front of me that uses PNP transistors as switches to connect a supply voltage directly to the TX line of a RS-232 output. I believe this is pretty much identical to shorting that line to supply voltage. So I would say that it would also be safe to directly drive lines in your case. I've also once seen 4.7k resistors in series with RS-232 lines. It is probably a good idea to limit the current that way in case of a short circuit. I can't say if that violates any standards. I certainly wouldn't bet on the manufacturer of this board to stick to specs if it that meant saving a few components :) The last reference I saw to the actual EIA RS-232 standard said something to the effect that 'Any line can be shorted to any other line, or ground, for an indefinite period of time, without causing damage to the port'. How you implement this is up to you. Hooking directly to a power supply without some kind of current limiting might violate this if the power supply does not shut down in case of a short. On the other hand, it's probably not desired behaviour to have your whole box shut down if someone happens to cut a communications cable. I would recommend an approach that limits the current to, say, about 10mA. Since this is a static signal, you can probably simply connect it up via a resistor as you suggest. -- -- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Upgrading gEDA
Hi, Karel Kulhavy [EMAIL PROTECTED] said: I had an old installation of gEDA that segfaulted every 5 minutes. I have been told to upgrade. So I downloaded gschem and it complained about libgeda so I downloaded libgeda. Compiled and installed libgeda and compiled and installed gschem. Now gschem doesn't segfault but generates invalid postscript so I cannot update the Ronja website because every time I type make rsync, it ends up with an error message during compilation of the schematic into a PNG through postscript. This should have worked, unless your system-gschemrc file or one of the other system scheme files has gotten corrupted. I have been told that this is because something in my installation of gEDA is screwed. Can you run your scripts and retreive the log file that gschem creates when you print? If there is a problem finding the prolog file then there should be a message to that effect in the log file. The postscript file you posted is missing the prolog, which gets copied from the geda data directory verbatim into the postscript output. You should have a file called 'prolog.ps' somewhere under $prefix/share/gEDA. This piece of postscript is where 'GEDAFont' gets defined. ($prefix is the what you supplied to ./configure when you built gschem and libgeda as --prefix=some path) Do you have the gedadata enviroment variable set? If so, perhaps it is pointing at an old installation of the system-rc files. There is a command in the current startup guile scripts that sets the path and filename for the prolog file. If this command is missing, because of gschem reading an old version of the startup script, then gschem will behave as you have shown. Verify in the log file that the system guile files that are being read are the ones that you most recently installed, especially if you have used a different prefix for your latest installation, compared to the old installation. Use the 'find' (or 'locate' if it's available) command on your system to find all the copies of the system-gschem files. If you have more than one copy, then you have multiple installations of the tool, and this may be the source of your grief, especially if one of the installations lives under /usr/ or /, as the shared libraries there will get loaded if the LD_LIBRARY_PATH is not set correctly, or you have edited ld.so.conf. Mike -- -- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: CPLDs and other high-density logic chips...
On Sun, 2006-09-03 at 15:57 +1000, John Sheahan wrote: Samuel A. Falvo II wrote: I am working on a project that, in the end, may require me to utilize a CPLD just to get the thing working and cost-effective. But I really have no knowledge of how to prototype with such beasts. Is there a body of resources that you folks would recommend to a *total* neophyte with respect to CPLDs and FPGAs? The farthest I've gotten in Verilog was to actually get something to simulate via Icarus, but actual synthesis and resynthesis is something that still escapes me, unfortunately. you probably want to choose either Xilinx or Altera for a start. Both make good things. Don't discount Lattice either, they are #3, and they have a line of FPGA devices the 'EC' family that has a programmable array that has FPGA properties, but also has built in Flash to download the bitstream. You get the best of both worlds, non-volatility, and fine grained FPGA architecture. Some of the devices also have built in core voltage regulators too, so all you need is 3.3V to power them. There are some smaller devices that have built in block ram and a goodly number of logic elements to use for circuitry. The program with JTAG, so all you need is a cable. The Official Lattice cable might set you back about $200 if you pay full price, but you can build one with a bus buffer and a DB-25 connector. once that choice is made, visit their web site for docs. if you have code that simulates, you need to add a file mapping IO's to pins, a wrapper instantiating IO drivers, and you are pretty much done. For example, if you were to pick xilinx, and with what you have mentioned, you might want to drop the cpld, put a small spartan device on the board, and add a configuration device for that. your tool budget is then just a programmer for the configuration device. icarus and the web tools will do the rest. Also, what kind of capital investment am I looking at? The tool download and use should be free for smaller devices. I just used Quartus II web edition to design a simple text mode VGA controller in an Altera Cyclone II '35 device and it took up 1% of the 33,000 logic elements! That leave lots of other room for other bits to put in there. These things have gotten huge, even for the free versions of the tools. ;-) My plan was to use a relatively simple CPLD for address decoding and other glue logic functions, but also perhaps an FPGA for generating VGA (640x480) video. this would work - but is probably 1 device more than required. 1 is usually easier than 2. john Thanks. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- -- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: SMD soldering challenge status
Hi, Perhaps a bit more low-tech, how about an astable multivibrator? This circuit needs 2 transistors, 6 (or 7) resistors, and two caps. Add two LED's and you have a blinker. We used to build these out of leaded components on a 1.5 x 1.5 inch piece of perfboard. We had students who were in grade 5 assemble these from loose components, and they all got the circuit to work. The circuit can be built in one layer if you allow a single trace underneath one of the components. On Sat, 2006-08-05 at 09:34 -0400, DJ Delorie wrote: Even just a little 555-based LED blinker or something would count as functional in this case, I think. 0603 cap = 1 cent 0603 led = 7 cents Even the venerable 555 is too expensive in the small sizes appropriate to this project (about $0.60). SOT-23 transistors come in at $0.10CDN at DigiKey in single unit quantities. Now, if you can think of a circuit that uses a flip flop and some inverters, plus low-valued caps (even resistors cost 3x what caps cost), that might be feasible. The success of this circuit depends on what `low' valued means here. To get visual frequencies, for a couple of Hertz we might need between 0.1 and 1 microfarad or so. We would have to breadboard the circuit to find out appropriate values for the cross coupling capacitors. (Although probably not with those 01005 components... ;-) (ok, so it's more than just a *soldering* challenge ;) -- -- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Patch to utils/src/convert_sym.c
Hi, Patrick Doyle wrote: Attached (perhaps) is a trivial patch to convert_sym.c to enable it to handle viewlogic schematics with pins marked as PWR. I applied the patch to CVS. This did not appear to be a major change, and fixed a bug. Thanks. Mike -- -- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gnetlist Verilog
Hi, On Sat, 2006-07-22 at 10:39 -0700, User Tomdean wrote: How do I cause 'gnetlist -g verilog' to pick up the pinlabel rather than the pin number for the module port name? At the moment, no. The backend uses the pinnumber information as passed directly from the gnetlist core. When I wrote the backend I had physical simulation in mind. Whatever appeared in the pin number attribute was used ad the module port name. I don't remember if at the time I could get by-pin attributes from gnetlist. If you want to do something else, make sure that it's configurable and does not break the current way of doing things. From the drc2 backend it looks like gnetlist:get-attribute-by-pinnumber can fetch other attributes to use. Using pinlabel attribute would be closer to what the Cadence tool does. It should not be too hard to use this but you will have to replace the call to gnetlist:get-pins-nets in the Verilog back-end with your own custom one that calls gnetlist:get-attributes-by-pinnumber internally after getting the pin names with gnetlist:get-pins-nets, and then returns your own list to the rest of the code. From your next post, it sounds like you are attempting this already? Is there a doc that describes the flow in gnetlist? tomdean ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- -- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
