Re: gEDA-user: unconnected tracks
On Thu, Sep 15, 2011 at 3:43 PM, DJ Delorie wrote: > >> But then I realized that I don't really understand what "all >> connected objects" is supposed ot mean. > > Read as "all found objects" and it makes more sense. > Still not making sense to me, found by what metric? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: unconnected tracks
On Thu, Sep 15, 2011 at 7:41 AM, Kai-Martin Knaak wrote: > Is there any way in PCB to select all unconnected track segments in a > layout? This would come handy on redesign. > I thought "select all visible objects" followed by "unselect all connected objects" might work. But then I realized that I don't really understand what "all connected objects" is supposed ot mean. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Speaker SPICE modeling with gschem and ng-spice/gnucap
On Mon, Sep 12, 2011 at 2:39 PM, John Doty wrote: > > On Sep 12, 2011, at 3:09 PM, Hannu Vuolasaho wrote: > >> I have been playing with one guitar amplifier project for a while and so far >> the amplifier design has been more or less copy and paste and simulate and >> guess from graphs. However I bumped in net this blog post >> >> http://nordicnerd.blogspot.com/2011/08/active-speakers-spice-with-actual-audio.html >> >> Is it possible to do same thing? Input wav to simulator and get speaker's >> output and hear it? I know it's not perfect but it could be very helpful. >> Has someone done this before and provide some hints, examples or links? > > Shouldn't be too hard. ngspice seems to have no limit to the length of a PWL > spec. Put the audio in some simple form (like raw binary samples), write a > tiny program to convert to PWL. Generate output with .PRINT, write another > tiny program to convert to binary samples. > Here's the spice raw reader that jpd and Hannu are both missing out on: http://www.h-renrew.de/h/python_spice/spicedata.html Even outputs to hdf5: http://www.hdfgroup.org/HDF5/ You'd probably be able to glue together the spice raw reader and this fairly quickly to get wav output from ngspice: http://www.ar.media.kyoto-u.ac.jp/members/david/softwares/audiolab/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Speaker SPICE modeling with gschem and ng-spice/gnucap
On Mon, Sep 12, 2011 at 2:09 PM, Hannu Vuolasaho wrote: > > Hi! > > I have been playing with one guitar amplifier project for a while and so far > the amplifier design has been more or less copy and paste and simulate and > guess from graphs. However I bumped in net this blog post > > http://nordicnerd.blogspot.com/2011/08/active-speakers-spice-with-actual-audio.html > > Is it possible to do same thing? Input wav to simulator and get speaker's > output and hear it? I know it's not perfect but it could be very helpful. Has > someone done this before and provide some hints, examples or links? > Output is really easy to get from ngspice in the form of a raw file. There are some python modules out there that do a good job of reading this. As far as input, I see two options. One is to embed a pwl (piece wise linear) b source (or xspice source for more smoothing) into your circuit. You'd want to make a script that would read in the the wav data, and output a pwl. Your other option would be to use a digital source, which can also read from a file but you'd get digital data for which you'd need to build a dac (possible out of xspice dacs). In either case, You'd probably need some additional elements to remove the high frequency artifacts from the signal and to give it the appropriate impedance. For the most part though, I would just run through a number of different frequency sine waveforms and see what kind of distortion you get. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: CERN goes for KiCAD
>> That's a good point. Where could things be best shared >> between KiCad and gEDA? >> > > Footprint editor ? > > https://github.com/bert/fped > > Fped lives in Ubuntu and Fedora, and maybe other distros, with support for > KiCAD users. > > Anyone interested in a parametric footprint editor with support for pcb ? > > Just clone, add code and stuff, and send patches to here. > > This way we can have common files for interoptable footprints. It would be quite handy to make a backend for fped that outputs PCB footprints. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: test repo
On Mon, Sep 5, 2011 at 9:53 PM, Bert Timmerman wrote: > Hi Russell, > >> -Original Message- >> From: geda-user-boun...@moria.seul.org >> [mailto:geda-user-boun...@moria.seul.org] On Behalf Of Russell Dill >> Sent: Monday, September 05, 2011 10:21 PM >> To: gEDA user mailing list >> Cc: geda-u...@seul.org >> Subject: Re: gEDA-user: test repo >> >> >> with one checked-out version you know works, or maintain your own >> >> bugfix branch. Git head is where development happens, and >> when we're >> >> bringing in big changes, stuff breaks. >> > >> > This is why other projects like KiCAD provide a dedicated >> testing repo. >> > Debian even has four stages (experimental, unstable, >> testing and stable). >> > By the way, stuff also breaks with small changes. See the first >> > commits of the new layer selector. >> >> gEDA PCB's developer and testing community is much smaller >> than Debian's. I don't know about a size comparison to KiCAD. >> The only way bugs can be fixed is by someone finding that >> it's broken in the first place. I fear that not only would >> the developer resources be there to maintain two separate >> branches, but the testing resources wouldn't be there either. >> Out of all the people testing on git HEAD, I think only you >> managed to find the large silk bug. This model is used with >> quite a bit of success in linux kernel development with the >> linux-next tree, so who knows, maybe it does have a place. >> >> I think the only way this gets solved is the suggestion that >> someone made of someone tagging "semi-stable" versions. Bug >> fix patches could be back-ported to those and at some point >> the branch could be abandoned for a newer semi-stable >> version. The nice thing about this solution is that it can >> easily scale based on how many people are willing to help >> maintain the various semi-stable branch points and don't >> depend on the core developers doing anything. Someone with a >> big enough itch to scratch could put something up on github today. >> >> > > Some of us have been there, done just that, and for some time: > > https://github.com/fruoff/pcb-fruoff.git > > https://github.com/jaredcasper/pcb.git > > https://github.com/peter-b/geda-gaf.git > > https://github.com/bert/pcb.git > > And maybe some more I didn't notice. > (Note, clip the .git for the web interface) I don't see any branching or tagging on any of these that would indicate maintenance of stable branches. Also, if someone was doing this, it'd be nice of them to send out an announcement each time they made a new stable branch point. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: test repo
>> with one checked-out version you know >> works, or maintain your own bugfix branch. Git head is where >> development happens, and when we're bringing in big changes, stuff >> breaks. > > This is why other projects like KiCAD provide a dedicated testing repo. > Debian even has four stages (experimental, unstable, testing and stable). > By the way, stuff also breaks with small changes. See the first commits > of the new layer selector. gEDA PCB's developer and testing community is much smaller than Debian's. I don't know about a size comparison to KiCAD. The only way bugs can be fixed is by someone finding that it's broken in the first place. I fear that not only would the developer resources be there to maintain two separate branches, but the testing resources wouldn't be there either. Out of all the people testing on git HEAD, I think only you managed to find the large silk bug. This model is used with quite a bit of success in linux kernel development with the linux-next tree, so who knows, maybe it does have a place. I think the only way this gets solved is the suggestion that someone made of someone tagging "semi-stable" versions. Bug fix patches could be back-ported to those and at some point the branch could be abandoned for a newer semi-stable version. The nice thing about this solution is that it can easily scale based on how many people are willing to help maintain the various semi-stable branch points and don't depend on the core developers doing anything. Someone with a big enough itch to scratch could put something up on github today. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb gtk: Toggle buttons for route styles?
On Fri, Sep 2, 2011 at 12:04 PM, Peter Clifton wrote: > On Thu, 2011-09-01 at 20:26 -0700, Russell Dill wrote: >> >> Throwing out a crazy idea.. in word-processors etc.., "styles" are found >> >> in a drop-down combo-box. I know that doesn't fit so well with where we >> >> have space for the route-style selector, but just a crazy though. >> >> >> > >> > One day, when we support an unlimited number of route styles. ;) >> > >> >> Yes, 4 hardly seems like enough. Especially since many designs require >> a different trace width based on the layer for the same signal. > > For impedance reasons? > > I was also aware that you could also have different requirements for > current carrying capacity - if different layers used different copper > weights. > > There are also different DRC rules on certain objects on inner layers > for some fabs IIRC. > > Perhaps this ought the be encompassed in a "smart" route-style which has > different settings for different layers. That would make assigning one > route-style to one net much more practical. You (and the auto-router) > wouldn't have to switch styles when switching layers etc.. Yes, for impedance reasons. Given the current state, I don't think its smart to do an all in one go solution for everybody, but instead do incremental improvements. I think the first step might be something like what kmk is suggesting, allowing a more dynamic set of layers, and then extending that to allow a route style to be broken up per layer. And at some later stage tying route styles to net attributes or sets of nets. While impedance matching is becoming more important, lack of per layer DRC is probably something that is probably more likely to bite people. But for me at least, its going to be a real pain to keep track of per layer trace widths and minimum spacing for different net types. Suppose I'll make a script that does a check to see if the trace widths in a given PCB match some set of rules. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to find which specific part of a PCB is shorted?
> > Since we have such a good, algorithmic method for finding these shorts, > perhaps we can write some code to do it for our puny human minds? ;) > > Usually, when I have power and ground shorted, it's because of a via placed > some where that was accidentally assigned thermals to the wrong layer. > I remember the old Quake maps had to be "sealed", so any loose seam would cause problems. Because the map editor doesn't know what you meant to be outside/inside, etc, the map editor had a feature to deal with this, it would create a line that would start in one area, and head to another. All you had to do was follow the line. A similar solution in PCB would be neat. if VCC and GND are shorted, pick a random GND pin and a random VCC pin. Find a path between them and show it as a orange dotted line. This could later be extended to find either the shortest orange dotted line, or the point on the board where several such lines meet. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb gtk: Toggle buttons for route styles?
>> Throwing out a crazy idea.. in word-processors etc.., "styles" are found >> in a drop-down combo-box. I know that doesn't fit so well with where we >> have space for the route-style selector, but just a crazy though. >> > > One day, when we support an unlimited number of route styles. ;) > Yes, 4 hardly seems like enough. Especially since many designs require a different trace width based on the layer for the same signal. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb gtk: Toggle buttons for route styles?
On Thu, Sep 1, 2011 at 10:55 AM, Andrew Poelstra wrote: > > Hey all, > > Can we use toggle buttons instead of radio buttons for the > route style selector? It would look like so: > > http://wpsoftware.net/andrew/dump/toggle.png > > This gives more clickable area and a cleaner look, I think. > Dunno, I think the radio buttons are ok. The mock-up is a bit confusing because the route style button is the same as the signal button. I'll just sit back and wish for auto-route style by net property. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gedasymbols.org down?
On Wed, Aug 31, 2011 at 1:37 PM, Kai-Martin Knaak wrote: > Russell Dill wrote: > >> I imagine I'm not the only one running a git mirror of >> gedasymbols.org. If you rely on gedasymbols.org in any way, It'd be >> wise to do the same. > > Is there a way to propagate changes in the git repo to DJs cvs? > (short of running cvs commit in a cron job) git cvsexportcommit ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gedasymbols.org down?
On Mon, Aug 29, 2011 at 4:58 PM, Kai-Martin Knaak wrote: > Peter Clifton wrote: > >> Yes - I got a message from DJ saying it has knocked his power and >> internet down. (The server lives in DJ's basement). >> > Time for a mirror server on a different continent? > > I got used to rely on the presence of gedasymbols.org. I use > it as a hinge to distribute my geda lib to my various desktops. > And of course lately for work on the essential lib. > > Git would be handy in this situation. With git everyone would > have all information locally, including history and branches. We > could just set up an interim repository and update the on at DJ > when it is up again. > I imagine I'm not the only one running a git mirror of gedasymbols.org. If you rely on gedasymbols.org in any way, It'd be wise to do the same. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb HID GUI options: gtk, lesstif?
> One of my "dream projects" is to do a GUI for pcb that uses two or > more monitors, with one monitor heavy on the toolbars and showing an > overview "thumber" window, and the other monitor being 100% layout. eh, one of the reasons I really like having two monitors is so I can have reference information on one screen, and my design, schematic, or layout on the other. I suppose while deep into just routing it might be helpful. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Nanometer conversion pushed to git head
On Mon, Aug 15, 2011 at 6:34 PM, Andrew Poelstra wrote: > > Exciting news everyone! > > I have just pushed the nanometer conversion patches to git HEAD. > > > Please test and let me know how things are working. I have > compiled all 56 commits (by script) to confirm that they can > compile so "git bisect" will work. > > I have done a few save/load tests. There does not appear to > be any breaks in the file format. > > > Thank you all for your support and testing as I have worked > on this over the last month or two. > Congrats, I just saw that it hit HEAD! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Constraint-based PCB footprint design
On Sun, Aug 7, 2011 at 7:47 PM, Rob Spanton wrote:
> Hey all,
>
> I've recently been playing around with designing footprints by
> describing a set of constraints that position features relative to each
> other. This is rather than specifying the absolute co-ordinates of
> every feature.
>
> I've written a small tool that allows this to be done. It pumps out a
> gEDA PCB footprint when one wants :-)
>
> I've written more information about it in a blog post, where you'll also
> find a link to the code:
> https://xgoat.com/wp/2011/08/08/playing-with-footprints-and-constraints/
>
> The tool is by no means complete... it's the result of just a few hours
> work right now. Anyway, I hope either the tool or the concept of the
> tool might be of use to at least some in the gEDA community.
>
Reminds me of my turtle like c library for component creation (from
long, long ago...)
http://ftp.sunet.se/geda/mailinglist/geda-dev40/msg00036.html
#include
#include
#include "library.h"
#define DIMY 2.00
#define DIMG 3.50
#define DIMC 5.50
#define DIMZ 7.50
#define DIME 2.40
#define DIMD 5.00
#define DIMP 1.27
#define PAD_WIDTH 0.80
#define PAD_LEN DIMY
#define DIMA DIMP * 3.0
#define CENTERY DIMD / 2.0
void make_element(void)
{
set_mm();
set_pad(PAD_WIDTH, PAD_LEN, 0.20, PAD_WIDTH + 0.10);
pen_width(0.3);
header("SOIC-8", "U1", "SOIC-8", 0, -1.50, RIGHT);
pads(PAD_LEN / 2.0, CENTERY - DIMA / 2.0, DIMA, DOWN, 1, 4, 1);
right(DIMC);
pads_up(DIMA, 5, 8, 1);
place((DIMZ - DIME) / 2.0, 0);
pen_on();
down(DIMD);
right(DIME);
up(DIMD);
left(DIME / 2.0 - .25);
down(.5);
left(.5);
up(.5);
left(DIME / 2.0 - .25);
}
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Anybody ever had a board assembled (pick and place)?
To get an online assembly quote, you have to register on the my4pcb.com site. I don't know how competitive the cost is, but given the quantity and complexity, if I'm going to have an assembly house fck up a PCB that I had prototyped, I'd rather it be the house that make the PCB. I didn't ask about reels because my quantities are not up in the reel numbers. They also have a page with assembly house referrals. On Wed, Jul 27, 2011 at 12:35 PM, yamazakir2 wrote: > I sometimes get boards done at 4pcb, I didn't know they do assembly. > How much to they charge? And how big of a reel do you have to send > them? And you just cut tape the amount of parts you need to assemble > the amount of boards you want to manufacture? > > On Wed, Jul 27, 2011 at 11:23 AM, Russell Dill wrote: >> I'm planning on having some proto boards assembled by Advanced >> Circuits (4pcb.com). And yes, I have to supply all the components, and >> no, they don't provide storage until you've actually put the order in >> (Many components are very moisture sensitive). >> >> On Wed, Jul 27, 2011 at 10:28 AM, yamazakir2 wrote: >>> I have had many boards manufactured but never had one also assembled. >>> What are the costs to do this? Are there any (cheap) manufactures that >>> also do pick and place? Do they buy the components for you or do you >>> have to send them reels, meaning you have to buy 1000's of components >>> at a time? >>> >>> >>> ___ >>> geda-user mailing list >>> geda-user@moria.seul.org >>> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user >>> >> >> >> ___ >> geda-user mailing list >> geda-user@moria.seul.org >> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user >> > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Anybody ever had a board assembled (pick and place)?
I'm planning on having some proto boards assembled by Advanced Circuits (4pcb.com). And yes, I have to supply all the components, and no, they don't provide storage until you've actually put the order in (Many components are very moisture sensitive). On Wed, Jul 27, 2011 at 10:28 AM, yamazakir2 wrote: > I have had many boards manufactured but never had one also assembled. > What are the costs to do this? Are there any (cheap) manufactures that > also do pick and place? Do they buy the components for you or do you > have to send them reels, meaning you have to buy 1000's of components > at a time? > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Crash in pcb_vprintf when getting object report of unplated hole
82721122dae63a96c89d273bba7abd8b3e6e8337 #0 0x755db386 in _IO_vfprintf_internal (s=, format=, ap=) at vfprintf.c:1620 #1 0x75691e38 in __vasprintf_chk (result_ptr=0x7fffc328, flags=1, format=0xf3b170 "%s", args=0x7fffc348) at vasprintf_chk.c:68 #2 0x772893fb in vasprintf (string=0x7fffc328, format=, args=) at /usr/include/bits/stdio2.h:199 #3 g_vasprintf (string=0x7fffc328, format=, args=) at /build/buildd/glib2.0-2.29.8/./glib/gprintf.c:314 #4 0x77264fcd in g_strdup_vprintf (format=, args=) at /build/buildd/glib2.0-2.29.8/./glib/gstrfuncs.c:253 #5 0x7726506c in g_strdup_printf (format=) at /build/buildd/glib2.0-2.29.8/./glib/gstrfuncs.c:279 #6 0x00473563 in pcb_vprintf ( fmt=0x52168f "s.\nIt is a pure hole of diameter %$mS.\nName = \"%s\".%s", args=0x7fffc4b8) at pcb-printf.c:301 #7 0x00473c7f in pcb_sprintf (string=0x7fffc6a0 "", fmt=) at pcb-printf.c:389 #8 0x004859c9 in ReportDialog (argc=, argv=, x=, y=) at report.c:147 ---Type to continue, or q to quit--- #9 0x00497694 in hid_actionv (name=, argc=0, argv=0x0) at hid/common/actions.c:246 #10 0x00497a44 in hid_parse_actionstring ( rstr=0xd49590 "ReportObject()", require_parens=1 '\001') at hid/common/actions.c:330 #11 0x004c9309 in ghid_menu_cb (action=, data=) at hid/gtk/gui-top-window.c:623 #12 ghid_menu_cb (action=, data=) at hid/gtk/gui-top-window.c:514 #13 0x764b3d54 in g_closure_invoke (closure=0xd8af10, return_value=0x0, n_param_values=1, param_values=0xe18540, invocation_hint=) at /build/buildd/glib2.0-2.29.8/./gobject/gclosure.c:771 #14 0x764c5bbb in signal_emit_unlocked_R (node=, detail=0, instance=0xd8b1b0, emission_return=0x0, instance_and_params=0xe18540) at /build/buildd/glib2.0-2.29.8/./gobject/gsignal.c:3256 #15 0x764cf1c7 in g_signal_emit_valist ( instance=, signal_id=, detail=, var_args=0x7fffd308) at /build/buildd/glib2.0-2.29.8/./gobject/gsignal.c:2987 #16 0x764cf392 in g_signal_emit (instance=, signal_id=, detail=) ---Type to continue, or q to quit--- at /build/buildd/glib2.0-2.29.8/./gobject/gsignal.c:3044 #17 0x76c3d163 in _gtk_action_emit_activate (action=0xd8b1b0) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkaction.c:794 #18 0x76c3da09 in closure_accel_activate (closure=0xd8be10, return_value=0x7fffd5a0, n_param_values=, param_values=, invocation_hint=, marshal_data=) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkaction.c:1764 #19 closure_accel_activate (closure=0xd8be10, return_value=0x7fffd5a0, n_param_values=, param_values=, invocation_hint=, marshal_data=) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkaction.c:1755 #20 0x764b3d54 in g_closure_invoke (closure=0xd8be10, return_value=0x7fffd5a0, n_param_values=4, param_values=0x11e8d20, invocation_hint=) at /build/buildd/glib2.0-2.29.8/./gobject/gclosure.c:771 #21 0x764c5bbb in signal_emit_unlocked_R (node=, detail=2085, instance=0xcf1600, emission_return=0x7fffd6e0, instance_and_params=0x11e8d20) at /build/buildd/glib2.0-2.29.8/./gobject/gsignal.c:3256 #22 0x764cf056 in g_signal_emit_valist ( instance=, signal_id=, detail=, var_args=0x7fffd748) ---Type to continue, or q to quit--- at /build/buildd/glib2.0-2.29.8/./gobject/gsignal.c:2997 #23 0x764cf392 in g_signal_emit (instance=, signal_id=, detail=) at /build/buildd/glib2.0-2.29.8/./gobject/gsignal.c:3044 #24 0x76c38354 in IA__gtk_accel_group_activate (accel_group=0xcf1600, accel_quark=2085, acceleratable=0x864030, accel_key=114, accel_mods=GDK_CONTROL_MASK) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkaccelgroup.c:890 #25 0x76c396f9 in IA__gtk_accel_groups_activate (object=0x864030, accel_key=114, accel_mods=GDK_CONTROL_MASK) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkaccelgroup.c:927 #26 0x76e3223c in IA__gtk_window_activate_key (window=0x864030, event=) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkwindow.c:8967 #27 0x76e322a9 in gtk_window_key_press_event (widget=0x864030, event=0xf2d6a0) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkwindow.c:5750 #28 0x76cff848 in _gtk_marshal_BOOLEAN__BOXED (closure=0x8118a0, return_value=0x7fffdac0, n_param_values=, param_values=0x1214a70, invocation_hint=, marshal_data=) at /build/buildd/gtk+2.0-2.24.5/gtk/gtkmarshalers.c:86 #29 0x764b3d54 in g_closure_invoke (closure=0x8118a0, return_value=0x7fffdac0, n_param_values=2, param_values=0x1214a70, ---Type to continue, or q to quit--- invocation_hint=) at /build/buildd/glib2.0-2.29.8/./gobject/gclosure.c:771 #30 0x764c59f4 in signal_emit_unlocked_R (node=, detail=0, instance=0x864030, emission_return=0x7fffdc00, instance_and
gEDA-user: PCB invalid free with latest git
I was selecting a net when PCB crashed. 82721122dae63a96c89d273bba7abd8b3e6e8337 *** glibc detected *** /home/russ/src/pcb/_install/usr/bin/pcb: free(): invalid next size (fast): 0x027f4d60 *** === Backtrace: = /lib/x86_64-linux-gnu/libc.so.6(+0x78a8f)[0x7f8d5f0a8a8f] /lib/x86_64-linux-gnu/libc.so.6(cfree+0x73)[0x7f8d5f0ac8e3] /home/russ/src/pcb/_install/usr/bin/pcb(FreeLayoutLookupMemory+0xa2)[0x458c12] /home/russ/src/pcb/_install/usr/bin/pcb(LookupConnection+0x164)[0x45ec04] /home/russ/src/pcb/_install/usr/bin/pcb[0x429ed2] /home/russ/src/pcb/_install/usr/bin/pcb(hid_actionv+0xb4)[0x497694] /home/russ/src/pcb/_install/usr/bin/pcb[0x497a44] /home/russ/src/pcb/_install/usr/bin/pcb[0x4c9309] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_closure_invoke+0x154)[0x7f8d5ff4fd54] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(+0x20bbb)[0x7f8d5ff61bbb] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_signal_emit_valist+0x767)[0x7f8d5ff6b1c7] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_signal_emit+0x82)[0x7f8d5ff6b392] /usr/lib/libgtk-x11-2.0.so.0(+0x75163)[0x7f8d606d9163] /usr/lib/libgtk-x11-2.0.so.0(+0x75a09)[0x7f8d606d9a09] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_closure_invoke+0x154)[0x7f8d5ff4fd54] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(+0x20bbb)[0x7f8d5ff61bbb] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_signal_emit_valist+0x5f6)[0x7f8d5ff6b056] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_signal_emit+0x82)[0x7f8d5ff6b392] /usr/lib/libgtk-x11-2.0.so.0(gtk_accel_group_activate+0x104)[0x7f8d606d4354] /usr/lib/libgtk-x11-2.0.so.0(gtk_accel_groups_activate+0x109)[0x7f8d606d56f9] /usr/lib/libgtk-x11-2.0.so.0(gtk_window_activate_key+0x19c)[0x7f8d608ce23c] /usr/lib/libgtk-x11-2.0.so.0(+0x26a2a9)[0x7f8d608ce2a9] /usr/lib/libgtk-x11-2.0.so.0(+0x137848)[0x7f8d6079b848] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_closure_invoke+0x154)[0x7f8d5ff4fd54] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(+0x209f4)[0x7f8d5ff619f4] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_signal_emit_valist+0x5f6)[0x7f8d5ff6b056] /usr/lib/x86_64-linux-gnu/libgobject-2.0.so.0(g_signal_emit+0x82)[0x7f8d5ff6b392] /usr/lib/libgtk-x11-2.0.so.0(+0x251f61)[0x7f8d608b5f61] /usr/lib/libgtk-x11-2.0.so.0(gtk_propagate_event+0x197)[0x7f8d60799b17] /usr/lib/libgtk-x11-2.0.so.0(gtk_main_do_event+0x283)[0x7f8d60799da3] /usr/lib/libgdk-x11-2.0.so.0(+0x5c09c)[0x7f8d6040e09c] /lib/x86_64-linux-gnu/libglib-2.0.so.0(g_main_context_dispatch+0x1dd)[0x7f8d60ce385d] /lib/x86_64-linux-gnu/libglib-2.0.so.0(+0x44058)[0x7f8d60ce4058] /lib/x86_64-linux-gnu/libglib-2.0.so.0(g_main_loop_run+0x162)[0x7f8d60ce4592] /usr/lib/libgtk-x11-2.0.so.0(gtk_main+0xa7)[0x7f8d60798dd7] /home/russ/src/pcb/_install/usr/bin/pcb(ghid_do_export+0x4e)[0x4cbd3e] /home/russ/src/pcb/_install/usr/bin/pcb(main+0x88a)[0x4241ba] /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xff)[0x7f8d5f04ee1f] /home/russ/src/pcb/_install/usr/bin/pcb[0x4246a9] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB DRC accuracy?
On Tue, Jun 21, 2011 at 5:06 PM, DJ Delorie wrote: > > We use cmils for gerber (0.01 mil). PCB's DRC precision should be > 0.000254 mm Are you saying that 0.000254 mm should be added to your DRC rule if exporting to gerber? (ie, a 4mil DRC would become 4.01mil) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB DRC accuracy?
On Tue, Jun 21, 2011 at 1:50 PM, Andrew Poelstra wrote: > On Tue, Jun 21, 2011 at 01:29:02PM -0700, Russell Dill wrote: >> >> I've always worried about this too, especially when doing a design in >> metric and sending it to an imperial board house. My guess is you need >> to calculate the worst case error and add that to the DRC. The >> difficult part would be finding all the possible sources of roundoff. >> >> Perhaps if you could translate the design to a mil grid with a given >> precision and *then* run DRC. >> > > We are working on moving pcb toward metric base units -- then > a mm would be 10^6 nm rather than "about 3937.00787 cmils" > like we have now. > > mils would also be an integer (254) number of base units, so > hopefully a lot of precision issues will go away. If one point is on 228600nm and another on 126988nm, it would seem to make a 4 mil (101600nm) trace/space rule (101612nm). But when converted to mils: 228600nm = 9 mil 126988nm = ~4.99952756mil If you output to a X.YYY gerber format, that will round to 5mil and your features will then only be 4 mil apart. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB DRC accuracy?
On Tue, Jun 21, 2011 at 11:23 AM, Phil Taylor wrote: > On 6/21/2011 6:53 AM, Richard Rasker wrote: >> >> So I wonder what tolerance PCB's DRC has? I realize that 0.006 mm (6 >> micron) is a tiny distance, but it can make all the difference between >> an accepted and rejected board -- and thus delay in the manufacturing >> process. > > I wonder too. I've often set my DRC clearance to 4+/-.1 mils to get it > through Advanced Circuits 4 mil spec. I would consider this a known bug. > Of course I don't know if anyone indeed knows about it.(!) > > The code for DRC may round up and down for mathematical precision, but > should not be rounding but padding all 'rounded' computations in preference > of more clearance. > I've always worried about this too, especially when doing a design in metric and sending it to an imperial board house. My guess is you need to calculate the worst case error and add that to the DRC. The difficult part would be finding all the possible sources of roundoff. Perhaps if you could translate the design to a mil grid with a given precision and *then* run DRC. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Jumpers on single layer PCBs
On Tue, May 31, 2011 at 2:09 PM, Levente Kovacs wrote: > On Tue, 31 May 2011 21:59:04 +0100 > Thomas Oldbury wrote: > >> Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like >> each jumper to have a refdes and BOM entry if possible.) > > What I'd do is define a copper layer. Draw your jumpers on the that layer. > Don't send the layer data to the fab house. Make sure you have mask openings > on vias. Solder jumpers in the vias. > > I recommend using double sided boards. > I was just writing an email recommending that. If you want a BOM of jumper wires, you could make a script that takes all the traces on the jumper wire layer and spits out a list by length and location. Bonus points if it collates jumper wires of the same length and provides a count. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Two things ... or actually, three
> To my knowledge this is not the case right now. Of course the pin numbers > should not be shown on the schematics: they would use up too much schematics > real estate and are not interesting anyway (even relatively simple and cheap > FPGA devices like XC3S700A has 88 power pins in the 256 pins BGA package, > that's ~35% of the pins): you can't check anything in a BGA package and even > on package that can be probed, it is extremely hard to find, say, a bad solder > joint since all pins of the same power rail are internally connected together. I find that in FPGA design having all pins on the schematic is not an annoyance and is actually a necessity. I usually just make a single component that has all the pins of one type. Eg, a component that contains all the ground pins. I can then draw a net across all the pins connecting them all and then a single ground symbol. The separated out pins are very important for bank power as individual banks can be power by different supplies. For an XC3S700A, a single schematic page showing how power and ground pins are connected is extremely cheap and provides an easy way to do a verification against the data sheet, even by a third party review. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Darter - SPICE based IBIS modelling tool
As edge rates increase, signal intergrity (SI) becomes more and more important, even for the hobbyist. Unfortunately, the models provided by semiconductor vendors typically come in only 2 forms, encrypted HSPICE and IBIS. No open tools exist for handling either. An open HSPICE decryption utility would only either encourage encryption changes or take-down notices. Enter Darter, a tool for creating SPICE models based on IBIS models. The basic idea is to create a SPICE subcircuit for each IBIS model within an IBIS file. Each subcircuit is then wrapped in one of several different subcircuits depending on component and pin (or signal name). This gives subcircuit names like (note that spaces in the model name get converted to underscores): DQ_FULL_ODT50_800 for bare buffers and: MT47H128M16U69A_DQ_FULL_ODT50_800_DQ14 for a buffer with parasitics. The buffers can then be connected with transmission lines for simulating SI problems. https://gitorious.org/darter http://www.gedasymbols.org/user/russell_dill/darter.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: git: quick check for new commits
On Mon, May 30, 2011 at 10:15 AM, DJ Delorie wrote: > > Is there a quick way to check to see if a local repo is out of date > relative to a remote repo? I'd like to write a shell script that > rebuilds pcb but only if something's been committed to the master > repo. Rather than check out the whole tree and see if anything > changed, I'd rather just compare head revisions. I tried git > rev-parse but it's "origin/master" result is based on cached values, > not actual upstream values. > > Perhaps I need to fetch, then rev-parse? > git remote update origin would be the easiest way. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: IPC standard SMT footprints (0603, 0402 vs. RESC0603N etc.)
On Wed, May 25, 2011 at 2:40 PM, Colin D Bennett wrote: > On Wed, 25 May 2011 23:03:06 +0200 > Gabriel Paubert wrote: > >> This said, most capacitors look to have a square profile, but >> resonance frequencies observed on microstrip line change between >> mounting the layers parallel or perpendicular to the ground plane. >> The problem is that, for most capacitors, it is very hard to >> determine the orientation of the layers. > > That's interesting. Are you saying that for high-frequency, critical > signals, the orientation of the chip capacitor affects its performance > in the circuit? Is the SMD tape/reel packed in such a way that the > capacitors are optimally oriented, ready for pick-and-place onto a > PCB? > My understanding is that many resistors have a similar problem in that the thin resistive strip is on the "top" or "bottom" of the device. Mounting it upside down increases inductance. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: IPC standard SMT footprints (0603, 0402 vs. RESC0603N etc.)
On Wed, May 25, 2011 at 7:56 AM, Gabriel Paubert wrote: > On Wed, May 25, 2011 at 07:11:49AM -0700, Colin D Bennett wrote: >> On Wed, 25 May 2011 06:41:26 -0700 >> Colin D Bennett wrote: >> >> > (1) Why is RESC0603L/N/M much smaller than '0603'? >> > (2) Why is there no similarly named set of RESC0805L/N/M for 0805 >> > size? (3) Why does RESC1608M nearly match the '0603' footprint? >> > Is there an imperial/metric naming confusion happening? I thought >> > 0603 was a standard name for this size. >> >> I think I've answered some of this for myself... from Wikipedia's >> “Surface-mount technology” article: >> >> 01005 (0402 metric) : 0.016" × 0.008" (0.4 mm × 0.2 mm) >> 0201 (0603 metric) : 0.024" × 0.012" (0.6 mm × 0.3 mm) >> 0402 (1005 metric) : 0.04" × 0.02" (1.0 mm × 0.5 mm) >> 0603 (1608 metric) : 0.063" × 0.031" (1.6 mm × 0.8 mm) >> 0805 (2013 metric) : 0.08" × 0.05" (2.0 mm × 1.25 mm) >> 1206 (3216 metric) : 0.126" × 0.063" (3.2 mm × 1.6 mm) >> >> So the source of the confusion over footprints is that '0603' is a valid >> name for both a metric and an imperial size.. both different? Whoever >> decided to name the packages that was must have been on crack. > > Indeed. I found a set of recommended footprints that distinguishes > resistors from capacitors: > > http://www.ibselectronics.com/pdf/pa/walsin/smt_notes.pdf > > I have used it quite successfully, including for long edge > capacitors (0612 or 1632 metric) and 4 resistors in a single package > (4x0603 or 4x1608 metric). I also took into account the recommendations > on page 10 when ordering the stencil, shrinking a bit the solder paste > apertures generated by PCB. > And don't forget Tom Hausher's blog series on the subject "PCB Design Perfection Starts in the CAD Library": http://blogs.mentor.com/tom-hausherr/blog/2010/07/08/metric-vs-imperial-measurement-systems/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Reinventing the wheel
On Thu, May 19, 2011 at 10:27 AM, Stephan Boettcher wrote: > Kai-Martin Knaak writes: > >> Stephan Boettcher wrote: >> >>> The way to promote gedasymbols and to fix the default library is to >>> remove the default library, except for a small set of very generic >>> symbols. >> >> ack. >> This set of symbols should provide the ability to start working as is >> and generally be examples for complete working symbols. That is, they >> should contain footprint attributes. And when applicable simulation >> attributes, too. HOWTOs and manuals may refer to these items. > > nack. There is no way for a footprint attribute to be generic. > > These symbols shall exactly not be examples, and exactly not just work. > > They shall be symbols that can be use as they are for any workflow, by > adding the required attributes after instantiation, or by editing a copy > in a project lib, i.e., the first easy steps in learning symbol editing. > No, but what would be really cool is if gschem knew about PCB symbols so that when you open the properties window, footprint is a dropdown list of available PCB footprints. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: IBIS to SPICE conversion work
I'm currently working on simulating IBIS models in ngspice. Its a work in progress, but I have something that is at least somewhat usable at this point. I put my current work on gEDA symbols: http://www.gedasymbols.org/user/russell_dill/ I'll be doing more testing and refinement, and most importantly adding at least some support for package models (parasitics) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB: simple FreeType fonts implementation -- update?
On Fri, May 13, 2011 at 9:34 AM, Colin D Bennett wrote: > > On Fri, 13 May 2011 12:14:45 -0400 > DJ Delorie wrote: > > > > > IIRC my primary objection to the patch-as-was was, "where do we store > > the TTF files?" PCB has no way to store binary blobs with the board, > > and if you don't keep them together you risk someone else getting > > different results. However, perhaps we could keep both "plain text" > > and "TTF text" as different text types, so those who value pretty over > > self-contained can get some love ahead of time? > > Can we just store it as BASE64-encoded or something blob for now? > Yeah, it might take 200 KB+ to store a font, but that's a drop in the > bucket compared to disk storage capacity these days. It's not as if I > have 100 000 .pcb files on my disk either so I'm not at all concerned > about size. BASE64 seems like a good way to go. The side by side option would work well if you included a hash along with the file name. PCB would provide a warning or error if the hash did not match and you would be given the option of updating the hash. For those who don't want huge files with a ton of BASE64 text, I would recommend using an include of the PCB file containing the BASE64 encoded fonts. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb+gl
Did the clone succeed? Did you cd into the cloned repo? On Wed, May 11, 2011 at 12:53 PM, Thomas Oldbury <[1]toldb...@gmail.com> wrote: � I'm getting this problem when trying to run the last command: � thomas@thinkpadone:~/pcb2$ git checkout -b pcb+gl_experimental � origin/pcb+gl_experimental � fatal: Not a git repository (or any of the parent directories): .git � Any ideas? � On 11 May 2011 18:41, Peter Clifton <[1][2]pc...@cam.ac.uk> wrote: � On Wed, 2011-05-11 at 16:51 +0100, Thomas Oldbury wrote: � > I've heard a lot about this pcb+gl and I like it... and it turns out � I � > � � fetched my git a few days from the enabling of it, so I think I � missed � > � � the bus for it... � � In git HEAD, there is "some" GL support. What I've always called � � "pcb+gl" is a feature branch I've been maintaining separately from � � the � � main PCB git repository. � � The aim is to merge it all to upstream git HEAD eventually!. � � To get the most speed and fancyness (including the more translucent � � thin-draw polygons), check out PCB from here: � � git clone git://[2][3]repo.or.cz/geda-pcb/pcjc2.git � � git checkout -b pcb+gl_experimental origin/pcb+gl_experimental � � (If your card can cope with it, the "pcb+gl_experimental" branch has � � better rendering speed and a few extra bits and pieces). � � Otherwise, the default checkout should be the "pcb+gl" branch. � � As others have said, just run ./configure and GL should be enabled � � as � � the default. You might need to install your distro's libgtkglext-dev � � package before it will build. � � Best wishes, � � -- � � Peter Clifton � � Electrical Engineering Division, � � Engineering Department, � � University of Cambridge, � � 9, JJ Thomson Avenue, � � Cambridge � � CB3 0FA � � Tel: +44 (0)7729 980173 - (No signal in the lab!) � � Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) � � ___ � � geda-user mailing list � � [3][4]geda-user@moria.seul.org � � [4][5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References � 1. mailto:[6]pc...@cam.ac.uk � 2. [7]http://repo.or.cz/geda-pcb/pcjc2.git � 3. mailto:[8]geda-user@moria.seul.org � 4. [9]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [10]geda-user@moria.seul.org [11]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:toldb...@gmail.com 2. mailto:pc...@cam.ac.uk 3. http://repo.or.cz/geda-pcb/pcjc2.git 4. mailto:geda-user@moria.seul.org 5. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 6. mailto:pc...@cam.ac.uk 7. http://repo.or.cz/geda-pcb/pcjc2.git 8. mailto:geda-user@moria.seul.org 9. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 10. mailto:geda-user@moria.seul.org 11. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Adding inner polygons to a plane
On Wed, May 11, 2011 at 11:19 AM, Peter Clifton <[1]pc...@cam.ac.uk> wrote: On Wed, 2011-05-11 at 19:05 +0100, Thomas Oldbury wrote: > Sometimes, I want to add an inner polygon area to a plane in PCB. The > � � area might be a power supply which only has to cover a small area; e.g. > � � 1.8V in a predominantly 3.3V area. However, if I just draw a polygon on > � � top of the plane, there is no cut-out formed and I get shorts. To do > � � what I want, I must cut a hole in the main polygon plane, then add my > � � smaller polygon into it. This is very time consuming and changing the > � � plane once created is very difficult. Is there a way to get PCB to > � � support nested polygons? Not easily. For many power plane cases, these polygons won't actually be truly nested, so it is impossible to infer which polygon the user wishes to clip the other. Perhaps it would be possible to support a flag on the "smaller", clippiING polygon which makes it "bully" other polygons away from it, but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). This class of object would not be so much a "pour", but behave more like a line or arc segment. I'm guessing we would still need to retain support for clipping it against pins, pads, lines and arcs. Shouldn't take "that" much code to make it happen (I already implemented a similar feature once before), I just need to hear that there is general consensus that it is a sensible thing to do. I'm more in favor of "anti-traces". They'd be equivalent to zero width traces, but still push polygon out of the way. Then you wouldn't need a nested polygon, just an anti-trace that goes around the border of the new region. References 1. mailto:pc...@cam.ac.uk ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Out and In symbols in gschem & getting net names to come out in PCB
On Sun, May 1, 2011 at 3:49 PM, Rob Butts wrote: > I'm using out and in symbols in gschem to label nets in a schematic and > tie nets together without traces running everywhere. I set the net > attribute of the corresponding out and in symbols in the schematic to > the same value (clk for example) and connect these symbols to various > pins of various chips. When I run gsch2pcb and look at the netlist I > don't see those nets listed which makes me feel the pins of all the > chips I tie the out and in symbols to are not connected. How do I use > these symbols correctly? > Thanks Just put the attribute on the net and drag the attribute name over to the in/out symbol ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
On Wed, Apr 13, 2011 at 1:31 AM, Andy Fierman wrote: > If you are going to model the PA - particularly to look at resonance > effects - then you should include reasonably accurate models for the > inductors and capacitors which include their major parasitic > components. > > The Murata Chip S-Parameter & Impedance Library is a handy tool for > looking at their ceramic capacitor and inductor behaviour. > > http://www.murata.com/products/design_support/mcsil/index.html > > or there's an online version: > > http://ds.murata.com/software/simsurfing/en-us/index.html > Hmm...it seems to be an .exe. Do they have a table or something? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Attribute Net (without pin assignment) - for Power and Port Symbols
On Mon, Apr 11, 2011 at 6:45 PM, John Doty wrote: > > On Apr 11, 2011, at 4:25 PM, Peter Clifton wrote: > >> I would advise a note of caution. In general, I don't like it when tools >> start special casing things like this.. it just feels wrong. > > I've long thought it a minor design flaw that indexed attributes attach the > index to the value rather than the name. So, I would prefer net:1=Vcc, while > preserving backward compatibility, of course. > You totally win! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Fri, Apr 8, 2011 at 2:18 PM, DJ Delorie wrote: > >> # shorting trace >> Pad [ -1.550mm 0.000mm 1.550mm 0.000mm 0.5mm 0.5mm 0.700mm "c" "c" >> "square" ] > > > Perhaps a new flag for pads that means "non-net copper" ? Then > "square,nonnet" (for example) tells 'o' to ignore that copper when > determining connectivity, but DRC would still check it for > manufacturability. > > In theory, we could support that flag in *any* object, but I'm not > sure how to manage the relationship between, say, a non-net trace on > an inner plane and the schematic/netlist. I asked someone who used a > BigName EDA package how they did it, and they had a completely > different class of object for these - a net-linking object in the > schematics, netlist, and layout. > Seems like a neat concept. Suppose it would be treated as regular copper throughout PCB except that when the netlister got to it, it would not cross it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Fri, Apr 8, 2011 at 9:39 AM, rickman wrote: > On 4/7/2011 1:13 PM, Stephan Boettcher wrote: >> >> rickman writes: >> >>> I have to say I am philosophically opposed to any feature that allows >>> a design to pass DRC when the layout differs from the schematic. >> >> Just to get the terminology right: >> >> DRC has no business to care about the schematics at all. There shall be >> a tool to check if the layout implements the schematics netlist, but >> that is a different issue. >> >> PCB implements this distiction properly. DRC checks consider coper >> structures as layed out when evaluating the rules, without regard to the >> netlist. >> >> The Rat's-nest (O-key) ignores DRC rules when checking connectivity. > > Ok, if you want to be pedantic the net list is not the schematic, but if > the netlist differs from the schematic, then you have another problem. > > DRC is a part of my design process which includes a verification that the > layout matches the net list. In fact, my number 1 "design rule" to be > checked is that they match. What button I push to get the tool to do my > required design rule checking is irrelevant. It is just a tool and does not > define my process. > > So my point is that adding an attribute to any copper to tell the tool to > ignore the connectivity violates my idea of design rule checking. > I'm not sure if it could be done simpler, but for a special copper trace that connects two planes, you would do DRC twice, one time ignoring between the trace and plane A, and another between the trace and plane B. Or perhaps just run that portion of the DRC twice. Or just make a special region where the connectivity between net A and net B is ignored where they touch. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: zview/ngscope
2011/4/7 Rubén Gómez Antolí : > Hi: > > El 06/04/11 16:42, John Doty escribió: >> >> On Apr 6, 2011, at 8:26 AM, Dave McGuire wrote: >> >>> On 4/6/11 3:01 AM, Stephan Boettcher wrote: > > Specifically, the suite misses a way for fast turnaround of schematic > modification, simulation and display. make >>> >>> Exactly. >> >> Especially for simulation, where you very often aren't just running the >> simulator itself. >> >> You may need to process netlists with spicepp.pl or some other script, to >> fix SPICE dialect dependencies or other problems. >> >> You may need to generate stimulus files or command files. >> >> You may need to update subcircuit libraries before simulating. >> >> You may need to postprocess the simulation data to extract the information >> you seek. >> >> The simulation may be part of some larger process. For example the final >> product may be a report containing plots or other data generated from >> simulations. >> >> This is one place where gEDA's modular toolkit approach really shines. It >> saves me an enormous amount of time relative to the more integrated tools I >> once used. One really nice thing about makefiles is that while I often >> forget how to make some data product, the makefile doesn't. > > You are right but, what about the users? > eh, I think spice is always going to be one of those things that takes some learning. An IBIS tool would be a much better match for GUI integration. For me, the most non-intuitive things were the naming of the '0' net and the use of the tran command in ngspice, past that, everything was pretty intuitive. One of the problems is the howto is more of a manual: http://www.geda.seul.org/wiki/geda:csygas A tutorial with an example design would be of enormous help. A nice example might be an unterminated vs terminated transmission line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Wed, Apr 6, 2011 at 2:51 PM, Stephen Ecob wrote: >> What, if there was a way to flag a track as "don't look" for connectivity >> check? You'd attach the flag to the segment that bridges the domains. >> That way, the DRC check would still be sensitive to violations at other >> places. Such a DRCignore flag might have more legitimate uses. E.g, the >> outline lines may be be marked like this if vias deliberately hang over >> the edge of the board. > > It would certainly be useful - I'd use it on just about every board I lay out. > This idea is close to what was discussed in January 24-28 in the > thread "gEDA-user: gschem: directly connecting two nets?" > The thread seems to be discussing a slightly different topic. From what I gather, a schematic has two nets, say VCC2V5 and VCCAUX. At some point, you just want to bridge the two so that VCC2V5 is providing VCCAUX. When transitioning over to PCB from gschem, there is then no difference between connecting a component to VCC2V5 or VCCAUX. The use case I'm talking about, you have two nets, say GND and AGND1 which are two planes that are connected at a single point. Connecting a component on the AGND1 side is different that connecting a component on the GND side. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Wed, Apr 6, 2011 at 2:41 PM, Kai-Martin Knaak wrote: > Kovacs Levente wrote: > >> I think the workaround in gEDA is still a good way to go. > > The bogus DRC error potentially masks erroneous connections between > the planes elsewhere. > > What, if there was a way to flag a track as "don't look" for connectivity > check? You'd attach the flag to the segment that bridges the domains. > That way, the DRC check would still be sensitive to violations at other > places. Such a DRCignore flag might have more legitimate uses. E.g, the > outline lines may be be marked like this if vias deliberately hang over > the edge of the board. > Yes, but then if I forgot that track for a given isolated ground plane, there would be no netlist error. That's why I was thinking more along the lines of a component that can exist on any layer. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Split ground planes and zero ohm jumpers
On Tue, Apr 5, 2011 at 1:53 AM, Kovacs Levente wrote: > On Mon, 4 Apr 2011 23:30:21 -0700 > Russell Dill wrote: > >> The common way to track common ground planes seems to be to place a >> jumper between the planes so that the netlist can be sane. This >> requires a component to be placed on one of the outer layers of the >> board, which is a bit of an annoyance. Is there any other way of doing >> this? Maybe some kind of hacked component on an inner layer? > > What I do is I place a 0Ohm resistor, and when the layout is ready, I short it > with a line. This will give DRC error, but I ignore it. Perhaps I'll go with a solder blob jumper. A "drawbridge" component in PCB that is just a special type of trace would be really nice. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Split ground planes and zero ohm jumpers
The common way to track common ground planes seems to be to place a jumper between the planes so that the netlist can be sane. This requires a component to be placed on one of the outer layers of the board, which is a bit of an annoyance. Is there any other way of doing this? Maybe some kind of hacked component on an inner layer? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: New mass attribute tool: gattrib_csv
On Fri, Apr 1, 2011 at 2:19 PM, Joshua wrote: > Hey guys. I wrote a tool which exports and imports the properties from a > project to and to a csv file. The format is simular to that of the bom2 > format as it groups lines together which have similar data. This way I > could use oocalc to mass edit the attributes. Each component in my design > now has its price, distributer, manufactuer, width. height. etc etc. > asociated with it. Because similar data shows up on the same line I could > specify the vendor for all 40 resistors of a particular value with a single > edit, and then the vendor for 20 caps with another single edit. I can copy > and paste a row of attributes from one group of parts to another group of > parts. It accepts an filter file to specify which attributes to export. > Parts do not need to have refdeses before the tool can work. Parts are > distinguished by position in the csv when the refdes is not specific enough. > Do backup your project before you try it. It can be downloaded from > > http://public.laserlinc.com/Joshua/gattrib_csv.java > > I know. It is written in java. The following command compiles it to exe. > > gcj --main=gattrib_csv -o gattrib_csv gattrib_csv.java > > Have fun :-) > ~Joshua You may find that there is some effort duplication going on: http://www.gedasymbols.org/user/dj_delorie/ # sch2csv - extract part attributes to a comma seperated list (open with openoffice calc) # csv2sch - merge part attributes to schematics. To use these: $ sch2csv [-o foo.csv] *.sch $ ooffice foo.csv $ csv2sch foo.csv [*.sch] If you don't specify -o file for sch2csv, the CSV is printed to stdout. If you don't specify any schematics for csv2sch, all the schematics mentioned in the CSV are updated. The new schematics are named foo.sch.new - the original schematics are not changed. > On 4/1/2011 12:00 PM, geda-user-requ...@moria.seul.org wrote: >> >> Send geda-user mailing list submissions to >> geda-user@moria.seul.org >> >> To subscribe or unsubscribe via the World Wide Web, visit >> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user >> or, via email, send a message with subject or body 'help' to >> geda-user-requ...@moria.seul.org >> >> You can reach the person managing the list at >> geda-user-ow...@moria.seul.org >> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of geda-user digest..." >> >> >> Today's Topics: >> >> 1. Re: SC70-6, which is pin 1? (Stephen Trier) >> 2. Re: SC70-6, which is pin 1? (Duncan Drennan) >> 3. Re: SC70-6, which is pin 1? (Cullen Newsom) >> >> >> -- >> >> Message: 1 >> Date: Fri, 1 Apr 2011 06:21:30 -0400 >> From: Stephen Trier >> Subject: Re: gEDA-user: SC70-6, which is pin 1? >> To: gEDA user mailing list >> Message-ID: >> >> Content-Type: text/plain; charset="iso-8859-1" >> >> It's hard to be sure from the picture, though my best guess matches yours. >> If you want to be sure, take a look in the data sheet for the package >> markings section. It will tell you what to look for. >> >> Stephen >> -- next part -- >> It's hard to be sure from the picture, though my best guess matches >> yours. If you want to be sure, take a look in the data sheet for the >> package markings section. It will tell you what to look for. >> >> Stephen >> >> -- >> >> Message: 2 >> Date: Fri, 1 Apr 2011 12:58:41 +0200 >> From: Duncan Drennan >> Subject: Re: gEDA-user: SC70-6, which is pin 1? >> To: gEDA user mailing list >> Message-ID: >> >> Content-Type: text/plain; charset=ISO-8859-1 >> >>> I'm guessing based off that mark the bottom left pin is pin 1. The >>> datasheet isn't clear. Does anybody know for sure if thats pin 1? >> >> Yes, bottom left is pin 1. >> >> >> -- >> >> Message: 3 >> Date: Fri, 1 Apr 2011 07:21:06 -0500 >> From: Cullen Newsom >> Subject: Re: gEDA-user: SC70-6, which is pin 1? >> To: gEDA user mailing list >> Message-ID: >> >> Content-Type: text/plain; charset="iso-8859-1" >> >> Have you got a part number for it? What's inside? You could use a DMM to >> confirm, if you consider its internals. Your guess of bottom left seems >> reasonable. >> >> -CN >> >> On Fri, Apr 1, 2011 at 4:13 AM, yamazakir2 wrote: >> >>> I'm guessing based off that mark the bottom left pin is pin 1. The >>> datasheet isn't clear. Does anybody know for sure if thats pin 1? >>> >>> >>> >>> ___ >>> geda-user mailing list >>> geda-user@moria.seul.org >>> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user >>> >>> >> -- next part -- >> Have you got a part number for it? What's inside? You could use a DMM >> to confirm, if you consider its internals. Your guess of bottom left >> seems reasonable. >>
Re: gEDA-user: nice C++ (was Re: pcb plugin smartdisperse fails on load)
On Fri, Feb 25, 2011 at 4:20 PM, Cyril Hrubis wrote: > Hi! >> Tastes may vary, but some years ago when I went looking for a clean >> C++ matrix math class library, I was favorably impressed by newmat >> http://www.robertnz.net/nm_intro.htm >> Operator overloading with a clear purpose! > > Thanks a lot. That is quite impressive library. Now all I need is rainy > day to play with the code... > I had good luck with boost's ublas, but as the ROS people have noted there are some holes: http://www.ros.org/wiki/ROS/MathLibraries On a somewhat related note, boost is a pretty good option if you are looking for platform and toolkit independence in a general sense. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Breaking up power planes
On Mon, Feb 21, 2011 at 12:40 AM, Stephan Boettcher wrote: > Russell Dill writes: > >> On Sun, Feb 20, 2011 at 10:05 AM, Kai-Martin Knaak wrote: >>> Russell Dill wrote: >>> >>>> I'm just wondering what everyones preferred method of breaking up >>>> power/ground planes is. >>> >>> My preferred method is to break the planes as little as possible :-) >>> IMHO, a continuous copper plane is the best you can get for shielding >>> purposes. If large amounts current need to be canalized, I prefer to >>> guide them in fat tracks rather than polygons. With tracks it is easier >>> to ensure a minimum diameter. >>> >> >> My design has several different power and IO rails, and so it requires >> split power planes.I realize its possible to do with the polygon >> editor, it just seems like it'd be much easier with the line drawing >> tool. > > You want to split a polygon into different nets? Does that work? Even > if you invoke the special magic to not loose isolated parts of the > polygon, will the connectivity check treat them as separate copper and > assign them to different nets? > > I've drawn separate polys for each power/gnd net on my boards. > > Let's see, ok, it does work. I'd still be uncomfortable with such a > layout. > I haven't had the chance to test it yet, but I just found the magic command that completes the cycle: --- MorphPolygon(Object|Selected) Converts dead polygon islands into separate polygons. If a polygon is divided into unconnected "islands", you can use this command to convert the otherwise disappeared islands into separate polygons. Be sure the cursor is over a portion of the polygon that remains visible. Very small islands that may flake off are automatically deleted. --- So draw a polygon pour that fills the board, then draw traces that clear the desired amount of spacing to split up the planes. Perform a :MorphPolygon(Object), and then delete the traces. Of course, editing is still a bit of an issue. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: General Layers questions
On Thu, Feb 24, 2011 at 3:04 PM, Martin Kupec wrote: > Hi, > > I have written something to: http://geda.seul.org/wiki/geda:pcb_layers > > It is still a bit work in progess, but you can start editing it to fit your > ideas. I have tried to incorporate all ideas discussed. > > Martin Kupec > It'd also be nice to have a courtyard and assembly drawing layer, at the very least a courtyard layer so that component silkscreen can be defined differently than just the minimum component spacing. http://blogs.mentor.com/tom-hausherr/blog/2010/11/18/pcb-design-perfection-starts-in-the-cad-library-part-6/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb plugin smartdisperse fails on load
On Thu, Feb 24, 2011 at 8:50 AM, Peter Clifton wrote: > On Thu, 2011-02-24 at 08:38 -0700, John Doty wrote: >> On Feb 24, 2011, at 8:22 AM, Peter Clifton wrote: >> >> > Means C didn't find the function, and it assumes it returns integer in >> > that case. Dumb convention IMO. >> >> "C is quirky, flawed, and an enormous success." - Dennis M. Ritchie. > > True.. very true. I believe the behaviour in question dates back to the > days where prototypes were very different, and C sometimes had to > assume. > > I've been debugging some problems in a large 3D CAD + FEA system written > in C++ recently. Give me nice C code that ANY day over that impenetrable > crap. > > ...if only there was some sort of flag or option that could be passed to the compiler to convince it otherwise... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Metric, Imperial, Rounding, DRC, and board houses
I'm starting a new design and all my components are metric based, including a few 1mm pitch BGA components. I'd really like to do the layout in metric, but I'm worried about two factors. The first of which is that PCB does not yet have the option to store things internally in metric (at least from what I understand) so rounding may occur on that end. In addition, my board house rounds everything to 2.4 format (0.1 mil). I can envision several scenarios where my design meets DRC in PCB, but fails when I send it to the board house. What is my best option? Just use imperial units and cope with weird grids? Use metric spacing, but recalculate DRC based on worst case rounding? Some other option? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Breaking up power planes
On Sun, Feb 20, 2011 at 10:05 AM, Kai-Martin Knaak wrote: > Russell Dill wrote: > >> I'm just wondering what everyones preferred method of breaking up >> power/ground planes is. > > My preferred method is to break the planes as little as possible :-) > IMHO, a continuous copper plane is the best you can get for shielding > purposes. If large amounts current need to be canalized, I prefer to > guide them in fat tracks rather than polygons. With tracks it is easier > to ensure a minimum diameter. > My design has several different power and IO rails, and so it requires split power planes.I realize its possible to do with the polygon editor, it just seems like it'd be much easier with the line drawing tool. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Breaking up power planes
I'm just wondering what everyones preferred method of breaking up power/ground planes is. Way back when I used to break them up by using the polygon editor which was really a pain. It seems like using a 0 width trace might work well, but it produces a zero width line on the gerber, bummer. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
