Re: gEDA-user: TV card question
Ales (and everybody else), My apologies, I inadvertently posted this to the wrong group! :-0 Vaughn Ales Hvezda wrote: Hi, Here's a question for the MythTV experts in the group. [snip] You may want to post these questions to the MythTV users group. I'm sure there are more MythTV experts there. Whoa, that seems like quite a lively list based on the archives. http://www.mythtv.org/mailman/listinfo/mythtv-users/ Thanks, -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Transformer as voltage transducer?
Randall, I just happened to do some research on this. The following part: NEC PS2505L-4-A is a quad optocoupler. On the input side, each optocoupler has two diodes connected in opposite directions. These stimulate a phototranistor output. I was using them mainly to see if an 24 VAC control voltage was on or off, so I set up the circuit to go into saturation. I also put a large cap on the output to smooth the voltage. But you can limit the current on the input so you get an output that's proportional to the input. One possible downside (for your application) is that this circuit will full-wave rectify your signal. There's another part, the 2501, which has only a single diode on the input. You could use two 2501 couplers to measure the positive and negative parts of the waveform. Vaughn John Doty wrote: On May 25, 2007, at 7:21 PM, Randall Nortman wrote: I would like to measure mains voltage (110-240V, 60Hz), but I want my measurement circuit to be isolated from the voltage being measured. I am going to be sampling the waveform at a high sample rate (relative to the 60Hz waveform being measured) and comparing that with the current on the same lines with (near-)simultaneous measurement. So it is important to me that the voltage waveform not be distorted or phase-shifted, and the voltage I see should be related to the source voltage by a simple linear ratio. Seems like a simple transformer will do it, in theory. But I'm not sure about how they will work in the real world. Do transformers distort the voltage waveform or phase? Some. Cores are nonlinear, there are ohmic losses, eddy current losses, magnetization inductance, leakage inductance, capacitance, ... For a stiff voltage drive and a light load, you'll probably find the distortion minimal. But you haven't stated a quantitative requirement and transformer manufacturers generally don't write specs in a way you can relate to here, so you'll want to to get a transformer and make some measurements, I suppose. What happens if I put a load on the secondary of more than a few nA? For a small power transformer you'll probably find the difference between no load and 1 mA difficult to measure. What non-linearities are there? Mainly the nonlinear hysteresis curve of the core. What sort of transformers are going to give me the best response? Hard to say. Again, you haven't stated quantitative requirements, and the usual specs won't tell you anyway. So, I suggest just getting a cheap power transformer, trying it (look at the AC in and out on a scope, say), and if it isn't good enough come back here with details of the problem. Or if the transformer idea is awful, any other ideas for isolated voltage transducers? A transformer is probably fine. Alternatively, google isolation amplifier. These are good for sensing current (through a small resistor) too. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some Linux distros to consider
Marc Moreau wrote: On Wed, 28 Mar 2007 20:15:23 -0700 (PDT) Jason Elder [EMAIL PROTECTED] wrote: I recently installed linux on my machine for the sole purpose to install gEDA. I went through a couple of Linux installations before I got gEDA to work and I would like to share my feedback. (Short answer below...see conclusion) There were 3 criteria I wanted the distro to fulfill be fore I chose: 1) It had to have Firefox 2.0 or later, 2) It had to have the latest version of OpenOffice, 3) I wanted the source code as well as development packages to be installed with a full install of the distro. In these three regards, might I sugest Gentoo. That is the distro I use. The only thing that my be an issue is in your conclusion. [cut] My goal here was to find one that I can download, burn, install, have the latest version of firefox and openoffice, and then install gEDA with minimum hassle. Gentoo is great IMO for the top three criteria, however it does require some tinkering. The just works quotient is pretty low. For a home where tinkering is okay, it's great. *nix experience is most decidedly required -- not a newbie distro. my 2c. -Marc CentOS has worked out fine for me. I actually chose it because I had to have a clone of Red Hat Enterprise Linux for another project. It just happened to work will with gEDA. Vaughn T. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PIC TQFP symbol
Mark Rages wrote: On 11/4/06, Vaughn Treude [EMAIL PROTECTED] wrote: John Luciani wrote: On 11/4/06, Vaughn Treude [EMAIL PROTECTED] wrote: Hello all: Excuse me if I've missed this in some obvious place, but I can't find a symbol in standard library for the TQFP version of the PIC18F4420. I know that other gEDA contributors sometimes keep symbols on their own sites. Does anyone have one already done? Thanks! Vaughn Treude I have a footprint which *may* work --- QFP-80P-1380L1-1380L2-44N 0.8mm pitch, 13.8mm lead span, 44 pins John, Thanks, but what I was really looking for was the symbol with the TQFP pinout, which is different than the DIP-40 pinout. Vaughn It's not too hard to make your own using djboxsym. http://www.gedasymbols.org/user/dj_delorie/tools/djboxsym.html Mark, Thanks for the suggestion. I did already make my own, by copying the file for the DIP-40 part and changing it, mostly by editing the text in emacs and then by moving stuff around in gschem. Next time I'll have to check out djboxsym. Vaughn If you don't want to install it, try the interactive interface I made: http://vivara.net/cgi-bin/djboxsym.cgi Regards, Mark [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PIC TQFP symbol
Hello all: Excuse me if I've missed this in some obvious place, but I can't find a symbol in standard library for the TQFP version of the PIC18F4420. I know that other gEDA contributors sometimes keep symbols on their own sites. Does anyone have one already done? Thanks! Vaughn Treude ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Newbie PCB DRC questions
I forgot to thank everyone for their helpful responses to my question. The ensuing message thread also brought up additional interesting information. I was able to complete my board and get the files to the board house for production. I did end up doing a lot of manual modification to the auto-routed traces; but had I been more experienced I think there would have been less of this. For example, it would have made sense to manually connect the isolation capacitors to their respective IC's, and THEN run the auto-route, because the auto-router knew nothing of these location considerations. I'll know better next time. :=) Thanks again! Vaughn On Mon, 2006-10-02 at 10:27, Vaughn Treude wrote: Hello everyone: I've been checking my board layout with the Design Rule Checker command in PCB. I was encountering some mysterious behavior and wondering if anybody could explain this a little. 1. The default minimum spacing is 10 mils, yet DRC flags everything that is exactly 10 mils. This is a problem because the auto-router put traces 10 mils apart in many places. I tried changing the minimum spacing to 9.9 or 9, but apparently that's not valid because it does not retain that value. (In fact, the preferences dialog experiences an error if I do this, and refuses to close the second time I bring it up.) So I set the min-spacing to 5 mils and DRC found a few problems in the lines I'd added manually, which I was able to correct. Does this mean the actual minimum spacing should be 15 mils or something like that, so that auto-routed traces will pass the DRC 10 mil guideline? 2. I've been seeing potential for broken trace error a lot. In some cases I can see that a line has some unnecessary jags in it which I've then straightened out. In other cases the only problem seems to be that two connecting lines that go in the same direction have for some reason not been merged into a single line. It's my understanding that if the trace _looks_ continuous (at a pretty high zoom) it _is_ continuous. Is DRC flagging nonexistent errors here or is my understanding incorrect? 3. Sometimes when DRC reports copper areas too close, I go to the coordinates specified in the message and I cannot for the life of me find anything closer than 10 mils. (And I still have it checking for 5 mil spacings.) Does DRC sometimes get fooled into thinking that connected lines should be separated? Or am I misinterpreting the errors? Thanks! Vaughn T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Newbie PCB DRC questions
Hello everyone: I've been checking my board layout with the Design Rule Checker command in PCB. I was encountering some mysterious behavior and wondering if anybody could explain this a little. 1. The default minimum spacing is 10 mils, yet DRC flags everything that is exactly 10 mils. This is a problem because the auto-router put traces 10 mils apart in many places. I tried changing the minimum spacing to 9.9 or 9, but apparently that's not valid because it does not retain that value. (In fact, the preferences dialog experiences an error if I do this, and refuses to close the second time I bring it up.) So I set the min-spacing to 5 mils and DRC found a few problems in the lines I'd added manually, which I was able to correct. Does this mean the actual minimum spacing should be 15 mils or something like that, so that auto-routed traces will pass the DRC 10 mil guideline? 2. I've been seeing potential for broken trace error a lot. In some cases I can see that a line has some unnecessary jags in it which I've then straightened out. In other cases the only problem seems to be that two connecting lines that go in the same direction have for some reason not been merged into a single line. It's my understanding that if the trace _looks_ continuous (at a pretty high zoom) it _is_ continuous. Is DRC flagging nonexistent errors here or is my understanding incorrect? 3. Sometimes when DRC reports copper areas too close, I go to the coordinates specified in the message and I cannot for the life of me find anything closer than 10 mils. (And I still have it checking for 5 mil spacings.) Does DRC sometimes get fooled into thinking that connected lines should be separated? Or am I misinterpreting the errors? Thanks! Vaughn T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: auto router quirks
On Thu, 2006-09-28 at 17:30, DJ Delorie wrote: I've noticed that if you mention the auto-router there's a deathly silence here. That's because the guy that wrote the autorouter isn't participating any more. This brings up the question: how reliable is the auto-router anyway? Is it a reasonable idea to use it for non-critical projects - providing, of course, a person does a careful visual inspection of the traces? Vaughn T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem: how to connect signals between sheets?
Hello everyone: Sorry, but I'm having a little trouble figuring this one out. My circuit diagram is on two sheets. I need to connect a small number of signals between them. I found the symbols input-1 and output-1 which looked just like the ones that people use for this purpose. I added them to the circuit and designated them IO1 through IO6. One one board, IO1 through IO3 were inputs and IO4 through IO6 were outputs, on the other, vice versa. Of course the net list does not generate correctly; I have to edit it by hand to merge the twelve nets with IO designators in them. Also I ended up defining slots, since gschem didn't like the duplicate designators. So now the program complains about incomplete slot definitions. I'm sure there's something I'm missing. Is there a special property or something I can define for these symbols so this works correctly? Thanks! Vaughn T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On Wed, 2006-09-27 at 07:48, John Luciani wrote: On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote: I also hadn't yet figured out how to connect Vcc to +5V and Vss to ground. Googling I found a reference to using netname for this purpose. So I added the netname Vcc to one of the +5V symbols and Vss to one of the ground symbols, and yet these aren't hooking up either. I wonder if there's something else I might be missing. You are probably using schematic symbols with embedded power pins that have names that differ from your netnames. Use a text editor and look for the net attributes in the symbols you are using. If you search the list you will see various discussions of embedded power pins. I've opened the different IC symbols and displayed the details. Some use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a +5V symbol and the other two to the ground symbol. Didn't help, sad to say. It is best to Just say no! to embedded power pins ;-) Sorry, I'm a newbie, I don't know how to do that. If it involves redesigning existing symbols, I don't have time to change them all. If there is another way to do it, I'm open to suggestions. Vaughn (* jcl *) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On Wed, 2006-09-27 at 09:59, John Luciani wrote:
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
On Wed, 2006-09-27 at 07:48, John Luciani wrote:
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
I also hadn't yet figured out how to connect Vcc to +5V and Vss to
ground. Googling I found a reference to using netname for this
purpose. So I added the netname Vcc to one of the +5V symbols and Vss
to one of the ground symbols, and yet these aren't hooking up either.
I wonder if there's something else I might be missing.
You are probably using schematic symbols with embedded power pins that
have
names that differ from your netnames. Use a text editor and look for the
net
attributes in the symbols you are using. If you search the list you
will see various discussions of embedded power pins.
I've opened the different IC symbols and displayed the details. Some
use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a
+5V symbol and the other two to the ground symbol. Didn't help, sad to
say.
You should be able to connect these. Create a *simple* schematic using
embedded symbols and post it. To get embedded symbols select the
Embed component in schematic option in the Select component
window.
Does it only work when all the components are embedded? Sounds like
that could make the resulting file pretty big.
I've attached the SCH file rather than putting it in line - hope that's
OK. I've embedded all the components, and it still doesn't consolidate
+5V and Vcc.
I'm using gschem version 20060123. Do any of the versions have known
bugs in this respect?
Vaughn T
It is best to Just say no! to embedded power pins ;-)
Sorry, I'm a newbie, I don't know how to do that. If it involves
redesigning existing symbols, I don't have time to change them all. If
there is another way to do it, I'm open to suggestions.
The script below will create a symbol without embedded power connections
for each symbol file found in the current working directory. See the script
for usage information. Backup your files in the CWD just in case.
(* jcl *)
-
http://www.luciani.org
#!/usr/bin/perl
# Copyright (C) 2006 John C. Luciani Jr.
# This program may be distributed or modified under the terms of
# version 0.2 of the No-Fee Software License published by
# John C. Luciani Jr.
# A copy of the license is at the end of this file.
#
# For each symbol in the current directory this script creates a new
# symbol without the embedded power connections and a new symbol with
# only the power pins. The symbol without the power pins has an _np
# suffix. The symbol containing only the power pins has a _pwr
# suffix. Since many symbols contain the same pinout for power pins
# the power pin symbol is a symlink to a generic symbol.
# This script only works for symbols with one power net and one
# ground. The routine that creates the power pin symbols has
# specifications for only two pins.
use strict;
use warnings;
use Carp;
use IO::File;
# @Power_pins ... each element of this array is an anonymous hash containing
# the filename, Vcc pin number, and GND pin number.
# @Net_names names of the power nets to remove.
# @Files all of the symbol files in the current directory.
my @Net_names = $#ARGV == -1 ? qw(Vcc GND) : @ARGV;
my @Files = *.sym;
my @Power_pins;
# To find the power pins we look for a text line followed by a
# net=NET_NAME line where NET_NAME is an element in the array
# @Net_names
foreach my $filename (@Files) {
# skip the files that were created by this script.
next if $filename =~ /_np.sym$/; # already done
next if $filename =~ /^pwr/; # generic power symbol
next if $filename =~ /_pwr.sym$/; # power symbol symlink
print $filename\n;
@ARGV = ($filename);
my $np_filename = $filename;
$np_filename =~ s/\.sym/_np.sym/;
my %pins; # contains the filename and power pins for the current symbol
open(OUT, $np_filename) || croak Could not open $np_filename
for output: $!;
while () {
print(OUT), next unless /^\s*T/;
# Found a text line.
my $text = $_;
my $line = ;
my $power_net_p;
foreach my $net_name (@Net_names) {
next unless $line =~ /^\s*net\s*=\s*$net_name\s*:\s*(\d+)/;
$pins{$net_name} = $1;
$power_net_p = 1;
last;
}
print(OUT $text, $line) unless defined $power_net_p;
}
close(OUT) || croak Could not close $np_filename;
push @Power_pins, { filename = $filename, %pins };
}
# gschem constants --- DO NOT CHANGE THESE
use constant NORMAL_PIN = 0;
use constant FIRST_POINT_ACTIVE = 0;
use constant VISIBLE = 1;
use constant SHOW_VALUE = 1;
use constant ANCHOR_SW = 0;
use constant ANCHOR_NW = 2;
use constant ANCHOR_N = 5;
use constant ANCHOR_S
Re: gEDA-user: gschem: how to connect signals between sheets?
snip Does it only work when all the components are embedded? Sounds like that could make the resulting file pretty big. No. Embedding components is useful when sending your schematic to someone else who may not use the library that you are using. I've attached the SCH file rather than putting it in line - hope that's OK. I've embedded all the components, and it still doesn't consolidate +5V and Vcc. The problem is that you did not connect your power symbols to their respective components with a net. You have the pin ends against each other. If you move the power symbols and use net connections the schematic will netlist and load into PCB. The schematic below will netlist and load into PCB (provided that you update the footprint attributes to match footprints on your system). (* jcl *) You're right, I goofed. :-) It's easy to miss that because the red square goes away making it look like the two components connected. I did a netlist of the modified file and it looked the same as the previous one I had. Perhaps it gets modified when it's sucked into PCB. I'm not actually averse to creating custom devices; In the last couple of weeks I've created about a dozen gschem symbols and at least that many pcb footprints. It's just that I'm getting tired of all the work! :-) I'm beginning to think it may be worthwhile to convert the 14 or so devices on my existing schematic to a no embedded net format. Your script would make that easier; I was afraid I'd have to do it manually. I like the idea of having the +5 and ground connections shown with the decoupling capacitor. It's unfortunate it requires a separate symbol, but I don't think there's any really clean way to approach it, considering that the power pins don't fit into the slot concept. I did something similar when I created a symbol for the 2013 open-collector driver device. There's a pin for a common pull up (which does not connect directly to the power), and I didn't really know how to implement the embedded nets, so I just created a separate triangular buffer symbol which had an extra pin on it, and put just one instance of that on my schematic. Thanks to you, and to John G., for all your help! Vaughn ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On Wed, 2006-09-27 at 14:54, John Luciani wrote: On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote: snip Does it only work when all the components are embedded? Sounds like that could make the resulting file pretty big. No. Embedding components is useful when sending your schematic to someone else who may not use the library that you are using. I've attached the SCH file rather than putting it in line - hope that's OK. I've embedded all the components, and it still doesn't consolidate +5V and Vcc. The problem is that you did not connect your power symbols to their respective components with a net. You have the pin ends against each other. If you move the power symbols and use net connections the schematic will netlist and load into PCB. The schematic below will netlist and load into PCB (provided that you update the footprint attributes to match footprints on your system). (* jcl *) You're right, I goofed. :-) It's easy to miss that because the red square goes away making it look like the two components connected. I did a netlist of the modified file and it looked the same as the previous one I had. Perhaps it gets modified when it's sucked into PCB. I'm not actually averse to creating custom devices; In the last couple of weeks I've created about a dozen gschem symbols and at least that many pcb footprints. It's just that I'm getting tired of all the work! :-) Managing a component library is a fair amount of work that is not much fun to do. There is no way around it. For schematic symbols you need to verify that the symbols match the manufacturer specification sheet. For PCB footprints you need to verify that the footprints match the manufacturerspecifications and your manufacturing process. I am surprised that you needed to create that many footprints since there are quite a few already created. Have you checked out gedasymbols.org and my website http://www.luciani.org/geda/pcb/pcb-footprint-list.html I did not know you had such a big collection of footprints! It would have saved me some work. My circuit has a few off-beat components on it, but I was surprised to see that a number of standard SMD components were not in there, and I ended up creating them. I'm beginning to think it may be worthwhile to convert the 14 or so devices on my existing schematic to a no embedded net format. Your script would make that easier; I was afraid I'd have to do it manually. I like the idea of having the +5 and ground connections shown with the decoupling capacitor. It's unfortunate it requires a separate symbol, but I don't think there's any really clean way to approach it, considering that the power pins don't fit into the slot concept. Having a separate symbol is a little more work but is not too bad. We have discussed (at the Freedog meetings) having multiple types of slots in a component symbol. I hate to be a pest on this issue, but I never did get gnetlist to handle the embedded nets correctly. Not that I mind that much changing the symbols to eliminate embedded power pins (I'll do whatever works) but I don't know how else to handle the connections between the sheets of the schematic. I can't afford the time to keep manually correcting the netlists. I don't know what version of gnetlist I'm using, as the usage message didn't seem to include version info. But am I correct in using the -g PCB flag? I don't see what I'm doing wrong, but there must be something. When I netlist the modified SCH file you sent me still does not consolidate the +5V and Vcc nets. I get the following result: +5V R1-1 unnamed_net3U1-10 R1-2 R2-1 GND R2-2 U1-7 Vcc U1-14 unnamed_net2U1-6 U1-2 unnamed_net1U1-9 U1-4 U1-3 Besides gnetlist, is there some other way to generate a netlist? Thanks again, Vaughn Thanks to you, and to John G., for all your help! Your welcome. (* jcl *) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB a bad name ?
On Wed, 2006-09-20 at 21:51, Dave McGuire wrote: On Sep 21, 2006, at 12:49 AM, Vaughn Treude wrote: Yes, I agree. A large number of PCB beginners, however, complain about the UI and assume it's unusual because it was thrown together without any sort of attention, while I'm certain the opposite is true. I didn't mean to imply that it was badly designed, just that it was the earliest program in the suite, and it was written for an OS that's not (to my knowledge) in common use anymore. Therefore it may have been designed to different standards. UNIX isn't in common use anymore?! -Dave It was my understanding that the very first version of PCB was written for an Atari. If I'm mistaken about that, I stand corrected. Vaughn -- Dave McGuire Cape Coral, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating SMT element in PCB
On Thu, 2006-09-21 at 07:26, DJ Delorie wrote: I am trying to create a footprint for an SMT device (it's an SDIP, which doesn't appear to be in the library.) The manufacturer spec gave me the exact dimensions for http://www.gedasymbols.org/user/dj_delorie/tools/dilpad.html the pads, which I created using the rectangle tool. No, use the line tool. sigh I was hoping there was some arcane command that could convert the pads into something the program would understand. It sure would be cool if you could create pads using the rectangle tool. But I don't want to be restricted to the four different line widths that PCB gives me; You can change those widths on the fly; it doesn't affect the lines already on the board. The four are the four you can quickly choose between, but you can change them all you want. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating SMT element in PCB
On Thu, 2006-09-21 at 09:07, DJ Delorie wrote: sigh I was hoping there was some arcane command that could convert the pads into something the program would understand. It sure would be cool if you could create pads using the rectangle tool. Yeah, that would be cool. However, rectangles are just one simplification of polygons; they're stored as four-point polys internally. How do we convert an arbitrary polygon? We can't, really. And when you convert back to parts (break up the element), do you use lines or rectangles? Not insurmountable problems, but reasons why we went with the easy options ;-) Yeah, I can understand that. The lines do work, but they're a bit tricky, since you have to account for line width when figuring out the length. Thanks for your help! Vaughn ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Creating SMT element in PCB
On Thu, 2006-09-21 at 10:14, ptay wrote: Vaughn Treude wrote: pads into something the program would understand. It sure would be cool if you could create pads using the rectangle tool. Thanks for the suggestion. I actually did do a couple of them by the text method, but it was time-consuming for me - I make mistakes pretty easily in that mode. I have been editing the text files after I use the GUI to create them, because I don't know how to make the GUI number the pins correctly. :-) Vaughn There is the sheet explaining the footprints I read to learn the footprints ... you learn it and writing footprints by hand is pretty easy until you get up to parts with dozens of pins. You want to read the section called pad in the document land_patterns found on this page: http://www.brorson.com/gEDA/ You write the footprints in text and achieve an incredible level of control and precision. After doing a few footprints the process becomes second nature (or close). Save the text files as name_of_footprint.fp in your personal footprints directory. best, phil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB a bad name ?
On Wed, 2006-09-20 at 08:41, Dave McGuire wrote: On Sep 20, 2006, at 10:24 AM, Vaughn Treude wrote: PCB's UI in particular deviates from Linux norms. Linux norms?? What exactly are the UI norms in the Linux world? Please don't tell me GTK or KDE, as some of us use neither, and some of us don't even run it under Linux. (Solaris here, in particular) -Dave LOL. Well, maybe Linux norms is a contradiction in terms. :-) But I do a lot of work on both Linux and Windows (preferably the former) and nothing in PCB seemed very intuitive to me. Vaughn -- Dave McGuire Cape Coral, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB: Moving the endpoint of a line
Hello all, I'm new to gEDA; I've been playing with it for a few weeks now, mostly gschem and pcb. Whereas the gschem interface seems reasonably standard, pcb is often maddeningly arcane. I understand that this program has evolved over many years, so perhaps that explains it. I've been trying diligently to understand the manual, but either I'm misinterpreting it or they've omitted some crucial information. This is my problem: the manual says you can either move a line or the end point of a line. I interpret the first part to mean you can move the line without changing its shape or its orientation. The second part, I think, means that pcb should allow you to grab one end of a line segment, and while the other end stays fixed, you should be able to drag that end point to lengthen, shorten, or change the angle of that segment. Am I right? If so, I have not been able to figure out how to get it to work. I've tried selecting the line first, or just clicking without selecting, and it _always_ moves the whole line, _never_ an endpoint. Note that I've read the manual enough to know that I should check the allow lines of any angle box, so I'm not restricted to multiples of 45 degrees. So what's the trick? Since gschem allows you to do this with lines in the circuit diagram, I would hope that pcb also has this capability. Thanks! Vaughn ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
