gEDA-user: Request for VHDL and Hierarchical Spice References
I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that would make simulation of complex designs interesting. Thanks, Steve Meier ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
On Wed, Nov 28, 2007 at 08:17:49AM -0800, Steve Meier wrote: I am seeking good references for verilog, VHDL and spice syntext You want the LRMs. VHDL is IEEE standard 1076; Verilog is IEEE standard 1364. The correct way would be to purchase them from the IEEE. There may be copies (legal or otherwise) available somewhere on the net if you look hard enough. HTH... -- David Smith| Tel: +44 (0)1454 462380Home: +44 (0)1454 616963 STMicroelectronics | Fax: +44 (0)1454 462305 Mobile: +44 (0)7932 642724 1000 Aztec West| TINA: 065 2380 GPG Key: 0xF13192F2 Almondsbury| Work Email: [EMAIL PROTECTED] BRISTOL, BS32 4SQ | Home Email: [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
On Wednesday 28 November 2007, Steve Meier wrote: I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that would make simulation of complex designs interesting. The Verilog-AMS LRM can be downloaded from: http://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.2/AMS-LRM-2-2.pdf The development version of gnucap accepts (and prefers) netlists in Verilog format. For Spice, there is no standard. The closest thing there is to a standard is the way Spice-2 works. Almost everything else is a proprietary superset of that. A better spec for a Spice standard is to take the intersection of what Spice-2 does and what Spice-3 does. It's a mess. It started out as a good design, with two obvious defects that could have been easily fixed at the time, but later extensions were done poorly and have become rather hard to deal with. What are the two obvious defects? 1. The use of the first letter of the label to indicate type. 2. Irregular and inconsistent syntax. To see an example of a Spice-derived format that has the two obvious defects fixed, look at the Spectre format, which is technically proprietary. It's an excellent format. Too bad it isn't used anywhere else except Spectre (and now gnucap, through a plugin). Gnucap still accepts Spice format, and always will. In future, plugins will make it possible to support variants of the Spice format. If all you care about is netlists, it is easy, except Spice. It might make sense to look at the gnucap language plugins. By making a simple driver, we could easily have a complete netlist translation system. If it doesn't get done first, that driver will be one of my proposals for next summer's google soc. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
Steve Meier wrote: I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that would make simulation of complex designs interesting. Thanks, Steve Meier For verilog and spice (I'm including things like spice2, spice3, hspice, spectre, etc under the spice heading), it is quite simple. note, exact syntax may vary for the passing of parameters, but this should demonstrate the idea. See http://www.ece.uci.edu/docs/hspice/hspice_2001_2-43.html for examples of hspice. You'll note that there is almost nothing special or extra to do with hierarchy. You simply have a flat netlist for each level in the hierarchy and instantiate subcircuits. --- SPICE -- * basic CMOS inverter with parameter passing (in, out, vdd, vss) .subckt myinv 1 2 100 200 WP=30u WN=10u M1 2 1 100 100 PFET W='WP' L=1u M2 2 1 200 200 NFET W='WN' L=1u .ends * a buffer (non inverting) .subckt mybuf in out vdd vss N=1 xinv1 in inv vdd vss myinv WP='N*10u' WN='N*5u' xinv2 inv out vdd vss myinv WP='N*30u' WN='N*15u' .ends * and now a circuit which uses the buffer * power/ground vvdd vdd 0 dc 5.0 vvss vss 0 dc 0.0 * a 1x buffer xbuf1 in buf1_out vdd vss mybuf * a 4x buffer xbuf2 in buf2_out vdd vss mybuf N=4 * add stimulus, etc here... --- SPICE -- --- spectre -- // basic CMOS inverter with parameter passing (in, out, vdd, vss) subckt myinv 1 2 100 200 parameters WP=30u WN=10u M1 (2 1 100 100) PFET W=WP L=1u M2 (2 1 200 200) NFET W=WN L=1u ends myinv // a buffer (non inverting) subckt mybuf in out vdd vss parameters N=1 xinv1 (in inv vdd vss) myinv WP=N*10u WN=N*5u xinv2 (inv out vdd vss) myinv WP=N*30u WN=N*15u ends mybuf // and now a circuit which uses the buffer // power/ground vvdd (vdd 0) vsource type=dc dc=5.0 vvss (vss 0) vsource type=dc dc=0.0 // a 1x buffer xbuf1 (in buf1_out vdd vss) mybuf // a 4x buffer xbuf2 (in buf2_out vdd vss) mybuf N=4 // add stimulus, etc here... --- spectre -- --- verilog -- module myinv(in out vdd vss) input in, vdd, vss; output out; wire out; parameter DELAY=5; // (I may have the delay syntax wrong, verilog book isn't in front of me) assign #DELAY out = ~in; endmodule module mybuf(in out vdd vss) input in, vdd, vss; output out; wire int, out; defparam inv1.DELAY=2 myinv inv1(.in(in), .out(int), .vdd(vdd), .vss(vss)) defparam inv1.DELAY=3 myinv inv2(.in(int),.out(out), .vdd(vdd), .vss(vss)) endmodule module testbench wire in, out1, out2; reg vdd, vss; mybuf buf1(.in(in), .out(out1), .vdd(vdd), .vss(vss)) mybuf buf2(.in(in), .out(out2), .vdd(vdd), .vss(vss)) // some stimulus here... endmodule --- verilog -- In all of these, the basic idea is the same. Each level of hierarchy has its own netlist inside of a subcircuit or a module. Then other blocks are instantiated. Note the decided lack of doing anything silly like producing a flattened netlist for the whole design. That kills the ability for humans to effectively read the netlist (needed all too often) and simulators to do various optimizations. Hope this helps. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
Since I build a flat netlist for each sheet it should be fairly streight forward to build a hierarchical netlist thus I think it will just be a syntax issue for the various formats. As a side note: I have moved the reading of schematics from the c code to a guile script. I am in process of doing the same for symbols and plan to also write the schematics, symbol files with guile scripts. The netlist application will allow the user to select which script they want for reading and writting thus it should support both standard gda and my non-stock, (tm) Peter C, file formats. Theoretically, given a file structure one should be able to write scripts for any schematic capture program and then this could function as a translator as well. I have been putting together a more extensive and documented guile api to interact with the library contanded data structures. All of this together with a functioning hierarchical bus support and the addition of hierarchical netlists should as I claimed earlier be interesting. Thanks David, Dan and Al for the pointers to the netlist formats. Steve Meier On Wed, 2007-11-28 at 12:54 -0500, Dan McMahill wrote: Steve Meier wrote: I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase. I desire this material as my code is reaching a level of maturity that would make simulation of complex designs interesting. Thanks, Steve Meier For verilog and spice (I'm including things like spice2, spice3, hspice, spectre, etc under the spice heading), it is quite simple. note, exact syntax may vary for the passing of parameters, but this should demonstrate the idea. See http://www.ece.uci.edu/docs/hspice/hspice_2001_2-43.html for examples of hspice. You'll note that there is almost nothing special or extra to do with hierarchy. You simply have a flat netlist for each level in the hierarchy and instantiate subcircuits. --- SPICE -- * basic CMOS inverter with parameter passing (in, out, vdd, vss) .subckt myinv 1 2 100 200 WP=30u WN=10u M1 2 1 100 100 PFET W='WP' L=1u M2 2 1 200 200 NFET W='WN' L=1u .ends * a buffer (non inverting) .subckt mybuf in out vdd vss N=1 xinv1 in inv vdd vss myinv WP='N*10u' WN='N*5u' xinv2 inv out vdd vss myinv WP='N*30u' WN='N*15u' .ends * and now a circuit which uses the buffer * power/ground vvdd vdd 0 dc 5.0 vvss vss 0 dc 0.0 * a 1x buffer xbuf1 in buf1_out vdd vss mybuf * a 4x buffer xbuf2 in buf2_out vdd vss mybuf N=4 * add stimulus, etc here... --- SPICE -- --- spectre -- // basic CMOS inverter with parameter passing (in, out, vdd, vss) subckt myinv 1 2 100 200 parameters WP=30u WN=10u M1 (2 1 100 100) PFET W=WP L=1u M2 (2 1 200 200) NFET W=WN L=1u ends myinv // a buffer (non inverting) subckt mybuf in out vdd vss parameters N=1 xinv1 (in inv vdd vss) myinv WP=N*10u WN=N*5u xinv2 (inv out vdd vss) myinv WP=N*30u WN=N*15u ends mybuf // and now a circuit which uses the buffer // power/ground vvdd (vdd 0) vsource type=dc dc=5.0 vvss (vss 0) vsource type=dc dc=0.0 // a 1x buffer xbuf1 (in buf1_out vdd vss) mybuf // a 4x buffer xbuf2 (in buf2_out vdd vss) mybuf N=4 // add stimulus, etc here... --- spectre -- --- verilog -- module myinv(in out vdd vss) input in, vdd, vss; output out; wire out; parameter DELAY=5; // (I may have the delay syntax wrong, verilog book isn't in front of me) assign #DELAY out = ~in; endmodule module mybuf(in out vdd vss) input in, vdd, vss; output out; wire int, out; defparam inv1.DELAY=2 myinv inv1(.in(in), .out(int), .vdd(vdd), .vss(vss)) defparam inv1.DELAY=3 myinv inv2(.in(int),.out(out), .vdd(vdd), .vss(vss)) endmodule module testbench wire in, out1, out2; reg vdd, vss; mybuf buf1(.in(in), .out(out1), .vdd(vdd), .vss(vss)) mybuf buf2(.in(in), .out(out2), .vdd(vdd), .vss(vss)) // some stimulus here... endmodule --- verilog -- In all of these, the basic idea is the same. Each level of hierarchy has its own netlist inside of a subcircuit or a module. Then other blocks are instantiated. Note the decided lack of doing anything silly like producing a flattened netlist for the whole design. That kills the ability for humans to effectively read the netlist (needed all too often) and simulators to do various optimizations. Hope this helps. -Dan ___ geda-user mailing list geda-user@moria.seul.org
Re: gEDA-user: Request for VHDL and Hierarchical Spice References
To be fair . The same circuit --- verilog-A -- // basic CMOS inverter with parameter passing (in, out, vdd, vss) module myinv (2 1 100 200); inout 2, 1, 100, 200; electrical 2, 1, 100, 200; parameter WP=30u, WN=10u; pfet #(.w(WP), .l(1u)) M1 (2 1 100 100) ; nfet #(.w(WN), .l(1u)) M2 (2 1 200 200); endmodule // a buffer (non inverting) module mybuf(in out vdd vss) inout in, vdd, vss,out; electrical in, vdd, vss,out; parameter N=1; myinv #(.WP(N*30u), .WN(N*15u)) xinv1 (in, inv, vdd, vss); myinv #(.WP(N*30u), .WN(N*15u)) xinv2 (inv, out, vdd, vss); endmodule // and now a circuit which uses the buffer module testbench; electrical vdd, vss, in, buf1_out, buf2_out); // power/ground vsource #(.dc(5)) vvdd (vdd 0); vsource #(.dc(0)) vvss (vss 0); // a 1x buffer mybuf xbuf1 (in buf1_out vdd vss); // a 4x buffer mybuf #(.N(4)) xbuf2 (in buf2_out vdd vss); endmodule --- verilog-A -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
