To be fair ..... The same circuit .... --- verilog-A ------------------------------------------------------
// basic CMOS inverter with parameter passing (in, out, vdd, vss) module myinv (2 1 100 200); inout 2, 1, 100, 200; electrical 2, 1, 100, 200; parameter WP=30u, WN=10u; pfet #(.w(WP), .l(1u)) M1 (2 1 100 100) ; nfet #(.w(WN), .l(1u)) M2 (2 1 200 200); endmodule // a buffer (non inverting) module mybuf(in out vdd vss) inout in, vdd, vss,out; electrical in, vdd, vss,out; parameter N=1; myinv #(.WP(N*30u), .WN(N*15u)) xinv1 (in, inv, vdd, vss); myinv #(.WP(N*30u), .WN(N*15u)) xinv2 (inv, out, vdd, vss); endmodule // and now a circuit which uses the buffer module testbench; electrical vdd, vss, in, buf1_out, buf2_out); // power/ground vsource #(.dc(5)) vvdd (vdd 0); vsource #(.dc(0)) vvss (vss 0); // a 1x buffer mybuf xbuf1 (in buf1_out vdd vss); // a 4x buffer mybuf #(.N(4)) xbuf2 (in buf2_out vdd vss); endmodule --- verilog-A ------------------------------------------------------ _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user