I am seeking good references for verilog, VHDL and spice syntext specificaly with the idea of supporting hierarchical net lists. Online or recomendations for purchase.
I desire this material as my code is reaching a level of maturity that would make simulation of complex designs interesting. Thanks, Steve Meier _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user