Re: gEDA-user: any last minute advice prior to sending out for PCB fab
John Griessen wrote: Bob Paddock wrote: Not sure. I know our CM loves that I put fuducials on the QFN So these footprint fiducials are outboard of the part so they show in a vision system as the part is being placed? Do you put silk outline outside them or some silk circles around each one to clue the CM about what they are good for, or does that just need some notes and documentation and phone calls? maybe this helps : http://www.carltonindustriesonline.com/cic_Fiducial.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Fiducials and Keepouts -- The last mfg I dealt with recommended that the fiducial be a copper circle with a diameter between 0.5mm and 3.5mm and that the solder mask diameter be three times larger than the copper. I made a single 1mm pad footprint with the 3mm clearance. IIRC the requested placement was three corners and 3mm from the edge. There were also component fiducials required for fine pitch devices. I do not recall the specifications since they didn't apply to the boards I was doing. They also specified a minimum keepout of 118mils for their Fuji machine and 125mils for their ATE. I made the keepout 125mils on all sides. (* jcl *) -- You can't create open hardware with closed EDA tools. twitter: [1]http://twitter.com/jluciani blog:[2]http://www.luciani.org References 1. http://twitter.com/jluciani 2. http://www.luciani.org/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, Feb 23, 2010 at 10:01:55PM -0500, gene glick wrote: what else? Any suggestions? Check your hole dimensions, especially on connectors - a correctly-routed board is not much use if your connector pins won't fit through the holes... -- David SmithWork Email: dave.sm...@st.com STMicroelectronics Home Email: david.sm...@ds-electronics.co.uk Bristol, England GPG Key: 0xF13192F2 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, 23 Feb 2010 22:18:02 -0500, gene glick wrote: I'll have to order up a bunch of parts to make it happen but that's ok. This is an important part of the check. It is too easy to misread some aspect of the physical dimensions in the data sheet. Think SO16 vs SO16- wide. This has hit me hard some years ago. ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, Feb 23, 2010 at 10:01 PM, gene glick carzr...@optonline.net wrote: After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. I'm making the assumption you will have a contractor build quantities someday, in automated equipment. These will (at least should) lower production costs: Do you have at least three Fudicuals on all of your boards? I typically place at least three. One on each long edge of the board in a line, with the third centered in the middle of the line on the opposite edge, like a sideways triangle: * * * These compensate for film stretching, board alignment during assembly etc. Have you specified tooling holes for panels?: 1/4 waste material around all sided, 0.125 tooling hole in each corner of the waste materiel, of each panel. Fudicals on the waste material. Have you specified how to route and/or score the boards? Do you care if you have secondary sanding operations (you don't wan't those)? Do you have any ceramic caps or such along an edge that will break when boards are depanalized from descoring? Have you put Fudicuals on components, such as tiny QFN packages, or even massive TQFP and BGAs. Always a nice touch, but frequently not room. Really helps out if parts are at angles to the board edge. Two, one each in diagonal corners of the package. Having to many Fudicuals is bad, more than four to six per boad, and having them not in some kind of alignment makes them useless in most cases. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Hi - On Wed, Feb 24, 2010 at 02:40:50PM -0500, Bob Paddock wrote: I'm making the assumption you will have a contractor build quantities someday, in automated equipment. These will (at least should) lower production costs: Although OT, I appreciate and try to learn from discussions like this. Do you have at least three Fudicuals on all of your boards? I know what fiducials look like, but haven't seen a footprint for one within pcb. Am I blind? Is there a standard recipe for making one? These compensate for film stretching, board alignment during assembly etc. The last time I asked a board loading house about fiducials, they said they gave up and just optically register to the component footprint itself. Have you specified tooling holes for panels?: [chop] Have you specified how to route and/or score the boards? This is something I have never gotten into. I guess my boards are always too large and/or the order too few to care. Have you put Fudicuals on components, such as tiny QFN packages, or even massive TQFP and BGAs. I don't think you said what you wanted to say. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Wed, Feb 24, 2010 at 3:24 PM, Larry Doolittle ldool...@recycle.lbl.gov wrote: Hi - On Wed, Feb 24, 2010 at 02:40:50PM -0500, Bob Paddock wrote: I'm making the assumption you will have a contractor build quantities someday, in automated equipment. These will (at least should) lower production costs: Although OT, I appreciate and try to learn from discussions like this. Do you have at least three Fudicuals on all of your boards? I know what fiducials look like, but haven't seen a footprint for one within pcb. Am I blind? Is there a standard recipe for making one? Simply a pad with no solder mask. I use 30 or 40mil pads, with 50 to 80mil solder mask opening, depending on how much space I have. The last time I asked a board loading house about fiducials, they said they gave up Yes. Because so few do it correctly. Have you put Fudicuals on components, such as tiny QFN packages, or even massive TQFP and BGAs. I don't think you said what you wanted to say. Not sure. I know our CM loves that I put fuducials on the QFN accelerometer and compass IC's. They get mounted at funny angles on the board. My intent was to say, that if space is available put fudcials at the component footprint level, when space is available, especially on very small or very large packages, that have multiple pins. Putting on things like resistors and caps would be silly. I've learned most of this by working at a large CM, and 'The Hard Way' of doing it wrong. For example the job today is 5,000 boards. When you get into quantities, you start to do things differently. See the note at the bottom of my blog http://blog.designer-iii.com/avr_isp_spi/20081116-10511-Digital-MEMS-Accelerometers-will-not-work-with-AVR-ISP-using-SPI . You are supposed to isolated the AVR ISP pins with 1k resistors, as the Atmel documentation shows. This is true. However that takes four resistors per board, on a board that already did not have enough space. Also at 50,000 units per year, with an design lifetime of five years, that is 10,000,000 resistors. After a while these resistors start to add up to real money, for what is a single event at manufacturing time. Design for Manufacturing always should be given consideration. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Wed, Feb 24, 2010 at 04:07:13PM -0500, Bob Paddock wrote: I've learned most of this by working at a large CM, and 'The Hard Way' of doing it wrong. For example the job today is 5,000 boards. When you get into quantities, you start to do things differently. See the note at the bottom of my blog http://blog.designer-iii.com/avr_isp_spi/20081116-10511-Digital-MEMS-Accelerometers-will-not-work-with-AVR-ISP-using-SPI . You are supposed to isolated the AVR ISP pins with 1k resistors, as the Atmel documentation shows. I would have just ensured that my AVR image didn't contain any sequences that trigger the problem. It might be possible to just modify AVRdude to detect such sequences and modify the programming sequence to avoid them. Sort of like bit stuffing with NRZI. -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Feb 24, 2010, at 1:07 PM, Bob Paddock wrote: On Wed, Feb 24, 2010 at 3:24 PM, Larry Doolittle ldool...@recycle.lbl.gov wrote: Hi - On Wed, Feb 24, 2010 at 02:40:50PM -0500, Bob Paddock wrote: I'm making the assumption you will have a contractor build quantities someday, in automated equipment. These will (at least should) lower production costs: Although OT, I appreciate and try to learn from discussions like this. Do you have at least three Fudicuals on all of your boards? I know what fiducials look like, but haven't seen a footprint for one within pcb. Am I blind? Is there a standard recipe for making one? Simply a pad with no solder mask. I use 30 or 40mil pads, with 50 to 80mil solder mask opening, depending on how much space I have. The last time I asked a board loading house about fiducials, they said they gave up Yes. Because so few do it correctly. Have you put Fudicuals on components, such as tiny QFN packages, or even massive TQFP and BGAs. I don't think you said what you wanted to say. Not sure. I know our CM loves that I put fuducials on the QFN accelerometer and compass IC's. They get mounted at funny angles on the board. My intent was to say, that if space is available put fudcials at the component footprint level, when space is available, especially on very small or very large packages, that have multiple pins. Putting on things like resistors and caps would be silly. I've learned most of this by working at a large CM, and 'The Hard Way' of doing it wrong. For example the job today is 5,000 boards. When you get into quantities, you start to do things differently. See the note at the bottom of my blog http://blog.designer-iii.com/avr_isp_spi/20081116-10511-Digital-MEMS-Accelerometers-will-not-work-with-AVR-ISP-using-SPI . You are supposed to isolated the AVR ISP pins with 1k resistors, as the Atmel documentation shows. This is true. However that takes four resistors per board, on a board that already did not have enough space. Also at 50,000 units per year, with an design lifetime of five years, that is 10,000,000 resistors. After a while these resistors start to add up to real money, for what is a single event at manufacturing time. Design for Manufacturing always should be given consideration. Solder jumpers are how I get around crap like this, were you can't connect something till its powered up and programmed properly, or else it blows a safety circuit. Examples from DJ http://www.delorie.com/pcb/solderjumpers.html But of course paying someone to solder that jumper also costs money over time ;-) Sounds like you needed pre-programmed parts Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Bob Paddock wrote: On Wed, Feb 24, 2010 at 3:24 PM, Larry Doolittle ldool...@recycle.lbl.gov wrote: Have you put Fudicuals on components, such as tiny QFN packages, or even massive TQFP and BGAs. I don't think you said what you wanted to say. Not sure. I know our CM loves that I put fuducials on the QFN accelerometer and compass IC's. They get mounted at funny angles on the board. My intent was to say, that if space is available put fudcials at the component footprint level, So these footprint fiducials are outboard of the part so they show in a vision system as the part is being placed? Do you put silk outline outside them or some silk circles around each one to clue the CM about what they are good for, or does that just need some notes and documentation and phone calls? John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
I would have just ensured that my AVR image didn't contain any sequences that trigger the problem. It might be possible to just modify AVRdude to detect such sequences and modify the programming sequence to avoid them. Sort of like bit stuffing with NRZI. I'm sorry, you cannot program an 86 here. Please select a different value for the speed of light. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
I would have just ensured that my AVR image didn't contain any sequences that trigger the problem. How? Its a crap shoot as to know if any particular image will generate the bad sequence. Then you waste time trying to figure out how to get around it. To DJ's comment. We usually do go with pre-programmed parts eventually. Solder jumpers are a really bad idea when doing anything more than few boards. Even zero ohm resisters jumpers cost real money. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Wed, Feb 24, 2010 at 04:41:35PM -0500, Bob Paddock wrote: I would have just ensured that my AVR image didn't contain any sequences that trigger the problem. How? Its a crap shoot as to know if any particular image will generate the bad sequence. Then you waste time trying to figure out how to get around it. You can waste time spinning the board or waste time working around the programming issue. If it's just part of your normal board spins, obviously you just change the board. If you didn't happen to encounter a problem issue until after you have 50,000 made, then you spend time avoiding the problem at the programming stage. I bet it wouldn't be that hard to modify AVRdude to avoid a specific output bit sequence during programming without modifying your image at all. Worst case is to find a bootloader that doesn't trigger the problem (or is easily modified to avoid it) and then you control both ends. -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, Feb 23, 2010 at 10:01 PM, gene glick [1]carzr...@optonline.net wrote: After a very long time, I am just about ready to send out 3 different boards for fab. ?I would appreciate any advice to improve my chances of success. Don't send all three at once. Send one and get it all the way through your process before sending the last two. John Eaton References 1. mailto:carzr...@optonline.net ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Wed, 24 Feb 2010 15:22:54 -0600, John Griessen wrote: So these footprint fiducials are outboard of the part so they show in a vision system as the part is being placed? Do you put silk outline outside them or some silk circles around each one to clue the CM about what they are good for, or does that just need some notes and documentation and phone calls? For me, just copper, no solder mask but described in the bom and appeared in the pick and place data. Communicaton starts typically when they are missed ... Frank Bergmann. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
gene glick wrote: After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. The cash layout for PCB fab is going to be large enough that I am nervous about not getting it right. Still, I have a CPU card and SMPS to do which can wait a bit while this gets put together. what else? Any suggestions? don't even consider ordering boards without loading up the photoplot files into something like gerbv and doing some sanity checks. This advice applies to a design done with any layout tool and not just pcb. A minimal list would be: - From 20,000 feet, does each layer look right or are there glaring errors like a big missing chunk of a ground plane. - On your plane layer(s), make sure that you see some pins/vias that go through the plane *without* connecting. Now make sure you see some that *do* connect. Yes, I have seen a case where someone (not me) ordered a board that had exactly 0 connections to the ground plane. All thermals were missing. Didn't work so well. - Mounting holes there? In the right place? - If you're using new footprints, especially high pin count QFN's, and QFP's where there are versions with different pin pitch for the same pin count, then do at least some sanity checks on pin pitch. For example on a 128 pin TQFP, measure from pin 1 center to pin 32 center , divide by 31 and make sure you get the right answer. - On new leaded connector footprints, at least spot check your hole sizes. - for the top and bottom layers, toggle on/off the associated soldermask relieve layer and see that it appears that your pads and pins are covered. I don't usually check every single pad but at least do a high level check to see that it is about right. - for the top and bottom layers, turn on the solder mask relief and toggle the silk screen layers and look for silk over pad openings. For these last 2 cases, I'd love to see a tool that used libgerbv that could do boolean operations on layers to compute things like: err_top_silk = layer_and(top_silk, top_soldermask_relief) In other words something that could do an after the fact set of DRC checks. But that is a whole other project. -Dan - Ma ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
don't even consider ordering boards without loading up the photoplot files into something like gerbv and doing some sanity checks. This advice applies to a design done with any layout tool and not just pcb. A minimal list would be: - From 20,000 feet, does each layer look right or are there glaring errors like a big missing chunk of a ground plane. - On your plane layer(s), make sure that you see some pins/vias that go through the plane *without* connecting. Now make sure you see some that *do* connect. Yes, I have seen a case where someone (not me) ordered a board that had exactly 0 connections to the ground plane. All thermals were missing. Didn't work so well. As another interesting aside - not likely to happen if you're using gEDA - a tech in the company I work for sent off a pcb design in the raw Altium pcb format (ie - not the generated gerb files). This was a not uncommon practice as Altium was considered *industry standard* and every pcb fab house we deal with has a copy. In this case however the fab house opened the designs in a slightly older version than what the files were generated in. AFTER the boards were fabbed AND populated it was discovered that due to the difference in version a whole bunch of nets had been fused to various power planes. The whole thing was fubar. Expensively fubar. The pcb fab house were not at fault as we hadn't specified which version of Altium had been used etc etc. There are a multitude of serious process errors involved in how the build was handled... if you follow what has been discussed so far I don't think you will have the same problems. Geoff ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Feb 24, 2010, at 1:41 PM, Bob Paddock wrote: To DJ's comment. We usually do go with pre-programmed parts eventually. Solder jumpers are a really bad idea when doing anything more than few boards. Even zero ohm resisters jumpers cost real money. I believe it was my comment that referenced DJ's solder jumpers. Solder jumpers are not always a really bad idea. They can be hand populated much easier than 0 ohm resistors and cost less. The whole point of the solder jumpers have two uses. 1. A jumper with a dollop of solder applied at SMT using the solder mask is cheaper than a 0 ohm resistor for rework purposes, As the resistor needs solder + resistor. After the design is finalized a new board can be spun that shorts the jumper with copper. When you need to disconnect for rework, just use solderwik and remove. 2. A jumper with the solder not applied at SMT, so that the connection is not made until the solder is applied at a later time. This jumper is much easier to apply than a resistor by an operator. A hot iron and solder are the only things needed, not tweezers or parts. #2 is used to manufacture products built on the millions of units scale. Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
So these footprint fiducials are outboard of the part so they show in a vision system as the part is being placed? Do you put silk outline outside them or some silk circles around each one to clue the CM about what they are good for, or does that just need some notes and documentation and phone calls? I don't put silk around the fiducials. For the parts that have them, they are in two diagonal corners of the part footprint, as part of the footprint. My current CM knows our process and we know theirs now, so we don't usually say much about them. Going to a new CM I would have lots of fab notes in a ReadMe. Where things usually fall about is the people on the line don't get to talk to the customers. Make it a point to ask to the people that are on the line doing the work. Not the CM salesmen nor the company managers. The line people know how to make things go well, and what can be done to improve things, but it frequently gets lost in the hierarchy of politics between the workers and the customer, and doesn't make it back to the board designers. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Wed, Feb 24, 2010 at 7:47 PM, Steven Michalske smichal...@gmail.com wrote: On Feb 24, 2010, at 1:41 PM, Bob Paddock wrote: To DJ's comment. We usually do go with pre-programmed parts eventually. Solder jumpers are a really bad idea when doing anything more than few boards. Even zero ohm resisters jumpers cost real money. I believe it was my comment that referenced DJ's solder jumpers. Yes, sorry. Solder jumpers are not always a really bad idea. They can be hand populated much easier than 0 ohm resistors and cost less. I'll stand by what I said. Solder jumpers are a bad idea in any quantity beyond a few prototypes. After the design is finalized a new board can be spun that shorts the jumper with copper. I agree. This jumper is much easier to apply than a resistor by an operator. A hot iron and solder are the only things needed, not tweezers or parts. #2 is used to manufacture products built on the millions of units scale. I don't want to pay a person to solder that many jumpers. Not a good use of their skills. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Feb 24, 2010, at 4:59 PM, Bob Paddock wrote: On Wed, Feb 24, 2010 at 7:47 PM, Steven Michalske smichal...@gmail.com wrote: On Feb 24, 2010, at 1:41 PM, Bob Paddock wrote: To DJ's comment. We usually do go with pre-programmed parts eventually. Solder jumpers are a really bad idea when doing anything more than few boards. Even zero ohm resisters jumpers cost real money. I believe it was my comment that referenced DJ's solder jumpers. Yes, sorry. Solder jumpers are not always a really bad idea. They can be hand populated much easier than 0 ohm resistors and cost less. I'll stand by what I said. Solder jumpers are a bad idea in any quantity beyond a few prototypes. I guess my gripe is that your outright stating its bad, when in truth its a manufacturing decision. When it is the best choice for some assembly requirements, like connection sequencing. e.g. Solder these 4 jumpers in order. The example I know that is used in millions of products is generalized as this. Solder these 20 wires onto the PCB, and tack this solder jumper. The solder jumper uses the least effort of the assembly, and specifying the order of the wire connections doesn't omit the many momentary connections inserting the wire and soldering. At times it is the only cost effective option. Here the cost effective option is pre-programmed, no argument. After the design is finalized a new board can be spun that shorts the jumper with copper. I agree. This jumper is much easier to apply than a resistor by an operator. A hot iron and solder are the only things needed, not tweezers or parts. #2 is used to manufacture products built on the millions of units scale. I don't want to pay a person to solder that many jumpers. Not a good use of their skills. It is more of a waste to solder resistors. I don't want folks to rule out this option because of the quote Solder jumpers are a bad idea in any quantity beyond a few prototypes Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: any last minute advice prior to sending out for PCB fab
After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. The cash layout for PCB fab is going to be large enough that I am nervous about not getting it right. Still, I have a CPU card and SMPS to do which can wait a bit while this gets put together. what else? Any suggestions? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Print out your surface copper layers and put the parts on the printout to make sure they match. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
DJ Delorie wrote: Print out your surface copper layers and put the parts on the printout to make sure they match. that's a really good idea, thanks! It'll delay things some, but yeah, sounds like the conservative way to go. I'll have to order up a bunch of parts to make it happen but that's ok. Printing out 1:1 should be close enough on a laser printer, I think. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Check the gerbers and drill files using gerbv. I use a script that zips and renames all the files for the fab house. I take the zip file that is created, unzip it and check those files with gerbv. For a system of boards that plug into each I might panelize them so that they all align. You would quickly see misalignment. You would also save some money on the fabrication. (* jcl *) On Tue, Feb 23, 2010 at 10:01 PM, gene glick [1]carzr...@optonline.net wrote: After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. The cash layout for PCB fab is going to be large enough that I am nervous about not getting it right. Still, I have a CPU card and SMPS to do which can wait a bit while this gets put together. what else? Any suggestions? thanks gene ___ geda-user mailing list [2]geda-u...@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- You can't create open hardware with closed EDA tools. twitter: [4]http://twitter.com/jluciani blog:[5]http://www.luciani.org References 1. mailto:carzr...@optonline.net 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 4. http://twitter.com/jluciani 5. http://www.luciani.org/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
John Luciani wrote: Check the gerbers and drill files using gerbv. I use a script that zips and renames all the files for the fab house. I take the zip file that is created, unzip it and check those files with gerbv. For a system of boards that plug into each I might panelize them so that they all align. You would quickly see misalignment. You would also save some money on the fabrication. (* jcl *) I completely forgot to mention that I generated the Ben-mode prints to check it all out - that is really helpful. And yes, like you, run a script to generate and rename the gerber files. Gerbv is a great tool, I like it a bunch. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, Feb 23, 2010 at 8:01 PM, gene glick carzr...@optonline.net wrote: After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. Make a rendering with --photo-mode and check that it looks like what you are expecting. Errors become more obvious to my eyes with a realistic-looking rendering than the false color of gerbv or pcb. If the design isn't secret, post the rendering online (eg., imgur.com) and we'll all take a look. You can use Advanced Circuit's freedfm.com and see what it says. Regards, Mark markra...@gmail -- Mark Rages, Engineer Midwest Telecine LLC markra...@midwesttelecine.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, 23 Feb 2010 22:18:02 -0500 gene glick carzr...@optonline.net wrote: DJ Delorie wrote: Print out your surface copper layers and put the parts on the printout to make sure they match. that's a really good idea, thanks! It'll delay things some, but yeah, sounds like the conservative way to go. I'll have to order up a bunch of parts to make it happen but that's ok. Printing out 1:1 should be close enough on a laser printer, I think. Watch out, I stumbled on that one not too long ago. My particular laser printer (an ooddd Konica KL-3015) needs a ratio of 1:1.07, otherwise everything comes out too small. I assume this is from the paper shrinking ever so slightly as goes through the fusor rollers. Otherwise, it's an excellent idea. -- There are some things in life worth obsessing over. Most things aren't, and when you learn that, life improves. http://starbase.globalpc.net/~ezekowitz Vanessa Ezekowitz vanessaezekow...@gmail.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
