Re: gEDA-user: terminators
DJ Delorie wrote: Follow up... http://www.delorie.com/electronics/sdram/ Just for fun, I figured out how to make room to add traditional serpentines and a few other tricks, and have all the SDRAM traces within 7 mil of the CLK length (1.89). Looks good as pro, DJ, but then you once were pro... John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ Delorie wrote: Just for fun, I figured out how to make room to add traditional serpentines and a few other tricks, and have all the SDRAM traces within 7 mil of the CLK length (1.89). That looks really cool. Did you write some code to do that? -Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
That looks really cool. Did you write some code to do that? I added the Report(AllNetLengths), then wrote a perl script to run that report and tell me what adjustments needed to be made, and I used plain PCB editing to edit them. *That* part turned out easy; have the perl script tell me how far each end had to move, then mark the end and move it with rubberband on. After it was all done, I moved all the right ends right one grid (6.25 mil grid), and replaced all the ends with arcs. I suppose one could write a plug-in to do the arc replacement, but it's not really needed for real boards. I did notice that rubberbanding and 180 degree arcs don't get along, otherwise I'd have added the arcs earlier in the process. The W-shaped wiggles were just cut and paste. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On May 3, 2009, at 1:55 AM, DJ Delorie wrote: Follow up... http://www.delorie.com/electronics/sdram/ Just for fun, I figured out how to make room to add traditional serpentines and a few other tricks, and have all the SDRAM traces within 7 mil of the CLK length (1.89). Wow...NICE work!! -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Wow...NICE work!! Thanks! Now I just have to get the fpga timing right... Oh, and build the board, too ;-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On May 3, 2009, at 8:28 PM, DJ Delorie wrote: Wow...NICE work!! Thanks! Now I just have to get the fpga timing right... Oh, and build the board, too ;-) So, 10-15 minutes? =) -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
So, 10-15 minutes? =) Not quite *that* fast. A couple min to print, 2 min for expose, 15 min to harden, 10 min to develop, 5-10 min to etch, 3-4 min to strip. That's per layer, but the steps can overlap. Assuming I don't have to redo any of the layers. Then add drill time, paste, and component placement. 4 min to reflow. Then I have to solder all the vias and through-hole parts. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On May 3, 2009, at 8:36 PM, DJ Delorie wrote: So, 10-15 minutes? =) Not quite *that* fast. A couple min to print, 2 min for expose, 15 min to harden, 10 min to develop, 5-10 min to etch, 3-4 min to strip. That's per layer, but the steps can overlap. Assuming I don't have to redo any of the layers. Then add drill time, paste, and component placement. 4 min to reflow. Then I have to solder all the vias and through-hole parts. I'm sure you could shave a few minutes off of those times with enough caffeine. ;) -Dave -- Dave McGuire Port Charlotte, FL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Follow up... http://www.delorie.com/electronics/sdram/ Just for fun, I figured out how to make room to add traditional serpentines and a few other tricks, and have all the SDRAM traces within 7 mil of the CLK length (1.89). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
I think the only way to rotate the sdram chip and have nearly-equal traces is to rotate 90 degrees and have the fpga pins nearest the sdram go under the sdram to the furthest pins, so that the fpga pins furthest from the sdram don't have to go as far. You end up using more vias for power that way, though, and they take up space as well. If I build this at home, I can't put vias under parts. Alternately, have every other fpga pin connect to the far side, and route traces between pins on the near side. Again with the power pins. Another alternative is to rotate the fpga 45 degrees, and the sdram 90 degrees, to bring the furthest fpga pins closer. http://www.delorie.com/electronics/sdram/rot9045.png At the moment, though, I have the traces within half an inch of each other, which I think is close enough for my purposes. On a real board, the sdram and fpga would be BGA packages and you'd just match up pin patterns on both to get equal traces. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Hi DJ, On Tue, 2009-04-21 at 23:35 -0400, DJ Delorie wrote: Update... I added serpentines to the short traces, and re-routed the long traces to go under the sdram chip instead of around it, and got the following... Only 381 mils difference between the shortest and longest. http://www.delorie.com/electronics/sdram/ snip Your board looks nice, as always. I was told to avoid 90 degree angles in traces, it was something about impedance or EMI, IIRC. You do not expect some EMI problems or high impedance from the 90 degree cornered angles ? And yes, I added a command to show the length of all nets. Report(AllNetLengths). I also used a script to remove the logic analyzer traces from the above report, and pull out the nets I wanted. Report(SelectedNetLengths) comes to mind (may be, or may be not implemented yet). Kind regrds, Bert Timmerman. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 21, 2009, at 11:04 PM, Bert Timmerman wrote: Hi DJ, On Tue, 2009-04-21 at 23:35 -0400, DJ Delorie wrote: Update... I added serpentines to the short traces, and re-routed the long traces to go under the sdram chip instead of around it, and got the following... Only 381 mils difference between the shortest and longest. http://www.delorie.com/electronics/sdram/ snip Your board looks nice, as always. I was told to avoid 90 degree angles in traces, it was something about impedance or EMI, IIRC. You do not expect some EMI problems or high impedance from the 90 degree cornered angles ? Em fields are concentrated at sharp points, thats the main reason for not having 90 degree bends. In this case it is the sharp inside edge. I forget if the close parallel traces affect it but they might have an effect on impedance at much higher frequencies I wonder if by mentioning the serpentines would look cool as arcs, we would get a plugin that makes arc serpentines out of a line. ;-) And yes, I added a command to show the length of all nets. Report(AllNetLengths). I also used a script to remove the logic analyzer traces from the above report, and pull out the nets I wanted. Report(SelectedNetLengths) comes to mind (may be, or may be not implemented yet). Kind regrds, Bert Timmerman. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ Delorie wrote: And yes, I added a command to show the length of all nets. Report(AllNetLengths). That's a really cool feature. Can we have it too? :) Now that you've removed the LA traces, why not snug that DRAM chip up close to the FPGA and make the traces short? Regarding right angle traces, I've seen a lot written about it. 45's are technically better for all the reasons listed (arcs are even better, I think), but in practice, at these frequencies, I don't think it really matters. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Your board looks nice, as always. Thanks! I was told to avoid 90 degree angles in traces, it was something about impedance or EMI, IIRC. The one case I saw where someone actually built two boards, one each way, and tested - it made no difference. Besides, at these scales, the rounded corners PCB uses are probably as effective as arcs anyway. You do not expect some EMI problems or high impedance from the 90 degree cornered angles ? For this board, I don't care about radiated EMI. I'm not even sure I could *etch* a real 90 degree corner in my basement, anyway. Report(SelectedNetLengths) comes to mind (may be, or may be not implemented yet). Not implemented yet. The syntax allows for a unit after the command, like Report(AllNetLengths,mm) and I was thinking of allowing a regex after that, or the key words selected or found. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
That's a really cool feature. Can we have it too? :) I checked it in when I wrote it, so just update your git tree and build. Now that you've removed the LA traces, why not snug that DRAM chip up close to the FPGA and make the traces short? I didn't remove them, I just won't be connecting them unless I need them. The script that measures the traces copies the .pcb and removes the vias and traces in order to accurately measure the parts I'm interested in. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Update... I added serpentines to the short traces, and re-routed the long traces to go under the sdram chip instead of around it, and got the following... Only 381 mils difference between the shortest and longest. http://www.delorie.com/electronics/sdram/ Net R_WElength 1.509 in Net R_RAS length 1.519 in Net R_CAS length 1.539 in Net R_DQML length 1.554 in Net R_A10 length 1.586 in Net R_BA1 length 1.586 in Net R_A0length 1.587 in Net R_DQ0 length 1.591 in Net R_DQ3 length 1.592 in Net R_A3length 1.600 in Net R_DQ2 length 1.614 in Net R_DQ5 length 1.614 in Net R_A1length 1.615 in Net R_BA0 length 1.615 in Net R_A11 length 1.620 in Net R_A2length 1.620 in Net R_DQ1 length 1.625 in Net R_DQ4 length 1.627 in Net R_CSlength 1.657 in Net R_CKE length 1.666 in Net R_DQ7 length 1.675 in Net R_DQ6 length 1.695 in Net R_A9length 1.729 in Net R_A8length 1.742 in Net R_A7length 1.762 in Net R_A6length 1.775 in Net R_A5length 1.795 in Net R_DQ8 length 1.798 in Net R_A4length 1.826 in Net R_DQ13 length 1.852 in Net R_DQ11 length 1.855 in Net R_DQ9 length 1.857 in Net R_DQ12 length 1.867 in Net R_DQ10 length 1.869 in Net R_DQMH length 1.879 in Net R_DQ14 length 1.883 in Net R_DQ15 length 1.886 in Net R_CLK length 1.890 in And yes, I added a command to show the length of all nets. Report(AllNetLengths). I also used a script to remove the logic analyzer traces from the above report, and pull out the nets I wanted. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Tim Hanson wrote: I've laid out an interface to a 133Mhz SDRAM, and the path lengths were similar to yours. Works great. No LA connector, though. Tim I just looked at the reference design for atmel AT91SAM9260 and it uses similar if not the same memory. Guess what, no clock termination. I can't find any gerbers though, and the pcb file is for snOrcad. If we could get a peek at the layout maybe some insight into a working layout. The only picture I've found is a top view of the board but it doesn't show the traces. The sdram appears not too close to the micro. Wish I could see those traces. Maybe Tim is is right. Still, I'd watch your timing budget closely and probably terminate the clock line. DJ, you could consider the XC3S200-4PQG208C for additional IO. $20 from digikey. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Before you create another board, could you try using a razor to cut all the logic analyzer traces right near or at the vias? I haven't made any boards yet - I'm trying to avoid making more than one ;-) I suppose I could make the board and just leave the via wires out, which disconnects the stub traces on the other side. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Mon, Apr 06, 2009 at 10:41:57PM -0400, DJ Delorie wrote: That could work too. But, honestly, from what I see on your board what's the problem besides the stubs? If I knew that answer, I wouldn't need to ask all these questions. Oh, and make sure to set the constraints on your fpga so the timing is right-on. Yet another thing to learn how to do... Well, in most cases this reduces to forcing the synthesis/mapping tools to use the IOB flip-flops (in VHDL it becomes something like attribute IOB of whatever:signal is true; in the top level file). Otherwise difference in routing delays between internal flip-flops and IOB is much larger than an inch of trace length difference on the board. Yesterday the automatic placer did something extremely stupid on a test of mine and I had 2 nS of routing only beween an IOB and a FF. The simulated annealing or however it's called sometimes produces awful placements (and I had less than 1% of the chip used, an XC3S200A-FT256). Floorplanning can help a lot in these cases. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
- Original Message - From: John Griessen [jg]I think HJ might have meant length of the ramp up or ramp down when he said edge. I can't see how length of a square wave half cycle translates to fractions of wavelengths at some resonance...which is where 1/4 * 'length of the edge' must come from. Yep, it's the edge not the cycle. A 1ns edge has 500 MHz component. That's true even if the square wave were 1 kHz. If you think you don't have a transmission line for that example, you'd be wrong. That 1nS edge will rattle around on a long trace if not terminated. You'd see it as ringing. By saying 1/4 length of the edge is the longest you can go without termination means that all the ratling due to reflections is damped out long before the edge reaches it's full value. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
The simulated annealing or however it's called sometimes produces awful placements (and I had less than 1% of the chip used, an XC3S200A-FT256). Floorplanning can help a lot in these cases. Gabriel I would refrain from floorplanning on small designs. Are you using a constraints file? You just need to set the constraints properly - it usually works pretty good. The trick is writing good constraints. ISE will tell you if it exceeds your constraints. Also, I'm pretty sure you can tell the synthesis tools and PAR tool that you want to use IOB flip-flops. Personally, I don't like to write verilog code with manufacturer specific constructs - it's not portable. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 7, 2009, at 10:48 AM, [1]carzr...@optonline.net wrote: - Original Message - From: John Griessen [jg]I think HJ might have meant length of the ramp up or ramp down when he said edge. I can't see how length of a square wave half cycle translates to fractions of wavelengths at some resonance...which is where 1/4 * 'length of the edge' must come from. i was using a sine wave to approximate the triangle wave from perfect ramps up and perfect ramps down, (full cycles, not half. ), cutting out the rest periods to simplify the math. Yep, it's the edge not the cycle. A 1ns edge has 500 MHz component. That's true even if the square wave were 1 kHz. If you think you don't have a transmission line for that example, you'd be wrong. That 1nS edge will rattle around on a long trace if not terminated. You'd see it as ringing. By saying 1/4 length of the edge is the longest you can go without termination means that all the ratling due to reflections is damped out long before the edge reaches it's full value. This math is why a 3 inch trace woulden't The 500 MHz component for a 1kHZ clock is at 1/50th the energy. or 3.3 volts * 2E-6 or 6.6 micro volts. IF and only IF it has a 0 second edge rate. Guy's, I'm trying to keep it to rules of thumb, that my co workers and I use to build computers with the latest ram and IO technologies. USB2, at 480 mbps, aww, short stubs, match the impedance keep them close and not care. From doctorates in the field and have years of experience. no parts you are using are really square waves, they are trapezoidal. you can't just look at the ramp from the edge, your sending a series, and they sum up constructively or destructively, on the bounce back. the mismatched impedance interfaces are also not perfect reflectors. ( I'm not pulling the reflection coefficient in to this. ) now to defend my rule of thumb, it's not just the edge, it is the whole standing wave. take the Fourier series below, from mathworld [2]http://mathworld.wolfram.com/FourierSeries.html FourierSeriesSquareWave take your Fourier series and expand it till you get a sum of sine waves matching your edge. thats all the content you need, the higher order harmonics aren't a significant part of your energy, they are there but they drop off rapidly. a 1/n relationship from the series. and square waves only include odd harmonics of the waveform. 133MHz at full strength 399MHz at 1/3rd the energy 665MHz at 1/5th the energy 931MHz at 1/7th the energy 1.197 GHz at 1/9th the energy - nearly nonexistent on DJ's transmission lines, any radio card guys want to explain why? these lines are lossy so the energy gets absorbed in the lines, the SWR is low because the lines are short. now if you treat it as a ramp, you have a whole different set of Fourier sums that are required to make it start at the bottom and stay at the top. I'm not getting in to that math because it's not relevant in a clocked periodic system. DJ is building a 133MHz, and its a medium speed interface, slow edges will help him, making his timing meet the specifications of his memory will help him use the speed of light in a vacuum and 1/8th wave antenna. use the speed of light on FR4 and a 1/4 wave antenna. they equate. References 1. mailto:carzr...@optonline.net 2. http://mathworld.wolfram.com/FourierSeries.html inline: FourierSeriesSquareWave_800.gif ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Hi DJ, loved your CC article and can't wait to see your next one. On Mon April 6 2009 11:36:38 pm DJ Delorie wrote: Do you have the other side of your board to route on? Maybe that would help. I do, but I have to manually solder in every single via. My vias are small, but not *that* small. Plus, I can't put vias under anything. What do you mean manually solder? Are you actually installing vias or are you just doing feed-thru's with wire? I ask because I have a *vague* memory from many years ago of someone pressing in their own vias. -Mark S. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
I use feed-through wires. Usually I strip down some 22ga stranded speaker wire and use the strands. They fit in 13 mil holes very nicely :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Hi Steven, I thought your rule of thumb and mine were nearly the same, actually. Let's just drop the math out of it. Leave it as an exercise for student to run a spice simulation (or hyperlinx if you have it) and see for themselves :) If you want to ask the heavy-weights on this matter, the SI-LIST is the place to go. DJ is just looking for the best way to solve his design problem. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ is just looking for the best way to solve his design problem. I think what I'll do is leave the chip where it is, and add what serpentines I can to the shorter traces. I'll leave in the LA connector but solder in the via wires in such a way that I can remove them later - that way, I can debug the state machine at slow speed then crank it up later. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
2 thoughts, tune down your edge rate in the FPGA to make the effective bandwidth of your edges lower. square waves are an infinite series of sine waves, trapezoidal are finite. ( roughly speaking ) 3 inches is a 1/8th wave antenna for 500MHz, again roughly ( 1GHz ~= 12 inches ~=1 nS at the speed of light. ) if you worried about signal integrity, ignore the logic analyzer hookup, use some diff probes. as for the terminators, look at the xilinx demo boards, and their drive strength settings. look how closely they matched the clock and data lines lengths. good luck. On Apr 4, 2009, at 12:29 PM, DJ Delorie wrote: I'm getting close to a final design for my SDRAM board, but I'm thinking about termination for the SDRAM signals. This board is faster than anything else I've done before (133MHz 3.3v). Updated images here: http://www.delorie.com/electronics/sdram/ The left half of the board (U2 left, U1) runs at 24 MHz, no problem. The right half of U2, and U2, run at 133MHz. The longest trace is the CLK line, at just over 3 inches, the shortest is just under an inch. However, most of those lines are brought out to logic analyzer connectors, which may add up to another 1.8 inches (DQ11, for example, has a combined length of 3.9 inches). I'm thinking I have enough space to put in some series terminator packs (8x 0402 SMT) but where and how big? Is it relative to which chip is driving the trace? Should the logic analyzer go on the fast side or the slow side, or does it matter? (it's a 500Ms/s analyzer) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
tune down your edge rate in the FPGA to make the effective bandwidth of your edges lower. square waves are an infinite series of sine waves, trapezoidal are finite. ( roughly speaking ) 3 inches is a 1/8th wave antenna for 500MHz, again roughly ( 1GHz ~= 12 inches ~=1 nS at the speed of light. ) if you worried about signal integrity, ignore the logic analyzer Yeah but on a pcb, flight-time on FR-4 is around 170pS / inch (off the top of my head, anyway). By way of 'rule of thumb' the trace looks like a transmission line if the flight time is greater than 1/4 wavelength. If 1ns edge rate, then it's 1/4 of 4nS, which translates into about 1 (I think I did that right). So anything longer than 1 will have transmission line affects, and you should consider termination. Xilinx fpga's are very capable of producing 1 nS edges or maybe better. That translates to around 500 MHz. My experience with the slew rate limiting on the spartan-2 is that it doesn't do very much. Dropping the drive strength will definitely slow the edges since the output impedance of the gate goes up and you get an RC rise time affect on the line. As long as the degraded rise-time is ok in your design, this is a good method. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 6, 2009, at 2:51 PM, [1]carzr...@optonline.net wrote: tune down your edge rate in the FPGA to make the effective bandwidth of your edges lower. square waves are an infinite series of sine waves, trapezoidal are finite. ( roughly speaking ) 3 inches is a 1/8th wave antenna for 500MHz, again roughly ( 1GHz ~= 12 inches ~=1 nS at the speed of light. ) if you worried about signal integrity, ignore the logic analyzer Yeah but on a pcb, flight-time on FR-4 is around 170pS / inch (off the top of my head, anyway). By way of 'rule of thumb' the trace looks like a transmission line if the flight time is greater than 1/4 wavelength. If 1ns edge rate, then it's 1/4 of 4nS, which translates into about 1 (I think I did that right). So anything longer than 1 will have transmission line affects, and you should consider termination. my old timer gave me a different way use 1/8th wave antenna on PCB, and the speed of light. 1/4 wave antenna open air interestingly enough they are about the same, it's interesting to see the difference in rules of thumb. a 1ns edge rate if perfectly toggled looks like a sine wave (RC effects) that has just over 2nS period or just under 500MHz 500MHz on FR4 using your numbers of 170ps/inch, about 0.5C :-). From Mathematica, to keep track of my units. Units` Take 170 ps per inch and multiply it by 500 Mega Hertz (170. Pico Second)/(1 Inch) 500 Mega Hertz (85000. Hertz Mega Pico Second)/Inch What is per inches, invert. 1/% (0.117647 Inch)/(Hertz Mega Pico Second) clean it up to inches, nice that Mathematica leaves all of the units in there :-) Convert[%, Inch] 11.7647 Inch Make it a quarter wave antenna %/4 2.94118 Inch How long you need to care after about 3 inches. So slow up your edge rate, with some source resistors or through your drive strength and other settings in the FPGA. now for the 1/8th wave rule of thumb PhysicalConstants` Lets look at the 1/8 th rule and speed of light SpeedOfLight /( 500 Mega Hertz) (149896229 Meter)/(250 Hertz Mega Second) Take it to inches N[Convert[%,Inch]] 23.6057 Inch 1/8th wave antenna %/8 2.95071 Inch All rules of Thumb. Xilinx fpga's are very capable of producing 1 nS edges or maybe better. That translates to around 500 MHz. My experience with the slew rate limiting on the spartan-2 is that it doesn't do very much. Dropping the drive strength will definitely slow the edges since the output impedance of the gate goes up and you get an RC rise time affect on the line. As long as the degraded rise-time is ok in your design, this is a good method. Check your ram's spec sheets, also look at the additional delay that the traces on the far side will be exposed. longest clock Vs. shortest data and vice versa. You want your data eye to be nice and big, the sampling clock right in the middle of it. The cleaner the eye the slower your edge rates can go. gene ___ geda-user mailing list [2]geda-u...@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:carzr...@optonline.net 2. mailto:geda-user@moria.seul.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
longest clock Vs. shortest data and vice versa. You want your data eye to be nice and big, the sampling clock right in the middle of it. The cleaner the eye the slower your edge rates can go. So, long story short... I need to redesign the board :-( I tried adding serpentines but there isn't enough room to add more than an inch or so, leaving another inch of mismatch. If I reroute the signals under the chip instead of around it, I can save an inch or more, then serpentine the rest to match trace lengths. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Mon, Apr 06, 2009 at 10:03:36PM -0400, DJ Delorie wrote: I tried adding serpentines but there isn't enough room to add more Excellent news for PCB, though. If DJ has trouble laying out serpentines or trombones, a plugin is sure to follow. ;-) -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Excellent news for PCB, though. If DJ has trouble laying out serpentines or trombones, a plugin is sure to follow. ;-) I didn't have trouble laying them out, I just ran out of room to put them in. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 6, 2009, at 7:03 PM, DJ Delorie wrote: longest clock Vs. shortest data and vice versa. You want your data eye to be nice and big, the sampling clock right in the middle of it. The cleaner the eye the slower your edge rates can go. So, long story short... I need to redesign the board :-( I tried adding serpentines but there isn't enough room to add more than an inch or so, leaving another inch of mismatch. If I reroute the signals under the chip instead of around it, I can save an inch or more, then serpentine the rest to match trace lengths. did you do the math? an inch is 170ps of mismatch. 133MHz is 7.518 ns period so 2.2% error. how good are your memories? if this were say 1033MHz DDR ram modules, you would be hosed. 1.033 GHz is 968ps period 1 inch is 17.6% Its DDR so. 2x 35% error that's toast. but north bridges have tricks up their sleeve they adjust delays in the output and inputs to the ram banks to compensate. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
did you do the math? No, I was going by the micron recommendations for SDRAM. They suggest a much closer length match than I'm getting. I suppose I could just clock it slower if it turns out to be too mis-matched. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Steven Michalske wrote: Hey Steven, that's a pretty interesting analysis. I just want to add something from Dr. Howard Johnson's book on this stuff. His claim is that you can treat a pcb trace as a lumped system if the trace is less than 1/4 * 'length of the edge'. Well, at 170 ps/inch the length of the edge is about 5.8 - that's exactly 1/2 your result. OK, I see it. Your units work out as: (.170nS/inch) * (500e6 cycles/second) = 0.085 cycles/inch or 11.76 inches/cycle. BUT - this is only 1/2 cycle (only 1 edge), so 11.7 inches/cyle * 0.5 cycle = 5.8 If it were a full cycle, like you said, toggle the edge up then down, the complete wave-length is 11.76 inches in FR4. The whole idea is to keep the trace length short so that reflections don't come back and reclock things, or have the wrong levels, or ringing, or just make a lot of emi. All that junk comes from the signal rattling around from end-to-end. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Hey Steven, that's a pretty interesting analysis. I just want to add something from Dr. Howard Johnson's book on this stuff. His claim is that you can treat a pcb trace as a lumped system if the trace is less than 1/4 * 'length of the edge'. Well, at 170 ps/inch the length of the edge is about 5.8 - that's exactly 1/2 your result. If I remove the LA connector and shove the sdram closer to the fpga, I get a trace length range of 2027 mils (CLK) down to 281 mils (DQ7), a mis-match of 1.7 inches, or just under 1/3 of 5.8. I wonder if I could drive the shorter traces less than the longer ones, to match up the edges at the sdram? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
So, long story short... I need to redesign the board :-( that's funny :) Seriously though, as long as the signal is clean and you make the setup/hold times then you are golden. I don't think %skew is the best way to analyze it. Use the absolute time, draw yourself a timing diagram and see if you are close. You *could* always jockey the output timing from your fpga - but that's not a great way to fix it. Didn't someone else mention using a pll? That could work too. But, honestly, from what I see on your board what's the problem besides the stubs? Oh, and make sure to set the constraints on your fpga so the timing is right-on. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
That could work too. But, honestly, from what I see on your board what's the problem besides the stubs? If I knew that answer, I wouldn't need to ask all these questions. Oh, and make sure to set the constraints on your fpga so the timing is right-on. Yet another thing to learn how to do... ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Mon, Apr 6, 2009 at 9:35 PM, DJ Delorie d...@delorie.com wrote: If I remove the LA connector and shove the sdram closer to the fpga, I get a trace length range of 2027 mils (CLK) down to 281 mils (DQ7), a mis-match of 1.7 inches, or just under 1/3 of 5.8. I wonder if I could drive the shorter traces less than the longer ones, to match up the edges at the sdram? I would get rid of the LA connector. On all my SDRAM designs, I concentrated on short trace lengths rather than matching. Most of my traces were less than 1 inch. All seem to work well at 133 MHz. You may be able to delay some signals in the FPGA with DCMs or IOB delays. I have had one failed board with high speed signals. The nets were all well matched in length (+- 1 inch), but over 6 inches long and with 2 connectors. It was an FPGA board I made connected to an adaptor board connected to a Xilinx FPGA development kit. The traces on the XIlinx board are 4 inches. I was attempting to use 3.3V CMOS, and was having severe problems with reflections. I gave that approach up and will be building my own board with the FG676 Xilinx FPGA on it so that I can reduce trace lengths and/or use LVDS. I was forced into a high data rate by only having 18 pins in each direction and needing to move 250 MB/s in each direction. Darrell Harmon ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ Delorie wrote: Hey Steven, that's a pretty interesting analysis. I just want to add something from Dr. Howard Johnson's book on this stuff. His claim is that you can treat a pcb trace as a lumped system if the trace is less than 1/4 * 'length of the edge'. Well, at 170 ps/inch the length of the edge is about 5.8 - that's exactly 1/2 your result. If I remove the LA connector and shove the sdram closer to the fpga, I get a trace length range of 2027 mils (CLK) down to 281 mils (DQ7), a mis-match of 1.7 inches, or just under 1/3 of 5.8. I wonder if I could drive the shorter traces less than the longer ones, to match up the edges at the sdram? sounds tricky to do in practice. With the dimensions you just quotes, an sdram write will gain some setup time because the clock gets there later and looses some hold time for the same reason. 1.7 * 170ps/inch = 289 pS. Peeking at the data sheet, that sdram has some tight specs - like 0.8 nS setup. So that mismatch in line length is going to cost you a little less than 1/2 of your budget. I think you are going to need nice crisp edges in order to make the timing specs. Keeping the data and clock lines relatively equal will eliminate skew headaches. Do you have the other side of your board to route on? Maybe that would help. Why don't you use the PQFP208 fpga and use the extra pins for debugging? That will get rid of the stub junk to the emulator. Then move the the SDRAM around to even up the trace length. Terminate the clock line (series terminate at fpga, RC at the other end). Hey, just wondered if you turn the SDRAM 90 degrees, does that help even out the traces? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
With the dimensions you just quotes, an sdram write will gain some setup time because the clock gets there later and looses some hold time for the same reason. 1.7 * 170ps/inch = 289 pS. Peeking at the data sheet, that sdram has some tight specs - like 0.8 nS setup. So that mismatch in line length is going to cost you a little less than 1/2 of your budget. If the traces are short enough and delays short enough, I can do the setup a half cycle earlier. It makes the state machine a little more difficult, though. It means my time window is now 3.75 nS instead of 7.5 nS but it lets me separate data changes and data sampling. I think the 3A allows me to generate an internal clock that's a quarter phase off from the external clock, too. That gives me another 2nS of setup and hold times. Do you have the other side of your board to route on? Maybe that would help. I do, but I have to manually solder in every single via. My vias are small, but not *that* small. Plus, I can't put vias under anything. Why don't you use the PQFP208 fpga and use the extra pins for debugging? The 3A is not available in that package. The 3E requires 2.5v during programming. Kinda limits my options :-( Hey, just wondered if you turn the SDRAM 90 degrees, does that help even out the traces? I don't know. I'll have to try and see. There's still the 0.8 inches of the sdram's length. I think my best bet is to keep the sdram oriented the way it is, but run the traces to the right-side pins between the left-side pins and under the chip. That way, I only have to make up 450mil of difference due to the chip, and 250 mil due to the FPGA pinout. That's only 700 mil, if I put the chips that far apart a serpentine can make it up. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ - Before you create another board, could you try using a razor to cut all the logic analyzer traces right near or at the vias? This may help, and if the board doesn't work now, there is no harm in a minute with the knife. I've laid out an interface to a 133Mhz SDRAM, and the path lengths were similar to yours. Works great. No LA connector, though. Tim On Mon, Apr 6, 2009 at 10:35 PM, DJ Delorie d...@delorie.com wrote: Hey Steven, that's a pretty interesting analysis. I just want to add something from Dr. Howard Johnson's book on this stuff. His claim is that you can treat a pcb trace as a lumped system if the trace is less than 1/4 * 'length of the edge'. Well, at 170 ps/inch the length of the edge is about 5.8 - that's exactly 1/2 your result. If I remove the LA connector and shove the sdram closer to the fpga, I get a trace length range of 2027 mils (CLK) down to 281 mils (DQ7), a mis-match of 1.7 inches, or just under 1/3 of 5.8. I wonder if I could drive the shorter traces less than the longer ones, to match up the edges at the sdram? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
but the GUI application is DRMed. Well, that may not work for me then, as I have to funnel the data through an MCU, then USB, then to the Linux box. I also have nothing connected to the jtag port, although I suppose I could wire that to the mcu too. What would be cool is getting the LA data into a gtkwave-compatible format. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 4, 2009, at 11:08 PM, DJ Delorie wrote: but the GUI application is DRMed. And it's also Windows-only from what I recall. I only use it on XP anyway... Well, that may not work for me then, as I have to funnel the data through an MCU, then USB, then to the Linux box. I also have nothing connected to the jtag port, although I suppose I could wire that to the mcu too. What would be cool is getting the LA data into a gtkwave-compatible format. I've had good luck capturing data inside the FPGA in BRAM at the full clock speed, then reading it out slowly over SPI to an ARM processor where it gets formatted sent via a USB CDC interface to code running on a PC. It's not screaming fast, but then neither is Chipscope via JTAG. It would probably be straight-forward to write C/Perl/whatever to format data dumped from BRAM as a VCD to load into gtkwave. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Yeah, it didn't occur to me,but chipscope is a good method. If it's not free, and you have some extra fpga pins, bring out a couple of test pins to a header, then route the internal signals to that header. I'm at a loss for the name, it may be fpgaeditor, but it is really easy to route/reroute signals to the test pins without editing and recompiling the chip design. I did it all the time on my last job. Anyway, this method can give you some visibility into the internal fpga workings without resorting to chip scope. Also, chipscope uses up block ram (it uses minimum 2 block ram, if I remember right), so if that's a concern for you, this way may be an alternative. From your earlier email, I thought you were worried about the signals on the bus. If you just care about things at the functional level, this is a good way to go. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
I built a very similar circuit using an Altera FPGA and a 100MHz SDRAM with good results. To keep things easy, I did a couple of things. One, I kept the signals to the SDRAM as short as possible (around an inch long, in most cases). Second, I made sure that the clock that the SDRAM controller sees and the clock of the SDRAM have minimal skew. I did this by running the original clock into the FPGA and then running it out 2 pins. One went to the SDRAMs and the other went back into the FPGA, but the etch length was the same as the length that went to the SDRAMs. Then, I used a PLL in the FPGA to look at the arriving clock and skew it (which are really the output clocks) to match the clock of the SDRAM controller. That way, I could be sure that the clock that the SDRAM sees and the clock of the controller were the same. Without that, it's very hard to meet all the max/min setup and hold times of the SDRAM and SDRAM contoller. Steve DJ Delorie wrote: That's what I'd do. At the sort of volumes you and I work with it's a lot cheaper to use a FPGA big enough to include chipscope/signaltap even in the full design than to allow for an LA hookup. I'm limited to QFP packages, though. I picked the 3A family for some reason, ah, power - the 3A doesn't need a 2.5v interface block. I haven't tried synthesizing into the 3A yet to see how much space I'm using. Why not just use chipscope? I thought you could get that for free these days (although admittedly I use Altera mainly for free Signaltap myself). Well, if chipscope is freely downloadable, I'm OK with that. Hard to believe the LA expects signals that fast without active probes. Well, I said Ms/s, not MHz. It's mostly useful for measuring skew and jitter relative to other pins. I usually run at one of the slower speeds, as the LA's compression doesn't work at the fastest speed. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Eric Brombaugh wrote: There was an open-source (ish) work-alike that got a write-up in Xilinx's X-cell magazine a few years back that used the Xilinx JTAG library elements along with an external JTAG access API, but it's been pulled from all the websites mentioned in the article. There's a chipscope-like core at opencores: http://www.opencores.org/?do=projectwho=log_anal John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
From your earlier email, I thought you were worried about the signals on the bus. If you just care about things at the functional level, this is a good way to go. I care about both, of course. I want it to work, but if it doesn't work at first I need to be able to figure out why. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: terminators
I'm getting close to a final design for my SDRAM board, but I'm thinking about termination for the SDRAM signals. This board is faster than anything else I've done before (133MHz 3.3v). Updated images here: http://www.delorie.com/electronics/sdram/ The left half of the board (U2 left, U1) runs at 24 MHz, no problem. The right half of U2, and U2, run at 133MHz. The longest trace is the CLK line, at just over 3 inches, the shortest is just under an inch. However, most of those lines are brought out to logic analyzer connectors, which may add up to another 1.8 inches (DQ11, for example, has a combined length of 3.9 inches). I'm thinking I have enough space to put in some series terminator packs (8x 0402 SMT) but where and how big? Is it relative to which chip is driving the trace? Should the logic analyzer go on the fast side or the slow side, or does it matter? (it's a 500Ms/s analyzer) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Sat, Apr 04, 2009 at 03:29:16PM -0400, DJ Delorie wrote: The right half of U2, and U2, run at 133MHz. The longest trace is the CLK line, at just over 3 inches, the shortest is just under an inch. However, most of those lines are brought out to logic analyzer connectors, which may add up to another 1.8 inches (DQ11, for example, has a combined length of 3.9 inches). I think you'd be fine without the stubs going to the header. Even with the stubs your SDRAM will probably work but there will be terrible EMI. I chased down an EMI problem on a board with ONE stub at 125MHz (due to leaving a clock testpoint enabled). You have 20+ stubs. Ideally you'd put the LA connector in the middle of the bus. Just pick a higher density connector. AMP MICTOR connectors are a popular choice. I'm thinking I have enough space to put in some series terminator packs (8x 0402 SMT) but where and how big? Does the FPGA you're using have controllable drive strength? That alone is probably enough for your design. Otherwise put the series resistors on the driving side. The value is a bit of a black art, but 27..51R is in the right ballpark. To measure their effectiveness beyond pass/fail you'd need a very fast (6G+) scope. -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
I think you'd be fine without the stubs going to the header. Even with the stubs your SDRAM will probably work but there will be terrible EMI. This is a proof-of-concept board, so EMI isn't an issue (yet). Certainly, adding the analyzer's probes will add EMI all over the place too. I chased down an EMI problem on a board with ONE stub at 125MHz (due to leaving a clock testpoint enabled). You have 20+ stubs. Series resistors on the back (stub) side, maybe? Near the via? Ideally you'd put the LA connector in the middle of the bus. Just pick a higher density connector. AMP MICTOR connectors are a popular choice. The problem is, the connector is somewhat pre-defined for me - I'm using old hard drive cables as the LA's connector is a standard 2x20 ribbon cable connector. And, my software doesn't let me rearrange the signals in a bus so I had to bring them out in the right order. I'm thinking I have enough space to put in some series terminator packs (8x 0402 SMT) but where and how big? Does the FPGA you're using have controllable drive strength? Hmmm... yes, it does - it has both slew rate control and drive current control. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ Delorie wrote: I'm getting close to a final design for my SDRAM board, but I'm thinking about termination for the SDRAM signals. This board is faster than anything else I've done before (133MHz 3.3v). Updated images here: http://www.delorie.com/electronics/sdram/ The left half of the board (U2 left, U1) runs at 24 MHz, no problem. The right half of U2, and U2, run at 133MHz. The longest trace is the CLK line, at just over 3 inches, the shortest is just under an inch. However, most of those lines are brought out to logic analyzer connectors, which may add up to another 1.8 inches (DQ11, for example, has a combined length of 3.9 inches). I'm thinking I have enough space to put in some series terminator packs (8x 0402 SMT) but where and how big? Is it relative to which chip is driving the trace? Should the logic analyzer go on the fast side or the slow side, or does it matter? (it's a 500Ms/s analyzer) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user That Spartan is capable of sub-nanosecond edges which will far exceed the frequency of your clock. Xilinx will allow you to adjust the slew-rate within limits. Use the built-in terminator resistors on the clock-out pins, not the data lines. If you are so inclined, terminate the clock at the end of line (not at the FPGA source, and past the end of line) with an R-C style, where R = 51-Ohm and C=100 pF. That setup will get you source termination at the FPGA plus end termination with the RC. Terminating data lines is always difficult because they're bidirectional. I suppose you could end-terminate them on both sides, but am sure if it buys you anything, timing wise. Those mictor connectors are a great option, like Ben pointed out. Are you willing to put some buffers at the end of your bus? You know, between the bus and the LA? At least you can minimize the stubs that way. You really don't want to destroy your timing budget due to stubs and the signal integrity headache that comes along for the ride. You could depopulate the buffer in production - or what if the buffer is part of another board, that has the LA connector on it? Just a thought. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
Are you willing to put some buffers at the end of your bus? Like a pair of 74AVC16244's ? They'd have to be mounted on the back of the board, under the bus where the stubs go. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ Delorie wrote: Are you willing to put some buffers at the end of your bus? Like a pair of 74AVC16244's ? They'd have to be mounted on the back of the board, under the bus where the stubs go. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Yeah that looks ok. It's got a 6 pF input capacitance. For a 1-nS edge, I figure 6 pF is going to have around 27-Ohm reactance. So you'll have a little mismatch to your trace, maybe a little ringing. Beats loading it with an inductive stub. I think this is an ok method as long as you realize there will be some timing distortion in your measurements. At 133 MHz, the cycle time is 7.5 nS. Hopefully, the internal skew inside the buffer is fairly constant (within a single package, it'll be pretty tight), and the flight time on your cable is matched. What voltage are you running? I see the tpd gets slow as the supply is lowered. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
have a little mismatch to your trace, maybe a little ringing. Beats loading it with an inductive stub. What about just putting a 100 ohm series resistor right after the via, on the stub? At least it will isolate the sdram lines from the stubs. What voltage are you running? 3.3v ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
DJ Delorie wrote: have a little mismatch to your trace, maybe a little ringing. Beats loading it with an inductive stub. What about just putting a 100 ohm series resistor right after the via, on the stub? At least it will isolate the sdram lines from the stubs. You're in a tough spot. You have 7.5 ns cycle time. With 100 ohm, it only takes 75pF to consume the entire timing budget. The rise time of the network will completely distort the readings at the LA. I think your ribbon cable is going to have at least that much capacitance (and probably a bunch of ugly inductance to ruin your day). This is why the mictor connector exists. Placing such a small stub on the line, with the LA pod having very low input capacitance, and the pod has buffers right at the mictor end of things, the signal does not degrade. The PCI guys struggled with this very problem 10 years ago. I'm willing to bet the input capacitance of the LA is high enough to make more problems too. What voltage are you running? 3.3v They don't mention edge rates in the data sheet, but tpd is 1.7 nS worst case. I think you will get some idea of what is going on your bus - albeit with some timing distortion. Here's another idea. Instead of the LA, use a scope - assuming you can deal with looking at just a couple of signals at a time. Put the scope into 50-ohm mode. Connect a 50-ohm coax with BNC on one end to the scope. Cut the end of the coax to expose the center and the shield. Solder one end of a 1K resistor to the center - the other end gets soldered to your bus where you want to probe. Solder the shield to the board as close as possible to the place where the resistor is soldered. You should get a very faithful reproduction of the signal (with the possible exception of amplitude distortion - maybe). I've heard of people using SMA connectors for this, and buying cool resistor divider probes for their scope. But for the diy guy, just do what I said in the last paragraph. It works really well - amazingly well actually. In fact, you could just stub out some soldering test pads on the traces, and sprinkle some grounds around. Then just solder the resistor wherever you want to probe. Not very elegant - but it works. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
With 100 ohm, it only takes 75pF to consume the entire timing budget. Hmmm... maybe I'm going about this the wrong way. Would it make more sense to get rid of the LA on that side, move the sdram chip as close as I can to the FPGA, and use something like chipscope to monitor the signals? I've got both SPI and addr/data connections to the MCU on the other side to get the data out. This is why the mictor connector exists. Yeah, but that's pushing the project outside the effort I want to put into this board - basically, it's a one-time board to try some things with. Here's another idea. Instead of the LA, use a scope My scope is nowhere near fast enough for that. The LA is 500 ms/s or can be externally clocked up to 200 mhz. The scope is only 32 ms/s. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Sun, Apr 05, 2009 at 01:19:32AM -0400, DJ Delorie wrote: Hmmm... maybe I'm going about this the wrong way. Would it make more sense to get rid of the LA on that side, move the sdram chip as close as I can to the FPGA, and use something like chipscope That's what I'd do. At the sort of volumes you and I work with it's a lot cheaper to use a FPGA big enough to include chipscope/signaltap even in the full design than to allow for an LA hookup. If things are going wrong due to external timing or signal issues the LA won't help anyway -- you'll need a good scope. signals? I've got both SPI and addr/data connections to the MCU on the other side to get the data out. Why not just use chipscope? I thought you could get that for free these days (although admittedly I use Altera mainly for free Signaltap myself). Here's another idea. Instead of the LA, use a scope My scope is nowhere near fast enough for that. The LA is 500 ms/s or can be externally clocked up to 200 mhz. The scope is only 32 ms/s. Hard to believe the LA expects signals that fast without active probes. The probes I've seen have the .1 type headers on the LA end, but the far end have active probes and other connectors (typically mictor) and cost $1500/set. -- Ben Jackson AD7GD b...@ben.com http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
On Apr 4, 2009, at 10:25 PM, Ben Jackson wrote: Why not just use chipscope? I thought you could get that for free these days (although admittedly I use Altera mainly for free Signaltap myself). I use Chipscope pretty much constantly, both on my day-job designs (Virtex 5) and on personal projects (Spartan 3E). It's a great way to get visibility control inside the design and I'd recommend it. As far as I'm aware though, it's not free. IIRC, Xilinx provides a free 60-day trial, but to use it beyond that requires about $700 outlay for the permanent license. The hardware library elements to support it are free, but the GUI application is DRMed. There was an open-source (ish) work-alike that got a write-up in Xilinx's X-cell magazine a few years back that used the Xilinx JTAG library elements along with an external JTAG access API, but it's been pulled from all the websites mentioned in the article. It mainly provided register read/write access via JTAG and an external TCL-TK UI. As far as I know there was no internal logic analyzer provided. It probably wouldn't be too tough to duplicate and expand to include that functionality though. Eric ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: terminators
That's what I'd do. At the sort of volumes you and I work with it's a lot cheaper to use a FPGA big enough to include chipscope/signaltap even in the full design than to allow for an LA hookup. I'm limited to QFP packages, though. I picked the 3A family for some reason, ah, power - the 3A doesn't need a 2.5v interface block. I haven't tried synthesizing into the 3A yet to see how much space I'm using. Why not just use chipscope? I thought you could get that for free these days (although admittedly I use Altera mainly for free Signaltap myself). Well, if chipscope is freely downloadable, I'm OK with that. Hard to believe the LA expects signals that fast without active probes. Well, I said Ms/s, not MHz. It's mostly useful for measuring skew and jitter relative to other pins. I usually run at one of the slower speeds, as the LA's compression doesn't work at the fastest speed. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
