Re: [gem5-dev] Review Request 2680: cpu: o3: record cpi stacks

[Nilay Vaish via gem5-dev]

On Wed, 4 Mar 2015, Andreas Hansson wrote:



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Should this perhaps be a probe rather?



OK, I just read the commit message from the changeset 10023 91faf6649de0. 
I am going to argue against separating statistics gathering from the so 
called functional code.  One of the ways I use to learn gem5 (or have 
used) is observing how the statistics are being collected.  Moving 
statistics collection to a separate file, makes that collection code less 
visible, which is as important as the functional code itself.  This 
approach was being used in ruby originally.  And I changed it (changeset 
67d9da312ef0) so that a person reading the code knows what statistic is 
being updated when.


--
Nilay
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Re: [gem5-dev] Review Request 2619: cpu: Add L-TAGE branch predictor

[Nilay Vaish via gem5-dev]

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OK.  I am sorry for not realizing that so many changes would be required to 
separate out
the params just meant for LTAGE.  Had I had realized that, I probably would not 
have asked for it.
I think we should break this latest version into two separate patches.  The 
first patch
creates these separate sim objects for different predictor types. The second 
patch adds LTAGE.

And I am willing to go with either order between those two patches.  That is, 
if you prefer, you
can add LTAGE first and then separate out the predictors.

- Nilay Vaish


On March 4, 2015, 5:52 p.m., Dibakar Gope wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2619/
> ---
> 
> (Updated March 4, 2015, 5:52 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> It is the L-TAGE predictor from the Branch Prediction Championship, 
> originally coded by Vignyan Reddy, and modified by me.
> 
> 
> Diffs
> -
> 
>   configs/common/O3_ARM_v7a.py 8a20e2a1562d 
>   src/cpu/inorder/InOrderCPU.py 8a20e2a1562d 
>   src/cpu/minor/MinorCPU.py 8a20e2a1562d 
>   src/cpu/o3/O3CPU.py 8a20e2a1562d 
>   src/cpu/pred/2bit_local.hh 8a20e2a1562d 
>   src/cpu/pred/2bit_local.cc 8a20e2a1562d 
>   src/cpu/pred/BranchPredictor.py 8a20e2a1562d 
>   src/cpu/pred/SConscript 8a20e2a1562d 
>   src/cpu/pred/bi_mode.hh 8a20e2a1562d 
>   src/cpu/pred/bi_mode.cc 8a20e2a1562d 
>   src/cpu/pred/bpred_unit.hh 8a20e2a1562d 
>   src/cpu/pred/bpred_unit.cc 8a20e2a1562d 
>   src/cpu/pred/bpred_unit_impl.hh 8a20e2a1562d 
>   src/cpu/pred/ltage.hh PRE-CREATION 
>   src/cpu/pred/ltage.cc PRE-CREATION 
>   src/cpu/pred/tournament.hh 8a20e2a1562d 
>   src/cpu/pred/tournament.cc 8a20e2a1562d 
>   src/cpu/simple/BaseSimpleCPU.py 8a20e2a1562d 
> 
> Diff: http://reviews.gem5.org/r/2619/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Dibakar Gope
> 
>

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Re: [gem5-dev] Review Request 2680: cpu: o3: record cpi stacks

[Andreas Hansson via gem5-dev]

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Should this perhaps be a probe rather?

- Andreas Hansson


On March 4, 2015, 9 a.m., Nilay Vaish wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2680/
> ---
> 
> (Updated March 4, 2015, 9 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 10735:c8c9b6d902cb
> ---
> cpu: o3: record cpi stacks
> 
> This patch labels each empty slot of the commit width every cycle using four
> different types of delays: misprediction, fetch, memory and execution.  For
> memory delays, we check if a memory reference instruction is at the head of 
> the
> rob.  Otherwise, we label the slot as execution delayed.  If the rob is empty,
> we assume the reason for the vacancy to be delay in fetching the instuction.
> Lastly, if the cpu is squashing instructions, then we assume that slots are
> going vacant because of misprediction.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/commit.hh 8a20e2a1562d 
>   src/cpu/o3/commit_impl.hh 8a20e2a1562d 
> 
> Diff: http://reviews.gem5.org/r/2680/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Nilay Vaish
> 
>

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[gem5-dev] Review Request 2680: cpu: o3: record cpi stacks

[Nilay Vaish via gem5-dev]

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Review request for Default.


Repository: gem5


Description
---

Changeset 10735:c8c9b6d902cb
---
cpu: o3: record cpi stacks

This patch labels each empty slot of the commit width every cycle using four
different types of delays: misprediction, fetch, memory and execution.  For
memory delays, we check if a memory reference instruction is at the head of the
rob.  Otherwise, we label the slot as execution delayed.  If the rob is empty,
we assume the reason for the vacancy to be delay in fetching the instuction.
Lastly, if the cpu is squashing instructions, then we assume that slots are
going vacant because of misprediction.


Diffs
-

  src/cpu/o3/commit.hh 8a20e2a1562d 
  src/cpu/o3/commit_impl.hh 8a20e2a1562d 

Diff: http://reviews.gem5.org/r/2680/diff/


Testing
---


Thanks,

Nilay Vaish

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[gem5-dev] Review Request 2679: cpu: o3: another assert instead of check

[Nilay Vaish via gem5-dev]

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Review request for Default.


Repository: gem5


Description
---

Changeset 10734:c922ae8d84f9
---
cpu: o3: another assert instead of check


Diffs
-

  src/cpu/o3/commit_impl.hh 8a20e2a1562d 

Diff: http://reviews.gem5.org/r/2679/diff/


Testing
---


Thanks,

Nilay Vaish

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Re: [gem5-dev] Review Request 2619: cpu: Add L-TAGE branch predictor

[Nilay Vaish via gem5-dev]

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Several lines seem to have more than 80 characters.


src/cpu/pred/BranchPredictor.py


I suggest that we create a new class for TAGE predictor and move these 
parameters to that class.


- Nilay Vaish


On March 3, 2015, 2:53 a.m., Dibakar Gope wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2619/
> ---
> 
> (Updated March 3, 2015, 2:53 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> It is the L-TAGE predictor from the Branch Prediction Championship, 
> originally coded by Vignyan Reddy, and modified by me.
> 
> Changeset 10727:73315fc01762
> ---
> [mq]: ltage_updated.patch
> 
> 
> Diffs
> -
> 
>   src/cpu/pred/2bit_local.hh 8a20e2a1562d 
>   src/cpu/pred/2bit_local.cc 8a20e2a1562d 
>   src/cpu/pred/BranchPredictor.py 8a20e2a1562d 
>   src/cpu/pred/SConscript 8a20e2a1562d 
>   src/cpu/pred/bi_mode.hh 8a20e2a1562d 
>   src/cpu/pred/bi_mode.cc 8a20e2a1562d 
>   src/cpu/pred/bpred_unit.hh 8a20e2a1562d 
>   src/cpu/pred/bpred_unit.cc 8a20e2a1562d 
>   src/cpu/pred/bpred_unit_impl.hh 8a20e2a1562d 
>   src/cpu/pred/ltage.hh PRE-CREATION 
>   src/cpu/pred/ltage.cc PRE-CREATION 
>   src/cpu/pred/tournament.hh 8a20e2a1562d 
>   src/cpu/pred/tournament.cc 8a20e2a1562d 
> 
> Diff: http://reviews.gem5.org/r/2619/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Dibakar Gope
> 
>

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[gem5-dev] Review Request 2678: cpu: o3: Remove unused code in iew, add assert instead.

[Nilay Vaish via gem5-dev]

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Review request for Default.


Repository: gem5


Description
---

Changeset 10733:143028d952ec
---
cpu: o3: Remove unused code in iew, add assert instead.


Diffs
-

  src/cpu/o3/iew_impl.hh 8a20e2a1562d 

Diff: http://reviews.gem5.org/r/2678/diff/


Testing
---


Thanks,

Nilay Vaish

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[gem5-dev] Cron /z/m5/regression/do-regression quick

[Cron Daemon via gem5-dev]

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