[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED!
[gem5-dev] Change in gem5/gem5[master]: dev: Turn EtherObject into an interface class.
Hello Jason Lowe-Power, Nikos Nikoleris, Gabor Dozsa, Weiping Liao, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17028 to look at the new patch set (#3). Change subject: dev: Turn EtherObject into an interface class. .. dev: Turn EtherObject into an interface class. This class used to drive from SimObject so that it could be derived from to get both the interface and SimObject while still using single inheritance. With this change, EtherObject is now just an interface class with only one pure virtual function which can be inherited alongside SimObject. This makes it more flexible so that it can be used in places where you might want a different inheritance hierarchy, for instance to inherit from MemObject. Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7 --- M src/dev/net/Ethernet.py M src/dev/net/SConscript M src/dev/net/dist_etherlink.cc M src/dev/net/dist_etherlink.hh M src/dev/net/etherbus.cc M src/dev/net/etherbus.hh M src/dev/net/etherlink.cc M src/dev/net/etherlink.hh M src/dev/net/etherobject.hh M src/dev/net/etherswitch.cc M src/dev/net/etherswitch.hh M src/dev/net/ethertap.cc M src/dev/net/ethertap.hh A src/dev/net/python.cc 14 files changed, 79 insertions(+), 42 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17028 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7 Gerrit-Change-Number: 17028 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Gabor Dozsa Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem: Move the Port base class into sim.
Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17036 to look at the new patch set (#3). Change subject: mem: Move the Port base class into sim. .. mem: Move the Port base class into sim. The Port class is going to be officially used for more than just memory system connections. Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af --- M src/mem/port.cc M src/mem/port.hh M src/sim/SConscript A src/sim/port.cc A src/sim/port.hh 5 files changed, 154 insertions(+), 53 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17036 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af Gerrit-Change-Number: 17036 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Change || to && for MessageBuffers in connectPorts.
Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17031 to look at the new patch set (#3). Change subject: python: Change || to && for MessageBuffers in connectPorts. .. python: Change || to && for MessageBuffers in connectPorts. The connectPorts function currently checks if *either* of the peers in a port connection are a MessageBuffer, and if so will ignore the connection. This CL changes that || into a && so that *both* of the peers need to be a Ruby types (either a MessageBuffer or Network) for the connection to be ignored. That makes it easier to contain that abnormal behavior to those types instead of having it apply even when other types of port owners are involved. Unfortunately the number of interesting Ruby types is unbounded, but these are the types with ports as of today. This mechanism will hopefully be replacedall together so this should be a temporary issue. Change-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab --- M src/python/pybind11/pyobject.cc 1 file changed, 6 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17031 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab Gerrit-Change-Number: 17031 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem: Track the MemObject owner in MasterPort and SlavePort.
Hello Anthony Gutierrez, Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17032 to look at the new patch set (#3). Change subject: mem: Track the MemObject owner in MasterPort and SlavePort. .. mem: Track the MemObject owner in MasterPort and SlavePort. These types are much more tied to MemObjects and the gem5 memory protocol than the Port or BaseMasterPort and BaseSlavePort classes. Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742 --- M src/mem/port.cc M src/mem/port.hh 2 files changed, 25 insertions(+), 25 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17032 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742 Gerrit-Change-Number: 17032 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim: Add a getPort function to SimObject.
Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17037 to look at the new patch set (#3). Change subject: sim: Add a getPort function to SimObject. .. sim: Add a getPort function to SimObject. This will retrieve a Port object from a given SimObject (which might not be a MemObject) no matter what flavor of Port it is. Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1 --- M src/python/m5/SimObject.py M src/sim/sim_object.cc M src/sim/sim_object.hh 3 files changed, 23 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17037 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1 Gerrit-Change-Number: 17037 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem: Move bind() and unbind() into the Port class.
Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17038 to look at the new patch set (#3). Change subject: mem: Move bind() and unbind() into the Port class. .. mem: Move bind() and unbind() into the Port class. These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 --- M src/dev/net/etherint.cc M src/dev/net/etherint.hh M src/mem/port.cc M src/mem/port.hh M src/sim/port.cc M src/sim/port.hh 6 files changed, 61 insertions(+), 29 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17038 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Gerrit-Change-Number: 17038 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17040 to look at the new patch set (#3). Change subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort. .. arch, cpu, dev, gpu, mem, sim, python: start using getPort. Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 --- M src/arch/arm/table_walker.cc M src/arch/arm/table_walker.hh M src/arch/arm/tlb.cc M src/arch/arm/tlb.hh M src/arch/generic/tlb.hh M src/arch/x86/interrupts.hh M src/arch/x86/pagetable_walker.cc M src/arch/x86/pagetable_walker.hh M src/arch/x86/tlb.cc M src/arch/x86/tlb.hh M src/cpu/base.cc M src/cpu/base.hh M src/cpu/testers/directedtest/RubyDirectedTester.cc M src/cpu/testers/directedtest/RubyDirectedTester.hh M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh M src/cpu/testers/memtest/memtest.cc M src/cpu/testers/memtest/memtest.hh M src/cpu/testers/rubytest/RubyTester.cc M src/cpu/testers/rubytest/RubyTester.hh M src/cpu/testers/traffic_gen/base.cc M src/cpu/testers/traffic_gen/base.hh M src/cpu/trace/trace_cpu.cc M src/dev/dma_device.cc M src/dev/dma_device.hh M src/dev/io_device.cc M src/dev/io_device.hh M src/dev/net/Ethernet.py M src/dev/net/SConscript M src/dev/net/dist_etherlink.cc M src/dev/net/dist_etherlink.hh M src/dev/net/etherbus.cc M src/dev/net/etherbus.hh M src/dev/net/etherdevice.hh M src/dev/net/etherlink.cc M src/dev/net/etherlink.hh M src/dev/net/etherswitch.cc M src/dev/net/etherswitch.hh M src/dev/net/ethertap.cc M src/dev/net/ethertap.hh M src/dev/net/i8254xGBe.cc M src/dev/net/i8254xGBe.hh M src/dev/net/ns_gige.cc M src/dev/net/ns_gige.hh M src/dev/net/sinic.cc M src/dev/net/sinic.hh M src/dev/pci/copy_engine.cc M src/dev/pci/copy_engine.hh M src/dev/x86/i82094aa.cc M src/dev/x86/i82094aa.hh M src/gpu-compute/compute_unit.hh M src/gpu-compute/dispatcher.cc M src/gpu-compute/dispatcher.hh M src/gpu-compute/gpu_tlb.cc M src/gpu-compute/gpu_tlb.hh M src/gpu-compute/lds_state.hh M src/gpu-compute/tlb_coalescer.cc M src/gpu-compute/tlb_coalescer.hh M src/learning_gem5/part2/simple_cache.cc M src/learning_gem5/part2/simple_cache.hh M src/learning_gem5/part2/simple_memobj.cc M src/learning_gem5/part2/simple_memobj.hh M src/mem/addr_mapper.cc M src/mem/addr_mapper.hh M src/mem/bridge.cc M src/mem/bridge.hh M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/comm_monitor.cc M src/mem/comm_monitor.hh M src/mem/dram_ctrl.cc M src/mem/dram_ctrl.hh M src/mem/dramsim2.cc M src/mem/dramsim2.hh M src/mem/external_master.cc M src/mem/external_master.hh M src/mem/external_slave.cc M src/mem/external_slave.hh M src/mem/mem_checker_monitor.cc M src/mem/mem_checker_monitor.hh M src/mem/mem_delay.cc M src/mem/mem_delay.hh M src/mem/mem_object.cc M src/mem/mem_object.hh M src/mem/qos/mem_sink.cc M src/mem/qos/mem_sink.hh M src/mem/ruby/network/MessageBuffer.hh M src/mem/ruby/network/Network.hh R src/mem/ruby/network/dummy_port.hh M src/mem/ruby/slicc_interface/AbstractController.cc M src/mem/ruby/slicc_interface/AbstractController.hh M src/mem/ruby/system/RubyPort.cc M src/mem/ruby/system/RubyPort.hh M src/mem/serial_link.cc M src/mem/serial_link.hh M src/mem/simple_mem.cc M src/mem/simple_mem.hh M src/mem/xbar.cc M src/mem/xbar.hh M src/python/SConscript M src/python/pybind11/pybind.hh D src/python/pybind11/pyobject.cc M src/sim/SConscript M src/sim/cxx_manager.cc M src/sim/init.cc R src/sim/python.cc M src/sim/system.cc M src/sim/system.hh 108 files changed, 394 insertions(+), 750 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17040 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Gerrit-Change-Number: 17040 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Improve how templated SimObject classes are handled.
Hello Jason Lowe-Power, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17228 to look at the new patch set (#2). Change subject: python: Improve how templated SimObject classes are handled. .. python: Improve how templated SimObject classes are handled. When setting up a SimObject's Param structure, gem5 will autogenerate a header file which attempts to declare the SimObject's C++ type. It has had at least some level of sophistication there where it would pull off the namespaces ahead of the class name and handle them properly, but it didn't know how to handle templates. This change improves that handling in two ways. First, it adds a new magical SimObject attribute called 'cxx_template_params' which is used to specify what the template parameters are as a list. For instance, if your SimObject was a template which took an integer constant as its first parameter and a type as its second, this attribute could look like the following: cxx_template_params = [ 'int FOO', 'class Bar' ] Importantly, if there are any default values for these template parameters, they should *not* be included here, they should be specified where the class is later defined. The second new mechanism is to add an internal CxxClass in the SimObject.cxx_param_decl method. This class accepts the class signature in the cxx_class attribute and the cxx_template_params and does two things. First, it strips off namespaces like in the old implementation. Second, it extracts and processes any template arguments attached to the class. If these are constants (as determined by the contents of cxx_template_params), then they are stored verbatim. If they're types, then they're recursively expanded into a CxxClass and stored that way. Note that these are the *values* of the template arguments, where as cxx_template_params lists the *types* and *names* of those arguments. In our earlier example, if cxx_class was: cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>' Then CxxClass would extract the namespace 'CoolClasses', the class name 'ClassName', the argument '12', and the argument 'Fruit::Apple'. That second argument would be expanded into a CxxClass with the namespace 'Fruit' and the class name 'Apple'. Importantly here, because there were no default arguments given in cxx_template_params, all "hidden" arguments which would fall through to their defaults need to be fully specified in cxx_class. The CxxClass has a method called declare() which uses the information extracted earlier to output all of the "stuff" necessary for declaring the given class, including opening any containing namespaces and putting template<...> ahead of the actual class declaration with the template parameters specified. If any of the template arguments are themselves CxxClass instances, then they'll be recursively declared immediately before the current class is. An alternative solution to this problem might be to include the header file which actually defines the cxx_class type to avoid having to come up with a declaration. Unfortunately this doesn't work since it can set up include loops where the SimObject C++ header file includes the param header to get access to the Param type, but that includes the C++ header to get access to the SimObject type. This also makes it harder for SimObjects to refer to each other, since they rely on the declaration in the params header files when declaring a member pointer to that type in their own Param structures. Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1 --- M src/python/m5/SimObject.py 1 file changed, 80 insertions(+), 7 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17228 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1 Gerrit-Change-Number: 17228 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] ToT build failures for ARM
Great, thanks for the quick fix!
Gabe
On Thu, Mar 14, 2019 at 12:33 PM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:
> Hi Gabe,
>
> thanks for pointing that out.
> We have addressed the issues with the following patches:
>
> https://gem5-review.googlesource.com/c/public/gem5/+/17288/1
> https://gem5-review.googlesource.com/c/public/gem5/+/17289/1
>
> Thanks
>
> Giacomo
> --
> *From:* gem5-dev on behalf of Gabe Black <
> gabebl...@google.com>
> *Sent:* 14 March 2019 13:10
> *To:* gem5 Developer List
> *Subject:* [gem5-dev] ToT build failures for ARM
>
> These look like issues exposed by compiler version and that (if that's what
> they are) have known fixes. They should be easy to fix, but I'm going to
> bed. If they haven't been fixed in the near future I'll send some patches.
>
> Representative compiler errors below.
>
> Gabe
>
>
> In file included from
> build/ARM/arch/arm/generated/generic_cpu_exec_6.cc:10:0:
> build/ARM/arch/arm/generated/exec-ns.cc.inc: In member function 'Fault
> ArmISAInst::SvePredBic<_Element>::execute(ExecContext*, Trace::InstRecord*)
> const':
> build/ARM/arch/arm/generated/exec-ns.cc.inc:220568:40: error: '~' on an
> expression of type bool [-Werror=bool-operation]
> destElem = srcElem1 & ~srcElem2;
>^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:220568:40: note: did you mean
> to use logical not ('!')?
> build/ARM/arch/arm/generated/exec-ns.cc.inc: In member function 'Fault
> ArmISAInst::SvePredBics<_Element>::execute(ExecContext*,
> Trace::InstRecord*) const':
> build/ARM/arch/arm/generated/exec-ns.cc.inc:220634:40: error: '~' on an
> expression of type bool [-Werror=bool-operation]
> destElem = srcElem1 & ~srcElem2;
>^~~~
>
> In file included from build/ARM/arch/arm/generated/inst-constrs-3.cc:9:0:
> build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr
> ArmISAInst::Aarch64::decodeSveInt(ArmISA::ExtMachInst)':
> build/ARM/arch/arm/generated/decoder-ns.cc.inc:73599:17: error: this
> statement may fall through [-Werror=implicit-fallthrough=]
> }
> ^
> build/ARM/arch/arm/generated/decoder-ns.cc.inc:73601:11: note: here
> case 0x1:
> ^~~~
> build/ARM/arch/arm/generated/decoder-ns.cc.inc:73637:17: error: this
> statement may fall through [-Werror=implicit-fallthrough=]
> }
> ^
> build/ARM/arch/arm/generated/decoder-ns.cc.inc:73639:11: note: here
> case 0x2:
> ^~~~
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Re: [gem5-dev] Port configuration overhaul
Definitely. This makes ports a lot more abstract, where they just represent a potential association between two objects. The nature and function of that association is up to either side of the connection, as implement in their Port subclasses. That *could* be the traditional MemObject style of connection, but it could also be for Ethernet connections, Ruby connections, or TLM socket connections as implemented in these CLs, or interrupt source/sink, etc. That's not to say, of course, that it's always a preferrable substitute for setting objects as parameters in other objects. I haven't thought about it super deeply, but I think setting SimObjects as parameter values in other SimObjects reflects an ownership relationship, where a Port connection is more of a peer relationship and reflects an actual structural element of the simulation. Gabe On Thu, Mar 14, 2019 at 6:48 AM Jason Lowe-Power wrote: > Hey Gabe, > > I'll need to think about this a bit more myself, but do you think these > changes will increase the places we can use ports? Like Andreas was saying, > it would be nice to use it for things like interrupt routing, connecting > TLBs, and connecting all of the wavefronts in the GPU to the coalescer, > etc. These are a few places that I can think of trying to use ports where > it wasn't a great semantic before. > > Cheers, > Jason > > On Thu, Mar 14, 2019 at 6:12 AM Gabe Black wrote: > > > Great, I'm glad you're in favor of this. I have a new, hopefully more > final > > batch of patches incoming soon which also include application of the new > > mechanism to TLM sockets. > > > > Gabe > > > > On Thu, Mar 14, 2019 at 2:47 AM Andreas Sandberg < > andreas.sandb...@arm.com > > > > > wrote: > > > > > Hi Everyone, > > > > > > I remember talking to Andreas H about this many years ago. If I > remember > > > correctly, the main reason the patch wasn't committed at the time was > > > performance related. IIRC, the patch series had a ~10%-20% performance > > > hit. I suspect it the patch Jason pointed to isn't the main reason for > > > any performance issues though, it's more likely one of the subsequent > > > patches that added TLM-like 4-phase handshakes. > > > > > > I'm very much in favour of sorting out the ports vs protocol issue once > > > and for all. A generic port interface would be extremely useful for > > > interrupt routing which is currently very ad-hoc. > > > > > > Cheers, > > > Andreas > > > > > > On 07/03/2019 19:42, Steve Reinhardt wrote: > > > > Thanks for digging this up, Jason. I knew this issue had been > > addressed > > > > multiple times before (I think I even had a patch at one point that > > was a > > > > smaller change, but held it off in favor of Andreas's version). I > > don't > > > > know why Andreas's change was never committed either. > > > > > > > > Anyway, it will be good to see this cleaned up, regardless of whether > > we > > > go > > > > with Andreas's code or Gabe's proposal or some hybrid. I've been out > > of > > > > the loop long enough that I don't have a specific preference. > > > > > > > > Steve > > > > > > > > > > > > On Thu, Mar 7, 2019 at 10:19 AM Jason Lowe-Power < > ja...@lowepower.com> > > > > wrote: > > > > > > > >> Hey Gabe, > > > >> > > > >> I was digging through the old reviewboard and found this patch that > > also > > > >> re-did this interface: http://reviews.gem5.org/r/1301 > > > >> > > > >> I'm not sure why this was never committed. > > > >> > > > >> I believe Andreas H's goal was to enable TLM-2 interfaces with the > > gem5, > > > >> IIRC. > > > >> > > > >> Just something to consider. > > > >> > > > >> Cheers, > > > >> Jason > > > >> > > > >> On Thu, Mar 7, 2019 at 7:00 AM Gabe Black > > wrote: > > > >> > > > >>> Hey folks, specifically folks looking at this doc. I have a series > of > > > >>> patches which largely implement what I was going for, although it > > > turned > > > >>> out differently than what I have in my doc. I'll update the doc > > > soon(ish) > > > >>> to describe the current version. Go ahead and review the CLs if you > > > want, > > > >>> although I should probably run another test or two on them and the > > > >>> discussion of the design is still open over on the doc. > > > >>> > > > >>> > > > >>> > > > >> > > > > > > https://gem5-review.googlesource.com/q/topic:%22tlm%22+(status:open%20OR%20status:merged) > > > >>> Gabe > > > >>> > > > >>> On Wed, Mar 6, 2019 at 12:20 AM Gabe Black > > > wrote: > > > >>> > > > Hi folks. I've been looking at how to configure TLM sockets > through > > > >>> gem5's > > > port configuration mechanism and how gem5's port configuration > > > >> mechanism > > > works in general, and I think I've mostly come up with a plan. > I've > > > >>> written > > > everything up in a doc over here: > > > > > > > > > > > > >> > > > > > > https://docs.google.com/document/d/17eXkE9YtzvYXEgkHFNR1my_xYKl3mYNNtXM9pIAX-t0/edit?usp=sharing > > > Please take a look if you have a ch
Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5
I think gem5 would benefit from it for the same reason SystemC simulations do, namely speeding up simulations when doing fast forwarding (perhaps with a binary translating CPU... hypothetically...). It would also be very nice to enable software development for not-yet-existing hardware that has gem5 models available. Then gem5 users could do both software development and performance evaluation in parallel and only have to build models once. This is very nice when large bodies of software need to be written to support a bit of hardware, for instance if they have large complex drivers, need application level support, etc. It would also be great not to have to wait for hours for android to boot to get to the interesting part of a simulation or when debugging at a guest software level. Gabe On Thu, Mar 14, 2019 at 6:41 AM Dr. Matthias Jung wrote: > Hi Gabe, > > one of the main reasons for DMI is to speedup simulations, similar to the > temporal decoupling in TLM LT or debug transport in order to make the > boot-loading. AFAIK DMI is mainly used in virtual platforms that target > software development and not hardware architecture design space > explorations, because you skip interconnects, caches etc. In commercial > tools you can just switch on or switch off DMI and therefore you can have a > nice trade-off between speed and accuracy by using the same models. > > Since gem5 is mainly there for computer-system architecture research, I’m > not sure if the DMI feature is really required. From a TLM2 perspective, > even if a TLM target model included in gem5 offers DMI, the gem5 core model > (initiator) does not have to use it, right? Do you have any concrete use > case where you could exploit DMI? > > For KVM: maybe somebody with KVM experience should comment that. > > Best regards, > Matthias > > > Am 28.02.2019 um 06:13 schrieb Gabe Black : > > > > Hi folks. TLM is a communication protocol/mechanism built on top of > > systemc. It supports a mechanism called DMI which stands for direct > memory > > interface. The idea is that an entity sending a request into the system > can > > ask if the target can give it a pointer it can use to directly access > that > > memory in the future. The target, if it supports that sort of thing, > > returns a descriptor which describes a region of memory that can be > > accessed in that way. If that needs to be invalidated in the future, then > > there's another mechanism the target can use to communicate back to the > > sender telling it to throw away that descriptor. > > > > The way this mechanism is implemented in TLM is a bit less than ideal > since > > every request has a field that says whether the requester wants to know > > about DMI, and so the target has to perform an extra check on all the > > requests in case someone is asking when that's useful to communicate > only a > > very small fraction of the time, perhaps only once during an entire > > simulation. > > > > Aside from that though, this mechanism has some nice properties. First, > it > > avoids having to globally identify what a memory is or where it is for a > > particular simulation. A memory is just a thing on the other end of a > > request that may let you get at it directly if you ask nicely. Also, if > > there's something in the way that would get messed up if you skipped over > > it, say a cache, it can block those requests from getting through to > > targets. This could be useful for KVM for instance, when it's collecting > > regions to act as RAM for the virtual machine. > > > > I haven't fully figured out what a good way to avoid the check-every-time > > problem of the systemc mechanism, and ideally whatever I/we come up with > > will be compatible enough to be bridged effectively, but I'm thinking > some > > sort of explicit additional call like getAddrRanges which would propogate > > through the hierarchy at specific points, either to a specific address or > > as a broadcast. > > > > I know some folks have looked at gem5's memory system protocol and > > systemc's TLM before, for instance either to try making gem5 use TLM > > natively, or for the systemc TLM bridges. What do you think about adding > > this sort of mechainsm to gem5? Are there any pitfalls to avoid, known > > issues to figure out, suggested avenues to explore, etc? Please let me > > know. This is likely something I'm going to want to pursue in the next > few > > weeks. > > > > Gabe > > ___ > > gem5-dev mailing list > > gem5-dev@gem5.org > > http://m5sim.org/mailman/listinfo/gem5-dev > > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Correct cast of template parameter
Andrea Mondelli has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/17308 ) Change subject: arch-arm: Correct cast of template parameter .. arch-arm: Correct cast of template parameter Clang with -Wconstant-conversion is _very_ restrictive on casting. The shift operator results in an incorrect promotion. This patch add a compile-time static cast that remove the error when clang is used. Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 --- M src/arch/arm/isa/insts/sve.isa M src/base/bitfield.hh 2 files changed, 13 insertions(+), 5 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17308 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 Gerrit-Change-Number: 17308 Gerrit-PatchSet: 2 Gerrit-Owner: Andrea Mondelli Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arm: Correct cast of template parameter
Andrea Mondelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17308
Change subject: arm: Correct cast of template parameter
..
arm: Correct cast of template parameter
Clang with -Wconstant-conversion is _very_ restrictive on casting.
The shift operator results in an incorrect promotion.
This patch add a compile-time static cast that remove the error
when clang is used.
Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
---
M src/arch/arm/isa/insts/sve.isa
M src/base/bitfield.hh
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f..14395d8 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -4278,7 +4278,9 @@
bool negSrc1 = (srcElem1 < 0);
bool negSrc2 = (srcElem2 < 0);
if ((negDest != negSrc1) && (negSrc1 == negSrc2)) {
-destElem = (Element)1 << (sizeof(Element) * 8 - 1);
+destElem = static_cast(
+static_cast(1) << (sizeof(Element) * 8 - 1)
+);
if (negDest)
destElem -= 1;
}
@@ -4293,7 +4295,9 @@
bool negSrc = (srcElem1 < 0);
bool posCount = ((count * imm) >= 0);
if ((negDest != negSrc) && (negSrc == posCount)) {
-destElem = (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1);
+destElem = static_cast<%(dstType)s>(
+(%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
+);
if (negDest)
destElem -= 1;
}
@@ -4350,7 +4354,9 @@
bool negSrc = (srcElem1 < 0);
bool negCount = ((count * imm) < 0);
if ((negDest != negSrc) && (negSrc == negCount)) {
-destElem = (%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1);
+destElem = static_cast<%(dstType)s>(
+(%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
+);
if (negDest)
destElem -= 1;
}
@@ -4407,7 +4413,9 @@
bool negSrc1 = (srcElem1 < 0);
bool posSrc2 = (srcElem2 >= 0);
if ((negDest != negSrc1) && (negSrc1 == posSrc2)) {
-destElem = (Element)1 << (sizeof(Element) * 8 - 1);
+destElem = static_cast(
+static_cast(1) << (sizeof(Element) * 8 - 1)
+);
if (negDest)
destElem -= 1;
}
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index d696715..ec1ffce 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -182,7 +182,7 @@
assert(size <= sizeof(T));
T output = 0;
-for (auto byte = 0; byte < size; byte++, val >>= 8) {
+for (auto byte = 0; byte < size; byte++, val = static_cast(val >>
8)) {
output = (output << 8) | reverseLookUpTable[val & 0xFF];
}
--
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Gerrit-Branch: master
Gerrit-Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
Gerrit-Change-Number: 17308
Gerrit-PatchSet: 1
Gerrit-Owner: Andrea Mondelli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: python: Teach cxxMethod how to set return_value_policy.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17034 )
Change subject: python: Teach cxxMethod how to set return_value_policy.
..
python: Teach cxxMethod how to set return_value_policy.
This is passed through to the underlying call to PyBindMethod.
Change-Id: Ib46c55664ba0707464bb84e137a0fad817aea1bb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17034
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/python/m5/SimObject.py
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 7f19c07..97f6847 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -882,6 +882,7 @@
name = func.__name__
override = kwargs.get("override", False)
cxx_name = kwargs.get("cxx_name", name)
+return_value_policy = kwargs.get("return_value_policy", None)
args, varargs, keywords, defaults = inspect.getargspec(func)
if varargs or keywords:
@@ -906,7 +907,8 @@
return func(self, *args, **kwargs)
f = py_call if override else cxx_call
-f.__pybind = PyBindMethod(name, cxx_name=cxx_name, args=args)
+f.__pybind = PyBindMethod(name, cxx_name=cxx_name, args=args,
+ return_value_policy=return_value_policy)
return f
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib46c55664ba0707464bb84e137a0fad817aea1bb
Gerrit-Change-Number: 17034
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Weiping Liao
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: python: Teach PyBindMethod how to set return_value_policy.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17033 )
Change subject: python: Teach PyBindMethod how to set return_value_policy.
..
python: Teach PyBindMethod how to set return_value_policy.
Change-Id: Ia208e43672672556b36f905e8f71dce44b978d22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17033
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/python/m5/util/pybind.py
1 file changed, 9 insertions(+), 6 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/python/m5/util/pybind.py b/src/python/m5/util/pybind.py
index 4b5e03d..4664c16 100644
--- a/src/python/m5/util/pybind.py
+++ b/src/python/m5/util/pybind.py
@@ -58,10 +58,12 @@
code('.${export}("${{self.name}}", &${cname}::${{self.cxx_name}})')
class PyBindMethod(PyBindExport):
-def __init__(self, name, cxx_name=None, args=None):
+def __init__(self, name, cxx_name=None, args=None,
+ return_value_policy=None):
self.name = name
self.cxx_name = cxx_name if cxx_name else name
self.args = args
+self.return_value_policy = return_value_policy
def _conv_arg(self, value):
if isinstance(value, bool):
@@ -72,6 +74,10 @@
raise TypeError("Unsupported PyBind default value type")
def export(self, code, cname):
+arguments = [ '"${{self.name}}"', '&${cname}::${{self.cxx_name}}' ]
+if self.return_value_policy:
+arguments.append('pybind11::return_value_policy::'
+ '${{self.return_value_policy}}')
if self.args:
def get_arg_decl(arg):
if isinstance(arg, tuple):
@@ -81,8 +87,5 @@
else:
return 'py::arg("%s")' % arg
-code('.def("${{self.name}}", &${cname}::${{self.name}}, ')
-code('' + \
- ', '.join([ get_arg_decl(a) for a in self.args ]) + ')')
-else:
-code('.def("${{self.name}}", &${cname}::${{self.cxx_name}})')
+arguments.extend(list([ get_arg_decl(a) for a in self.args ]))
+code('.def(' + ', '.join(arguments) + ')')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia208e43672672556b36f905e8f71dce44b978d22
Gerrit-Change-Number: 17033
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Weiping Liao
Gerrit-MessageType: merged
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Re: [gem5-dev] ToT build failures for ARM
Hi Gabe,
thanks for pointing that out.
We have addressed the issues with the following patches:
https://gem5-review.googlesource.com/c/public/gem5/+/17288/1
https://gem5-review.googlesource.com/c/public/gem5/+/17289/1
Thanks
Giacomo
From: gem5-dev on behalf of Gabe Black
Sent: 14 March 2019 13:10
To: gem5 Developer List
Subject: [gem5-dev] ToT build failures for ARM
These look like issues exposed by compiler version and that (if that's what
they are) have known fixes. They should be easy to fix, but I'm going to
bed. If they haven't been fixed in the near future I'll send some patches.
Representative compiler errors below.
Gabe
In file included from
build/ARM/arch/arm/generated/generic_cpu_exec_6.cc:10:0:
build/ARM/arch/arm/generated/exec-ns.cc.inc: In member function 'Fault
ArmISAInst::SvePredBic<_Element>::execute(ExecContext*, Trace::InstRecord*)
const':
build/ARM/arch/arm/generated/exec-ns.cc.inc:220568:40: error: '~' on an
expression of type bool [-Werror=bool-operation]
destElem = srcElem1 & ~srcElem2;
^~~~
build/ARM/arch/arm/generated/exec-ns.cc.inc:220568:40: note: did you mean
to use logical not ('!')?
build/ARM/arch/arm/generated/exec-ns.cc.inc: In member function 'Fault
ArmISAInst::SvePredBics<_Element>::execute(ExecContext*,
Trace::InstRecord*) const':
build/ARM/arch/arm/generated/exec-ns.cc.inc:220634:40: error: '~' on an
expression of type bool [-Werror=bool-operation]
destElem = srcElem1 & ~srcElem2;
^~~~
In file included from build/ARM/arch/arm/generated/inst-constrs-3.cc:9:0:
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr
ArmISAInst::Aarch64::decodeSveInt(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73599:17: error: this
statement may fall through [-Werror=implicit-fallthrough=]
}
^
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73601:11: note: here
case 0x1:
^~~~
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73637:17: error: this
statement may fall through [-Werror=implicit-fallthrough=]
}
^
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73639:11: note: here
case 0x2:
^~~~
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix use of bitwise operators on booleans
Hello Javier,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/17288
to review the following change.
Change subject: arch-arm: Fix use of bitwise operators on booleans
..
arch-arm: Fix use of bitwise operators on booleans
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f..b1c351f 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3178,11 +3178,11 @@
sveBinInst('asrr', 'Asrr', 'SimdAluOp', unsignedTypes, asrrCode,
PredType.MERGE, True)
# BIC (vectors, predicated)
-bicCode = 'destElem = srcElem1 & ~srcElem2;'
+bicCode = 'destElem = srcElem1 && !srcElem2;'
sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
PredType.MERGE, True)
# BIC (vectors, unpredicated)
-bicCode = 'destElem = srcElem1 & ~srcElem2;'
+bicCode = 'destElem = srcElem1 && !srcElem2;'
sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
# BIC, BICS (predicates)
svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
--
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Gerrit-Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Gerrit-Change-Number: 17288
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Javier
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add missing fall-through defaults
Hello Javier,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/17289
to review the following change.
Change subject: arch-arm: Add missing fall-through defaults
..
arch-arm: Add missing fall-through defaults
Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/formats/sve_top_level.isa
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 3c5e01c..ff7e50e 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -118,6 +118,7 @@
return new Unknown64(machInst);
}
}
+break;
}
case 0x3:
{
@@ -532,6 +533,7 @@
return new SveIndexII(machInst,
zd, imm5, imm5b);
}
+break;
}
case 1:
{ // INDEX (scalar, immediate)
@@ -552,6 +554,7 @@
return new SveIndexRI(machInst,
zd, zn, imm5);
}
+break;
}
case 2:
{ // INDEX (immediate, scalar)
@@ -572,6 +575,7 @@
return new SveIndexIR(machInst,
zd, imm5, zm);
}
+break;
}
case 3:
{ // INDEX (scalars)
diff --git a/src/arch/arm/isa/formats/sve_top_level.isa
b/src/arch/arm/isa/formats/sve_top_level.isa
index f4f1ab5..b8e1d46 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -128,6 +128,7 @@
return decodeSveIntArithUnaryPred(machInst);
}
}
+break;
}
case 0x1:
{
@@ -166,6 +167,7 @@
case 0x3:
return decodeSveElemCount(machInst);
}
+break;
}
case 0x2:
if (bits(machInst, 20)) {
@@ -195,6 +197,7 @@
case 0x3:
return decodeSveSelVec(machInst);
}
+break;
}
case 0x4:
return decodeSveIntCmpVec(machInst);
@@ -279,6 +282,7 @@
case 0x3:
return decodeSveFpAccumReduc(machInst);
}
+break;
}
case 0x2:
return decodeSveFpArithPred(machInst);
@@ -286,6 +290,7 @@
return decodeSveFpUnaryPred(machInst);
}
}
+break;
}
case 0x3:
return decodeSveFpFusedMulAdd(machInst);
--
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Gerrit-Change-Number: 17289
Gerrit-PatchSet: 1
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Gerrit-Reviewer: Javier
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem: Removed circular include ref
Ryan Gambord has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17270
Change subject: mem: Removed circular include ref
..
mem: Removed circular include ref
If BasicLink.hh is modified, the style checker forces a reordering of
the includes, which results in build errors because it ends up including
Topology.hh before including its xxxParams.hh files, which include
forward declarations of the BasicLink family of classes, and so
Topology.hh throws errors that BasicLink etc. are not declared.
Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Signed-off-by: Ryan Gambord
---
M src/mem/ruby/network/BasicLink.hh
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/network/BasicLink.hh
b/src/mem/ruby/network/BasicLink.hh
index 39c2096..755e5c7 100644
--- a/src/mem/ruby/network/BasicLink.hh
+++ b/src/mem/ruby/network/BasicLink.hh
@@ -33,14 +33,15 @@
#include
#include
+#include "mem/ruby/network/BasicRouter.hh"
+#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "params/BasicExtLink.hh"
#include "params/BasicIntLink.hh"
#include "params/BasicLink.hh"
-#include "mem/ruby/network/BasicRouter.hh"
-#include "mem/ruby/network/Topology.hh"
-#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "sim/sim_object.hh"
+class Topology;
+
class BasicLink : public SimObject
{
public:
--
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Gerrit-Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397
Gerrit-Change-Number: 17270
Gerrit-PatchSet: 1
Gerrit-Owner: Ryan Gambord
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: misc: Removed inconsistency in BPRED* debug msgs
Hello Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17248 to look at the new patch set (#2). Change subject: misc: Removed inconsistency in BPRED* debug msgs .. misc: Removed inconsistency in BPRED* debug msgs Added consistency in the DEBUG message form, to allow a better parsing. Fixed sn/tid type parameter. Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b --- M src/arch/mips/isa.cc M src/cpu/o3/commit_impl.hh M src/cpu/o3/cpu.cc M src/cpu/o3/decode_impl.hh M src/cpu/o3/fetch_impl.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/inst_queue_impl.hh M src/cpu/o3/lsq_unit.hh M src/cpu/o3/lsq_unit_impl.hh M src/cpu/o3/mem_dep_unit_impl.hh M src/cpu/o3/rename_impl.hh M src/cpu/o3/rob_impl.hh M src/cpu/pred/bpred_unit.cc 13 files changed, 343 insertions(+), 279 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17248 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b Gerrit-Change-Number: 17248 Gerrit-PatchSet: 2 Gerrit-Owner: Andrea Mondelli Gerrit-Reviewer: Andrea Mondelli Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: misc: Removed inconsistency in BPRED* debug msgs
Andrea Mondelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17248
Change subject: misc: Removed inconsistency in BPRED* debug msgs
..
misc: Removed inconsistency in BPRED* debug msgs
- Added consistency in the DEBUG message form, to allow a better parsing
- Added SN number information to some DEBUG msg for tracing purpose
Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
---
M src/arch/mips/isa.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/indirect.cc
M src/cpu/pred/indirect.hh
12 files changed, 211 insertions(+), 175 deletions(-)
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 2711712..eaee294 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -450,7 +450,7 @@
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
-"[tid:%i]: Setting (direct set) CP0 Register:%u "
+"[tid:%i] Setting (direct set) CP0 Register:%u "
"Select:%u (%s) to %#x.\n",
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
@@ -463,7 +463,7 @@
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
-"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
+"[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
miscRegFile_WriteMask[misc_reg][reg_sel] = val;
}
@@ -479,7 +479,7 @@
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
-"[tid:%i]: Setting CP0 Register:%u "
+"[tid:%i] Setting CP0 Register:%u "
"Select:%u (%s) to %#x, with effect.\n",
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ec3d610..434f148 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -704,7 +704,7 @@
const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
-DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head
of"
+DPRINTF(Commit,"[tid:%i] Instruction [sn:%lli] PC %s is head
of"
" ROB and ready to commit\n",
tid, inst->seqNum, inst->pcState());
@@ -713,12 +713,12 @@
ppCommitStall->notify(inst);
-DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli]
PC "
+DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%lli]
PC "
"%s is head of ROB and not ready\n",
tid, inst->seqNum, inst->pcState());
}
-DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
+DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n",
tid, rob->countInsts(tid), rob->numFreeEntries(tid));
}
@@ -862,17 +862,18 @@
if (fromIEW->mispredictInst[tid]) {
DPRINTF(Commit,
-"[tid:%i]: Squashing due to branch mispred PC:%#x
[sn:%i]\n",
+"[tid:%i] Squashing due to branch mispred "
+"PC:%#x [sn:%i]\n",
tid,
fromIEW->mispredictInst[tid]->instAddr(),
fromIEW->squashedSeqNum[tid]);
} else {
DPRINTF(Commit,
-"[tid:%i]: Squashing due to order violation [sn:%i]\n",
+"[tid:%i] Squashing due to order violation [sn:%i]\n",
tid, fromIEW->squashedSeqNum[tid]);
}
-DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
+DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n",
tid,
fromIEW->pc[tid].nextInstAddr());
@@ -1364,7 +1365,7 @@
for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
assert(fromIEW->insts[inst_num]);
if (!fromIEW->insts[inst_num]->isSquashed()) {
-DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
+DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%lli] ready "
"within ROB.\n",
fromIEW->insts[inst_num]->threadNumber,
fromIEW->insts[inst_num]->pcState(),
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 965ab04..5c88c50 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -689,11 +689,11 @@
list::iterator isActive =
std::find(activeThreads.begin(), activeThreads.end(), tid);
-DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
+DP
[gem5-dev] Change in gem5/gem5[master]: cpu: Added namespace to O3 Cpu Model
Hello Anthony Gutierrez, Jason Lowe-Power, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16950 to look at the new patch set (#4). Change subject: cpu: Added namespace to O3 Cpu Model .. cpu: Added namespace to O3 Cpu Model The O3 cpu folder doesn't offer a namespace implementation like others model (i.e. Simple). This lack of a proper namespace creates a conflict if a new O3-like cpu model is added, preventing the reuse of typical O3-related keyword names for classes and structures. FUPool is renamed to O3FUPool according to the other o3 objects. Classes used as a parameter (params/*.hh) are defined out of the O3 namespace due to their global scope when created at compile time. Change-Id: I4a9ce60b94937fb8d8fe8d0b35d92819feb7037f --- M src/cpu/o3/O3CPU.py R src/cpu/o3/O3FUPool.py M src/cpu/o3/SConscript M src/cpu/o3/base_dyn_inst.cc M src/cpu/o3/checker.cc M src/cpu/o3/checker.hh M src/cpu/o3/comm.hh M src/cpu/o3/commit.cc M src/cpu/o3/commit.hh M src/cpu/o3/commit_impl.hh M src/cpu/o3/cpu.cc M src/cpu/o3/cpu.hh M src/cpu/o3/cpu_policy.hh M src/cpu/o3/decode.cc M src/cpu/o3/decode.hh M src/cpu/o3/decode_impl.hh M src/cpu/o3/dep_graph.hh M src/cpu/o3/deriv.hh M src/cpu/o3/dyn_inst.cc M src/cpu/o3/dyn_inst.hh M src/cpu/o3/dyn_inst_impl.hh M src/cpu/o3/fetch.cc M src/cpu/o3/fetch.hh M src/cpu/o3/fetch_impl.hh M src/cpu/o3/free_list.cc M src/cpu/o3/free_list.hh M src/cpu/o3/fu_pool.cc M src/cpu/o3/fu_pool.hh M src/cpu/o3/iew.cc M src/cpu/o3/iew.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/impl.hh M src/cpu/o3/inst_queue.cc M src/cpu/o3/inst_queue.hh M src/cpu/o3/inst_queue_impl.hh M src/cpu/o3/lsq.cc M src/cpu/o3/lsq.hh M src/cpu/o3/lsq_impl.hh M src/cpu/o3/lsq_unit.cc M src/cpu/o3/lsq_unit.hh M src/cpu/o3/lsq_unit_impl.hh M src/cpu/o3/mem_dep_unit.cc M src/cpu/o3/mem_dep_unit.hh M src/cpu/o3/mem_dep_unit_impl.hh M src/cpu/o3/probe/elastic_trace.cc M src/cpu/o3/probe/elastic_trace.hh M src/cpu/o3/probe/simple_trace.cc M src/cpu/o3/probe/simple_trace.hh M src/cpu/o3/regfile.cc M src/cpu/o3/regfile.hh M src/cpu/o3/rename.cc M src/cpu/o3/rename.hh M src/cpu/o3/rename_impl.hh M src/cpu/o3/rename_map.cc M src/cpu/o3/rename_map.hh M src/cpu/o3/rob.cc M src/cpu/o3/rob.hh M src/cpu/o3/rob_impl.hh M src/cpu/o3/scoreboard.cc M src/cpu/o3/scoreboard.hh M src/cpu/o3/store_set.cc M src/cpu/o3/store_set.hh M src/cpu/o3/thread_context.cc M src/cpu/o3/thread_context.hh M src/cpu/o3/thread_context_impl.hh M src/cpu/o3/thread_state.hh 66 files changed, 330 insertions(+), 56 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16950 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4a9ce60b94937fb8d8fe8d0b35d92819feb7037f Gerrit-Change-Number: 16950 Gerrit-PatchSet: 4 Gerrit-Owner: Andrea Mondelli Gerrit-Reviewer: Andrea Mondelli Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Andreas Sandberg Gerrit-CC: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Refactor of Physical Register implementation
Andrea Mondelli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16908 )
Change subject: cpu: Refactor of Physical Register implementation
..
cpu: Refactor of Physical Register implementation
The implementation of the PhyRegId class is shared between multiple
cpu models. The o3/misc.hh should only be included in o3 models.
This patch removes the dependencies between different model
implementations, allowing to add new O3-like CPU model.
Change-Id: Ibb812517043befe75c48fab3ce9605a0d272870b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16908
Reviewed-by: Anthony Gutierrez
Reviewed-by: Bradley Wang
Reviewed-by: Andreas Sandberg
Reviewed-by: Jason Lowe-Power
Maintainer: Andreas Sandberg
---
M src/cpu/base_dyn_inst.hh
M src/cpu/o3/comm.hh
M src/cpu/reg_class.hh
3 files changed, 99 insertions(+), 100 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Anthony Gutierrez: Looks good to me, approved
Bradley Wang: Looks good to me, approved
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 9a1ab06..f1c7829 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -61,7 +61,6 @@
#include "cpu/exetrace.hh"
#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
-#include "cpu/o3/comm.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index df518b1..e2fda99 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -52,105 +52,6 @@
#include "cpu/inst_seq.hh"
#include "sim/faults.hh"
-/** Physical register index type.
- * Although the Impl might be a better for this, but there are a few
classes
- * that need this typedef yet are not templated on the Impl.
- */
-using PhysRegIndex = short int;
-
-/** Physical register ID.
- * Like a register ID but physical. The inheritance is private because the
- * only relationship between this types is functional, and it is done to
- * prevent code replication. */
-class PhysRegId : private RegId {
- private:
-PhysRegIndex flatIdx;
-
- public:
-explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1) {}
-
-/** Scalar PhysRegId constructor. */
-explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
- PhysRegIndex _flatIdx)
-: RegId(_regClass, _regIdx), flatIdx(_flatIdx)
-{}
-
-/** Vector PhysRegId constructor (w/ elemIndex). */
-explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
- ElemIndex elem_idx, PhysRegIndex flat_idx)
-: RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx) { }
-
-/** Visible RegId methods */
-/** @{ */
-using RegId::index;
-using RegId::classValue;
-using RegId::isZeroReg;
-using RegId::className;
-using RegId::elemIndex;
- /** @} */
-/**
- * Explicit forward methods, to prevent comparisons of PhysRegId with
- * RegIds.
- */
-/** @{ */
-bool operator<(const PhysRegId& that) const {
-return RegId::operator<(that);
-}
-
-bool operator==(const PhysRegId& that) const {
-return RegId::operator==(that);
-}
-
-bool operator!=(const PhysRegId& that) const {
-return RegId::operator!=(that);
-}
-/** @} */
-
-/** @return true if it is an integer physical register. */
-bool isIntPhysReg() const { return isIntReg(); }
-
-/** @return true if it is a floating-point physical register. */
-bool isFloatPhysReg() const { return isFloatReg(); }
-
-/** @Return true if it is a condition-code physical register. */
-bool isCCPhysReg() const { return isCCReg(); }
-
-/** @Return true if it is a vector physical register. */
-bool isVectorPhysReg() const { return isVecReg(); }
-
-/** @Return true if it is a vector element physical register. */
-bool isVectorPhysElem() const { return isVecElem(); }
-
-/** @return true if it is a vector predicate physical register. */
-bool isVecPredPhysReg() const { return isVecPredReg(); }
-
-/** @Return true if it is a condition-code physical register. */
-bool isMiscPhysReg() const { return isMiscReg(); }
-
-/**
- * Returns true if this register is always associated to the same
- * architectural register.
- */
-bool isFixedMapping() const
-{
-return !isRenameable();
-}
-
-/** Flat index accessor */
-const PhysRegIndex& flatIndex() const { return flatIdx; }
-
-static PhysRegId elemId(const PhysRegId* vid, ElemIndex elem)
-{
-assert(vid->isVectorPhysReg());
-return PhysRegId(VecElemClass, vid->index(), elem);
-}
-};
-
-/** Constant pointer definition.
- * PhysRegIds only need to be created once and then we can just share
- * pointers */
-using PhysRegI
[gem5-dev] Change in gem5/gem5[master]: sim-se: remove mem proxy in ThreadContext
Brandon Potter has uploaded a new patch set (#14). ( https://gem5-review.googlesource.com/c/public/gem5/+/12305 ) Change subject: sim-se: remove mem proxy in ThreadContext .. sim-se: remove mem proxy in ThreadContext Many parts of the source code use a memory proxy reference to access the simulated memory space in Syscall Emulation Mode. However, it would be nice if all memory responsibilities were delegated to a single object rather than spread across many objects. This patch helps to consolidate the memory responsibilities inside the MemState class by removing the ThreadContext's memory proxy. Change-Id: Ic1a6c3017c412a24db91770396d0a9bde790421d --- M src/arch/alpha/faults.cc M src/arch/alpha/linux/process.cc M src/arch/alpha/process.cc M src/arch/alpha/process.hh M src/arch/arm/freebsd/process.cc M src/arch/arm/linux/process.cc M src/arch/arm/process.cc M src/arch/arm/remote_gdb.cc M src/arch/arm/tlb.cc M src/arch/generic/tlb.cc M src/arch/mips/linux/process.cc M src/arch/mips/process.cc M src/arch/mips/remote_gdb.cc M src/arch/mips/tlb.cc M src/arch/power/linux/process.cc M src/arch/power/process.cc M src/arch/power/remote_gdb.cc M src/arch/power/tlb.cc M src/arch/riscv/linux/process.cc M src/arch/riscv/process.cc M src/arch/riscv/process.hh M src/arch/riscv/remote_gdb.cc M src/arch/riscv/tlb.cc M src/arch/sparc/faults.cc M src/arch/sparc/linux/syscalls.cc M src/arch/sparc/process.cc M src/arch/sparc/process.hh M src/arch/sparc/remote_gdb.cc M src/arch/sparc/solaris/process.cc M src/arch/x86/linux/process.cc M src/arch/x86/process.cc M src/arch/x86/process.hh M src/arch/x86/pseudo_inst.cc M src/arch/x86/remote_gdb.cc M src/arch/x86/tlb.cc M src/base/remote_gdb.cc M src/cpu/checker/thread_context.hh M src/cpu/o3/thread_context.hh M src/cpu/thread_context.hh M src/cpu/thread_state.cc M src/cpu/thread_state.hh M src/gpu-compute/cl_driver.cc M src/gpu-compute/compute_unit.cc M src/gpu-compute/gpu_tlb.cc M src/gpu-compute/shader.cc M src/mem/se_translating_port_proxy.cc M src/mem/se_translating_port_proxy.hh M src/sim/SConscript M src/sim/faults.cc A src/sim/mem_state.cc M src/sim/mem_state.hh R src/sim/mem_state_impl.hh M src/sim/process.cc M src/sim/process.hh M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh 56 files changed, 1,292 insertions(+), 644 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12305 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic1a6c3017c412a24db91770396d0a9bde790421d Gerrit-Change-Number: 12305 Gerrit-PatchSet: 14 Gerrit-Owner: Brandon Potter Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: change syscall function signature
Hello Jason Lowe-Power, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/12299 to look at the new patch set (#14). Change subject: sim-se: change syscall function signature .. sim-se: change syscall function signature The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access. With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error. This patch removes the redundancy by forcing access through the ThreadContext field within each system call. Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c --- M src/arch/alpha/linux/process.cc M src/arch/arm/freebsd/process.cc M src/arch/arm/linux/process.cc M src/arch/mips/linux/process.cc M src/arch/power/linux/process.cc M src/arch/riscv/linux/process.cc M src/arch/sparc/linux/syscalls.cc M src/arch/sparc/solaris/process.cc M src/arch/x86/linux/process.cc M src/gpu-compute/cl_driver.cc M src/gpu-compute/cl_driver.hh M src/sim/emul_driver.hh M src/sim/process.cc M src/sim/syscall_desc.cc M src/sim/syscall_desc.hh M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh 17 files changed, 372 insertions(+), 383 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12299 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Gerrit-Change-Number: 12299 Gerrit-PatchSet: 14 Gerrit-Owner: Brandon Potter Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: add a faux-filesystem
Hello Anthony Gutierrez, Jason Lowe-Power, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/12119 to look at the new patch set (#15). Change subject: sim-se: add a faux-filesystem .. sim-se: add a faux-filesystem This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected. This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change). Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode. Change-Id: I90821b3b403168b904a662fa98b85def1628621c --- A configs/common/FileSystemConfig.py M configs/common/Options.py M configs/example/se.py M src/kern/linux/linux.cc M src/sim/Process.py A src/sim/RedirectPath.py M src/sim/SConscript M src/sim/System.py M src/sim/process.cc M src/sim/process.hh A src/sim/redirect_path.cc A src/sim/redirect_path.hh M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh M src/sim/system.cc M src/sim/system.hh 16 files changed, 585 insertions(+), 87 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12119 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I90821b3b403168b904a662fa98b85def1628621c Gerrit-Change-Number: 12119 Gerrit-PatchSet: 15 Gerrit-Owner: Brandon Potter Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Andreas Sandberg Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Port configuration overhaul
Hey Gabe, I'll need to think about this a bit more myself, but do you think these changes will increase the places we can use ports? Like Andreas was saying, it would be nice to use it for things like interrupt routing, connecting TLBs, and connecting all of the wavefronts in the GPU to the coalescer, etc. These are a few places that I can think of trying to use ports where it wasn't a great semantic before. Cheers, Jason On Thu, Mar 14, 2019 at 6:12 AM Gabe Black wrote: > Great, I'm glad you're in favor of this. I have a new, hopefully more final > batch of patches incoming soon which also include application of the new > mechanism to TLM sockets. > > Gabe > > On Thu, Mar 14, 2019 at 2:47 AM Andreas Sandberg > > wrote: > > > Hi Everyone, > > > > I remember talking to Andreas H about this many years ago. If I remember > > correctly, the main reason the patch wasn't committed at the time was > > performance related. IIRC, the patch series had a ~10%-20% performance > > hit. I suspect it the patch Jason pointed to isn't the main reason for > > any performance issues though, it's more likely one of the subsequent > > patches that added TLM-like 4-phase handshakes. > > > > I'm very much in favour of sorting out the ports vs protocol issue once > > and for all. A generic port interface would be extremely useful for > > interrupt routing which is currently very ad-hoc. > > > > Cheers, > > Andreas > > > > On 07/03/2019 19:42, Steve Reinhardt wrote: > > > Thanks for digging this up, Jason. I knew this issue had been > addressed > > > multiple times before (I think I even had a patch at one point that > was a > > > smaller change, but held it off in favor of Andreas's version). I > don't > > > know why Andreas's change was never committed either. > > > > > > Anyway, it will be good to see this cleaned up, regardless of whether > we > > go > > > with Andreas's code or Gabe's proposal or some hybrid. I've been out > of > > > the loop long enough that I don't have a specific preference. > > > > > > Steve > > > > > > > > > On Thu, Mar 7, 2019 at 10:19 AM Jason Lowe-Power > > > wrote: > > > > > >> Hey Gabe, > > >> > > >> I was digging through the old reviewboard and found this patch that > also > > >> re-did this interface: http://reviews.gem5.org/r/1301 > > >> > > >> I'm not sure why this was never committed. > > >> > > >> I believe Andreas H's goal was to enable TLM-2 interfaces with the > gem5, > > >> IIRC. > > >> > > >> Just something to consider. > > >> > > >> Cheers, > > >> Jason > > >> > > >> On Thu, Mar 7, 2019 at 7:00 AM Gabe Black > wrote: > > >> > > >>> Hey folks, specifically folks looking at this doc. I have a series of > > >>> patches which largely implement what I was going for, although it > > turned > > >>> out differently than what I have in my doc. I'll update the doc > > soon(ish) > > >>> to describe the current version. Go ahead and review the CLs if you > > want, > > >>> although I should probably run another test or two on them and the > > >>> discussion of the design is still open over on the doc. > > >>> > > >>> > > >>> > > >> > > > https://gem5-review.googlesource.com/q/topic:%22tlm%22+(status:open%20OR%20status:merged) > > >>> Gabe > > >>> > > >>> On Wed, Mar 6, 2019 at 12:20 AM Gabe Black > > wrote: > > >>> > > Hi folks. I've been looking at how to configure TLM sockets through > > >>> gem5's > > port configuration mechanism and how gem5's port configuration > > >> mechanism > > works in general, and I think I've mostly come up with a plan. I've > > >>> written > > everything up in a doc over here: > > > > > > > > >> > > > https://docs.google.com/document/d/17eXkE9YtzvYXEgkHFNR1my_xYKl3mYNNtXM9pIAX-t0/edit?usp=sharing > > Please take a look if you have a chance, and please comment on the > doc > > >> if > > you have any questions, concerns, etc. > > > > I created the doc on my personal account but wrote it from my work > > >>> account > > so it *should* be accessible and commentable by anyone with the > link. > > Please let me know if that's not the case. > > > > Gabe > > > > >>> ___ > > >>> gem5-dev mailing list > > >>> gem5-dev@gem5.org > > >>> http://m5sim.org/mailman/listinfo/gem5-dev > > >> ___ > > >> gem5-dev mailing list > > >> gem5-dev@gem5.org > > >> http://m5sim.org/mailman/listinfo/gem5-dev > > > ___ > > > gem5-dev mailing list > > > gem5-dev@gem5.org > > > http://m5sim.org/mailman/listinfo/gem5-dev > > IMPORTANT NOTICE: The contents of this email and any attachments are > > confidential and may also be privileged. If you are not the intended > > recipient, please notify the sender immediately and do not disclose the > > contents to any other person, use it for any purpose, or store or copy > the > > information in any medium. Thank you. > >
Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5
Hi Gabe, one of the main reasons for DMI is to speedup simulations, similar to the temporal decoupling in TLM LT or debug transport in order to make the boot-loading. AFAIK DMI is mainly used in virtual platforms that target software development and not hardware architecture design space explorations, because you skip interconnects, caches etc. In commercial tools you can just switch on or switch off DMI and therefore you can have a nice trade-off between speed and accuracy by using the same models. Since gem5 is mainly there for computer-system architecture research, I’m not sure if the DMI feature is really required. From a TLM2 perspective, even if a TLM target model included in gem5 offers DMI, the gem5 core model (initiator) does not have to use it, right? Do you have any concrete use case where you could exploit DMI? For KVM: maybe somebody with KVM experience should comment that. Best regards, Matthias > Am 28.02.2019 um 06:13 schrieb Gabe Black : > > Hi folks. TLM is a communication protocol/mechanism built on top of > systemc. It supports a mechanism called DMI which stands for direct memory > interface. The idea is that an entity sending a request into the system can > ask if the target can give it a pointer it can use to directly access that > memory in the future. The target, if it supports that sort of thing, > returns a descriptor which describes a region of memory that can be > accessed in that way. If that needs to be invalidated in the future, then > there's another mechanism the target can use to communicate back to the > sender telling it to throw away that descriptor. > > The way this mechanism is implemented in TLM is a bit less than ideal since > every request has a field that says whether the requester wants to know > about DMI, and so the target has to perform an extra check on all the > requests in case someone is asking when that's useful to communicate only a > very small fraction of the time, perhaps only once during an entire > simulation. > > Aside from that though, this mechanism has some nice properties. First, it > avoids having to globally identify what a memory is or where it is for a > particular simulation. A memory is just a thing on the other end of a > request that may let you get at it directly if you ask nicely. Also, if > there's something in the way that would get messed up if you skipped over > it, say a cache, it can block those requests from getting through to > targets. This could be useful for KVM for instance, when it's collecting > regions to act as RAM for the virtual machine. > > I haven't fully figured out what a good way to avoid the check-every-time > problem of the systemc mechanism, and ideally whatever I/we come up with > will be compatible enough to be bridged effectively, but I'm thinking some > sort of explicit additional call like getAddrRanges which would propogate > through the hierarchy at specific points, either to a specific address or > as a broadcast. > > I know some folks have looked at gem5's memory system protocol and > systemc's TLM before, for instance either to try making gem5 use TLM > natively, or for the systemc TLM bridges. What do you think about adding > this sort of mechainsm to gem5? Are there any pitfalls to avoid, known > issues to figure out, suggested avenues to explore, etc? Please let me > know. This is likely something I'm going to want to pursue in the next few > weeks. > > Gabe > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5
Bump again. On Fri, Mar 1, 2019 at 2:31 PM Gabe Black wrote: > Bump... > > On Wed, Feb 27, 2019 at 9:13 PM Gabe Black wrote: > >> Hi folks. TLM is a communication protocol/mechanism built on top of >> systemc. It supports a mechanism called DMI which stands for direct memory >> interface. The idea is that an entity sending a request into the system can >> ask if the target can give it a pointer it can use to directly access that >> memory in the future. The target, if it supports that sort of thing, >> returns a descriptor which describes a region of memory that can be >> accessed in that way. If that needs to be invalidated in the future, then >> there's another mechanism the target can use to communicate back to the >> sender telling it to throw away that descriptor. >> >> The way this mechanism is implemented in TLM is a bit less than ideal >> since every request has a field that says whether the requester wants to >> know about DMI, and so the target has to perform an extra check on all the >> requests in case someone is asking when that's useful to communicate only a >> very small fraction of the time, perhaps only once during an entire >> simulation. >> >> Aside from that though, this mechanism has some nice properties. First, >> it avoids having to globally identify what a memory is or where it is for a >> particular simulation. A memory is just a thing on the other end of a >> request that may let you get at it directly if you ask nicely. Also, if >> there's something in the way that would get messed up if you skipped over >> it, say a cache, it can block those requests from getting through to >> targets. This could be useful for KVM for instance, when it's collecting >> regions to act as RAM for the virtual machine. >> >> I haven't fully figured out what a good way to avoid the check-every-time >> problem of the systemc mechanism, and ideally whatever I/we come up with >> will be compatible enough to be bridged effectively, but I'm thinking some >> sort of explicit additional call like getAddrRanges which would propogate >> through the hierarchy at specific points, either to a specific address or >> as a broadcast. >> >> I know some folks have looked at gem5's memory system protocol and >> systemc's TLM before, for instance either to try making gem5 use TLM >> natively, or for the systemc TLM bridges. What do you think about adding >> this sort of mechainsm to gem5? Are there any pitfalls to avoid, known >> issues to figure out, suggested avenues to explore, etc? Please let me >> know. This is likely something I'm going to want to pursue in the next few >> weeks. >> >> Gabe >> > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual: FAILED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHAN
[gem5-dev] Change in gem5/gem5[master]: systemc: Delete extra code from src/systemc/tlm_bridge.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17233
Change subject: systemc: Delete extra code from src/systemc/tlm_bridge.
..
systemc: Delete extra code from src/systemc/tlm_bridge.
Much of the code in src/systemc/tlm_bridge has been absorbed into the
TLM/gem5 bridge SimObjects and is no longer needed and redundant with
the original version in util/.
Change-Id: I0fa7af67649987cf9f6fc5cd4783002dde2242ac
---
M src/systemc/tlm_bridge/SConscript
D src/systemc/tlm_bridge/master_transactor.cc
D src/systemc/tlm_bridge/master_transactor.hh
D src/systemc/tlm_bridge/sc_master_port.cc
D src/systemc/tlm_bridge/sc_master_port.hh
D src/systemc/tlm_bridge/sc_slave_port.cc
D src/systemc/tlm_bridge/sc_slave_port.hh
D src/systemc/tlm_bridge/sim_control_if.hh
D src/systemc/tlm_bridge/slave_transactor.cc
D src/systemc/tlm_bridge/slave_transactor.hh
10 files changed, 1 insertion(+), 1,451 deletions(-)
diff --git a/src/systemc/tlm_bridge/SConscript
b/src/systemc/tlm_bridge/SConscript
index df56fdf..4ec7b72 100644
--- a/src/systemc/tlm_bridge/SConscript
+++ b/src/systemc/tlm_bridge/SConscript
@@ -33,11 +33,6 @@
SimObject('TlmBridge.py')
Source('gem5_to_tlm.cc')
-Source('tlm_to_gem5.cc')
-
-Source('master_transactor.cc')
Source('sc_ext.cc')
-Source('sc_master_port.cc')
Source('sc_mm.cc')
-Source('sc_slave_port.cc')
-Source('slave_transactor.cc')
+Source('tlm_to_gem5.cc')
diff --git a/src/systemc/tlm_bridge/master_transactor.cc
b/src/systemc/tlm_bridge/master_transactor.cc
deleted file mode 100644
index 58651b0..000
--- a/src/systemc/tlm_bridge/master_transactor.cc
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright
notice,
- *this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *contributors may be used to endorse or promote products derived from
- *this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Christian Menard
- */
-
-#include "systemc/tlm_bridge/master_transactor.hh"
-
-#include "systemc/ext/utils/sc_report_handler.hh"
-#include "systemc/tlm_bridge/sc_master_port.hh"
-#include "systemc/tlm_bridge/sim_control_if.hh"
-
-namespace Gem5SystemC
-{
-
-Gem5MasterTransactor::Gem5MasterTransactor(sc_core::sc_module_name name,
- const std::string& portName)
-: sc_core::sc_module(name),
- socket(portName.c_str()),
- sim_control("sim_control"),
- portName(portName)
-{
-if (portName.empty()) {
-SC_REPORT_ERROR(name, "No port name specified!\n");
-}
-}
-
-void
-Gem5MasterTransactor::before_end_of_elaboration()
-{
-auto *port = sim_control->getMasterPort(portName);
-
-port->bindToTransactor(this);
-}
-
-} // namespace Gem5SystemC
diff --git a/src/systemc/tlm_bridge/master_transactor.hh
b/src/systemc/tlm_bridge/master_transactor.hh
deleted file mode 100644
index 5033684..000
--- a/src/systemc/tlm_bridge/master_transactor.hh
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright
notice,
- *this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions a
[gem5-dev] Change in gem5/gem5[master]: systemc: Hook up gem5_getPort to the gem5 getPort mechanism.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17229
Change subject: systemc: Hook up gem5_getPort to the gem5 getPort mechanism.
..
systemc: Hook up gem5_getPort to the gem5 getPort mechanism.
Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3
---
M src/systemc/core/SystemC.py
M src/systemc/core/sc_module.cc
M src/systemc/ext/core/sc_module.hh
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/systemc/core/SystemC.py b/src/systemc/core/SystemC.py
index 649d6d3..74b7cec 100644
--- a/src/systemc/core/SystemC.py
+++ b/src/systemc/core/SystemC.py
@@ -25,7 +25,7 @@
#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from m5.SimObject import SimObject, cxxMethod
# This class represents the systemc kernel. There should be exactly one in
the
# simulation. It receives gem5 SimObject lifecycle callbacks (init,
regStats,
@@ -62,6 +62,10 @@
cxx_class = 'sc_core::sc_module'
cxx_header = 'systemc/ext/core/sc_module.hh'
+@cxxMethod(return_value_policy="reference", cxx_name="gem5_getPort")
+def getPort(self, if_name, iex):
+return None
+
try:
import _m5
except:
diff --git a/src/systemc/core/sc_module.cc b/src/systemc/core/sc_module.cc
index fc98aa3..ba9c76a 100644
--- a/src/systemc/core/sc_module.cc
+++ b/src/systemc/core/sc_module.cc
@@ -31,6 +31,7 @@
#include
#include
+#include "base/logging.hh"
#include "systemc/core/event.hh"
#include "systemc/core/kernel.hh"
#include "systemc/core/module.hh"
@@ -114,6 +115,12 @@
const sc_bind_proxy SC_BIND_PROXY_NIL;
+::Port &
+sc_module::gem5_getPort(const std::string &if_name, int idx)
+{
+fatal("%s does not have any port named %s\n", name(), if_name);
+}
+
sc_module::~sc_module() { delete _gem5_module; }
void
diff --git a/src/systemc/ext/core/sc_module.hh
b/src/systemc/ext/core/sc_module.hh
index 0c8bd9f..24a1aea 100644
--- a/src/systemc/ext/core/sc_module.hh
+++ b/src/systemc/ext/core/sc_module.hh
@@ -30,6 +30,7 @@
#ifndef __SYSTEMC_CORE_EXT_SC_MODULE_HH__
#define __SYSTEMC_CORE_EXT_SC_MODULE_HH__
+#include
#include
#include "sc_object.hh"
@@ -58,6 +59,9 @@
} // namespace sc_gem5
+// Gem5 prototype
+class Port;
+
namespace sc_core
{
@@ -95,6 +99,10 @@
class sc_module : public sc_object
{
public:
+// Gem5 specific extensions
+virtual ::Port &gem5_getPort(const std::string &if_name, int idx=-1);
+
+ public:
friend class ::sc_gem5::Kernel;
friend class ::sc_gem5::Module;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17229
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3
Gerrit-Change-Number: 17229
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: systemc: Templatize the gem5/TLM bridge SimObjects.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17234
Change subject: systemc: Templatize the gem5/TLM bridge SimObjects.
..
systemc: Templatize the gem5/TLM bridge SimObjects.
The C++ side is templated, and there are python versions for each
(currently two) width of bridge supported.
Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655
---
M src/systemc/tlm_bridge/TlmBridge.py
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
5 files changed, 165 insertions(+), 69 deletions(-)
diff --git a/src/systemc/tlm_bridge/TlmBridge.py
b/src/systemc/tlm_bridge/TlmBridge.py
index d2dff86..dcc5452 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -29,9 +29,10 @@
from m5.params import *
from m5.proxy import *
-class Gem5ToTlmBridge(SystemC_ScModule):
-type = 'Gem5ToTlmBridge'
-cxx_class = 'sc_gem5::Gem5ToTlmBridge'
+class Gem5ToTlmBridgeBase(SystemC_ScModule):
+type = 'Gem5ToTlmBridgeBase'
+abstract = True
+cxx_class = 'sc_gem5::Gem5ToTlmBridgeBase'
cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
system = Param.System(Parent.any, "system")
@@ -41,12 +42,39 @@
addr_ranges = VectorParam.AddrRange([],
'Addresses served by this port\'s TLM side')
-class TlmToGem5Bridge(SystemC_ScModule):
-type = 'TlmToGem5Bridge'
-cxx_class = 'sc_gem5::TlmToGem5Bridge'
+class TlmToGem5BridgeBase(SystemC_ScModule):
+type = 'TlmToGem5BridgeBase'
+abstract = True
+cxx_class = 'sc_gem5::TlmToGem5BridgeBase'
cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
system = Param.System(Parent.any, "system")
gem5 = MasterPort('gem5 master port')
tlm = SlavePort('TLM target socket')
+
+
+class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
+type = 'Gem5ToTlmBridge32'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::Gem5ToTlmBridge<32>'
+cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+class Gem5ToTlmBridge64(Gem5ToTlmBridgeBase):
+type = 'Gem5ToTlmBridge64'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::Gem5ToTlmBridge<64>'
+cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+
+class TlmToGem5Bridge32(TlmToGem5BridgeBase):
+type = 'TlmToGem5Bridge32'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::TlmToGem5Bridge<32>'
+cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
+
+class TlmToGem5Bridge64(TlmToGem5BridgeBase):
+type = 'TlmToGem5Bridge64'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::TlmToGem5Bridge<64>'
+cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index 4f1f6e4..54cf1a3 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -63,6 +63,8 @@
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+#include "params/Gem5ToTlmBridge32.hh"
+#include "params/Gem5ToTlmBridge64.hh"
#include "sim/system.hh"
#include "systemc/tlm_bridge/sc_ext.hh"
#include "systemc/tlm_bridge/sc_mm.hh"
@@ -106,8 +108,10 @@
}
}
+template
void
-Gem5ToTlmBridge::pec(Gem5SystemC::PayloadEvent *pe,
+Gem5ToTlmBridge::pec(
+Gem5SystemC::PayloadEvent> *pe,
tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase)
{
sc_core::sc_time delay;
@@ -163,8 +167,9 @@
}
// Similar to TLM's blocking transport (LT)
+template
Tick
-Gem5ToTlmBridge::recvAtomic(PacketPtr packet)
+Gem5ToTlmBridge::recvAtomic(PacketPtr packet)
{
panic_if(packet->cacheResponding(),
"Should not see packets where cache is responding");
@@ -205,8 +210,9 @@
return delay.value();
}
+template
void
-Gem5ToTlmBridge::recvFunctionalSnoop(PacketPtr packet)
+Gem5ToTlmBridge::recvFunctionalSnoop(PacketPtr packet)
{
// Snooping should be implemented with tlm_dbg_transport.
SC_REPORT_FATAL("Gem5ToTlmBridge",
@@ -214,8 +220,9 @@
}
// Similar to TLM's non-blocking transport (AT).
+template
bool
-Gem5ToTlmBridge::recvTimingReq(PacketPtr packet)
+Gem5ToTlmBridge::recvTimingReq(PacketPtr packet)
{
panic_if(packet->cacheResponding(),
"Should not see packets where cache is responding");
@@ -309,8 +316,9 @@
return true;
}
+template
bool
-Gem5ToTlmBridge::recvTimingSnoopResp(PacketPtr packet)
+Gem5ToTlmBridge::recvTimingSnoopResp(PacketPtr packet)
{
// Snooping should be implemented with tlm_dbg_transport.
SC_REPORT_FATAL("Gem5ToTlmBridge",
@@ -318,14 +326,16 @@
return false;
}
+template
bool
-Gem5ToTlmBridge::tryTiming(PacketPtr packet)
+Gem5ToTlmBridge::tryTiming(PacketPtr packet)
{
panic("tryTiming(PacketPtr) isn't implement
[gem5-dev] Change in gem5/gem5[master]: systemc: Provide a utility Port TLM socket wrapper class.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17230
Change subject: systemc: Provide a utility Port TLM socket wrapper class.
..
systemc: Provide a utility Port TLM socket wrapper class.
This class should make it easy to attach TLM sockets into the gem5
python Port config mechanism.
Change-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3
---
A src/systemc/tlm_port_wrapper.hh
1 file changed, 124 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_port_wrapper.hh
b/src/systemc/tlm_port_wrapper.hh
new file mode 100644
index 000..0553a18
--- /dev/null
+++ b/src/systemc/tlm_port_wrapper.hh
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2018 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __SYSTEMC_TLM_PORT_WRAPPER_HH__
+#define __SYSTEMC_TLM_PORT_WRAPPER_HH__
+
+#include "base/logging.hh"
+#include "sim/port.hh"
+#include "systemc/ext/tlm_core/2/sockets/sockets.hh"
+
+namespace sc_gem5
+{
+
+template
+class TlmInitiatorWrapper;
+
+template
+class TlmTargetWrapper;
+
+template
+class TlmInitiatorWrapper : public ::Port
+{
+ public:
+typedef tlm::tlm_base_initiator_socket,
+tlm::tlm_bw_transport_if, N, POL>
+InitiatorSocket;
+typedef typename InitiatorSocket::base_target_socket_type TargetSocket;
+typedef TlmTargetWrapper TargetWrapper;
+
+InitiatorSocket &initiator() { return _initiator; }
+
+TlmInitiatorWrapper(
+InitiatorSocket &i, const std::string &_name, PortID _id) :
+Port(_name, _id), _initiator(i)
+{}
+
+void
+bind(::Port &peer) override
+{
+auto *target = dynamic_cast(&peer);
+fatal_if(!target, "Attempt to bind TLM initiator socket %s to "
+"incompatible port %s.", name(), peer.name());
+
+initiator().bind(target->target());
+}
+
+void
+unbind() override
+{
+panic("TLM sockets can't be unbound.");
+}
+
+ private:
+InitiatorSocket &_initiator;
+};
+
+template
+class TlmTargetWrapper : public ::Port
+{
+ public:
+typedef tlm::tlm_base_target_socket,
+tlm::tlm_bw_transport_if, N, POL>
+TargetSocket;
+
+TargetSocket &target() { return _target; }
+
+TlmTargetWrapper(TargetSocket &t, const std::string &_name, PortID
_id) :
+Port(_name, _id), _target(t)
+{}
+
+void
+bind(::Port &peer) override
+{
+// Ignore attempts to bind a target socket. The initiator will
+// handle it.
+}
+
+void
+unbind() override
+{
+panic("TLM sockets can't be unbound.");
+}
+
+ private:
+TargetSocket &_target;
+};
+
+} // namespace sc_gem5
+
+#endif //__SYSTEMC_TLM_PORT_WRAPPER_HH__
--
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Gerrit-Branch: master
Gerrit-Change-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3
Gerrit-Change-Number: 17230
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: systemc: Create unified gem5/TLM bridge SimObjects.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17232
Change subject: systemc: Create unified gem5/TLM bridge SimObjects.
..
systemc: Create unified gem5/TLM bridge SimObjects.
These objects expose a standard TLM initiator or target socket with
width 64, and a gem5 slave or master port. What goes in one type of
port comes out the other with the appropriate conversion applied.
Change-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf
---
M src/systemc/tlm_bridge/SConscript
A src/systemc/tlm_bridge/TlmBridge.py
A src/systemc/tlm_bridge/gem5_to_tlm.cc
A src/systemc/tlm_bridge/gem5_to_tlm.hh
A src/systemc/tlm_bridge/tlm_to_gem5.cc
A src/systemc/tlm_bridge/tlm_to_gem5.hh
6 files changed, 1,277 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_bridge/SConscript
b/src/systemc/tlm_bridge/SConscript
index 6d91436..df56fdf 100644
--- a/src/systemc/tlm_bridge/SConscript
+++ b/src/systemc/tlm_bridge/SConscript
@@ -30,6 +30,11 @@
if not env['USE_SYSTEMC']:
Return()
+SimObject('TlmBridge.py')
+
+Source('gem5_to_tlm.cc')
+Source('tlm_to_gem5.cc')
+
Source('master_transactor.cc')
Source('sc_ext.cc')
Source('sc_master_port.cc')
diff --git a/src/systemc/tlm_bridge/TlmBridge.py
b/src/systemc/tlm_bridge/TlmBridge.py
new file mode 100644
index 000..d2dff86
--- /dev/null
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -0,0 +1,52 @@
+# Copyright 2019 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.objects.SystemC import SystemC_ScModule
+from m5.params import *
+from m5.proxy import *
+
+class Gem5ToTlmBridge(SystemC_ScModule):
+type = 'Gem5ToTlmBridge'
+cxx_class = 'sc_gem5::Gem5ToTlmBridge'
+cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+system = Param.System(Parent.any, "system")
+
+gem5 = SlavePort('gem5 slave port')
+tlm = MasterPort('TLM initiator socket')
+addr_ranges = VectorParam.AddrRange([],
+'Addresses served by this port\'s TLM side')
+
+class TlmToGem5Bridge(SystemC_ScModule):
+type = 'TlmToGem5Bridge'
+cxx_class = 'sc_gem5::TlmToGem5Bridge'
+cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
+
+system = Param.System(Parent.any, "system")
+
+gem5 = MasterPort('gem5 master port')
+tlm = SlavePort('TLM target socket')
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
new file mode 100644
index 000..4f1f6e4
--- /dev/null
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2019 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERC
[gem5-dev] Change in gem5/gem5[master]: python: Improve how templated SimObject classes are handled.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17228
Change subject: python: Improve how templated SimObject classes are handled.
..
python: Improve how templated SimObject classes are handled.
When setting up a SimObject's Param structure, gem5 will autogenerate
a header file which attempts to declare the SimObject's C++ type. It
has had at least some level of sophistication there where it would
pull off the namespaces ahead of the class name and handle them
properly, but it didn't know how to handle templates.
This change improves that handling in two ways. First, it adds a new
magical SimObject attribute called 'cxx_template_params' which is used
to specify what the template parameters are as a list. For instance, if
your SimObject was a template which took an integer constant as its
first parameter and a type as its second, this attribute could look
like the following:
cxx_template_params = [ 'int FOO', 'class Bar' ]
Importantly, if there are any default values for these template
parameters, they should *not* be included here, they should be
specified where the class is later defined.
The second new mechanism is to add an internal CxxClass in the
SimObject.cxx_param_decl method. This class accepts the class signature
in the cxx_class attribute and the cxx_template_params and does two
things. First, it strips off namespaces like in the old implementation.
Second, it extracts and processes any template arguments attached to
the class. If these are constants (as determined by the contents of
cxx_template_params), then they are stored verbatim. If they're types,
then they're recursively expanded into a CxxClass and stored that way.
Note that these are the *values* of the template arguments, where as
cxx_template_params lists the *types* and *names* of those arguments.
In our earlier example, if cxx_class was:
cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>'
Then CxxClass would extract the namespace 'CoolClasses', the class
name 'ClassName', the argument '12', and the argument 'Fruit::Apple'.
That second argument would be expanded into a CxxClass with the
namespace 'Fruit' and the class name 'Apple'.
Importantly here, because there were no default arguments given in
cxx_template_params, all "hidden" arguments which would fall through
to their defaults need to be fully specified in cxx_class.
The CxxClass has a method called declare() which uses the information
extracted earlier to output all of the "stuff" necessary for declaring
the given class, including opening any containing namespaces and
putting template<...> ahead of the actual class declaration with the
template parameters specified.
If any of the template arguments are themselves CxxClass instances,
then they'll be recursively declared immediately before the current
class is.
An alternative solution to this problem might be to include the header
file which actually defines the cxx_class type to avoid having to
come up with a declaration. Unfortunately this doesn't work since it
can set up include loops where the SimObject C++ header file includes
the param header to get access to the Param type, but that includes
the C++ header to get access to the SimObject type.
This also makes it harder for SimObjects to refer to each other, since
they rely on the declaration in the params header files when declaring
a member pointer to that type in their own Param structures.
Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1
---
M src/python/m5/SimObject.py
1 file changed, 71 insertions(+), 7 deletions(-)
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 7f19c07..9489a40 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -415,6 +415,7 @@
'cxx_extra_bases' : list,
'cxx_exports' : list,
'cxx_param_exports' : list,
+'cxx_template_params' : list,
}
# Attributes that can be set any time
keywords = { 'check' : FunctionType }
@@ -454,6 +455,8 @@
value_dict['cxx_exports'] += cxx_exports
if 'cxx_param_exports' not in value_dict:
value_dict['cxx_param_exports'] = []
+if 'cxx_template_params' not in value_dict:
+value_dict['cxx_template_params'] = []
cls_dict['_value_dict'] = value_dict
cls = super(MetaSimObject, mcls).__new__(mcls, name, bases,
cls_dict)
if 'type' in value_dict:
@@ -790,7 +793,70 @@
print(params)
raise
-class_path = cls._value_dict['cxx_class'].split('::')
+class CxxClass(object):
+def __init__(self, sig, template_params=[]):
+# Split the signature into its constituent parts. This
could
+# potentially be done with regular expressions, but
+# it's simple enough to pick appart a class signature
+# manua
[gem5-dev] Change in gem5/gem5[master]: python: Switch to the new getPort mechanism to connect ports.
Hello Jason Lowe-Power, Nikos Nikoleris, Weiping Liao, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17039 to look at the new patch set (#2). Change subject: python: Switch to the new getPort mechanism to connect ports. .. python: Switch to the new getPort mechanism to connect ports. This retrieves ports using the getPort method, and connects them using the bind method on the ports themselves. Any smarts as far as what type of peers are allowed to connect or how they connect is left up to the individual bind methods. Change-Id: Ic640d1fce8af1bed46e5830edc4a8a0f9d66 --- M src/python/m5/params.py 1 file changed, 3 insertions(+), 21 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17039 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic640d1fce8af1bed46e5830edc4a8a0f9d66 Gerrit-Change-Number: 17039 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Weiping Liao Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tlm: Initial import of tlm/gem5 bridge code.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17231
Change subject: tlm: Initial import of tlm/gem5 bridge code.
..
tlm: Initial import of tlm/gem5 bridge code.
This is a slightly mangled version of the existing bridge code in
util/tlm/src/. The changes fix some small style issues, change to gem5
specific include paths, and removes the Gem5SimControl code. That code
coordinates gem5 with the external systemc kernel, and in this usage
there's no external kernel.
The code imported here compiles, but it isn't yet expected to work.
Change-Id: I9c593a52e2554534720d21cd31a03e543ad897ad
---
A src/systemc/tlm_bridge/SConscript
A src/systemc/tlm_bridge/master_transactor.cc
A src/systemc/tlm_bridge/master_transactor.hh
A src/systemc/tlm_bridge/sc_ext.cc
A src/systemc/tlm_bridge/sc_ext.hh
A src/systemc/tlm_bridge/sc_master_port.cc
A src/systemc/tlm_bridge/sc_master_port.hh
A src/systemc/tlm_bridge/sc_mm.cc
A src/systemc/tlm_bridge/sc_mm.hh
A src/systemc/tlm_bridge/sc_peq.hh
A src/systemc/tlm_bridge/sc_slave_port.cc
A src/systemc/tlm_bridge/sc_slave_port.hh
A src/systemc/tlm_bridge/sim_control_if.hh
A src/systemc/tlm_bridge/slave_transactor.cc
A src/systemc/tlm_bridge/slave_transactor.hh
15 files changed, 1,878 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_bridge/SConscript
b/src/systemc/tlm_bridge/SConscript
new file mode 100644
index 000..6d91436
--- /dev/null
+++ b/src/systemc/tlm_bridge/SConscript
@@ -0,0 +1,38 @@
+# Copyright 2018 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+Import('*')
+
+if not env['USE_SYSTEMC']:
+Return()
+
+Source('master_transactor.cc')
+Source('sc_ext.cc')
+Source('sc_master_port.cc')
+Source('sc_mm.cc')
+Source('sc_slave_port.cc')
+Source('slave_transactor.cc')
diff --git a/src/systemc/tlm_bridge/master_transactor.cc
b/src/systemc/tlm_bridge/master_transactor.cc
new file mode 100644
index 000..58651b0
--- /dev/null
+++ b/src/systemc/tlm_bridge/master_transactor.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
notice,
+ *this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *contributors may be used to endorse or promote products derived from
+ *this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER C
Re: [gem5-dev] Port configuration overhaul
Great, I'm glad you're in favor of this. I have a new, hopefully more final batch of patches incoming soon which also include application of the new mechanism to TLM sockets. Gabe On Thu, Mar 14, 2019 at 2:47 AM Andreas Sandberg wrote: > Hi Everyone, > > I remember talking to Andreas H about this many years ago. If I remember > correctly, the main reason the patch wasn't committed at the time was > performance related. IIRC, the patch series had a ~10%-20% performance > hit. I suspect it the patch Jason pointed to isn't the main reason for > any performance issues though, it's more likely one of the subsequent > patches that added TLM-like 4-phase handshakes. > > I'm very much in favour of sorting out the ports vs protocol issue once > and for all. A generic port interface would be extremely useful for > interrupt routing which is currently very ad-hoc. > > Cheers, > Andreas > > On 07/03/2019 19:42, Steve Reinhardt wrote: > > Thanks for digging this up, Jason. I knew this issue had been addressed > > multiple times before (I think I even had a patch at one point that was a > > smaller change, but held it off in favor of Andreas's version). I don't > > know why Andreas's change was never committed either. > > > > Anyway, it will be good to see this cleaned up, regardless of whether we > go > > with Andreas's code or Gabe's proposal or some hybrid. I've been out of > > the loop long enough that I don't have a specific preference. > > > > Steve > > > > > > On Thu, Mar 7, 2019 at 10:19 AM Jason Lowe-Power > > wrote: > > > >> Hey Gabe, > >> > >> I was digging through the old reviewboard and found this patch that also > >> re-did this interface: http://reviews.gem5.org/r/1301 > >> > >> I'm not sure why this was never committed. > >> > >> I believe Andreas H's goal was to enable TLM-2 interfaces with the gem5, > >> IIRC. > >> > >> Just something to consider. > >> > >> Cheers, > >> Jason > >> > >> On Thu, Mar 7, 2019 at 7:00 AM Gabe Black wrote: > >> > >>> Hey folks, specifically folks looking at this doc. I have a series of > >>> patches which largely implement what I was going for, although it > turned > >>> out differently than what I have in my doc. I'll update the doc > soon(ish) > >>> to describe the current version. Go ahead and review the CLs if you > want, > >>> although I should probably run another test or two on them and the > >>> discussion of the design is still open over on the doc. > >>> > >>> > >>> > >> > https://gem5-review.googlesource.com/q/topic:%22tlm%22+(status:open%20OR%20status:merged) > >>> Gabe > >>> > >>> On Wed, Mar 6, 2019 at 12:20 AM Gabe Black > wrote: > >>> > Hi folks. I've been looking at how to configure TLM sockets through > >>> gem5's > port configuration mechanism and how gem5's port configuration > >> mechanism > works in general, and I think I've mostly come up with a plan. I've > >>> written > everything up in a doc over here: > > > > >> > https://docs.google.com/document/d/17eXkE9YtzvYXEgkHFNR1my_xYKl3mYNNtXM9pIAX-t0/edit?usp=sharing > Please take a look if you have a chance, and please comment on the doc > >> if > you have any questions, concerns, etc. > > I created the doc on my personal account but wrote it from my work > >>> account > so it *should* be accessible and commentable by anyone with the link. > Please let me know if that's not the case. > > Gabe > > >>> ___ > >>> gem5-dev mailing list > >>> gem5-dev@gem5.org > >>> http://m5sim.org/mailman/listinfo/gem5-dev > >> ___ > >> gem5-dev mailing list > >> gem5-dev@gem5.org > >> http://m5sim.org/mailman/listinfo/gem5-dev > > ___ > > gem5-dev mailing list > > gem5-dev@gem5.org > > http://m5sim.org/mailman/listinfo/gem5-dev > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] ToT build failures for ARM
These look like issues exposed by compiler version and that (if that's what
they are) have known fixes. They should be easy to fix, but I'm going to
bed. If they haven't been fixed in the near future I'll send some patches.
Representative compiler errors below.
Gabe
In file included from
build/ARM/arch/arm/generated/generic_cpu_exec_6.cc:10:0:
build/ARM/arch/arm/generated/exec-ns.cc.inc: In member function 'Fault
ArmISAInst::SvePredBic<_Element>::execute(ExecContext*, Trace::InstRecord*)
const':
build/ARM/arch/arm/generated/exec-ns.cc.inc:220568:40: error: '~' on an
expression of type bool [-Werror=bool-operation]
destElem = srcElem1 & ~srcElem2;
^~~~
build/ARM/arch/arm/generated/exec-ns.cc.inc:220568:40: note: did you mean
to use logical not ('!')?
build/ARM/arch/arm/generated/exec-ns.cc.inc: In member function 'Fault
ArmISAInst::SvePredBics<_Element>::execute(ExecContext*,
Trace::InstRecord*) const':
build/ARM/arch/arm/generated/exec-ns.cc.inc:220634:40: error: '~' on an
expression of type bool [-Werror=bool-operation]
destElem = srcElem1 & ~srcElem2;
^~~~
In file included from build/ARM/arch/arm/generated/inst-constrs-3.cc:9:0:
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr
ArmISAInst::Aarch64::decodeSveInt(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73599:17: error: this
statement may fall through [-Werror=implicit-fallthrough=]
}
^
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73601:11: note: here
case 0x1:
^~~~
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73637:17: error: this
statement may fall through [-Werror=implicit-fallthrough=]
}
^
build/ARM/arch/arm/generated/decoder-ns.cc.inc:73639:11: note: here
case 0x2:
^~~~
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[gem5-dev] Change in gem5/gem5[master]: python: Fix unknown params and proxy multiplication
Daniel Carvalho has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/17048 ) Change subject: python: Fix unknown params and proxy multiplication .. python: Fix unknown params and proxy multiplication One of the recent changes made params not visible anymore: NameError: global name 'params' is not defined This is fixed by adding the proper import statement. However, the second error makes the multiplication values be assigned to other proxies (that are not even used on the multiplication). A workaround is added to prevent this from happening by extending "*=". Change-Id: I3ad276a456efff62058672d16caac2b3ad1b326b Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17048 Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power Reviewed-by: Nikos Nikoleris Maintainer: Andreas Sandberg --- M src/python/m5/proxy.py 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved Andreas Sandberg: Looks good to me, approved; Looks good to me, approved Nikos Nikoleris: Looks good to me, approved diff --git a/src/python/m5/proxy.py b/src/python/m5/proxy.py index d289545..8632196 100644 --- a/src/python/m5/proxy.py +++ b/src/python/m5/proxy.py @@ -87,6 +87,7 @@ __rmul__ = __mul__ def _mulcheck(self, result, base): +from . import params for multiplier in self._multipliers: if isproxy(multiplier): multiplier = multiplier.unproxy(base) @@ -96,7 +97,7 @@ raise TypeError( "Proxy multiplier must be a numerical param") multiplier = multiplier.getValue() -result *= multiplier +result = result * multiplier return result def unproxy(self, base): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17048 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I3ad276a456efff62058672d16caac2b3ad1b326b Gerrit-Change-Number: 17048 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Carvalho Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 ) Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/op_class.hh M src/cpu/simple_thread.cc A util/cpt_upgraders/arm-sve.py 46 files changed, 11,605 insertions(+), 61 deletions(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 18 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Daniel Carvalho Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Port configuration overhaul
Hi Everyone, I remember talking to Andreas H about this many years ago. If I remember correctly, the main reason the patch wasn't committed at the time was performance related. IIRC, the patch series had a ~10%-20% performance hit. I suspect it the patch Jason pointed to isn't the main reason for any performance issues though, it's more likely one of the subsequent patches that added TLM-like 4-phase handshakes. I'm very much in favour of sorting out the ports vs protocol issue once and for all. A generic port interface would be extremely useful for interrupt routing which is currently very ad-hoc. Cheers, Andreas On 07/03/2019 19:42, Steve Reinhardt wrote: > Thanks for digging this up, Jason. I knew this issue had been addressed > multiple times before (I think I even had a patch at one point that was a > smaller change, but held it off in favor of Andreas's version). I don't > know why Andreas's change was never committed either. > > Anyway, it will be good to see this cleaned up, regardless of whether we go > with Andreas's code or Gabe's proposal or some hybrid. I've been out of > the loop long enough that I don't have a specific preference. > > Steve > > > On Thu, Mar 7, 2019 at 10:19 AM Jason Lowe-Power > wrote: > >> Hey Gabe, >> >> I was digging through the old reviewboard and found this patch that also >> re-did this interface: http://reviews.gem5.org/r/1301 >> >> I'm not sure why this was never committed. >> >> I believe Andreas H's goal was to enable TLM-2 interfaces with the gem5, >> IIRC. >> >> Just something to consider. >> >> Cheers, >> Jason >> >> On Thu, Mar 7, 2019 at 7:00 AM Gabe Black wrote: >> >>> Hey folks, specifically folks looking at this doc. I have a series of >>> patches which largely implement what I was going for, although it turned >>> out differently than what I have in my doc. I'll update the doc soon(ish) >>> to describe the current version. Go ahead and review the CLs if you want, >>> although I should probably run another test or two on them and the >>> discussion of the design is still open over on the doc. >>> >>> >>> >> https://gem5-review.googlesource.com/q/topic:%22tlm%22+(status:open%20OR%20status:merged) >>> Gabe >>> >>> On Wed, Mar 6, 2019 at 12:20 AM Gabe Black wrote: >>> Hi folks. I've been looking at how to configure TLM sockets through >>> gem5's port configuration mechanism and how gem5's port configuration >> mechanism works in general, and I think I've mostly come up with a plan. I've >>> written everything up in a doc over here: >> https://docs.google.com/document/d/17eXkE9YtzvYXEgkHFNR1my_xYKl3mYNNtXM9pIAX-t0/edit?usp=sharing Please take a look if you have a chance, and please comment on the doc >> if you have any questions, concerns, etc. I created the doc on my personal account but wrote it from my work >>> account so it *should* be accessible and commentable by anyone with the link. Please let me know if that's not the case. Gabe >>> ___ >>> gem5-dev mailing list >>> gem5-dev@gem5.org >>> http://m5sim.org/mailman/listinfo/gem5-dev >> ___ >> gem5-dev mailing list >> gem5-dev@gem5.org >> http://m5sim.org/mailman/listinfo/gem5-dev > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
