[gem5-dev] Jenkins build is back to normal : weekly #13

2021-11-30 Thread jenkins-no-reply--- via gem5-dev 
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[gem5-dev] Change in gem5/gem5[develop]: misc: Stop including arch/pcstate.hh.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52067 )


 (

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: misc: Stop including arch/pcstate.hh.
..

misc: Stop including arch/pcstate.hh.

Change-Id: Ic9ea62ae9c59fd838175fd6af4c075101d46a0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52067
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Daniel Carvalho 
---
M src/cpu/o3/decode.cc
M src/cpu/pred/bpred_unit.cc
M src/cpu/simple_thread.hh
M src/cpu/checker/cpu.hh
M src/cpu/pred/indirect.hh
M src/cpu/thread_context.hh
M src/cpu/nop_static_inst.cc
M src/cpu/o3/cpu.hh
M src/cpu/inst_pb_trace.hh
M src/arch/power/remote_gdb.cc
M src/arch/sparc/nativetrace.cc
M src/arch/x86/nativetrace.cc
M src/cpu/o3/comm.hh
M src/cpu/checker/thread_context.hh
M src/cpu/pred/btb.hh
M src/base/remote_gdb.hh
M src/dev/arm/css/scmi_platform.hh
17 files changed, 30 insertions(+), 14 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index 702439d..5955253 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -142,6 +142,7 @@
 #include "arch/power/gdb-xml/gdb_xml_power_fpu.hh"
 #include "arch/power/gdb-xml/gdb_xml_powerpc_32.hh"
 #include "arch/power/gdb-xml/gdb_xml_powerpc_64.hh"
+#include "arch/power/pcstate.hh"
 #include "arch/power/regs/misc.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index 0179fe4..ff2b8f1 100644
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -28,6 +28,7 @@

 #include "arch/sparc/nativetrace.hh"

+#include "arch/sparc/pcstate.hh"
 #include "arch/sparc/regs/int.hh"
 #include "cpu/thread_context.hh"
 #include "params/SparcNativeTrace.hh"
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index abb1a32..697fb18 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -28,6 +28,7 @@

 #include "arch/x86/nativetrace.hh"

+#include "arch/x86/pcstate.hh"
 #include "arch/x86/regs/float.hh"
 #include "arch/x86/regs/int.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 2248d71..59bccc5 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -50,7 +50,7 @@
 #include 
 #include 

-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/cprintf.hh"
 #include "base/pollevent.hh"
 #include "base/socket.hh"
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index eb0978f..b76c034 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -46,7 +46,7 @@
 #include 
 #include 

-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/statistics.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index 115fd1d..9e6c812 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -42,7 +42,7 @@
 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
 #define __CPU_CHECKER_THREAD_CONTEXT_HH__

-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/simple_thread.hh"
diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh
index cfcd47e..ee0ed64 100644
--- a/src/cpu/inst_pb_trace.hh
+++ b/src/cpu/inst_pb_trace.hh
@@ -38,7 +38,7 @@
 #ifndef __CPU_INST_PB_TRACE_HH__
 #define __CPU_INST_PB_TRACE_HH__

-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/static_inst_fwd.hh"
diff --git a/src/cpu/nop_static_inst.cc b/src/cpu/nop_static_inst.cc
index aa34481..4b73aa0 100644
--- a/src/cpu/nop_static_inst.cc
+++ b/src/cpu/nop_static_inst.cc
@@ -28,8 +28,7 @@

 #include "cpu/nop_static_inst.hh"

-#include "arch/pcstate.hh"
-#include "config/the_isa.hh"
+#include "arch/generic/pcstate.hh"
 #include "cpu/static_inst.hh"

 namespace gem5
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index b2da358..f2c6e60 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -44,7 +44,7 @@

 #include 

-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/inst_seq.hh"
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index ebbfd9a..670b92f 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -49,7 +49,7 @@
 #include 
 #include 

-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"

[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Fix a bug in SparcNativeTrace::check.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53363 )


Change subject: arch-sparc: Fix a bug in SparcNativeTrace::check.
..

arch-sparc: Fix a bug in SparcNativeTrace::check.

This method is responsible for comparing gem5's state against the state
of the real process. When checking the value of NPC, it accessed the
value of nnpc() by calling pc.nnpc(), but did not actually update regVal
with it, so the comparison was between the value from the real process
and npc().

It's mildly confusing that nnpc is compared against npc, and npc against
pc, but that's because of what the state looks like in the real process
when single stepping through it with ptrace.

You can actually see where this bug was introduced if you look at the
change which created the PCState types originally. There, you can see
how regVal was set using a method of the ThreadContext, but after that
change the value is only accessed and not actually used.

Change-Id: I0f0101db5f807640b8d25fef6448081d9cfa0213
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53363
Reviewed-by: Daniel Carvalho 
Reviewed-by: Boris Shingarov 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/sparc/nativetrace.cc
1 file changed, 30 insertions(+), 1 deletion(-)

Approvals:
  Boris Shingarov: Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index ff2b8f1..f10d0ad 100644
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -79,7 +79,7 @@
 // NPC
 read(, sizeof(realRegVal));
 realRegVal = betoh(realRegVal);
-pc.nnpc();
+regVal = pc.nnpc();
 checkReg("npc", regVal, realRegVal);

 // CCR

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0f0101db5f807640b8d25fef6448081d9cfa0213
Gerrit-Change-Number: 53363
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Remove the pcstate.hh switching header file.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52068 )


 (

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch: Remove the pcstate.hh switching header file.
..

arch: Remove the pcstate.hh switching header file.

Change-Id: I8c9cf0ec0c867b76ee8dd8f83b1d2d0835ecb3af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52068
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Daniel Carvalho 
---
M src/arch/SConscript
1 file changed, 13 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/SConscript b/src/arch/SConscript
index 3f65343..d9c19df 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -61,7 +61,6 @@
 Split('''
 decoder.hh
 isa.hh
-pcstate.hh
 vecregs.hh
 '''),
 env.subst('${TARGET_ISA}'))

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52068
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8c9cf0ec0c867b76ee8dd8f83b1d2d0835ecb3af
Gerrit-Change-Number: 52068
Gerrit-PatchSet: 16
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu-minor: Make the uReset method virtual in PCStateBase.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52064 )


 (

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch,cpu-minor: Make the uReset method virtual in  
PCStateBase.

..

arch,cpu-minor: Make the uReset method virtual in PCStateBase.

This is used in the minor CPU, but maybe shouldn't. This makes it
accessible from a generic PCStatePtr without having to cast it to a
PCState subclass.

Change-Id: Ied89e2c9c69b1a7d647129fdade10312e21dcaa1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52064
Tested-by: kokoro 
Reviewed-by: ZHENGRONG WANG 
Maintainer: ZHENGRONG WANG 
---
M src/cpu/minor/fetch2.cc
M src/arch/generic/pcstate.hh
2 files changed, 26 insertions(+), 3 deletions(-)

Approvals:
  ZHENGRONG WANG: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/generic/pcstate.hh b/src/arch/generic/pcstate.hh
index 10f6618..3e7b025 100644
--- a/src/arch/generic/pcstate.hh
+++ b/src/arch/generic/pcstate.hh
@@ -120,6 +120,12 @@
 return _upc;
 }

+virtual void
+uReset()
+{
+_upc = 0;
+}
+
 void
 serialize(CheckpointOut ) const override
 {
@@ -265,9 +271,9 @@

 // Reset the macroop's upc without advancing the regular pc.
 void
-uReset()
+uReset() override
 {
-_upc = 0;
+PCStateBase::uReset();
 _nupc = 1;
 }

diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 5215957..82648d0 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -447,7 +447,7 @@
  * may be pointing to a microop other than 0.  Once
  * advanced, however, the microop number *must* be 0
  */
-fetch_info.pc->as().uReset();
+fetch_info.pc->uReset();

 /* Advance PC for the next instruction */
 decoded_inst->advancePC(*fetch_info.pc);

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52064
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ied89e2c9c69b1a7d647129fdade10312e21dcaa1
Gerrit-Change-Number: 52064
Gerrit-PatchSet: 16
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: ZHENGRONG WANG 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Stop using and remove ThreadContext::instAddr.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52062 )


 (

14 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch,cpu: Stop using and remove ThreadContext::instAddr.
..

arch,cpu: Stop using and remove ThreadContext::instAddr.

Change-Id: I9cd8077fd72a9d7bff20f1bd7ba37e4e038b8fac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52062
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
---
M src/cpu/simple_thread.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/thread_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/commit.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/cpu/checker/thread_context.hh
M src/cpu/simple/base.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/arch/x86/kvm/x86_cpu.cc
M src/cpu/checker/cpu_impl.hh
M src/cpu/o3/mem_dep_unit.cc
M src/cpu/o3/probe/simple_trace.cc
M src/cpu/checker/cpu.hh
M src/cpu/o3/thread_context.hh
M src/cpu/minor/execute.cc
M src/arch/x86/tlb.cc
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/lsq.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/timing.cc
M src/arch/arm/kvm/armv8_cpu.cc
M src/cpu/o3/commit.cc
M src/arch/amdgpu/gcn3/tlb.cc
M src/cpu/base.cc
M src/cpu/o3/rename.cc
M src/cpu/o3/lsq_unit.cc
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/riscv/faults.cc
30 files changed, 69 insertions(+), 89 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/gcn3/tlb.cc b/src/arch/amdgpu/gcn3/tlb.cc
index 4a59c32..a6280da 100644
--- a/src/arch/amdgpu/gcn3/tlb.cc
+++ b/src/arch/amdgpu/gcn3/tlb.cc
@@ -512,7 +512,8 @@
 fatal("GpuTLB doesn't support full-system mode\n");
 } else {
 DPRINTF(GPUTLB, "Handling a TLB miss for  
address %#x "

-"at pc %#x.\n", vaddr, tc->instAddr());
+"at pc %#x.\n", vaddr,
+tc->pcState().instAddr());

 Process *p = tc->getProcessPtr();
 const EmulationPageTable::Entry *pte =
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 6d76eac..16c8250 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -590,12 +590,6 @@
 call().resource_write(_instId, result, pcRscId, pc);
 }

-Addr
-ThreadContext::instAddr() const
-{
-return pcState().instAddr();
-}
-
 RegVal
 ThreadContext::readMiscRegNoEffect(RegIndex misc_reg) const
 {
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index 620302f..e0a07d1 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -351,7 +351,6 @@

 const PCStateBase () const override;
 void pcState(const PCStateBase ) override;
-Addr instAddr() const override;

 RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
 RegVal
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index e462e4f..ecdc602 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -669,8 +669,8 @@
 setOneReg(ri->id, value);
 }

-DPRINTF(KvmContext, "kvm(PC) := 0x%x\n", tc->instAddr());
-setOneReg(REG_CORE32(usr_regs.ARM_pc), tc->instAddr());
+DPRINTF(KvmContext, "kvm(PC) := 0x%x\n", tc->pcState().instAddr());
+setOneReg(REG_CORE32(usr_regs.ARM_pc), tc->pcState().instAddr());

 for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs);
  ri->idx != NUM_MISCREGS; ++ri) {
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 06abd30..937b9c6 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -282,8 +282,8 @@
 setOneReg(ri.kvm, value);
 }

-setOneReg(INT_REG(regs.pc), tc->instAddr());
-DPRINTF(KvmContext, "  PC := 0x%x\n", tc->instAddr());
+setOneReg(INT_REG(regs.pc), tc->pcState().instAddr());
+DPRINTF(KvmContext, "  PC := 0x%x\n", tc->pcState().instAddr());
 }

 void
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 703b0ee..129e767 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -141,7 +141,7 @@
_cause |= (1L << 63);
 }
 tc->setMiscReg(cause, _cause);
-tc->setMiscReg(epc, tc->instAddr());
+tc->setMiscReg(epc, tc->pcState().instAddr());
 tc->setMiscReg(tval, trap_value());
 tc->setMiscReg(MISCREG_PRV, prv);
 tc->setMiscReg(MISCREG_STATUS, status);
diff --git a/src/arch/x86/kvm/x86_cpu.cc b/src/arch/x86/kvm/x86_cpu.cc
index 11c017c..34ac704

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Use PCStateBase for decoder methods.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52063 )


 (

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch,cpu: Use PCStateBase for decoder methods.
..

arch,cpu: Use PCStateBase for decoder methods.

Change-Id: I79f1c5dd39de7015a5c5b891e1888d9a176bb5b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52063
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Daniel Carvalho 
---
M src/cpu/checker/cpu_impl.hh
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/cpu/minor/fetch2.cc
M src/arch/sparc/decoder.hh
M src/arch/mips/decoder.hh
M src/cpu/o3/fetch.cc
M src/arch/power/decoder.hh
M src/arch/x86/decoder.cc
M src/arch/x86/decoder.hh
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/cpu/simple/base.cc
13 files changed, 52 insertions(+), 37 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 1867e90..835626f 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -152,8 +152,9 @@
 }

 void
-Decoder::moreBytes(const PCState , Addr fetchPC)
+Decoder::moreBytes(const PCStateBase &_pc, Addr fetchPC)
 {
+auto  = _pc.as();
 data = letoh(data);
 offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
 emi.thumb = pc.thumb();
@@ -171,11 +172,13 @@
 }

 StaticInstPtr
-Decoder::decode(ArmISA::PCState )
+Decoder::decode(PCStateBase &_pc)
 {
 if (!instDone)
 return NULL;

+auto  = _pc.as();
+
 const int inst_size((!emi.thumb || emi.bigThumb) ? 4 : 2);
 ExtMachInst this_emi(emi);

diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 34abf5e..5f0e68b 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -182,7 +182,7 @@
  * @param fetchPC The address this chunk was fetched from.
  * @param inst Raw instruction data.
  */
-void moreBytes(const PCState , Addr fetchPC);
+void moreBytes(const PCStateBase , Addr fetchPC);

 /**
  * Decode an instruction or fetch it from the code cache.
@@ -195,7 +195,7 @@
  * @return A pointer to a static instruction or NULL if the
  * decoder isn't ready (see instReady()).
  */
-StaticInstPtr decode(ArmISA::PCState );
+StaticInstPtr decode(PCStateBase );

 /**
  * Take over the state from an old decoder when switching CPUs.
diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 0e8e2ca..d90e9c5 100644
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -70,7 +70,7 @@
 //Use this to give data to the decoder. This should be used
 //when there is control flow.
 void
-moreBytes(const PCState , Addr fetchPC)
+moreBytes(const PCStateBase , Addr fetchPC)
 {
 emi = letoh(machInst);
 instDone = true;
@@ -111,12 +111,12 @@

   public:
 StaticInstPtr
-decode(MipsISA::PCState )
+decode(PCStateBase _pc)
 {
 if (!instDone)
 return NULL;
 instDone = false;
-return decode(emi, nextPC.instAddr());
+return decode(emi, next_pc.instAddr());
 }
 };

diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index c30af91..f3a2721 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -67,9 +67,9 @@
 // Use this to give data to the predecoder. This should be used
 // when there is control flow.
 void
-moreBytes(const PCState , Addr fetchPC)
+moreBytes(const PCStateBase , Addr fetchPC)
 {
-emi = gtoh(emi, pc.byteOrder());
+emi = gtoh(emi, pc.as().byteOrder());
 instDone = true;
 }

@@ -108,12 +108,12 @@

   public:
 StaticInstPtr
-decode(PowerISA::PCState )
+decode(PCStateBase _pc)
 {
 if (!instDone)
 return NULL;
 instDone = false;
-return decode(emi, nextPC.instAddr());
+return decode(emi, next_pc.instAddr());
 }
 };

diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index ac7e228..4091e56 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -48,7 +48,7 @@
 }

 void
-Decoder::moreBytes(const PCState , Addr fetchPC)
+Decoder::moreBytes(const PCStateBase , Addr fetchPC)
 {
 // The MSB of the upper and lower halves of a machine instruction.
 constexpr size_t max_bit = sizeof(machInst) * 8 - 1;
@@ -58,7 +58,7 @@
 DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
 fetchPC);

-bool aligned = pc.pc() % sizeof(machInst) == 0;
+bool aligned = pc.instAddr() % sizeof(machInst) == 0;
 if (aligned) {
 emi = inst;
 if (compressed(emi))
@@ -97,19 +97,21 @@
 }

 StaticInstPtr

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Make branching() a virtual member of PCStateBase.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52066 )


 (

14 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch,cpu: Make branching() a virtual member of  
PCStateBase.

..

arch,cpu: Make branching() a virtual member of PCStateBase.

Change-Id: I4422d07024e97dbd67e97ad95a16e1b06fd6be12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52066
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Daniel Carvalho 
---
M src/arch/x86/pcstate.hh
M src/arch/generic/pcstate.hh
M src/arch/arm/pcstate.hh
M src/cpu/o3/fetch.cc
M src/cpu/o3/iew.cc
M src/arch/riscv/pcstate.hh
M src/cpu/simple/base.cc
7 files changed, 24 insertions(+), 12 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/pcstate.hh b/src/arch/arm/pcstate.hh
index f2d85d2..7b75ed8 100644
--- a/src/arch/arm/pcstate.hh
+++ b/src/arch/arm/pcstate.hh
@@ -196,7 +196,7 @@
 uint8_t size() const { return _size; }

 bool
-branching() const
+branching() const override
 {
 return ((this->pc() + this->size()) != this->npc());
 }
diff --git a/src/arch/generic/pcstate.hh b/src/arch/generic/pcstate.hh
index 415e80d..f2501e6 100644
--- a/src/arch/generic/pcstate.hh
+++ b/src/arch/generic/pcstate.hh
@@ -127,6 +127,7 @@
 }

 virtual void advance() = 0;
+virtual bool branching() const = 0;

 void
 serialize(CheckpointOut ) const override
@@ -365,7 +366,7 @@
 };

 bool
-branching() const
+branching() const override
 {
 return this->npc() != this->pc() + InstWidth;
 }
@@ -414,7 +415,7 @@
 explicit UPCState(Addr val) { set(val); }

 bool
-branching() const
+branching() const override
 {
 return this->npc() != this->pc() + InstWidth ||
this->nupc() != this->upc() + 1;
@@ -486,7 +487,7 @@
 explicit DelaySlotPCState(Addr val) { set(val); }

 bool
-branching() const
+branching() const override
 {
 return !(this->nnpc() == this->npc() + InstWidth &&
  (this->npc() == this->pc() + InstWidth ||
@@ -559,7 +560,7 @@
 explicit DelaySlotUPCState(Addr val) { set(val); }

 bool
-branching() const
+branching() const override
 {
 return Base::branching() || this->nupc() != this->upc() + 1;
 }
diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh
index 53b358c..0125507 100644
--- a/src/arch/riscv/pcstate.hh
+++ b/src/arch/riscv/pcstate.hh
@@ -77,7 +77,7 @@
 bool rv32() const { return _rv32; }

 bool
-branching() const
+branching() const override
 {
 if (_compressed) {
 return npc() != pc() + 2 || nupc() != upc() + 1;
diff --git a/src/arch/x86/pcstate.hh b/src/arch/x86/pcstate.hh
index bfc7d4f..a0ed6ff 100644
--- a/src/arch/x86/pcstate.hh
+++ b/src/arch/x86/pcstate.hh
@@ -88,7 +88,7 @@
 void size(uint8_t newSize) { _size = newSize; }

 bool
-branching() const
+branching() const override
 {
 return (this->npc() != this->pc() + size()) ||
(this->nupc() != this->upc() + 1);
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 530fcfb..61ffc17 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -1287,7 +1287,7 @@

 // If we're branching after this instruction, quit fetching
 // from the same block.
-predictedBranch |= this_pc.as().branching();
+predictedBranch |= this_pc.branching();
 predictedBranch |= lookupAndUpdateNextPC(instruction,  
*next_pc);

 if (predictedBranch) {
 DPRINTF(Fetch, "Branch detected with PC = %s\n", this_pc);
diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
index 062a566..8dbd5b3 100644
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -461,8 +461,7 @@
 inst->seqNum < toCommit->squashedSeqNum[tid]) {
 toCommit->squash[tid] = true;
 toCommit->squashedSeqNum[tid] = inst->seqNum;
-toCommit->branchTaken[tid] =
-inst->pcState().as().branching();
+toCommit->branchTaken[tid] = inst->pcState().branching();

 set(toCommit->pc[tid], inst->pcState());
 inst->staticInst->advancePC(*toCommit->pc[tid]);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 84c729e..0f11eb9 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -461,8 +461,7 @@
 SimpleExecContext _info = *threadInfo[curThread];
 SimpleThread* thread = t_info.thread;

-const bool branching =
-thread->pcState().as().branching();
+const bool branching = thread->pcState().branching();

 //Since we're moving to a new pc, zero out the offset

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu,base: Make add a virtual method to stutter the PC for KVM.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52059 )


 (

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch,cpu,base: Make add a virtual method to stutter the  
PC for KVM.

..

arch,cpu,base: Make add a virtual method to stutter the PC for KVM.

As described in a comment in the base KVM CPU, there needs to be a way
to set the next PC of a PCState object to the actual current PC. Since
this is the only place that sort of operation is needed and it's a bit
of a hack to get around a quirk of calling pseudo instructions in a KVM
CPU, we can support it by adding a virtual method for it which is
implemented by the ISA specific subclasses of the KVM CPU.

Change-Id: Idf390e9c4ffa7398cd08e76846c61cb6da754dce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52059
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
---
M src/arch/x86/kvm/x86_cpu.hh
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/arch/arm/kvm/base_cpu.hh
M src/arch/arm/kvm/arm_cpu.hh
5 files changed, 52 insertions(+), 2 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/kvm/arm_cpu.hh b/src/arch/arm/kvm/arm_cpu.hh
index 95d5339..a16a095 100644
--- a/src/arch/arm/kvm/arm_cpu.hh
+++ b/src/arch/arm/kvm/arm_cpu.hh
@@ -41,6 +41,7 @@
 #include 
 #include 

+#include "arch/arm/pcstate.hh"
 #include "cpu/kvm/base.hh"
 #include "params/ArmKvmCPU.hh"

@@ -96,6 +97,11 @@

 void updateKvmState();
 void updateThreadContext();
+void
+stutterPC(PCStateBase ) const
+{
+pc.as().setNPC(pc->instAddr());
+}

 /**
  * Get a list of registers supported by getOneReg() and setOneReg().
diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index 3b2beb3..0da4789 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -40,6 +40,7 @@

 #include 

+#include "arch/arm/pcstate.hh"
 #include "cpu/kvm/base.hh"
 #include "dev/arm/base_gic.hh"

@@ -62,6 +63,12 @@
   protected:
 Tick kvmRun(Tick ticks) override;

+void
+stutterPC(PCStateBase ) const override
+{
+pc.as().setNPC(pc.instAddr());
+}
+
 /** Override for synchronizing state in kvm_run */
 void ioctlRun() override;

diff --git a/src/arch/x86/kvm/x86_cpu.hh b/src/arch/x86/kvm/x86_cpu.hh
index 69390a8..ae41b6b 100644
--- a/src/arch/x86/kvm/x86_cpu.hh
+++ b/src/arch/x86/kvm/x86_cpu.hh
@@ -31,6 +31,7 @@

 #include 

+#include "arch/x86/pcstate.hh"
 #include "cpu/kvm/base.hh"
 #include "cpu/kvm/vm.hh"
 #include "params/X86KvmCPU.hh"
@@ -91,6 +92,11 @@
 Tick kvmRunDrain() override;

 uint64_t getHostCycles() const override;
+void
+stutterPC(PCStateBase ) const override
+{
+pc.as().setNPC(pc.instAddr());
+}

 /**
  * Methods to access CPUID information using the extended
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index bda4d0e..79bbf02 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1110,8 +1110,10 @@
 //
 // We won't be able to rewind the current PC to the "correct"
 // value without figuring out how big the current instruction
-// is, and that's probably not worth the effort.
-tc->setNPC(tc->instAddr());
+// is, and that's probably not worth the effort
+std::unique_ptr pc(tc->pcState().clone());
+stutterPC(*pc);
+tc->pcState(*pc);
 // We currently assume that there is no need to migrate to a
 // different event queue when doing local accesses. Currently, they
 // are only used for m5ops, so it should be a valid assumption.
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 4f40064..449c5db 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -261,6 +261,15 @@
 virtual uint64_t getHostCycles() const;

 /**
+ * Modify a PCStatePtr's value so that its next PC is the current PC.
+ *
+ * This needs to be implemented in KVM base classes since modifying the
+ * next PC value is an ISA specific operation. This is only used in
+ * doMMIOAccess, for reasons explained in a comment there.
+ */
+virtual void stutterPC(PCStateBase ) const = 0;
+
+/**
  * Request KVM to run the guest for a given number of ticks. The
  * method returns the approximate number of ticks executed.
  *

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52059
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idf390e9c4ffa7398cd08e76846c61cb6da754dce
Gerrit-Change-Number: 52059
Gerrit-PatchSet: 16
Gerrit-Owner:

[gem5-dev] Change in gem5/gem5[develop]: cpu: Eliminate the ThreadContext::microPC method.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52061 )


 (

14 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: cpu: Eliminate the ThreadContext::microPC method.
..

cpu: Eliminate the ThreadContext::microPC method.

This was originally intended to make it more efficient to get the
microPC without making a copy of the entire PCState object to return.
Now that the PCState is returned through a pointer without a copy and
the microPC can be accessed with an inline accessor, we don't need to
create a special accessor for it.

Change-Id: I1d354dfca6be5d954e147f23dc9d27917b379bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52061
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
---
M src/cpu/simple_thread.hh
M src/cpu/checker/cpu.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/dyn_inst.cc
M src/cpu/o3/dyn_inst.hh
M src/cpu/thread_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/o3/commit.hh
M src/cpu/checker/thread_context.hh
M src/cpu/simple/atomic.hh
M src/arch/arm/fastmodel/iris/thread_context.hh
14 files changed, 23 insertions(+), 37 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index a343658..620302f 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -348,7 +348,6 @@
 }

 void pcStateNoRecord(const PCStateBase ) override { pcState(val); }
-MicroPC microPC() const override { return 0; }

 const PCStateBase () const override;
 void pcState(const PCStateBase ) override;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3d29d05..37b19aa 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -367,7 +367,6 @@
 thread->pcState(val);
 }
 Addr instAddr() { return thread->instAddr(); }
-MicroPC microPC() { return thread->microPC(); }
 //

 RegVal
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index dfc9524..81c4973 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -343,9 +343,6 @@
 /** Reads this thread's PC. */
 Addr instAddr() const override { return actualTC->instAddr(); }

-/** Reads this thread's next PC. */
-MicroPC microPC() const override { return actualTC->microPC(); }
-
 RegVal
 readMiscRegNoEffect(RegIndex misc_reg) const override
 {
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ed462e0..4a3b335 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -314,9 +314,6 @@
 /** Returns the PC of a specific thread. */
 Addr instAddr(ThreadID tid) { return pc[tid]->instAddr(); }

-/** Reads the micro PC of a specific thread. */
-Addr microPC(ThreadID tid) { return pc[tid]->microPC(); }
-
   private:
 /** Time buffer interface. */
 TimeBuffer *timeBuffer;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 462c029..6e88a28 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1325,12 +1325,6 @@
 return commit.instAddr(tid);
 }

-MicroPC
-CPU::microPC(ThreadID tid)
-{
-return commit.microPC(tid);
-}
-
 void
 CPU::squashFromTC(ThreadID tid)
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e7dd065..46dbefc 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -393,9 +393,6 @@
 /** Reads the commit PC of a specific thread. */
 Addr instAddr(ThreadID tid);

-/** Reads the commit micro PC of a specific thread. */
-MicroPC microPC(ThreadID tid);
-
 /** Initiates a squash of all in-flight instructions for a given
  * thread.  The source of the squash is an external update of
  * state through the TC.
diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc
index 36591ae..89a7594 100644
--- a/src/cpu/o3/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -219,7 +219,7 @@
  
DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",

  fetch,
  instAddr(),
- microPC(),
+ pcState().microPC(),
  seqNum,
  staticInst->disassemble(instAddr()));

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 832d5e8..7ffb779 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -518,9 +518,6 @@
 /** Returns the predicted PC immediately after the branch. */
 Addr predInstAddr() { return predPC->instAddr(); }

-/** Returns the predicted micro PC after the branch

[gem5-dev] Change in gem5/gem5[develop]: arch: Rename PCStateCommon to PCStateWithNext.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52486 )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch: Rename PCStateCommon to PCStateWithNext.
..

arch: Rename PCStateCommon to PCStateWithNext.

This intermediate class has a fairly vague name. This new name more
specifically describes what this PCState class adds to its base class.

Change-Id: I6d19383f3eb2895d924187ddbf8185352db71542
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52486
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Daniel Carvalho 
---
M src/arch/generic/pcstate.hh
1 file changed, 24 insertions(+), 8 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/generic/pcstate.hh b/src/arch/generic/pcstate.hh
index f2501e6..f1df6e7 100644
--- a/src/arch/generic/pcstate.hh
+++ b/src/arch/generic/pcstate.hh
@@ -246,18 +246,18 @@
 namespace GenericISA
 {

-class PCStateCommon : public PCStateBase
+class PCStateWithNext : public PCStateBase
 {
   protected:
 Addr _npc = 0;

 MicroPC _nupc = 1;

-PCStateCommon(const PCStateCommon ) : PCStateBase(other),
+PCStateWithNext(const PCStateWithNext ) : PCStateBase(other),
 _npc(other._npc), _nupc(other._nupc)
 {}
-PCStateCommon =(const PCStateCommon ) = default;
-PCStateCommon() {}
+PCStateWithNext =(const PCStateWithNext ) = default;
+PCStateWithNext() {}

   public:
 Addr pc() const { return _pc; }
@@ -296,7 +296,7 @@
 update(const PCStateBase ) override
 {
 PCStateBase::update(other);
-auto  = other.as();
+auto  = other.as();
 _npc = pcstate._npc;
 _nupc = pcstate._nupc;
 }
@@ -304,7 +304,7 @@
 bool
 equals(const PCStateBase ) const override
 {
-auto  = other.as();
+auto  = other.as();
 return PCStateBase::equals(other) &&
 _npc == ps._npc && _nupc == ps._nupc;
 }
@@ -335,10 +335,10 @@

 // The most basic type of PC.
 template 
-class SimplePCState : public PCStateCommon
+class SimplePCState : public PCStateWithNext
 {
   protected:
-typedef PCStateCommon Base;
+typedef PCStateWithNext Base;

   public:
 SimplePCState(const SimplePCState ) : Base(other) {}

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52486
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6d19383f3eb2895d924187ddbf8185352db71542
Gerrit-Change-Number: 52486
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Eliminate the ThreadContext::setNPC method.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52060 )


 (

14 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: cpu: Eliminate the ThreadContext::setNPC method.
..

cpu: Eliminate the ThreadContext::setNPC method.

It is no longer used.

Change-Id: Ic0526097550b109455cb09707e712775a0be56c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52060
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
---
M src/cpu/thread_context.hh
M src/cpu/checker/thread_context.hh
2 files changed, 15 insertions(+), 15 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index b210fea..dfc9524 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -335,13 +335,6 @@
 }

 void
-setNPC(Addr val)
-{
-checkerTC->setNPC(val);
-actualTC->setNPC(val);
-}
-
-void
 pcStateNoRecord(const PCStateBase ) override
 {
 return actualTC->pcState(val);
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 9e4d495..07eb7bb 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -233,14 +233,6 @@
 pcState(*new_pc);
 }

-void
-setNPC(Addr val)
-{
-std::unique_ptr pc_state(pcState().clone());
-pc_state->as().setNPC(val);
-pcState(*pc_state);
-}
-
 virtual void pcStateNoRecord(const PCStateBase ) = 0;

 virtual Addr instAddr() const = 0;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic0526097550b109455cb09707e712775a0be56c4
Gerrit-Change-Number: 52060
Gerrit-PatchSet: 16
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Make the advance() method virtual and in PCStateBase.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52065 )


 (

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch: Make the advance() method virtual and in  
PCStateBase.

..

arch: Make the advance() method virtual and in PCStateBase.

It's occasionally necessary to advance the PC to the next instruction
without having an instruction to do it with. This makes it available
without having to cast to a PCState subclass.

Change-Id: I3b7d94afdfb27b34279e58158782e87ab5066a37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52065
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Daniel Carvalho 
---
M src/arch/x86/pcstate.hh
M src/arch/generic/pcstate.hh
M src/cpu/nop_static_inst.cc
M src/arch/arm/pcstate.hh
M src/sim/syscall_emul.hh
5 files changed, 27 insertions(+), 8 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/pcstate.hh b/src/arch/arm/pcstate.hh
index 122cd9b..f2d85d2 100644
--- a/src/arch/arm/pcstate.hh
+++ b/src/arch/arm/pcstate.hh
@@ -288,7 +288,7 @@
 }

 void
-advance()
+advance() override
 {
 Base::advance();
 flags = nextFlags;
diff --git a/src/arch/generic/pcstate.hh b/src/arch/generic/pcstate.hh
index 3e7b025..415e80d 100644
--- a/src/arch/generic/pcstate.hh
+++ b/src/arch/generic/pcstate.hh
@@ -126,6 +126,8 @@
 _upc = 0;
 }

+virtual void advance() = 0;
+
 void
 serialize(CheckpointOut ) const override
 {
@@ -370,7 +372,7 @@

 // Advance the PC.
 void
-advance()
+advance() override
 {
 this->_pc = this->_npc;
 this->_npc += InstWidth;
@@ -493,7 +495,7 @@

 // Advance the PC.
 void
-advance()
+advance() override
 {
 this->_pc = this->_npc;
 this->_npc = this->_nnpc;
diff --git a/src/arch/x86/pcstate.hh b/src/arch/x86/pcstate.hh
index 8d74806..bfc7d4f 100644
--- a/src/arch/x86/pcstate.hh
+++ b/src/arch/x86/pcstate.hh
@@ -95,7 +95,7 @@
 }

 void
-advance()
+advance() override
 {
 Base::advance();
 _size = 0;
diff --git a/src/cpu/nop_static_inst.cc b/src/cpu/nop_static_inst.cc
index 64b542d..aa34481 100644
--- a/src/cpu/nop_static_inst.cc
+++ b/src/cpu/nop_static_inst.cc
@@ -50,9 +50,9 @@
 }

 void
-advancePC(PCStateBase ) const override
+advancePC(PCStateBase ) const override
 {
-pcState.as().advance();
+pc.advance();
 }

 std::string
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 54bd54b..c53175b 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1662,7 +1662,7 @@
 desc->returnInto(ctc, 0);

 std::unique_ptr cpc(tc->pcState().clone());
-cpc->as().advance();
+cpc->advance();
 ctc->pcState(*cpc);
 ctc->activate();

@@ -2226,7 +2226,7 @@
 new_p->initState();
 tc->activate();
 std::unique_ptr pc_state(tc->pcState().clone());
-pc_state->as().advance();
+pc_state->advance();
 tc->pcState(*pc_state);

 return SyscallReturn();

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Gerrit-Branch: develop
Gerrit-Change-Id: I3b7d94afdfb27b34279e58158782e87ab5066a37
Gerrit-Change-Number: 52065
Gerrit-PatchSet: 16
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: In SimpleIndirectPredictor, avoid an accidental nullptr deref.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53403 )


Change subject: cpu: In SimpleIndirectPredictor, avoid an accidental  
nullptr deref.

..

cpu: In SimpleIndirectPredictor, avoid an accidental nullptr deref.

The default value of IPredEntry::tag is 0, and if we just blindly
compare the tag we're looking for against this value, we might run into
cases where we match against an uninitialized IPredEntry. In that case,
IPredEntry::target has not been initialized, and if we try to use it in
lookup(...) we'll dereference nullptr and segfault.

To avoid that, we can just add one additional check that makes sure that
not only does the tag of the IPredEntry match, but also that the value
of target is not null, and so the IPredEntry *actually* has tag 0 and
isn't just uninitialized.

Change-Id: I892d0df7c00a0a4cd3ca215fe3a7586ddbca9395
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53403
Maintainer: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/pred/simple_indirect.cc
1 file changed, 27 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/pred/simple_indirect.cc  
b/src/cpu/pred/simple_indirect.cc

index 2a1fc7a..f09cdee 100644
--- a/src/cpu/pred/simple_indirect.cc
+++ b/src/cpu/pred/simple_indirect.cc
@@ -104,7 +104,9 @@
 DPRINTF(Indirect, "Looking up %x (set:%d)\n", br_addr, set_index);
 const auto  = targetCache[set_index];
 for (auto way = iset.begin(); way != iset.end(); ++way) {
-if (way->tag == tag) {
+// tag may be 0 and match the default in way->tag, so we also have  
to

+// check that way->target has been initialized.
+if (way->tag == tag && way->target) {
 DPRINTF(Indirect, "Hit %x (target:%s)\n", br_addr,  
*way->target);

 set(target, *way->target);
 return true;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I892d0df7c00a0a4cd3ca215fe3a7586ddbca9395
Gerrit-Change-Number: 53403
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Update ext/sst/INSTALL.md

2021-11-30 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53463 )



Change subject: ext: Update ext/sst/INSTALL.md
..

ext: Update ext/sst/INSTALL.md

Currently, the installation instructions are for installing
SST-core and SST-elements version 11.0.0. This change updates
instructions to the current SST-core and SST-element version,
11.1.0.

This change also reflects that manually downloading the
`bbl-busybox-boot-exit` is no longer necessary as the example
gem5 config will download automatically.

Change-Id: I616ca38316213dcbd71b6eab121b5ac89eed1962
Signed-off-by: Hoa Nguyen 
---
M ext/sst/INSTALL.md
1 file changed, 31 insertions(+), 15 deletions(-)



diff --git a/ext/sst/INSTALL.md b/ext/sst/INSTALL.md
index 4268724..46ff4f0 100644
--- a/ext/sst/INSTALL.md
+++ b/ext/sst/INSTALL.md
@@ -11,14 +11,14 @@
 ### Downloading the SST-Core Source Code

 ```sh
-wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.0.0_Final/sstcore-11.0.0.tar.gz

-tar xf sstcore-11.0.0.tar.gz
+wget  
https://github.com/sstsimulator/sst-core/releases/download/v11.1.0_Final/sstcore-11.1.0.tar.gz

+tar xf sstcore-11.1.0.tar.gz
 ```

 ### Installing SST-Core

 ```sh
-cd sstcore-11.0.0
+cd sstcore-11.1.0
 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \
 --disable-mpi # optional, used when MPI is not available.
 make all -j$(nproc)
@@ -36,14 +36,14 @@
 ### Downloading the SST-Elements Source Code

 ```sh
-wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.0.0_Final/sstelements-11.0.0.tar.gz

-tar xf sstelements-11.0.0.tar.gz
+wget  
https://github.com/sstsimulator/sst-elements/releases/download/v11.1.0_Final/sstelements-11.1.0.tar.gz

+tar xf sstelements-11.1.0.tar.gz
 ```

 ### Installing SST-Elements

-```shs
-cd sst-elements-library-11.0.0
+```sh
+cd sst-elements-library-11.1.0
 ./configure --prefix=$SST_CORE_HOME --with-python=/usr/bin/python3-config \
 --with-sst-core=$SST_CORE_HOME
 make all -j$(nproc)
@@ -75,20 +75,17 @@

 ### Running an example simulation

-Downloading the built bootloader containing a Linux Kernel and a workload,
-
-```sh
-wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit
-```
-
 Running the simulation

 ```sh
 sst --add-lib-path=./ sst/example.py
 ```

-`bbl-busybox-boot-exit` contains an m5 binary, and `m5 exit` will be called
-upon the booting process reaching the early userspace.
+The example SST system configuration will instantiate the gem5 system
+as specified in the gem5 system configuration located at
+`gem5/configs/example/sst/riscv_fs.py`. This configuration will download
+the `bbl-busybox-boot-exit` resource, which contains an m5 binary, and
+`m5 exit` will be called upon the booting process reaching the early  
userspace.
 More information about building a bootloader containing a Linux Kernel and  
a

 customized workload is available at
  
[https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-boot-exit-nodisk/].


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Gerrit-Change-Number: 53463
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Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Incorrect disassembly/register width in Aarch64 ?

2021-11-30 Thread Arthur Perais via gem5-dev 

Hi all,

I am using a fairly old gem5 version 
(566c113de1eb08ccbfba6e4b074f96c9977a0e16 from Nov 2020), but I noticed 
that the disassembly (and the register width) of some Aarch64 
instructions seems to be incorrectly reported by gem5.


Notably, instruction :

ldr  w1, [sp, #168] (0xb940abe1 according to objdump)

Is reported in gem5 as

ldr  x1, [sp, #168] (0xf94057e1 according to objdump)

And the getIntWidth() method that can be called on the staticInst 
reports 64 (when it reports 32 for instructions that write into a "word" 
register).


I have not found a patch addressing this but maybe this has been fixed 
already, or maybe this is known to happen under some specific 
configuration of an Aarch64 system.


Best,

Arthur Perais
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[gem5-dev] Change in gem5/gem5[develop]: mem: Fixed the bug of switching to ALLOCATE at once

2021-11-30 Thread Huang Jiasen (Gerrit) via gem5-dev 
Huang Jiasen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53384 )



Change subject: mem: Fixed the bug of switching to ALLOCATE at once
..

mem: Fixed the bug of switching to ALLOCATE at once

Change-Id: Ia76b0a91910a5d769c6ed1856b98bc14ed465aa0
---
M src/mem/cache/base.cc
1 file changed, 23 insertions(+), 5 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index dc21151..350af6d 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -2643,11 +2643,20 @@
 }
 }
 } else {
-// we did not see a write matching the previous one, start
-// over again
-byteCount = write_size;
-mode = WriteMode::ALLOCATE;
-resetDelay(blk_addr);
+// continuous switch back to ALLOCATE
+byteCount -= write_size;
+if (mode == WriteMode::NO_ALLOCATE) {
+if (byteCount < noAllocateLimit &&
+byteCount >= coalesceLimit) {
+mode = WriteMode::COALESCE;
+}
+}
+else if (mode == WriteMode::COALESCE) {
+if (byteCount < coalesceLimit) {
+mode = WriteMode::ALLOCATE;
+resetDelay(blk_addr);
+}
+}
 }
 nextAddr = write_addr + write_size;
 }

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Gerrit-Change-Id: Ia76b0a91910a5d769c6ed1856b98bc14ed465aa0
Gerrit-Change-Number: 53384
Gerrit-PatchSet: 1
Gerrit-Owner: Huang Jiasen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding style in utility.cc

2021-11-30 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53265 )


Change subject: arch-arm: Fix coding style in utility.cc
..

arch-arm: Fix coding style in utility.cc

Change-Id: I46318878a9ecfacdb1b891da6064d2058774856a
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53265
Reviewed-by: Richard Cooper 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/utility.cc
1 file changed, 143 insertions(+), 122 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index aa223bf..3cc4b43 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -414,7 +414,7 @@
 }

 int
-computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
+computeAddrTop(ThreadContext *tc, bool selbit, bool is_instr,
TCR tcr, ExceptionLevel el)
 {
 bool tbi = false;
@@ -455,15 +455,15 @@
 }

 }
-int res = (tbi && (!tbid || !isInstr))? 55: 63;
+int res = (tbi && (!tbid || !is_instr))? 55: 63;
 return res;
 }
 Addr
 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
- TCR tcr, bool isInstr)
+ TCR tcr, bool is_instr)
 {
 bool selbit = bits(addr, 55);
-int topbit = computeAddrTop(tc, selbit, isInstr, tcr, el);
+int topbit = computeAddrTop(tc, selbit, is_instr, tcr, el);

 if (topbit == 63) {
 return addr;
@@ -478,11 +478,11 @@

 Addr
 purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
- bool isInstr)
+ bool is_instr)
 {

 TCR tcr = tc->readMiscReg(MISCREG_TCR_EL1);
-return purifyTaggedAddr(addr, tc, el, tcr, isInstr);
+return purifyTaggedAddr(addr, tc, el, tcr, is_instr);
 }

 Addr
@@ -498,26 +498,26 @@
 }

 Fault
-mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
+mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
  ThreadContext *tc, uint32_t imm)
 {
 ExceptionClass ec = EC_TRAPPED_CP15_MCR_MRC;
-if (mcrMrc15TrapToHyp(miscReg, tc, imm, ))
-return std::make_shared(machInst, imm, ec);
-return AArch64AArch32SystemAccessTrap(miscReg, machInst, tc, imm, ec);
+if (mcrMrc15TrapToHyp(misc_reg, tc, imm, ))
+return std::make_shared(mach_inst, imm, ec);
+return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm,  
ec);

 }

 bool
-mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t  
iss,
+mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t  
iss,

   ExceptionClass *ec)
 {
-bool isRead;
+bool is_read;
 uint32_t crm;
 IntRegIndex rt;
 uint32_t crn;
 uint32_t opc1;
 uint32_t opc2;
-bool trapToHype = false;
+bool trap_to_hyp = false;

 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
@@ -527,30 +527,30 @@
 const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);

 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
-mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
-trapToHype  = ((uint32_t) hstr) & (1 << crn);
-trapToHype |= hdcr.tpm  && (crn == 9) && (crm >= 12);
-trapToHype |= hcr.tidcp && (
+mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
+trap_to_hyp  = ((uint32_t) hstr) & (1 << crn);
+trap_to_hyp |= hdcr.tpm  && (crn == 9) && (crm >= 12);
+trap_to_hyp |= hcr.tidcp && (
 ((crn ==  9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8 ||
 ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
 ((crn == 11) && ((crm <= 8) || (crm == 15;

-if (!trapToHype) {
-switch (unflattenMiscReg(miscReg)) {
+if (!trap_to_hyp) {
+switch (unflattenMiscReg(misc_reg)) {
   case MISCREG_CPACR:
-trapToHype = hcptr.tcpac;
+trap_to_hyp = hcptr.tcpac;
 break;
   case MISCREG_REVIDR:
   case MISCREG_TCMTR:
   case MISCREG_TLBTR:
   case MISCREG_AIDR:
-trapToHype = hcr.tid1;
+trap_to_hyp = hcr.tid1;
 break;
   case MISCREG_CTR:
   case MISCREG_CCSIDR:
   case MISCREG_CLIDR:
   case MISCREG_CSSELR:
-trapToHype = hcr.tid2;
+trap_to_hyp = hcr.tid2;
 break;
   case MISCREG_ID_PFR0:
   case MISCREG_ID_PFR1:
@@ -568,23 +568,23 @@
   case

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding style in isa.hh

2021-11-30 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53267 )


Change subject: arch-arm: Fix coding style in isa.hh
..

arch-arm: Fix coding style in isa.hh

Change-Id: Ib827e4ae9662e79512a18c13e1cd262213406fbf
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53267
Reviewed-by: Richard Cooper 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/isa.hh
1 file changed, 196 insertions(+), 62 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 2d30ded..645a765 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -119,8 +119,8 @@
 uint64_t _rao;   // read as one (fixed at 1)
   public:
 MiscRegLUTEntry() :
-  lower(0), upper(0),
-  _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
+lower(0), upper(0),
+_reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
 uint64_t reset() const { return _reset; }
 uint64_t res0()  const { return _res0; }
 uint64_t res1()  const { return _res1; }
@@ -139,239 +139,343 @@
 std::bitset 
 typedef const MiscRegLUTEntryInitializer& chain;
   public:
-chain mapsTo(uint32_t l, uint32_t u = 0) const {
+chain
+mapsTo(uint32_t l, uint32_t u = 0) const
+{
 entry.lower = l;
 entry.upper = u;
 return *this;
 }
-chain res0(uint64_t mask) const {
+chain
+res0(uint64_t mask) const
+{
 entry._res0 = mask;
 return *this;
 }
-chain res1(uint64_t mask) const {
+chain
+res1(uint64_t mask) const
+{
 entry._res1 = mask;
 return *this;
 }
-chain raz(uint64_t mask) const {
+chain
+raz(uint64_t mask) const
+{
 entry._raz  = mask;
 return *this;
 }
-chain rao(uint64_t mask) const {
+chain
+rao(uint64_t mask) const
+{
 entry._rao  = mask;
 return *this;
 }
-chain implemented(bool v = true) const {
+chain
+implemented(bool v = true) const
+{
 info[MISCREG_IMPLEMENTED] = v;
 return *this;
 }
-chain unimplemented() const {
+chain
+unimplemented() const
+{
 return implemented(false);
 }
-chain unverifiable(bool v = true) const {
+chain
+unverifiable(bool v = true) const
+{
 info[MISCREG_UNVERIFIABLE] = v;
 return *this;
 }
-chain warnNotFail(bool v = true) const {
+chain
+warnNotFail(bool v = true) const
+{
 info[MISCREG_WARN_NOT_FAIL] = v;
 return *this;
 }
-chain mutex(bool v = true) const {
+chain
+mutex(bool v = true) const
+{
 info[MISCREG_MUTEX] = v;
 return *this;
 }
-chain banked(bool v = true) const {
+chain
+banked(bool v = true) const
+{
 info[MISCREG_BANKED] = v;
 return *this;
 }
-chain banked64(bool v = true) const {
+chain
+banked64(bool v = true) const
+{
 info[MISCREG_BANKED64] = v;
 return *this;
 }
-chain bankedChild(bool v = true) const {
+chain
+bankedChild(bool v = true) const
+{
 info[MISCREG_BANKED_CHILD] = v;
 return *this;
 }
-chain userNonSecureRead(bool v = true) const {
+chain
+userNonSecureRead(bool v = true) const
+{
 info[MISCREG_USR_NS_RD] = v;
 return *this;
 }
-chain userNonSecureWrite(bool v = true) const {
+chain
+userNonSecureWrite(bool v = true) const
+{
 info[MISCREG_USR_NS_WR] = v;
 return *this;
 }
-chain userSecureRead(bool v = true) const {
+chain
+

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use ThreadContext when trapping MCR/MRC to cop14

2021-11-30 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53263 )


Change subject: arch-arm: Use ThreadContext when trapping MCR/MRC to cop14
..

arch-arm: Use ThreadContext when trapping MCR/MRC to cop14

We are aligning to cop15 read/writes. By passing the TC directly
we unlock the usage of TC based helper functions.

Change-Id: I1d06d31ce0bd04508f44f34cc0dcef8828d9c48c
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53263
Reviewed-by: Richard Cooper 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/arm/isa/insts/misc.isa
3 files changed, 31 insertions(+), 8 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index 80ba685..7253f85 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -897,8 +897,7 @@
 return std::make_shared(machInst, false,
   mnemonic);
 }
-if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
-  Hstr, Hcptr, imm)) {
+if (mcrMrc14TrapToHyp((MiscRegIndex) op1, xc->tcBase(), imm)) {
 return std::make_shared(machInst, imm,
 EC_TRAPPED_CP14_MCR_MRC);
 }
@@ -922,8 +921,7 @@
 return std::make_shared(machInst, false,
   mnemonic);
 }
-if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
-  Hstr, Hcptr, imm)) {
+if (mcrMrc14TrapToHyp(miscReg, xc->tcBase(), imm)) {
 return std::make_shared(machInst, imm,
 EC_TRAPPED_CP14_MCR_MRC);
 }
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 520716e..aa223bf 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -665,8 +665,7 @@


 bool
-mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
-  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
+mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t  
iss)

 {
 bool isRead;
 uint32_t crm;
@@ -674,6 +673,14 @@
 uint32_t crn;
 uint32_t opc1;
 uint32_t opc2;
+
+const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+const SCR scr = tc->readMiscReg(MISCREG_SCR);
+const HCR hcr = tc->readMiscReg(MISCREG_HCR);
+const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
+const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
+const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
+
 bool trapToHype = false;

 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 0d9b3bc..46dda3a 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -302,8 +302,8 @@
 bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
uint32_t iss, ExceptionClass *ec=nullptr);

-bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR  
scr,

-   HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
+bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
+   uint32_t iss);

 Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
  ThreadContext *tc, uint32_t imm);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1d06d31ce0bd04508f44f34cc0dcef8828d9c48c
Gerrit-Change-Number: 53263
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Allow EL2 trapping of secure AA32 instructions

2021-11-30 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53266 )


Change subject: arch-arm: Allow EL2 trapping of secure AA32 instructions
..

arch-arm: Allow EL2 trapping of secure AA32 instructions

With the introduction of FEAT_SEL2 we should allow trapping
to EL2 in secure mode. This is already implemented for AArch64
EL1. With this patch we are extending it to AArch32

Change-Id: I3551a93af7db0b1d2bdf0935c3a29e39e8db55f8
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53266
Reviewed-by: Richard Cooper 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/utility.cc
1 file changed, 22 insertions(+), 9 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 3cc4b43..d24f470 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -519,14 +519,12 @@
 uint32_t opc2;
 bool trap_to_hyp = false;

-const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
-const SCR scr = tc->readMiscReg(MISCREG_SCR);
 const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
 const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
 const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);

-if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
+if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
 mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
 trap_to_hyp  = ((uint32_t) hstr) & (1 << crn);
 trap_to_hyp |= hdcr.tpm  && (crn == 9) && (crm >= 12);
@@ -674,8 +672,6 @@
 uint32_t opc1;
 uint32_t opc2;

-const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-const SCR scr = tc->readMiscReg(MISCREG_SCR);
 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
 const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
 const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
@@ -683,7 +679,7 @@

 bool trap_to_hyp = false;

-if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
+if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
 mcrMrcIssExtract(iss, is_read, crm, rt, crn, opc1, opc2);
 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x,  
hstr %x\n",

 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
@@ -743,12 +739,10 @@
 bool is_read;
 bool trap_to_hyp = false;

-const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 const HCR hcr = tc->readMiscReg(MISCREG_HCR);
-const SCR scr = tc->readMiscReg(MISCREG_SCR);
 const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);

-if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
+if (EL2Enabled(tc) && (currEL(tc) < EL2)) {
 // This is technically the wrong function, but we can re-use it for
 // the moment because we only need one field, which overlaps with  
the

 // mcrmrc layout

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3551a93af7db0b1d2bdf0935c3a29e39e8db55f8
Gerrit-Change-Number: 53266
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove unused Hdcr/Hcptr operands

2021-11-30 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53264 )


Change subject: arch-arm: Remove unused Hdcr/Hcptr operands
..

arch-arm: Remove unused Hdcr/Hcptr operands

Change-Id: Id20c235e765195750a18c85eb4d19cc96865ae81
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53264
Reviewed-by: Richard Cooper 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/isa/operands.isa
1 file changed, 15 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 82e7466..7655291 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -425,8 +425,6 @@
 'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
 'Hcr': cntrlReg('MISCREG_HCR'),
 'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
-'Hdcr': cntrlReg('MISCREG_HDCR'),
-'Hcptr': cntrlReg('MISCREG_HCPTR'),
 'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
 'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
 'Hstr': cntrlReg('MISCREG_HSTR'),

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id20c235e765195750a18c85eb4d19cc96865ae81
Gerrit-Change-Number: 53264
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Move conversion to int outside from m5.ticks.fromSeconds

2021-11-30 Thread Meatboy 106 (Gerrit) via gem5-dev 
Meatboy 106 has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53423 )



Change subject: base: Move conversion to int outside from  
m5.ticks.fromSeconds

..

base: Move conversion to int outside from m5.ticks.fromSeconds

m5.ticks.fromSeconds now converts a /s value to a /tick value while keeping  
the

original value type (typically float or int). Conversion to int with warning
upon excessive rounding error has been moved to m5.util.convert.toint.

Related Jira: https://gem5.atlassian.net/browse/GEM5-1118

Change-Id: Ia3b866991108a57de23e258ca685a24af9ee578e
---
M configs/common/Simulation.py
M src/python/gem5/components/processors/linear_generator_core.py
M src/python/m5/util/convert.py
M src/python/gem5/components/processors/complex_generator_core.py
M tests/gem5/configs/realview64-kvm-dual.py
M tests/gem5/configs/switcheroo.py
M src/python/gem5/components/processors/random_generator_core.py
M tests/gem5/configs/checkpoint.py
M src/python/m5/params.py
M configs/example/read_config.py
M src/python/m5/ticks.py
11 files changed, 53 insertions(+), 44 deletions(-)



diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 3b9efc0..477edc9 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -645,7 +645,7 @@
  "absolute max tick")
 explicit_maxticks += 1
 if options.maxtime:
-maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime)
+maxtick_from_maxtime = toint(m5.ticks.fromSeconds(options.maxtime))
 explicit_maxticks += 1
 if explicit_maxticks > 1:
 warn("Specified multiple of --abs-max-tick, --rel-max-tick,  
--maxtime."\

diff --git a/configs/example/read_config.py b/configs/example/read_config.py
index 5e64a9a..fae49e2 100644
--- a/configs/example/read_config.py
+++ b/configs/example/read_config.py
@@ -99,7 +99,7 @@
 # Convert to byte/tick
 value = 1.0 / float(param)
 # Convert to byte/s
-value = ticks.fromSeconds(value)
+value = toint(ticks.fromSeconds(value))
 return cls('%fB/s' % value)

 # These parameters have trickier parsing from .ini files than might be
diff --git  
a/src/python/gem5/components/processors/complex_generator_core.py  
b/src/python/gem5/components/processors/complex_generator_core.py

index 583b318..cd52657 100644
--- a/src/python/gem5/components/processors/complex_generator_core.py
+++ b/src/python/gem5/components/processors/complex_generator_core.py
@@ -268,9 +268,9 @@
 :param data_limit: The amount of data in bytes to read/write by the
 generator before stopping generation.
 """
-duration = fromSeconds(toLatency(duration))
+duration = toint(fromSeconds(toLatency(duration)))
 rate = toMemoryBandwidth(rate)
-period = fromSeconds(block_size / rate)
+period = toint(fromSeconds(block_size / rate))
 min_period = period
 max_period = period
 yield self.generator.createLinear(
@@ -314,9 +314,9 @@
 :param data_limit: The amount of data in bytes to read/write by the
 generator before stopping generation.
 """
-duration = fromSeconds(toLatency(duration))
+duration = toint(fromSeconds(toLatency(duration)))
 rate = toMemoryBandwidth(rate)
-period = fromSeconds(block_size / rate)
+period = toint(fromSeconds(block_size / rate))
 min_period = period
 max_period = period
 yield self.generator.createRandom(
diff --git a/src/python/gem5/components/processors/linear_generator_core.py  
b/src/python/gem5/components/processors/linear_generator_core.py

index e6bf441..dcbd14e 100644
--- a/src/python/gem5/components/processors/linear_generator_core.py
+++ b/src/python/gem5/components/processors/linear_generator_core.py
@@ -25,7 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.ticks import fromSeconds
-from m5.util.convert import toLatency, toMemoryBandwidth
+from m5.util.convert import toLatency, toMemoryBandwidth, toint
 from m5.objects import PyTrafficGen, Port, BaseTrafficGen

 from .abstract_core import AbstractCore
@@ -95,9 +95,9 @@

 :rtype: Iterator[BaseTrafficGen]
 """
-duration = fromSeconds(toLatency(self._duration))
+duration = toint(fromSeconds(toLatency(self._duration)))
 rate = toMemoryBandwidth(self._rate)
-period = fromSeconds(self._block_size / rate)
+period = toint(fromSeconds(self._block_size / rate))
 min_period = period
 max_period = period
 yield self.generator.createLinear(
diff --git a/src/python/gem5/components/processors/random_generator_core.py  
b/src/python/gem5/components/processors/random_generator_core.py

index 219040c..90ee315 100644
--- a/src/python/gem5/components/processors/random_generator_core.py
+++

[gem5-dev] Change in gem5/gem5[develop]: python: Do not convert bandwidth parameters to int

2021-11-30 Thread Meatboy 106 (Gerrit) via gem5-dev 
Meatboy 106 has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53424 )



Change subject: python: Do not convert bandwidth parameters to int
..

python: Do not convert bandwidth parameters to int

NetworkBandwidth and MemoryBandwidth parameters do not convert to int and  
back

to float anymore to avoid rounding errors for high bandwidth values. C++
parameter type now is double to enable higher precision.

Related Jira: https://gem5.atlassian.net/browse/GEM5-1118

Change-Id: I99c86be81d5c10094d3f015669cef0144b2e51e0
---
M src/python/m5/params.py
1 file changed, 21 insertions(+), 6 deletions(-)



diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 9a8e041..1c19123 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1760,7 +1760,7 @@
 code('%s _ret;' % ret)

 class NetworkBandwidth(float,ParamValue):
-cxx_type = 'float'
+cxx_type = 'double'
 ex_str = "1Gbps"
 cmd_line_settable = True

@@ -1781,8 +1781,8 @@
 # convert to seconds per byte
 value = 8.0 / float(self)
 # convert to ticks per byte
-value = toint(ticks.fromSeconds(value))
-return float(value)
+value = ticks.fromSeconds(value)
+return value

 def ini_str(self):
 return '%f' % self.getValue()
@@ -1799,7 +1799,7 @@
 code('%s (std::istringstream(%s) >> %s).eof();' % (ret, src, dest))

 class MemoryBandwidth(float,ParamValue):
-cxx_type = 'float'
+cxx_type = 'double'
 ex_str = "1GiB/s"
 cmd_line_settable = True

@@ -1819,8 +1819,8 @@
 if value:
 value = 1.0 / float(self)
 # convert to ticks per byte
-value = toint(ticks.fromSeconds(value))
-return float(value)
+value = ticks.fromSeconds(value)
+return value

 def ini_str(self):
 return '%f' % self.getValue()

--
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Gerrit-Change-Id: I99c86be81d5c10094d3f015669cef0144b2e51e0
Gerrit-Change-Number: 53424
Gerrit-PatchSet: 1
Gerrit-Owner: Meatboy 106 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: In SimpleIndirectPredictor, avoid an accidental nullptr deref.

2021-11-30 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53403 )



Change subject: cpu: In SimpleIndirectPredictor, avoid an accidental  
nullptr deref.

..

cpu: In SimpleIndirectPredictor, avoid an accidental nullptr deref.

The default value of IPredEntry::tag is 0, and if we just blindly
compare the tag we're looking for against this value, we might run into
cases where we match against an uninitialized IPredEntry. In that case,
IPredEntry::target has not been initialized, and if we try to use it in
lookup(...) we'll dereference nullptr and segfault.

To avoid that, we can just add one additional check that makes sure that
not only does the tag of the IPredEntry match, but also that the value
of target is not null, and so the IPredEntry *actually* has tag 0 and
isn't just uninitialized.

Change-Id: I892d0df7c00a0a4cd3ca215fe3a7586ddbca9395
---
M src/cpu/pred/simple_indirect.cc
1 file changed, 23 insertions(+), 1 deletion(-)



diff --git a/src/cpu/pred/simple_indirect.cc  
b/src/cpu/pred/simple_indirect.cc

index 2a1fc7a..f09cdee 100644
--- a/src/cpu/pred/simple_indirect.cc
+++ b/src/cpu/pred/simple_indirect.cc
@@ -104,7 +104,9 @@
 DPRINTF(Indirect, "Looking up %x (set:%d)\n", br_addr, set_index);
 const auto  = targetCache[set_index];
 for (auto way = iset.begin(); way != iset.end(); ++way) {
-if (way->tag == tag) {
+// tag may be 0 and match the default in way->tag, so we also have  
to

+// check that way->target has been initialized.
+if (way->tag == tag && way->target) {
 DPRINTF(Indirect, "Hit %x (target:%s)\n", br_addr,  
*way->target);

 set(target, *way->target);
 return true;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I892d0df7c00a0a4cd3ca215fe3a7586ddbca9395
Gerrit-Change-Number: 53403
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: incMissCount should be cache line based

2021-11-30 Thread Huang Jiasen (Gerrit) via gem5-dev 
Huang Jiasen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53383 )



Change subject: mem: incMissCount should be cache line based
..

mem: incMissCount should be cache line based

Change-Id: I0ced667255b3672fc3960c8187092d674958e17d
---
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/base.cc
3 files changed, 46 insertions(+), 1 deletion(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index dc21151..7608704 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -522,6 +522,9 @@
 mshrQueue.markPending(mshr);
 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
 } else {
+// Reset the reference counter once the entry is released.
+mshr->resetRefCnt();
+
 // while we deallocate an mshr from the queue we still have to
 // check the isFull condition before and after as we might
 // have been using the reserved entries already
@@ -1406,7 +1409,16 @@
 // Can't satisfy access normally... either no block (blk == nullptr)
 // or have block but need writable

-incMissCount(pkt);
+MSHR *mshr = mshrQueue.findMatch(pkt->getBlockAddr(blkSize),
+pkt->isSecure());
+if (mshr) {
+mshr->incRefCnt();
+if (mshr->getRefCnt() < 2) {
+incHitCount(pkt);
+}
+} else {
+incMissCount(pkt);
+}

 lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);

diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 6aaaf9e..54b6193 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -68,6 +68,7 @@
 targets(name + ".targets"),
 deferredTargets(name + ".deferredTargets")
 {
+refCnt = 0;
 }

 MSHR::TargetList::TargetList(const std::string )
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index a9deec6..e6c731a 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -80,8 +80,25 @@
 template
 friend class Queue;
 friend class MSHRQueue;
+friend class BaseCache;

   private:
+/**
+ * Increase refCnt.
+ */
+void incRefCnt() const {
+MSHR* ptr = const_cast(this);
+ptr->refCnt++;
+}
+/**
+ * Reset refCnt.
+ */
+void resetRefCnt() const {
+MSHR* ptr = const_cast(this);
+ptr->refCnt = 0;
+}
+/** Accumulated hit record to the same cache line */
+int refCnt;

 /** Flag set by downstream caches */
 bool downstreamPending;
@@ -119,6 +136,12 @@
 bool postDowngrade;

   public:
+/**
+ * Get refCnt.
+ */
+int getRefCnt() {
+return refCnt;
+}

 /** Track if we sent this as a whole line write or not */
 bool wasWholeLineWrite;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53383
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ced667255b3672fc3960c8187092d674958e17d
Gerrit-Change-Number: 53383
Gerrit-PatchSet: 1
Gerrit-Owner: Huang Jiasen 
Gerrit-MessageType: newchange
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