[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of jalr
Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33155 )
Change subject: arch-riscv: Fix disassembling of jalr
..
arch-riscv: Fix disassembling of jalr
The 'jalr' instruction of 'format Jump' should have an immediate as
offset, and the Rd register could not be always omitted. This patch
fixes the problem.
Example output:
jalr ra, -168(ra)
jalr zero, 0(ra)
jalr ra, 0(a5)
Note that this does not apply to the other two instructions of the
same format: 'c.jr' and 'c.jalr'.
Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Signed-off-by: Ian Jiang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33155
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 5 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 11c06aa..5c75695 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -283,10 +283,13 @@
%(class_name)s::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
-std::vector indices = {%(regs)s};
std::stringstream ss;
ss << mnemonic << ' ';
-ss << registerName(indices[0]);
+if (QUADRANT == 0x3)
+ss << registerName(_destRegIdx[0]) << ", "
+ << imm << "(" << registerName(_srcRegIdx[0]) << ")";
+else
+ss << registerName(_srcRegIdx[0]);
return ss.str();
}
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Gerrit-Change-Number: 33155
Gerrit-PatchSet: 4
Gerrit-Owner: Ian Jiang
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Ian Jiang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix bug in getting branch target of jalr
Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33234 )
Change subject: arch-riscv: Fix bug in getting branch target of jalr
..
arch-riscv: Fix bug in getting branch target of jalr
The 'jalr' instruction is:
jalr rd, offset(rs1)t=pc+4; pc=(x[rs1]+sext(offset))&~1; x[rd]=t
And the branch target address is
pc=(x[rs1]+sext(offset))&~1
When rs1 == rd, x[rs1] will be updated after instruction execution. In
this situation the branch target computed with previous rule is not
correct.
For example, here is a piece of trace with --debug-flags=Exec,IntRegs:
: Setting int reg 0 (0) to 0.
: Reading int reg 1 (1) as 0x12d0f8.
: Setting int reg 1 (1) to 0x1d100.
: jalr ra, -168(ra) : IntAlu : D=0x0001d100
And the branch target expected should be (0x12d0f8-168), but not
(0x1d100-168).
This patch fix the problem. First detect if 'jalr' has been executed
or not by comparing the difference between pc and npc. Then, if
executed, use npc as the branch target, else compute branch target
with previous rule. It also applies to the compressed form 'c.jalr'.
Change-Id: I3ced4c259620763acde440bb876c9a2a8e43515c
Signed-off-by: Ian Jiang
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 11c06aa..e124ef1 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -275,7 +275,13 @@
%(class_name)s::branchTarget(ThreadContext *tc) const
{
PCState pc = tc->pcState();
-pc.set((tc->readIntReg(_srcRegIdx[0].index()) + imm)&~0x1);
+Addr pc_addr = pc.pc();
+Addr npc_addr = pc.npc();
+if ((pc.compressed() && (npc_addr == pc_addr +
sizeof(MachInst)/2)) ||
+(!pc.compressed() && (npc_addr == pc_addr + sizeof(MachInst
+pc.set((tc->readIntReg(_srcRegIdx[0].index()) + imm)&~0x1);
+else
+pc.set(npc_addr);
return pc;
}
--
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Gerrit-Change-Id: I3ced4c259620763acde440bb876c9a2a8e43515c
Gerrit-Change-Number: 33234
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of jalr
Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33155 )
Change subject: arch-riscv: Fix disassembling of jalr
..
arch-riscv: Fix disassembling of jalr
The 'jalr' instruction of 'format Jump' should have an immediate as
offset. This patch fixes the problem.
Note that this is not valid for the other two instructions of the
same format: 'c.jr' and 'c.jalr'.
Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Signed-off-by: Ian Jiang
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 11c06aa..a0460b5 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -286,7 +286,10 @@
std::vector indices = {%(regs)s};
std::stringstream ss;
ss << mnemonic << ' ';
-ss << registerName(indices[0]);
+if ((machInst & 0x3) == 0x3)
+ss << imm << '(' << registerName(indices[0]) << ')';
+else
+ss << registerName(indices[0]);
return ss.str();
}
}};
--
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Gerrit-Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Gerrit-Change-Number: 33155
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Add float registers in copyRegs
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/32934 ) Change subject: arch-riscv: Add float registers in copyRegs .. arch-riscv: Add float registers in copyRegs The origin copyRegs() does not include float registers. This patch fixes the problem. Change-Id: If4ad04b1eda6035486197879ff3e04ff32dd87bb Signed-off-by: Ian Jiang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32934 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/riscv/utility.hh 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index 32eaff6..d4cf221 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -127,6 +127,10 @@ for (int i = 0; i < NumIntRegs; ++i) dest->setIntReg(i, src->readIntReg(i)); +// Second loop through the float registers. +for (int i = 0; i < NumFloatRegs; ++i) +dest->setFloatReg(i, src->readFloatReg(i)); + // Lastly copy PC/NPC dest->pcState(src->pcState()); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32934 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If4ad04b1eda6035486197879ff3e04ff32dd87bb Gerrit-Change-Number: 32934 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Jiang Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Ian Jiang Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Add float registers in copyRegs
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/32934 ) Change subject: arch-riscv: Add float registers in copyRegs .. arch-riscv: Add float registers in copyRegs The origin copyRegs() does not include float registers. This patch fixes the problem. Change-Id: If4ad04b1eda6035486197879ff3e04ff32dd87bb Signed-off-by: Ian Jiang --- M src/arch/riscv/utility.hh 1 file changed, 4 insertions(+), 0 deletions(-) diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index 32eaff6..d4cf221 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -127,6 +127,10 @@ for (int i = 0; i < NumIntRegs; ++i) dest->setIntReg(i, src->readIntReg(i)); +// Second loop through the float registers. +for (int i = 0; i < NumFloatRegs; ++i) +dest->setFloatReg(i, src->readFloatReg(i)); + // Lastly copy PC/NPC dest->pcState(src->pcState()); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32934 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If4ad04b1eda6035486197879ff3e04ff32dd87bb Gerrit-Change-Number: 32934 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Jiang Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of CSR instructions
Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32814 )
Change subject: arch-riscv: Fix disassembling of CSR instructions
..
arch-riscv: Fix disassembling of CSR instructions
The correct formats of CSR instructions are:
- mnemonic rd, csr, rs1
- mnemonic rd, csr, uimm
This patch fixes the problem.
Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Signed-off-by: Ian Jiang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32814
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/insts/standard.cc
1 file changed, 5 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index 9a9aa9d..35f9ccd 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -60,13 +60,15 @@
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
-if (_numSrcRegs > 0)
-ss << registerName(_srcRegIdx[0]) << ", ";
auto data = CSRData.find(csr);
if (data != CSRData.end())
ss << data->second.name;
else
-ss << "?? (" << hex << "0x" << csr << ")";
+ss << "?? (" << hex << "0x" << csr << dec << ")";
+if (_numSrcRegs > 0)
+ss << ", " << registerName(_srcRegIdx[0]);
+else
+ss << uimm;
return ss.str();
}
--
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Gerrit-Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Gerrit-Change-Number: 32814
Gerrit-PatchSet: 3
Gerrit-Owner: Ian Jiang
Gerrit-Reviewer: Alec Roelke
Gerrit-Reviewer: Ian Jiang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of CSR instructions
Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32814 )
Change subject: arch-riscv: Fix disassembling of CSR instructions
..
arch-riscv: Fix disassembling of CSR instructions
The correct formats of CSR instructions are:
- mnemonic rd, csr, rs1
- mnemonic rd, csr, uimm
This patch fixes the problem.
Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Signed-off-by: Ian Jiang
---
M src/arch/riscv/insts/standard.cc
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index e6c2b67..42e0129 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -60,13 +60,15 @@
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
-if (_numSrcRegs > 0)
-ss << registerName(_srcRegIdx[0]) << ", ";
auto data = CSRData.find(csr);
if (data != CSRData.end())
ss << data->second.name;
else
ss << "?? (" << hex << "0x" << csr << ")";
+if (_numSrcRegs > 0)
+ss << ", " << registerName(_srcRegIdx[0]);
+else
+ss << uimm;
return ss.str();
}
--
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Gerrit-Owner: Ian Jiang
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of all register instructions
Ian Jiang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/32694 ) Change subject: arch-riscv: Fix disassembling of all register instructions .. arch-riscv: Fix disassembling of all register instructions How many Rs to output in disassembling register instructions? It does not depend on wheather the register index is zero, but on the count of source registers. This patch fixes the problem. Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86 Signed-off-by: Ian Jiang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/riscv/insts/standard.cc 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index e6c2b67..9a9aa9d 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -48,9 +48,9 @@ stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << registerName(_srcRegIdx[0]); -if (_srcRegIdx[1].index() != 0) +if (_numSrcRegs >= 2) ss << ", " << registerName(_srcRegIdx[1]); -if (_srcRegIdx[2].index() != 0) +if (_numSrcRegs >= 3) ss << ", " << registerName(_srcRegIdx[2]); return ss.str(); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32694 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86 Gerrit-Change-Number: 32694 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Jiang Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Ian Jiang Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of all register instructions
Ian Jiang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/32694 ) Change subject: arch-riscv: Fix disassembling of all register instructions .. arch-riscv: Fix disassembling of all register instructions How many Rs to output in disassembling register instructions? It does not depend on wheather the register index is zero, but on the count of source registers. This patch fixes the problem. Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86 Signed-off-by: Ian Jiang --- M src/arch/riscv/insts/standard.cc 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index e6c2b67..9a9aa9d 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -48,9 +48,9 @@ stringstream ss; ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << registerName(_srcRegIdx[0]); -if (_srcRegIdx[1].index() != 0) +if (_numSrcRegs >= 2) ss << ", " << registerName(_srcRegIdx[1]); -if (_srcRegIdx[2].index() != 0) +if (_numSrcRegs >= 3) ss << ", " << registerName(_srcRegIdx[2]); return ss.str(); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32694 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86 Gerrit-Change-Number: 32694 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Jiang Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Add checkpoint parameters for VMA list
Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31875 )
Change subject: sim: Add checkpoint parameters for VMA list
..
sim: Add checkpoint parameters for VMA list
Add checkpoint parameters (together with corresponding serialization
and unserialization) for VMA list of class MemState into a separate
section named 'vmalist'.
Without these VMA list parameters, a page table fault will occur when
running with --restore-simpoint-checkpoint, because of an empty VMA
list. For example:
$ ./build/RISCV/gem5.debug --debug-flags=Exec configs/example/se.py \
-c tests/test-progs/hello/bin/riscv/linux/hello \
--cpu-type=NonCachingSimpleCPU --restore-simpoint-checkpoint \
--checkpoint-dir m5out/ -r 2
...
2404000: system.switch_cpus: T0 : @_int_malloc+3392: sd a5, 8(a0) \
: MemWrite : D=0x0001ed21 A=0x862e8
panic: Page table fault when accessing virtual address 0x862e8
...
Example checkpoint output:
[system.cpu.workload.vmalist]
size=3
[system.cpu.workload.vmalist.Vma0]
name=stack
addrRangeStart=...
addrRangeEnd=...
[system.cpu.workload.vmalist.Vma1]
name=heap
addrRangeStart=...
addrRangeEnd=...
[system.cpu.workload.vmalist.Vma2]
...
Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Signed-off-by: Ian Jiang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31875
Reviewed-by: Daniel Carvalho
Reviewed-by: Bobby R. Bruce
Reviewed-by: Alexandru Duțu
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/mem_state.hh
1 file changed, 25 insertions(+), 0 deletions(-)
Approvals:
Alexandru Duțu: Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index 1ca80da..c052389 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -190,7 +190,18 @@
paramOut(cp, "stackMin", _stackMin);
paramOut(cp, "nextThreadStackBase", _nextThreadStackBase);
paramOut(cp, "mmapEnd", _mmapEnd);
+
+ScopedCheckpointSection sec(cp, "vmalist");
+paramOut(cp, "size", _vmaList.size());
+int count = 0;
+for (auto vma : _vmaList) {
+ScopedCheckpointSection sec(cp, csprintf("Vma%d", count++));
+paramOut(cp, "name", vma.getName());
+paramOut(cp, "addrRangeStart", vma.start());
+paramOut(cp, "addrRangeEnd", vma.end());
+}
}
+
void
unserialize(CheckpointIn ) override
{
@@ -201,6 +212,20 @@
paramIn(cp, "stackMin", _stackMin);
paramIn(cp, "nextThreadStackBase", _nextThreadStackBase);
paramIn(cp, "mmapEnd", _mmapEnd);
+
+int count;
+ScopedCheckpointSection sec(cp, "vmalist");
+paramIn(cp, "size", count);
+for (int i = 0; i < count; ++i) {
+ScopedCheckpointSection sec(cp, csprintf("Vma%d", i));
+std::string name;
+Addr start;
+Addr end;
+paramIn(cp, "name", name);
+paramIn(cp, "addrRangeStart", start);
+paramIn(cp, "addrRangeEnd", end);
+_vmaList.emplace_back(AddrRange(start, end), _pageBytes, name);
+}
}
/**
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Gerrit-Change-Number: 31875
Gerrit-PatchSet: 3
Gerrit-Owner: Ian Jiang
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Ian Jiang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of float register instructions
Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32054 )
Change subject: arch-riscv: Fix disassembling of float register instructions
..
arch-riscv: Fix disassembling of float register instructions
In disassembling of float register instructions, Gem5 always gives 2
source registers rs1 and rs2. However, this is not correct for Mul-Add
instructions which have three rs1, rs2, and rs3, and for Move, Convert
instructions which have only rs1.
For example: (Gem5 output vs Expected)
- fmadd.d fa0,fa0,fa4 vs fmadd.d fa0,fa0,fa4,fa5
- fcvt.d.l fa4,a6,zero vs fcvt.d.l fa4,a6
This patch fixes the problem.
Change-Id: I02d840eab602ac4a9782911b3cdff2935dfe5e68
Signed-off-by: Ian Jiang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32054
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/insts/standard.cc
1 file changed, 5 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index bb621ae..e6c2b67 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -47,8 +47,11 @@
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[1]);
+registerName(_srcRegIdx[0]);
+if (_srcRegIdx[1].index() != 0)
+ss << ", " << registerName(_srcRegIdx[1]);
+if (_srcRegIdx[2].index() != 0)
+ss << ", " << registerName(_srcRegIdx[2]);
return ss.str();
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I02d840eab602ac4a9782911b3cdff2935dfe5e68
Gerrit-Change-Number: 32054
Gerrit-PatchSet: 2
Gerrit-Owner: Ian Jiang
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Ian Jiang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix disassembling of float register instructions
Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32054 )
Change subject: arch-riscv: Fix disassembling of float register instructions
..
arch-riscv: Fix disassembling of float register instructions
In disassembling of float register instructions, Gem5 always gives 2
source registers rs1 and rs2. However, this is not correct for Mul-Add
instructions which have three rs1, rs2, and rs3, and for Move, Convert
instructions which have only rs1.
For example: (Gem5 output vs Expected)
- fmadd.d fa0,fa0,fa4 vs fmadd.d fa0,fa0,fa4,fa5
- fcvt.d.l fa4,a6,zero vs fcvt.d.l fa4,a6
This patch fixes the problem.
Change-Id: I02d840eab602ac4a9782911b3cdff2935dfe5e68
Signed-off-by: Ian Jiang
---
M src/arch/riscv/insts/standard.cc
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index bb621ae..e6c2b67 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -47,8 +47,11 @@
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[1]);
+registerName(_srcRegIdx[0]);
+if (_srcRegIdx[1].index() != 0)
+ss << ", " << registerName(_srcRegIdx[1]);
+if (_srcRegIdx[2].index() != 0)
+ss << ", " << registerName(_srcRegIdx[2]);
return ss.str();
}
--
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Gerrit-Change-Id: I02d840eab602ac4a9782911b3cdff2935dfe5e68
Gerrit-Change-Number: 32054
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Move checkpoint parameters for ptable into seperate section
Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31874 )
Change subject: sim: Move checkpoint parameters for ptable into seperate
section
..
sim: Move checkpoint parameters for ptable into seperate section
In checkpoint output files, the parameters for page table including
size and entries are organized not very clearly. For example:
[system.cpu.workload]
...
ptable.size=...
[system.cpu.workload.Entry0]
vaddr=...
paddr=...
flags=...
[system.cpu.workload.Entry1]
...
This commit moves these parameters into a separate section named
'ptable'. For example:
[system.cpu.workload.ptable]
size=...
[system.cpu.workload.ptable.Entry0]
vaddr=...
paddr=...
flags=...
[system.cpu.workload.ptable.Entry1]
...
Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Signed-off-by: Ian Jiang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31874
Reviewed-by: Daniel Carvalho
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/mem/page_table.cc
1 file changed, 4 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 400500b..601b9c5 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -168,7 +168,8 @@
void
EmulationPageTable::serialize(CheckpointOut ) const
{
-paramOut(cp, "ptable.size", pTable.size());
+ScopedCheckpointSection sec(cp, "ptable");
+paramOut(cp, "size", pTable.size());
PTable::size_type count = 0;
for (auto : pTable) {
@@ -185,7 +186,8 @@
EmulationPageTable::unserialize(CheckpointIn )
{
int count;
-paramIn(cp, "ptable.size", count);
+ScopedCheckpointSection sec(cp, "ptable");
+paramIn(cp, "size", count);
for (int i = 0; i < count; ++i) {
ScopedCheckpointSection sec(cp, csprintf("Entry%d", i));
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Gerrit-Change-Number: 31874
Gerrit-PatchSet: 3
Gerrit-Owner: Ian Jiang
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Ian Jiang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add checkpoint parameters for VMA list
Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31875 )
Change subject: sim: Add checkpoint parameters for VMA list
..
sim: Add checkpoint parameters for VMA list
Add checkpoint parameters (together with corresponding serialization
and unserialization) for VMA list of class MemState into a separate
section named 'vmalist'.
Without these VMA list parameters, a page table fault will occur when
running with --restore-simpoint-checkpoint, because of an empty VMA
list. For example:
$ ./build/RISCV/gem5.debug --debug-flags=Exec configs/example/se.py \
-c tests/test-progs/hello/bin/riscv/linux/hello \
--cpu-type=NonCachingSimpleCPU --restore-simpoint-checkpoint \
--checkpoint-dir m5out/ -r 2
...
2404000: system.switch_cpus: T0 : @_int_malloc+3392: sd a5, 8(a0) \
: MemWrite : D=0x0001ed21 A=0x862e8
panic: Page table fault when accessing virtual address 0x862e8
...
Example checkpoint output:
[system.cpu.workload.vmalist]
size=3
[system.cpu.workload.vmalist.Vma0]
vmaName=stack
addrRangeStart=...
addrRangeEnd=...
[system.cpu.workload.vmalist.Vma1]
vmaName=heap
addrRangeStart=...
addrRangeEnd=...
[system.cpu.workload.vmalist.Vma2]
...
Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Signed-off-by: Ian Jiang
---
M src/sim/mem_state.hh
1 file changed, 25 insertions(+), 0 deletions(-)
diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index 1ca80da..bb4fab3 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -190,7 +190,18 @@
paramOut(cp, "stackMin", _stackMin);
paramOut(cp, "nextThreadStackBase", _nextThreadStackBase);
paramOut(cp, "mmapEnd", _mmapEnd);
+
+ScopedCheckpointSection sec(cp, csprintf("vmalist"));
+paramOut(cp, "size", _vmaList.size());
+int count = 0;
+for (auto vma : _vmaList) {
+ScopedCheckpointSection sec(cp, csprintf("Vma%d", count++));
+paramOut(cp, "vmaName", vma.getName());
+paramOut(cp, "addrRangeStart", vma.start());
+paramOut(cp, "addrRangeEnd", vma.end());
+}
}
+
void
unserialize(CheckpointIn ) override
{
@@ -201,6 +212,20 @@
paramIn(cp, "stackMin", _stackMin);
paramIn(cp, "nextThreadStackBase", _nextThreadStackBase);
paramIn(cp, "mmapEnd", _mmapEnd);
+
+int count;
+ScopedCheckpointSection sec(cp, csprintf("vmalist"));
+paramIn(cp, "size", count);
+for (int i = 0; i < count; ++i) {
+ScopedCheckpointSection sec(cp, csprintf("Vma%d", i));
+std::string name;
+Addr start;
+Addr end;
+paramIn(cp, "vmaName", name);
+paramIn(cp, "addrRangeStart", start);
+paramIn(cp, "addrRangeEnd", end);
+_vmaList.emplace_back(AddrRange(start, end), _pageBytes, name);
+}
}
/**
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Move checkpoint parameters for ptable into seperate section
Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31874 )
Change subject: sim: Move checkpoint parameters for ptable into seperate
section
..
sim: Move checkpoint parameters for ptable into seperate section
In checkpoint output files, the parameters for page table including
size and entries are organized not very clearly. For example:
[system.cpu.workload]
...
ptable.size=...
[system.cpu.workload.Entry0]
vaddr=...
paddr=...
flags=...
[system.cpu.workload.Entry1]
...
This commit moves these parameters into a separate section named
'ptable'. For example:
[system.cpu.workload.ptable]
size=...
[system.cpu.workload.ptable.Entry0]
vaddr=...
paddr=...
flags=...
[system.cpu.workload.ptable.Entry1]
...
Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Signed-off-by: Ian Jiang
---
M src/mem/page_table.cc
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 400500b..20faf9b 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -168,7 +168,8 @@
void
EmulationPageTable::serialize(CheckpointOut ) const
{
-paramOut(cp, "ptable.size", pTable.size());
+ScopedCheckpointSection sec(cp, csprintf("ptable"));
+paramOut(cp, "size", pTable.size());
PTable::size_type count = 0;
for (auto : pTable) {
@@ -185,7 +186,8 @@
EmulationPageTable::unserialize(CheckpointIn )
{
int count;
-paramIn(cp, "ptable.size", count);
+ScopedCheckpointSection sec(cp, csprintf("ptable"));
+paramIn(cp, "size", count);
for (int i = 0; i < count; ++i) {
ScopedCheckpointSection sec(cp, csprintf("Entry%d", i));
--
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Gerrit-Change-Number: 31874
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang
Gerrit-MessageType: newchange
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