from:"Jason Lowe\-Power \(Gerrit\) via gem5\-dev"

[gem5-dev] [NoOp] Change in gem5/gem5[develop]: configs: Fix SPEC benchmarks example scripts

2023-07-10 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71738?usp=email )


Change subject: configs: Fix SPEC benchmarks example scripts
..

configs: Fix SPEC benchmarks example scripts

This small change fixes the gem5_library example
scripts for SPEC benchmarks to make them compatible
with the latest version of the std library.

Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71738
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
0 files changed, 0 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass





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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
Gerrit-Change-Number: 71738
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
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[gem5-dev] [M] Change in gem5/gem5[release-staging-v23-0]: misc: Add release notes for v23.0

2023-06-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71758?usp=email )



Change subject: misc: Add release notes for v23.0
..

misc: Add release notes for v23.0

Change-Id: I003f170339e69a445586fe0486a1db595a10683f
Signed-off-by: Jason Lowe-Power 
---
M RELEASE-NOTES.md
1 file changed, 96 insertions(+), 0 deletions(-)



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 931be69..5d55976 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -1,3 +1,99 @@
+# Version 23.0
+
+This release has approximately 500 contributions from 50 unique  
contributors.

+This release incorporates ...
+
+The big news in this release is gem5's migration from Gerrit (at  
gem5.googlesource.com) to GitHub (at github.com/gem5/).
+From now on, please issue *pull requests* to GitHub instead of change  
requests on Gerrit.

+Gerrit will be available in read-only mode to access prior conversations.
+
+## Significant API and user-facing changes
+
+### Major renaming of CPU stats
+
+The CPU stats have been renamed.
+See  for details.
+
+Now, each stage (fetch, execute, commit) have their own stat group.
+Stats that are shared between the different CPU model (O3, Minor, Simple)  
now have the exact same names.

+
+**Important:** Some stat names were misleading before this change.
+With this change, stats with the same names between different CPU models  
have the same meaning.

+
+### `fs.py` and `se.py` deprecated
+
+These scripts have not been well supported for many gem5 releases.
+With gem5 23.0, we have officially deprecated these scripts.
+They have been moved into the `deprecated` directory, **but they will be  
removed in a future release.**

+As a replacement, we strongly suggest using the gem5 standard library.
+
+### Other API changes
+
+- Removed deprecated namespaces. Namespace names were updated a couple of  
releases ago. This release removes the old names.
+- *Use `MemberEventWrapper` in favor of `EventWrapper` for instance member  
functions

+- Add an extension mechanism to `Packet` and `Request`
+- Set x86 CPU vendor string to "HygoneGenuine" to better support GLIBC
+
+## New features and improvements
+
+### Large improvements to gem5 resources and gem5 vision website
+
+We now have a new web portal for the gem5 resources:  


+
+This web portal will allow users to browse the resources available (e.g.,  
disk images, kernels, workloads, binaries, simpoints, etc.) to use  
out-of-the-box with the gem5 standard library.
+You can filter based on architecture, resource type, and compatible gem5  
versions.

+
+For each resource, there are examples of how to use the resource and  
pointers to examples using the resource in the gem5 codebase.

+
+More information can be found on gem5's website:  


+
+For instance, you can now add the following code to your config script to  
run the "ubuntu-boot" workload.

+
+```python
+board.set_workload(Workload("x86-ubuntu-18.04-boot"))
+```
+
+We will be expanding gem5 resources with more workloads over the course of  
the next release.
+If you would like to contribute to gem5 resources by uploading your own  
workloads, disk images, etc., please create and issue on GitHub.

+
+In addition to the new gem5 Resources web portal, the gem5 Resources API  
has been significantly updated and improved.
+There are now much simpler functions for getting resources such as  
`obtain_resource()` that will download the resource by name and  
return a reference that can be used (e.g., as a binary in `set_se_workload`  
function on the board).
+We also added the `set_workload` function that is a function of the  
`Board` that allows you to use a `Workload` from gem5 Resources with a  
board.
+This function will set up the workload including the disk image, kernel,  
and command line for full system workloads.
+Additionally, we have added support for SimPoints and checkpoints as  
workloads.

+
+### Arm v9 improvements
+
+Many improvements to Arm so that gem5 is mostly compatible with Armv9.2.
+
+Support for some Arm SME (matrix extensions) has been added and more  
support for Arm SVE is included this release.

+
+### Add support for DRAMSys
+
+gem5 can now use DRAMSys  as a DRAM  
backend.

+
+### Standard library improvements and new components
+
+- Add MESI_Three_Level component.
+- The gem5 standard library now supports both SimPoint and LoopPoint  
resources.

+- gem5 also now supports ELFies and LoopPoint analysis output from Sniper.
+- DRAMSys is supported in the stdlib.
+
+## Bugfixes and other small improvements
+
+- Lots of RISC-V bugfixes and improvements. Applications should be more  
stable now.

+- Fully implement RISC-V zbkb, Zk extension
+- Implement rv32 zicsr.
+- Remove deprecat

[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Fix SPEC benchmarks example scripts

2023-06-14 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71738?usp=email )



Change subject: configs: Fix SPEC benchmarks example scripts
..

configs: Fix SPEC benchmarks example scripts

This small change fixes the gem5_library example
scripts for SPEC benchmarks to make them compatible
with the latest version of the std library.

Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
---
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
M configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

index 60d93eb..10d5da0 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -262,7 +262,7 @@
 kernel=Resource("x86-linux-kernel-4.19.83"),
 # The location of the x86 SPEC CPU 2017 image
 disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
 ),
 readfile_contents=command,
 )
diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

index c491c9b..cb5f5d1 100644
--- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
@@ -278,7 +278,7 @@
 kernel=Resource("x86-linux-kernel-4.19.83"),
 # The location of the x86 SPEC CPU 2017 image
 disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
 ),
 readfile_contents=command,
 )

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[gem5-dev] [XS] Change in gem5/gem5[develop]: python: Ignore -s as gem5 option

2023-06-13 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71502?usp=email )


Change subject: python: Ignore -s as gem5 option
..

python: Ignore -s as gem5 option

This enables more compatibility with the normal python binary. This is
needed to get multiprocessing to work on some systems.

Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71502
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M src/python/m5/main.py
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index a68279b..4701dfa 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -193,6 +193,13 @@
 callback=collect_args,
 )

+option(
+"-s",
+action="store_true",
+help="IGNORED, only for compatibility with python. don't"
+"add user site directory to sys.path; also PYTHONNOUSERSITE",
+)
+
 # Statistics options
 group("Statistics Options")
 option(

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Gerrit-Change-Number: 71502
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: python: Ignore -s as gem5 option

2023-06-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71502?usp=email )



Change subject: python: Ignore -s as gem5 option
..

python: Ignore -s as gem5 option

This enables more compatibility with the normal python binary. This is
needed to get multiprocessing to work on some systems.

Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Signed-off-by: Jason Lowe-Power 
---
M src/python/m5/main.py
1 file changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index a68279b..4701dfa 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -193,6 +193,13 @@
 callback=collect_args,
 )

+option(
+"-s",
+action="store_true",
+help="IGNORED, only for compatibility with python. don't"
+"add user site directory to sys.path; also PYTHONNOUSERSITE",
+)
+
 # Statistics options
 group("Statistics Options")
 option(

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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add os import to marshall

2023-05-23 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70918?usp=email )


Change subject: scons: Add os import to marshall
..

scons: Add os import to marshall

This file was missing the `import os` after
I3ad28b6ee52fd347d2fe71f279baab629e88d12c

Change-Id: I7fde59e92f03fd240f48a304488d77628bfdb852
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70918
Maintainer: Jason Lowe-Power 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M build_tools/marshal.py
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/build_tools/marshal.py b/build_tools/marshal.py
index 4a1522f..58c78e1 100644
--- a/build_tools/marshal.py
+++ b/build_tools/marshal.py
@@ -50,6 +50,7 @@

 import locale
 import marshal
+import os
 import sys
 import zlib


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Gerrit-MessageType: merged
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Gerrit-Change-Id: I7fde59e92f03fd240f48a304488d77628bfdb852
Gerrit-Change-Number: 70918
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Luming Wang 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add os import to marshall

2023-05-23 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70918?usp=email )



Change subject: scons: Add os import to marshall
..

scons: Add os import to marshall

This file was missing the `import os` after
I3ad28b6ee52fd347d2fe71f279baab629e88d12c

Change-Id: I7fde59e92f03fd240f48a304488d77628bfdb852
Signed-off-by: Jason Lowe-Power 
---
M build_tools/marshal.py
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/build_tools/marshal.py b/build_tools/marshal.py
index 4a1522f..58c78e1 100644
--- a/build_tools/marshal.py
+++ b/build_tools/marshal.py
@@ -50,6 +50,7 @@

 import locale
 import marshal
+import os
 import sys
 import zlib


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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Add progress bars for long functions

2023-02-27 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67472?usp=email )


Change subject: stdlib: Add progress bars for long functions
..

stdlib: Add progress bars for long functions

This adds a progress bar for downloading large files and computing
md5sums on large files.

Change-Id: Iddc9faf61e861837cc1e2e3b3dbdbeebd6ccf529
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67472
Tested-by: kokoro 
Reviewed-by: Melissa Jost 
Maintainer: Jason Lowe-Power 
---
A optional-requirements.txt
M src/python/SConscript
M src/python/gem5/resources/downloader.py
M src/python/gem5/resources/md5_utils.py
A src/python/gem5/utils/progress_bar.py
5 files changed, 132 insertions(+), 6 deletions(-)

Approvals:
  kokoro: Regressions pass
  Melissa Jost: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/optional-requirements.txt b/optional-requirements.txt
new file mode 100644
index 000..f88787d
--- /dev/null
+++ b/optional-requirements.txt
@@ -0,0 +1 @@
+tqdm==4.64.1
diff --git a/src/python/SConscript b/src/python/SConscript
index 900723b..b0f11dd 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -267,6 +267,7 @@
 PySource('gem5.utils', 'gem5/utils/__init__.py')
 PySource('gem5.utils', 'gem5/utils/filelock.py')
 PySource('gem5.utils', 'gem5/utils/override.py')
+PySource('gem5.utils', 'gem5/utils/progress_bar.py')
 PySource('gem5.utils', 'gem5/utils/requires.py')
 PySource('gem5.utils.multiprocessing',
 'gem5/utils/multiprocessing/__init__.py')
diff --git a/src/python/gem5/resources/downloader.py  
b/src/python/gem5/resources/downloader.py

index 4a2ed5d..24b8970 100644
--- a/src/python/gem5/resources/downloader.py
+++ b/src/python/gem5/resources/downloader.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 The Regents of the University of California
+# Copyright (c) 2021-2023 The Regents of the University of California
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -42,6 +42,7 @@
 from typing import List, Dict, Set, Optional

 from .md5_utils import md5_file, md5_dir
+from ..utils.progress_bar import tqdm, progress_hook

 from ..utils.filelock import FileLock

@@ -286,10 +287,26 @@
 # get the file as a bytes blob
 request = urllib.request.Request(url)
 with urllib.request.urlopen(request, context=ctx) as fr:
-with open(download_to, "wb") as fw:
-fw.write(fr.read())
+with tqdm.wrapattr(
+open(download_to, "wb"),
+"write",
+miniters=1,
+desc="Downloading {download_to}",
+total=getattr(fr, "length", None),
+) as fw:
+for chunk in fr:
+fw.write(chunk)
 else:
-urllib.request.urlretrieve(url, download_to)
+with tqdm(
+unit="B",
+unit_scale=True,
+unit_divisor=1024,
+miniters=1,
+desc=f"Downloading {download_to}",
+) as t:
+urllib.request.urlretrieve(
+url, download_to, reporthook=progress_hook(t)
+)
 return
 except HTTPError as e:
 # If the error code retrieved is retryable, we retry using a
diff --git a/src/python/gem5/resources/md5_utils.py  
b/src/python/gem5/resources/md5_utils.py

index d7212ab..f4a1a87 100644
--- a/src/python/gem5/resources/md5_utils.py
+++ b/src/python/gem5/resources/md5_utils.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2022 The Regents of the University of California
+# Copyright (c) 2022-2023 The Regents of the University of California
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -31,7 +31,22 @@

 def _md5_update_from_file(filename: Path, hash: Hash) -> Hash:
 assert filename.is_file()
-with open(str(filename), "rb") as f:
+
+if filename.stat().st_size < 1024 * 1024 * 100:
+from ..utils.progress_bar import FakeTQDM
+
+# if the file is less than 100MB, no need to show a progress bar.
+tqdm = FakeTQDM()
+else:
+from ..utils.progress_bar import tqdm
+
+with tqdm.wrapattr(
+open(str(filename), "rb"),
+"read",
+miniters=1,
+desc=f"Computing md5sum on {filename}",
+total=filename.stat().st_size,
+) as f:
 for chunk in iter(lambda: f.read(4096), b""):
 hash.update(chunk)
 return hash
diff --git a/src/python/gem5/utils/progress_bar.py  
b/src/python/gem5/utils/progress_bar.py

new file mode 100644
index 000..0ac1320
--- /dev/null
+++ b/src/python/gem5/utils/pr

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Add fatal in BaseCPU for wrong workloads

2023-02-25 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67937?usp=email )


Change subject: cpu: Add fatal in BaseCPU for wrong workloads
..

cpu: Add fatal in BaseCPU for wrong workloads

The CPU models assume that the number of workloads (Processes) is equal
to the number of threads when using SE mode. This wasn't checked leading
to a segfault if there were no workloads. This change makes the error
more clear.

Change-Id: I9a7b21112b8f819c6eeca944ee0d73ae9ce9a57b
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67937
Reviewed-by: Ayaz Akram 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/base.cc
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Ayaz Akram: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 60d443a..d2c0a78 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -182,6 +182,12 @@
   "of threads (%i).\n", params().isa.size(), numThreads);
 }

+if (!FullSystem && params().workload.size() != numThreads) {
+fatal("Number of processes (cpu.workload) (%i) assigned to the  
CPU "

+  "does not equal number of threads (%i).\n",
+  params().workload.size(), numThreads);
+}
+
 modelResetPort.onChange([this](const bool &new_val) {
 setReset(new_val);
 });

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Gerrit-Change-Number: 67937
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Add support for ELFies

2023-02-17 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68038?usp=email )



Change subject: stdlib: Add support for ELFies
..

stdlib: Add support for ELFies

This enables the stdlib to load and run ELFie-based binaries

See https://github.com/intel/pinball2elf for more details on ELFies

Change-Id: Ic1b624df64da1c77afc0907257a9e989488912ec
Signed-off-by: Jason Lowe-Power 
---
M src/python/SConscript
M src/python/gem5/components/boards/se_binary_workload.py
A src/python/gem5/resources/elfie.py
3 files changed, 114 insertions(+), 0 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index f401c03..900723b 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -263,6 +263,7 @@
 PySource('gem5.resources', 'gem5/resources/resource.py')
 PySource('gem5.resources', 'gem5/resources/workload.py')
 PySource('gem5.resources', 'gem5/resources/looppoint.py')
+PySource('gem5.resources', 'gem5/resources/elfie.py')
 PySource('gem5.utils', 'gem5/utils/__init__.py')
 PySource('gem5.utils', 'gem5/utils/filelock.py')
 PySource('gem5.utils', 'gem5/utils/override.py')
diff --git a/src/python/gem5/components/boards/se_binary_workload.py  
b/src/python/gem5/components/boards/se_binary_workload.py

index ebdfa40..e4aa1ba 100644
--- a/src/python/gem5/components/boards/se_binary_workload.py
+++ b/src/python/gem5/components/boards/se_binary_workload.py
@@ -35,6 +35,7 @@
 SimpointDirectoryResource,
 )

+from gem5.resources.elfie import ELFieInfo
 from gem5.resources.looppoint import Looppoint

 from m5.objects import SEWorkload, Process
@@ -209,6 +210,37 @@
 checkpoint=checkpoint,
 )

+def set_se_elfie_workload(
+self,
+elfie: AbstractResource,
+elfie_info: ELFieInfo,
+arguments: List[str] = [],
+checkpoint: Optional[Union[Path, AbstractResource]] = None,
+) -> None:
+"""Set up the system to run a ELFie workload.
+
+**Limitations**
+* Dynamically linked executables are partially supported when the  
host

+  ISA and the simulated ISA are the same.
+
+:param elfie: The resource encapsulating the binary elfie to be  
run.

+:param arguments: The input arguments for the binary
+:param elfie_info: The ELFieInfo object that contain all the  
information

+for the ELFie
+"""
+
+assert isinstance(elfie_info, ELFieInfo)
+self._elfie_info_object = elfie_info
+
+self._elfie_info_object.setup_processor(self.get_processor())
+
+# Call set_se_binary_workload after LoopPoint setup is complete
+self.set_se_binary_workload(
+binary=elfie,
+arguments=arguments,
+checkpoint=checkpoint,
+)
+
 def get_looppoint(self) -> Looppoint:
 """
 Returns the LoopPoint object set. If no LoopPoint object has been  
set
diff --git a/src/python/gem5/resources/elfie.py  
b/src/python/gem5/resources/elfie.py

new file mode 100644
index 000..ae51388
--- /dev/null
+++ b/src/python/gem5/resources/elfie.py
@@ -0,0 +1,67 @@
+# Copyright (c) 2023 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import PcCountPair
+from m5.objects import PcCountTrackerManager
+
+from typing import List
+
+
+class ELFieInfo:
+"""Stores information to load/run ELFies
+
+See https://github.com/

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-x86,sim-se: Ignore the some mem syscalls

2023-02-17 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68037?usp=email )



Change subject: arch-x86,sim-se: Ignore the some mem syscalls
..

arch-x86,sim-se: Ignore the some mem syscalls

This makes the Linux SE mode ignore mlockall and modify_ldt. It is
needed to get ELFies working.

Change-Id: I9fce3c6a5531e5f1bb094c2d0587fa330d2892a9
Signed-off-by: Jason Lowe-Power 
---
M src/arch/x86/linux/syscall_tbl64.cc
1 file changed, 15 insertions(+), 2 deletions(-)



diff --git a/src/arch/x86/linux/syscall_tbl64.cc  
b/src/arch/x86/linux/syscall_tbl64.cc

index 1e7274c..26299d8 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -194,10 +194,10 @@
 { 148, "sched_rr_get_interval" },
 { 149, "mlock" },
 { 150, "munlock" },
-{ 151, "mlockall" },
+{ 151, "mlockall", ignoreFunc },
 { 152, "munlockall" },
 { 153, "vhangup" },
-{ 154, "modify_ldt" },
+{ 154, "modify_ldt", ignoreFunc },
 { 155, "pivot_root" },
 { 156, "_sysctl" },
 { 157, "prctl", ignoreFunc },

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[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Add fatal in BaseCPU for wrong workloads

2023-02-14 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67937?usp=email )



Change subject: cpu: Add fatal in BaseCPU for wrong workloads
..

cpu: Add fatal in BaseCPU for wrong workloads

The CPU models assume that the number of workloads (Processes) is equal
to the number of threads when using SE mode. This wasn't checked leading
to a segfault if there were no workloads. This change makes the error
more clear.

Change-Id: I9a7b21112b8f819c6eeca944ee0d73ae9ce9a57b
Signed-off-by: Jason Lowe-Power 
---
M src/cpu/base.cc
1 file changed, 23 insertions(+), 0 deletions(-)



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 60d443a..9095072 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -181,10 +181,18 @@
 fatal("Number of ISAs (%i) assigned to the CPU does not equal  
number "

   "of threads (%i).\n", params().isa.size(), numThreads);
 }
+<<< Updated upstream

 modelResetPort.onChange([this](const bool &new_val) {
 setReset(new_val);
 });
+===
+if (!FullSystem && params().workload.size() != numThreads) {
+fatal("Number of processes (cpu.workload) (%i) assigned to the  
CPU "

+  "does not equal number of threads (%i).\n",
+  params().workload.size(), numThreads);
+}
+>>> Stashed changes
 }

 void

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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix compiler-tests.sh build args passing

2022-12-17 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66772?usp=email )


Change subject: tests: Fix compiler-tests.sh build args passing
..

tests: Fix compiler-tests.sh build args passing

Reverts this fix:
https://gem5-review.googlesource.com/c/public/gem5/+/66631

While this did fix the case where no build args were passed, it broke
the case where build args were passed.

This fix ensures the script works in both cases.

Change-Id: I6cc8cc0c2a10c801d4a59e54b070383ac8ee93ae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66772
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/compiler-tests.sh
1 file changed, 31 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index f16e8e5..f5d4bb1 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -76,7 +76,13 @@
 base_url="gcr.io/gem5-test"

 # Arguments passed into scons on every build target test.
-build_args="$@"
+if [ $# -eq 0 ];then
+# If none is sepcified by the user we pass "-j1" (compile on one  
thread).

+# If `build_args` is left as an empty string, this script will fail.
+build_args="-j1"
+else
+build_args="$@"
+fi

 # Testing directory variables
 mkdir -p "${build_dir}" # Create the build directory if it doesn't exist.
@@ -135,7 +141,7 @@
 docker run --rm -v "${gem5_root}":"/gem5" -u $UID:$GID \
 -w /gem5 --memory="${docker_mem_limit}" $repo_name \
 /usr/bin/env python3 /usr/bin/scons --ignore-style \
-"${build_out} ${build_args}"
+"${build_out}" "${build_args}"
 }>"${build_stdout}" 2>"${build_stderr}"
 result=$?


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Gerrit-Change-Id: I6cc8cc0c2a10c801d4a59e54b070383ac8ee93ae
Gerrit-Change-Number: 66772
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix compiler-tests.sh for no build args passed case

2022-12-13 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66631?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Fix compiler-tests.sh for no build args passed case
..

tests: Fix compiler-tests.sh for no build args passed case

When a user ran "tests/compiler-tests.sh" without passing any arguments,
the compiler tests would fail with:

```
scons: Reading SConscript files ...
Error: No existing build directory and no variant for /gem5
```

However, when passed with arguments, such as:

```
./tests/compiler-tests.sh -j6
```

the tests passed.

The fix for this is to merge the "$build_out" and "$build_args" into a
single string when executing the docker. I do not know exactly why this
works, but it does fix the error.

Change-Id: Ibcd316668b60fb7706f0ee05ab6dadf56228319d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66631
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/compiler-tests.sh
1 file changed, 34 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index e01d9de..f16e8e5 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -135,7 +135,7 @@
 docker run --rm -v "${gem5_root}":"/gem5" -u $UID:$GID \
 -w /gem5 --memory="${docker_mem_limit}" $repo_name \
 /usr/bin/env python3 /usr/bin/scons --ignore-style \
-"${build_out}" "${build_args}"
+"${build_out} ${build_args}"
 }>"${build_stdout}" 2>"${build_stderr}"
 result=$?


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[gem5-dev] [S] Change in gem5/gem5[develop]: python: Add error for creating abstact SimObjects

2022-04-22 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/59049 )



Change subject: python: Add error for creating abstact SimObjects
..

python: Add error for creating abstact SimObjects

Currently, if you try to instantiate an abstract SimObject the error is
confusing and unhelpful.

"TypeError: _m5.param_.Params: No constructor defined!"

Now, it will instead say "Cannot instantiate an abstract SimObject"
and include the name of the object that causes the error.

Change-Id: Ia8c51e29dccd999ec90dcd39710cc91d9a5fb86f
Signed-off-by: Jason Lowe-Power 
---
M src/python/m5/SimObject.py
1 file changed, 20 insertions(+), 0 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 26a1227..26147a1 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1175,6 +1175,8 @@

 # Call C++ to create C++ object corresponding to this object
 def createCCObject(self):
+if self.abstract:
+fatal(f"Cannot instantiate an abstract SimObject  
({self.path()})")

 self.getCCParams()
 self.getCCObject() # force creation


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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix bug in error message

2022-04-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58429 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: scons: Fix bug in error message
..

scons: Fix bug in error message

The variable p doesn't exist in the context. Just remove the extra
print. Even without the specific variable printed the error message is
pretty helpful.

Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58429
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M build_tools/sim_object_param_struct_hh.py
1 file changed, 19 insertions(+), 1 deletion(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/build_tools/sim_object_param_struct_hh.py  
b/build_tools/sim_object_param_struct_hh.py

index ff525ee..261ac9b 100644
--- a/build_tools/sim_object_param_struct_hh.py
+++ b/build_tools/sim_object_param_struct_hh.py
@@ -73,7 +73,7 @@
 try:
 ptypes = [p.ptype for p in params]
 except:
-print(sim_object, p, p.ptype_str)
+print(sim_object)
 print(params)
 raise


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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add check for single protocol

2022-03-31 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58469 )



Change subject: mem-ruby: Add check for single protocol
..

mem-ruby: Add check for single protocol

Now that multiple protocols are built into a single binary, it's
possible that the user instantiates machines from different protocols.
Right now, Ruby doesn't allow this. This changes informs the user if
this happens with a hopefully helpful error statement.

This was tested by using machine from different protocols and the error
condition was hit.

Change-Id: I1ca4b60c360bf6fa5531291003079b39e407da26
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/slicc/symbols/StateMachine.py
3 files changed, 35 insertions(+), 3 deletions(-)



diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 91c4bc3..9d25ce8 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -104,8 +104,19 @@
 }

 void
-RubySystem::registerAbstractController(AbstractController* cntrl)
+RubySystem::registerAbstractController(AbstractController* cntrl,
+   std::string protocol_str)
 {
+// Check and enforce that controllers can only come from one protocol
+if (m_protocol_str.empty()) {
+m_protocol_str = protocol_str;
+} else {
+fatal_if(protocol_str != m_protocol_str,
+ "Ruby only supports using machines from a single  
protocol. "
+ "The current machine %s is part of the protocol %s.  
Other "

+ "controllers instantiated were part of protocol %s.",
+ cntrl->name(), protocol_str, m_protocol_str);
+}
 m_abs_cntrl_vec.push_back(cntrl);

 MachineID id = cntrl->getMachineID();
diff --git a/src/mem/ruby/system/RubySystem.hh  
b/src/mem/ruby/system/RubySystem.hh

index e16d699..b1e7b4b 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -35,6 +35,7 @@
 #ifndef __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
 #define __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__

+#include 
 #include 

 #include "base/callback.hh"
@@ -104,7 +105,7 @@
 bool functionalWrite(Packet *ptr);

 void registerNetwork(Network*);
-void registerAbstractController(AbstractController*);
+void registerAbstractController(AbstractController*, std::string);
 void registerMachineID(const MachineID& mach_id, Network* network);
 void registerRequestorIDs();

@@ -145,6 +146,8 @@
 memory::SimpleMemory *m_phys_mem;
 const bool m_access_backing_store;

+std::string m_protocol_str;
+
 //std::vector m_networks;
 std::vector> m_networks;
 std::vector m_abs_cntrl_vec;
diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 2faf19a..90f789f 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -619,7 +619,7 @@
 m_machineID.type = MachineType_${ident};
 m_machineID.num = m_version;
 m_num_controllers++;
-p.ruby_system->registerAbstractController(this);
+p.ruby_system->registerAbstractController(this, "${protocol}");

 m_in_ports = $num_in_ports;
 ''')

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[gem5-dev] Change in gem5/gem5[develop]: configs: Replace buildEnv with getRubyProtocol

2022-03-31 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58449 )



Change subject: configs: Replace buildEnv with getRubyProtocol
..

configs: Replace buildEnv with getRubyProtocol

Instead of using `buildEnv['PROTOCOL']` use the new function
`getRubyProtocol()`.

*User-facing change!*
We are deprecating the use of buildEnv['PROTOCOL'] when transitioning to
enable multiple Ruby protocols in a single binary. If you have any
configuration scripts that rely on buildEnv['PROTOCOL'] they should be
updated as shown below.

`buildEnv['PROTOCOL']` -> `getRubyProtocol()`

Change-Id: Ic4d010f93a027be03767d5306c2eee6c13ed9511
Signed-off-by: Jason Lowe-Power 
---
M configs/common/FSConfig.py
M configs/example/apu_se.py
M configs/example/gpufs/Disjoint_VIPER.py
M configs/example/ruby_random_test.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/test_caches.py
M configs/ruby/AMD_Base_Constructor.py
M configs/ruby/CHI.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/Garnet_standalone.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Three_Level_HTM.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M configs/ruby/Ruby.py
M configs/topologies/CustomMesh.py
M tests/configs/gpu-randomtest-ruby.py
M tests/configs/gpu-ruby.py
M tests/configs/rubytest-ruby.py
24 files changed, 72 insertions(+), 49 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index a7ba815..61d8958 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -41,6 +41,7 @@
 import m5
 from m5.objects import *
 from m5.util import *
+from m5.defines import *
 from common.Benchmarks import *
 from common import ObjectList

@@ -339,7 +340,7 @@
 self.system_port = self.membus.cpu_side_ports

 if ruby:
-if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
+if getRubyProtocol() == 'MI_example' and num_cpus > 1:
 fatal("The MI_example protocol cannot implement Load/Store "
   "Exclusive operations. Multicore ARM systems configured "
   "with the MI_example protocol will not work properly.")
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index b5fb9ff..6bb4151 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -34,6 +34,7 @@

 import m5
 from m5.objects import *
+from m5.defines import buildEnv, getRubyProtocol
 from m5.util import addToPath

 addToPath('../')
@@ -211,7 +212,7 @@
 ## Sanity Check 

 # Currently the gpu model requires ruby
-if buildEnv['PROTOCOL'] == 'None':
+if getRubyProtocol() == 'None':
 fatal("GPU model requires ruby")

 # Currently the gpu model requires only timing or detailed CPU
@@ -252,7 +253,7 @@
 # means pipeline initiates a acquire/release operation at kernel  
launch/end.

 # VIPER protocol is write-through based, and thus only impl_kern_launch_acq
 # needs to set.
-if (buildEnv['PROTOCOL'] == 'GPU_VIPER'):
+if (getRubyProtocol() == 'GPU_VIPER'):
 shader.impl_kern_launch_acq = True
 shader.impl_kern_end_rel = False
 else:
diff --git a/configs/example/gpufs/Disjoint_VIPER.py  
b/configs/example/gpufs/Disjoint_VIPER.py

index 8ddaeac..65d3d2f 100644
--- a/configs/example/gpufs/Disjoint_VIPER.py
+++ b/configs/example/gpufs/Disjoint_VIPER.py
@@ -27,7 +27,7 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.

-from m5.defines import buildEnv
+from m5.defines import getRubyProtocol
 from m5.objects import *
 from m5.util import fatal

@@ -45,7 +45,7 @@

 class Disjoint_VIPER(RubySystem):
 def __init__(self):
-if buildEnv['PROTOCOL'] != "GPU_VIPER":
+if getRubyProtocol() != "GPU_VIPER":
 fatal("This ruby config only supports the GPU_VIPER protocol")

 super(Disjoint_VIPER, self).__init__()
diff --git a/configs/example/ruby_random_test.py  
b/configs/example/ruby_random_test.py

index edc8ee8..7849cae 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -27,7 +27,7 @@

 import m5
 from m5.objects import *
-from m5.defines import buildEnv
+from m5.defines import getRubyProtocol
 from m5.util import addToPath
 import os, argparse, sys

@@ -79,7 +79,7 @@

 # Check the protocol
 check_flush = False
-if buildEnv['PROTOCOL'] == 'MOESI_hammer':
+if getRubyProtocol() == 'MOESI_hammer':
 check_flush = True

 tester = RubyTester(check_flush = check_flush,
diff --git a/configs/learning_gem5/part3/msi_caches.py  
b/configs/learning_gem5/part3/msi_caches.py

index 5abfff0..fb5e976 100644
--- a/configs/learning_gem5/part3/msi_cache

[gem5-dev] Change in gem5/gem5[develop]: stdlib,mem-ruby: Use protocol-spec. names

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58440 )



Change subject: stdlib,mem-ruby: Use protocol-spec. names
..

stdlib,mem-ruby: Use protocol-spec. names

Update the standard library Ruby protocols to use the protocol-specific
class names instead of the deprecated general names.

Unfortunately, some code became duplicated between similar controllers.
I tried multiple inheritance, but it didn't work out for me. I think the
correct solution is to move some of the shared code down into the
generated python. That's out of the scope for these changes.

Change-Id: I3444bee3c2917dcbe92b600b85e60244129aad35
Signed-off-by: Jason Lowe-Power 
---
M src/python/SConscript
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
D  
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py
M  
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py

12 files changed, 160 insertions(+), 280 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index bb069f5..30c0ec5 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -106,14 +106,6 @@
 'gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies.ruby.caches',
 'gem5/components/cachehierarchies/ruby/caches/__init__.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_directory.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
-'gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level',
 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/__init__.py')
 PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level',
diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py  
b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py

deleted file mode 100644
index e39a38c..000
---  
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py

+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import abstractmethod
-
-from m5.objects import Directory_Controller
-
-
-class AbstractDirectory(Directory_Controller):
-
-_version

[gem5-dev] Change in gem5/gem5[develop]: WIP: mem-ruby: Build gem5 binary with all protocols

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58443 )



Change subject: WIP: mem-ruby: Build gem5 binary with all protocols
..

WIP: mem-ruby: Build gem5 binary with all protocols

This changeset is hacky just to test out the build. It should not be
committed as-is. A better solution to the configuration is required
before committing as this increases the build time significantly.

Change-Id: I3187e0b884c185380bb23558f4b8e37432dd3bfb
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/protocol/SConscript
M src/mem/ruby/protocol/SConsopts
2 files changed, 18 insertions(+), 2 deletions(-)



diff --git a/src/mem/ruby/protocol/SConscript  
b/src/mem/ruby/protocol/SConscript

index 550dd73..bf0658f 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -116,7 +116,10 @@

 env.Append(BUILDERS={'SLICC' : slicc_builder})

-for protocol in [env['CONF']['PROTOCOL']]:
+if env['CONF']['BUILD_GPU']:
+env['ALL_PROTOCOLS'].append('GPU_VIPER')
+
+for protocol in env['ALL_PROTOCOLS']:
 if protocol == "None":
 continue
 protocol_dir = None
diff --git a/src/mem/ruby/protocol/SConsopts  
b/src/mem/ruby/protocol/SConsopts

index 2fcc57a..1009e22 100644
--- a/src/mem/ruby/protocol/SConsopts
+++ b/src/mem/ruby/protocol/SConsopts
@@ -31,7 +31,6 @@
 Import('*')

 main.Append(ALL_PROTOCOLS=[
-'GPU_VIPER',
 'MOESI_AMD_Base',
 'MESI_Two_Level',
 'MESI_Three_Level',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3187e0b884c185380bb23558f4b8e37432dd3bfb
Gerrit-Change-Number: 58443
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: Procotol-spec. names in CHI

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58439 )



Change subject: configs,mem-ruby: Procotol-spec. names in CHI
..

configs,mem-ruby: Procotol-spec. names in CHI

Use the protocol-specific controller names in CHI.

**Important**: This could change some scripts. As long as people use
CHI_config (likely), this shouldn't be a problem, but if you have a
different version of CHI_config.py locally, you will need to make the
following updates:

`Cache_Controller` -> `CHI_Cache_Controller`
`Memory_Controller` -> `CHI_Memory_Controller`

Website updates coming soon!

Change-Id: I7afdcede884ac5f9a9a76cc3d3dd35941e4e2faa
Signed-off-by: Jason Lowe-Power 
---
M configs/ruby/CHI_config.py
M src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
M src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
3 files changed, 35 insertions(+), 13 deletions(-)



diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py
index b596efa..8eb7aed 100644
--- a/configs/ruby/CHI_config.py
+++ b/configs/ruby/CHI_config.py
@@ -173,7 +173,7 @@
 class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
 ordered = True

-class CHI_Cache_Controller(Cache_Controller):
+class Base_CHI_Cache_Controller(CHI_Cache_Controller):
 '''
 Default parameters for a Cache controller
 The Cache_Controller can also be used as a DMA requester or as
@@ -181,8 +181,8 @@
 '''

 def __init__(self, ruby_system):
-super(CHI_Cache_Controller, self).__init__(
-version = Versions.getVersion(Cache_Controller),
+super(Base_CHI_Cache_Controller, self).__init__(
+version = Versions.getVersion(CHI_Cache_Controller),
 ruby_system = ruby_system,
 mandatoryQueue = MessageBuffer(),
 prefetchQueue = MessageBuffer(),
@@ -200,7 +200,7 @@
 # timeouts on unique lines when a store conditional fails
 self.sc_lock_enabled = False

-class CHI_L1Controller(CHI_Cache_Controller):
+class CHI_L1Controller(Base_CHI_Cache_Controller):
 '''
 Default parameters for a L1 Cache controller
 '''
@@ -232,7 +232,7 @@
 self.number_of_snoop_TBEs = 4
 self.unify_repl_TBEs = False

-class CHI_L2Controller(CHI_Cache_Controller):
+class CHI_L2Controller(Base_CHI_Cache_Controller):
 '''
 Default parameters for a L2 Cache controller
 '''
@@ -264,7 +264,7 @@
 self.number_of_snoop_TBEs = 16
 self.unify_repl_TBEs = False

-class CHI_HNFController(CHI_Cache_Controller):
+class CHI_HNFController(Base_CHI_Cache_Controller):
 '''
 Default parameters for a coherent home node (HNF) cache controller
 '''
@@ -297,7 +297,7 @@
 self.number_of_snoop_TBEs = 1 # should not receive any snoop
 self.unify_repl_TBEs = False

-class CHI_DMAController(CHI_Cache_Controller):
+class CHI_DMAController(Base_CHI_Cache_Controller):
 '''
 Default parameters for a DMA controller
 '''
@@ -545,8 +545,8 @@
 def __init__(self, ruby_system, parent):
 super(CHI_SNF_Base, self).__init__(ruby_system)

-self._cntrl = Memory_Controller(
-  version = Versions.getVersion(Memory_Controller),
+self._cntrl = CHI_Memory_Controller(
+  version =  
Versions.getVersion(CHI_Memory_Controller),

   ruby_system = ruby_system,
   triggerQueue = TriggerMessageBuffer(),
   responseFromMemory = MessageBuffer(),
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py

index e8797b6..285cd68 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
@@ -29,7 +29,7 @@
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.abstract_core import AbstractCore

-from m5.objects import Cache_Controller, MessageBuffer, RubyNetwork
+from m5.objects import CHI_Cache_Controller, MessageBuffer, RubyNetwork

 import math

@@ -45,7 +45,7 @@
 class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
 ordered = True

-class AbstractNode(Cache_Controller):
+class AbstractNode(CHI_Cache_Controller):
 """A node is the abstract unit for caches in the CHI protocol.

 You can extend the AbstractNode to create caches (private or shared)  
and
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py

index cf7d660..00fc225 100644
---  
a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
+++  
b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Use function for backwards compat. ruby

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58442 )



Change subject: mem-ruby: Use function for backwards compat. ruby
..

mem-ruby: Use function for backwards compat. ruby

Instead of simply renaming the class, add a function which can be
evaluated at runtime to get the new class name. Note that this will
break any code which uses these classes as a base class. This should be
fixed in prior changes.

Change-Id: Id0ff17026d89322f8506ffb0d0fb75eb3725d111
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/StateMachine.py
1 file changed, 28 insertions(+), 7 deletions(-)



diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 2a0d6a4..2faf19a 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -268,20 +268,26 @@

 code.dedent()

-# Needed for backwards compatibility while there is only one  
protocol
-# compiled. When moving to multiple protocols in the gem5 binary,  
this

-# will need to change.
+# Needed for backwards compatibility. This redefines the function  
in
+# the same way for every protocol, but it uses the  
`getRubyProtocol`
+# function to dynamically select the machine to use. Having  
multiple
+# copies of this function is not ideal, but generating a  
separate .py

+# for MachineType was not feasible.
+# This will be removed in a later version of gem5.
 code('''

-from m5.defines import buildEnv
+from m5.defines import getRubyProtocol
+from m5 import objects
 from m5.util import warn

-if getRubyProtocol() == "${protocol}":
+def ${c_ident}(**args):
 warn(
-"${c_indent} is deprecated. Use %s_${c_indent} instead",
+"${c_ident} is deprecated. Use %s_${c_ident} instead",
 getRubyProtocol()
 )
-${c_ident} = ${py_ident}
+full_name = getRubyProtocol() + "_${c_ident}"
+cls = getattr(objects, full_name)
+return cls(**args)
 ''')

 code.write(path, '%s.py' % gen_filename)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id0ff17026d89322f8506ffb0d0fb75eb3725d111
Gerrit-Change-Number: 58442
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby,configs: Update AMD protos with new names

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58441 )



Change subject: mem-ruby,configs: Update AMD protos with new names
..

mem-ruby,configs: Update AMD protos with new names

Update the MOESI_AMD_Base and GPU_VIPER configuration files with the new
full protocol-specific names for the controllers instead of the
deprecated names.

Note: If you have any files which use the `CntrlBase` base, you will
likely need to update the class names that you are inheriting from.

Change-Id: I623fea7dd4cd151f7b15fe7cb43f8a4c45492d89
Signed-off-by: Jason Lowe-Power 
---
M configs/ruby/GPU_VIPER.py
M configs/ruby/MOESI_AMD_Base.py
2 files changed, 25 insertions(+), 8 deletions(-)



diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index c73995f..9f341c5 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -85,7 +85,7 @@
 self.assoc = assoc
 self.replacement_policy = TreePLRURP()

-class CPCntrl(CorePair_Controller, CntrlBase):
+class CPCntrl(GPU_VIPER_CorePair_Controller, CntrlBase):

 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
@@ -134,7 +134,7 @@
 self.resourceStalls = options.no_tcc_resource_stalls
 self.replacement_policy = TreePLRURP()

-class TCPCntrl(TCP_Controller, CntrlBase):
+class TCPCntrl(GPU_VIPER_TCP_Controller, CntrlBase):

 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
@@ -264,7 +264,7 @@
 self.replacement_policy = TreePLRURP()


-class TCCCntrl(TCC_Controller, CntrlBase):
+class TCCCntrl(GPU_VIPER_TCC_Controller, CntrlBase):
 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
 self.L2cache = TCC()
@@ -293,7 +293,7 @@
 self.resourceStalls = False
 self.replacement_policy = TreePLRURP()

-class L3Cntrl(L3Cache_Controller, CntrlBase):
+class L3Cntrl(GPU_VIPER_L3Cache_Controller, CntrlBase):
 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
 self.L3cache = L3Cache()
@@ -314,7 +314,7 @@
 self.probeToL3 = probe_to_l3
 self.respToL3 = resp_to_l3

-class DirCntrl(Directory_Controller, CntrlBase):
+class DirCntrl(GPU_VIPER_Directory_Controller, CntrlBase):
 def create(self, options, dir_ranges, ruby_system, system):
 self.version = self.versionCount()

diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 12b8771..0833915 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -83,7 +83,7 @@
 self.assoc = options.l2_assoc
 self.replacement_policy = TreePLRURP()

-class CPCntrl(CorePair_Controller, CntrlBase):
+class CPCntrl(MOESI_AMD_Base_CorePair_Controller, CntrlBase):

 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
@@ -139,7 +139,7 @@
 self.resourceStalls = options.no_resource_stalls
 self.replacement_policy = TreePLRURP()

-class L3Cntrl(L3Cache_Controller, CntrlBase):
+class L3Cntrl(MOESI_AMD_Base_L3Cache_Controller, CntrlBase):
 def create(self, options, ruby_system, system):
 self.version = self.versionCount()
 self.L3cache = L3Cache()
@@ -161,7 +161,7 @@
 self.probeToL3 = probe_to_l3
 self.respToL3 = resp_to_l3

-class DirCntrl(Directory_Controller, CntrlBase):
+class DirCntrl(MOESI_AMD_Base_Directory_Controller, CntrlBase):
 def create(self, options, dir_ranges, ruby_system, system):
 self.version = self.versionCount()


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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Use shared and per-protocol SLICC files

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58431 )



Change subject: mem-ruby: Use shared and per-protocol SLICC files
..

mem-ruby: Use shared and per-protocol SLICC files

This changes extends SLICC to understand two different kinds of slicc
files: files that are protocol-specific and files that are shared or
included between different protocols.

Each declaration in SLICC can now be shared or not. If it is shared,
then we can take a different action in the code generation (e.g., wrap
in a namespace).

*Developer facing change*
Removes the RubySlicc_interfaces.slicc file from the SLICC includes of
every protocol.

Changes required: If you have a custom protocol, you will need to remove
the line `include "RubySlicc_interfaces.slicc" from your .slicc file.

Change-Id: Ia6c2dafe2b8fe86749a13d17daa885bddd166855
Signed-off-by: Jason Lowe-Power 
---
M src/learning_gem5/part3/MSI.slicc
M src/mem/ruby/protocol/GPU_VIPER.slicc
M src/mem/ruby/protocol/Garnet_standalone.slicc
M src/mem/ruby/protocol/MESI_Three_Level.slicc
M src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc
M src/mem/ruby/protocol/MESI_Two_Level.slicc
M src/mem/ruby/protocol/MI_example.slicc
M src/mem/ruby/protocol/MOESI_AMD_Base.slicc
M src/mem/ruby/protocol/MOESI_CMP_directory.slicc
M src/mem/ruby/protocol/MOESI_CMP_token.slicc
M src/mem/ruby/protocol/MOESI_hammer.slicc
M src/mem/ruby/protocol/RubySlicc_interfaces.slicc
M src/mem/ruby/protocol/SConscript
M src/mem/ruby/protocol/chi/CHI.slicc
M src/mem/slicc/ast/DeclAST.py
M src/mem/slicc/ast/DeclListAST.py
M src/mem/slicc/ast/EnumDeclAST.py
M src/mem/slicc/ast/StateDeclAST.py
M src/mem/slicc/ast/TypeDeclAST.py
M src/mem/slicc/main.py
M src/mem/slicc/parser.py
M src/mem/slicc/symbols/SymbolTable.py
M src/mem/slicc/symbols/Type.py
23 files changed, 104 insertions(+), 45 deletions(-)



diff --git a/src/learning_gem5/part3/MSI.slicc  
b/src/learning_gem5/part3/MSI.slicc

index c6fdc50..4c02fcb 100644
--- a/src/learning_gem5/part3/MSI.slicc
+++ b/src/learning_gem5/part3/MSI.slicc
@@ -1,5 +1,4 @@
 protocol "MSI";
-include "RubySlicc_interfaces.slicc";
 include "MSI-msg.sm";
 include "MSI-cache.sm";
 include "MSI-dir.sm";
diff --git a/src/mem/ruby/protocol/GPU_VIPER.slicc  
b/src/mem/ruby/protocol/GPU_VIPER.slicc

index 196058b..2a89d02 100644
--- a/src/mem/ruby/protocol/GPU_VIPER.slicc
+++ b/src/mem/ruby/protocol/GPU_VIPER.slicc
@@ -1,5 +1,4 @@
 protocol "GPU_VIPER";
-include "RubySlicc_interfaces.slicc";
 include "MOESI_AMD_Base-msg.sm";
 include "MOESI_AMD_Base-dir.sm";
 include "MOESI_AMD_Base-dma.sm";
diff --git a/src/mem/ruby/protocol/Garnet_standalone.slicc  
b/src/mem/ruby/protocol/Garnet_standalone.slicc

index e467f34..8c856af 100644
--- a/src/mem/ruby/protocol/Garnet_standalone.slicc
+++ b/src/mem/ruby/protocol/Garnet_standalone.slicc
@@ -1,5 +1,4 @@
 protocol "Garnet_standalone";
-include "RubySlicc_interfaces.slicc";
 include "Garnet_standalone-msg.sm";
 include "Garnet_standalone-cache.sm";
 include "Garnet_standalone-dir.sm";
diff --git a/src/mem/ruby/protocol/MESI_Three_Level.slicc  
b/src/mem/ruby/protocol/MESI_Three_Level.slicc

index a24b11c..d37b937 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level.slicc
+++ b/src/mem/ruby/protocol/MESI_Three_Level.slicc
@@ -1,5 +1,4 @@
 protocol "MESI_Three_Level";
-include "RubySlicc_interfaces.slicc";
 include "MESI_Two_Level-msg.sm";
 include "MESI_Three_Level-msg.sm";
 include "MESI_Three_Level-L0cache.sm";
diff --git a/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc  
b/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc

index 4ec31b5..88afc2f 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc
+++ b/src/mem/ruby/protocol/MESI_Three_Level_HTM.slicc
@@ -1,5 +1,4 @@
 protocol "MESI_Three_Level_HTM";
-include "RubySlicc_interfaces.slicc";
 include "MESI_Two_Level-msg.sm";
 include "MESI_Three_Level-msg.sm";
 include "MESI_Three_Level_HTM-L0cache.sm";
diff --git a/src/mem/ruby/protocol/MESI_Two_Level.slicc  
b/src/mem/ruby/protocol/MESI_Two_Level.slicc

index b5bf104..e0f6dda 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level.slicc
+++ b/src/mem/ruby/protocol/MESI_Two_Level.slicc
@@ -1,5 +1,4 @@
 protocol "MESI_Two_Level";
-include "RubySlicc_interfaces.slicc";
 include "MESI_Two_Level-msg.sm";
 include "MESI_Two_Level-L1cache.sm";
 include "MESI_Two_Level-L2cache.sm";
diff --git a/src/mem/ruby/protocol/MI_example.slicc  
b/src/mem/ruby/protocol/MI_example.slicc

index 7061478..b3c1585 100644
--- a/src/mem/ruby/protocol/MI_example.slicc
+++ b/src/mem/ruby/protocol/MI_example.slicc
@@ -1,5 +1,4 @@
 protocol "MI_example";
-include "RubySlicc_interfaces.slicc";
 include "MI_example-msg.sm";
 include "MI_example-cache.sm";
 include "MI_example-dir.sm";
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base.slicc  
b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc

index b381452..50aae8c 100644
--- a/src/mem/ruby/protoc

[gem5-dev] Change in gem5/gem5[develop]: scons: Fix bug in error message

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58429 )



Change subject: scons: Fix bug in error message
..

scons: Fix bug in error message

The variable p doesn't exist in the context. Just remove the extra
print. Even without the specific variable printed the error message is
pretty helpful.

Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793
Signed-off-by: Jason Lowe-Power 
---
M build_tools/sim_object_param_struct_hh.py
1 file changed, 15 insertions(+), 1 deletion(-)



diff --git a/build_tools/sim_object_param_struct_hh.py  
b/build_tools/sim_object_param_struct_hh.py

index ff525ee..261ac9b 100644
--- a/build_tools/sim_object_param_struct_hh.py
+++ b/build_tools/sim_object_param_struct_hh.py
@@ -73,7 +73,7 @@
 try:
 ptypes = [p.ptype for p in params]
 except:
-print(sim_object, p, p.ptype_str)
+print(sim_object)
 print(params)
 raise


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[gem5-dev] Change in gem5/gem5[develop]: python: Add function to get ruby protocol

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58430 )



Change subject: python: Add function to get ruby protocol
..

python: Add function to get ruby protocol

This changeset moves the auto-generated defines.py file to _defines and
replaces it with an explicit defines.py file in the m5 module. This
explicit module also includes a function to expose the ruby protocol.
This will make it easier to provide backwards compatibility and have a
"main" protocol as we add support for multiple protocols in a single
binary.

Change-Id: Id632d4af7d1e60f2c3ea0c492c0cba26c6d9af92
Signed-off-by: Jason Lowe-Power 
---
M src/SConscript
M src/python/SConscript
A src/python/m5/defines.py
3 files changed, 52 insertions(+), 2 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index d55520b..f356f00 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -609,9 +609,9 @@
 code.write(target[0].abspath)

 # Generate a file with all of the compile options in it
-env.Command('python/m5/defines.py', ToValue(dict(build_env)),
+env.Command('python/m5/_defines.py', ToValue(dict(build_env)),
 MakeAction(makeDefinesPyFile, Transform("DEFINES", 0)))
-PySource('m5', 'python/m5/defines.py')
+PySource('m5', 'python/m5/_defines.py')

 # Generate a file that wraps the basic top level files
 gem5py_env.Command('python/m5/info.py',
diff --git a/src/python/SConscript b/src/python/SConscript
index 343a696..bb069f5 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -219,6 +219,7 @@
 PySource('m5', 'm5/SimObject.py')
 PySource('m5', 'm5/core.py')
 PySource('m5', 'm5/debug.py')
+PySource('m5', 'm5/defines.py')
 PySource('m5', 'm5/event.py')
 PySource('m5', 'm5/main.py')
 PySource('m5', 'm5/options.py')
diff --git a/src/python/m5/defines.py b/src/python/m5/defines.py
new file mode 100644
index 000..9c1c98d
--- /dev/null
+++ b/src/python/m5/defines.py
@@ -0,0 +1,32 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from ._defines import buildEnv
+
+def getRubyProtocol() -> str:
+return buildEnv["PROTOCOL"]
+
+__all__ = ["buildEnv", "getRubyProtocol"]

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Update HTML output to include protocol

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58437 )



Change subject: mem-ruby: Update HTML output to include protocol
..

mem-ruby: Update HTML output to include protocol

Move the html output to be in a subdirectory with the protocol name.

Change-Id: I1510d2d5a531cc6db74d10a0478c23bc8a836a26
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/SymbolTable.py
1 file changed, 16 insertions(+), 0 deletions(-)



diff --git a/src/mem/slicc/symbols/SymbolTable.py  
b/src/mem/slicc/symbols/SymbolTable.py

index be3147b..1b29b38 100644
--- a/src/mem/slicc/symbols/SymbolTable.py
+++ b/src/mem/slicc/symbols/SymbolTable.py
@@ -164,6 +164,10 @@
 def writeHTMLFiles(self, path):
 makeDir(path)

+# Append the protocol to the path and make that directory
+path = os.path.join(path, self.slicc.protocol)
+makeDir(path)
+
 machines = list(self.getAllType(StateMachine))
 if len(machines) > 1:
 name = "%s_table.html" % machines[0].ident

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Move getNumControllers out of machines

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58435 )



Change subject: mem-ruby: Move getNumControllers out of machines
..

mem-ruby: Move getNumControllers out of machines

Move the getNumControllers function out of the protocol-specific
machine definitions (which are now in their own namespaces) to a
BaseMachine class that the protocol-specific machines inherit
from. This design was the simplest way to keep backwards compatibility.

The one caveat is that this design means that while you can compile
multiple protocols into one binary, you cannot use the same machine type
from different protocols in one simulation. This is the current
assumption, so it shouldn't change anything for users.

Change-Id: If9eeb78c24eb5076956b9f44fa04c7e6eb0f0dd4
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/Type.py
2 files changed, 44 insertions(+), 23 deletions(-)



diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 3ef6b5b..2a0d6a4 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -342,12 +342,11 @@

 extern std::stringstream ${ident}_transitionComment;

-class $c_ident : public AbstractController
+class $c_ident : public AbstractController, Base${ident}Machine
 {
   public:
 typedef ${py_ident}Params Params;
 $c_ident(const Params &p);
-static int getNumControllers();
 void init();

 MessageBuffer *getMandatoryQueue() const;
@@ -432,7 +431,6 @@

 static std::vector eventVec;
 static std::vector > transVec;
-static int m_num_controllers;

 // Internal functions
 ''')
@@ -596,7 +594,6 @@
 namespace ${protocol}
 {

-int $c_ident::m_num_controllers = 0;
 std::vector  $c_ident::eventVec;
 std::vector >  $c_ident::transVec;

@@ -1030,12 +1027,6 @@
 return m_counters[state][event];
 }

-int
-$c_ident::getNumControllers()
-{
-return m_num_controllers;
-}
-
 MessageBuffer*
 $c_ident::getMandatoryQueue() const
 {
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 282f55a..2973046 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -583,6 +583,20 @@
 MachineID get${{enum.ident}}MachineID(NodeID RubyNode);
 ''')

+# Machine types are expected to be overridden by protocol-
+# specific classes.
+if self.isMachineType:
+code('''
+
+class Base${{enum.ident}}Machine {
+  protected:
+static int m_num_controllers;
+  public:
+static int getNumControllers() { return m_num_controllers; }
+};
+
+''')
+
 if self.isStateDecl:
 code('''

@@ -699,10 +713,6 @@
 ''')

 if self.isMachineType:
-for enum in self.enums.values():
-if enum.primary:
-code('#include "mem/ruby/protocol/${{protocol}}/'
-'${{enum.ident}}_Controller.hh"')
 code('#include "mem/ruby/common/MachineID.hh"')

 code('''
@@ -858,13 +868,9 @@
 code.indent()
 code('  case ${{self.c_ident}}_NUM:')
 for enum in reversed(list(self.enums.values())):
-# Check if there is a defined machine with this type
-if enum.primary:
-code('''
-base += ${{protocol}}::${{enum.ident}}_Controller::getNumControllers();
+code('''
+base += Base${{enum.ident}}Machine::getNumControllers();
 ''')
-else:
-code('base += 0;')
 code('[[fallthrough]];')
 code('  case ${{self.c_ident}}_${{enum.ident}}:')
 code('break;')
@@ -890,9 +896,8 @@
 # For each field
 for enum in self.enums.values():
 code('case ${{self.c_ident}}_${{enum.ident}}:')
-if enum.primary:
-code('''
-return ${{protocol}}::${{enum.ident}}_Controller::getNumControllers();
+code('''
+return Base${{enum.ident}}Machine::getNumControllers();
 ''')

 # total num
@@ -916,6 +921,11 @@
   return mach;
 }
 ''')
+if self.isMachineType:
+code('''
+
+int Base${{enum.ident}}Machine::m_num_controllers = 0;
+''')

 # For protocol-specific types, close the protocol namespace
 if not self.shared:

--
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___
ge

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Rename SLICC SimObjs with compatibility

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58434 )



Change subject: mem-ruby: Rename SLICC SimObjs with compatibility
..

mem-ruby: Rename SLICC SimObjs with compatibility

Rename all SLICC generated SimObjects to have the protocol in their
name. This will allow for two different protocols to have the same
machine names (e.g., L1Cache). For compatiblity, we check to see if the
current protocol that is built matches the SimObject's protocol and
export the backwards-compatible name.

Change-Id: I2f1b2a541778de5b6316348386927141485c19b6
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/protocol/SConscript
M src/mem/slicc/ast/MachineAST.py
M src/mem/slicc/symbols/StateMachine.py
3 files changed, 50 insertions(+), 8 deletions(-)



diff --git a/src/mem/ruby/protocol/SConscript  
b/src/mem/ruby/protocol/SConscript

index 62e3e10..162c0db 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -124,7 +124,7 @@
 elif s.endswith('.py'):
 filename = os.path.basename(s)
 # We currently only expect ${ident}_Controller.py to be generated,  
and

-# for it to contain a single SimObject with the same name.
+# for it to contain a single SimObject with the same name +  
protocol.

 assert(filename.endswith('_Controller.py'))
-SimObject(f, sim_objects=[os.path.splitext(filename)[0]])
+SimObject(f,  
sim_objects=[protocol+'_'+os.path.splitext(filename)[0]])


diff --git a/src/mem/slicc/ast/MachineAST.py  
b/src/mem/slicc/ast/MachineAST.py

index 4114f01..17116da 100644
--- a/src/mem/slicc/ast/MachineAST.py
+++ b/src/mem/slicc/ast/MachineAST.py
@@ -43,9 +43,15 @@
 def files(self, parent=None):
 import os
 file_prefix = os.path.join(self.slicc.protocol, self.ident)
+# Can't have multiple python simobject files with the same name
+# So, we have to prepend the protocol name to the .py file
+py_prefix = os.path.join(
+self.slicc.protocol,
+self.slicc.protocol + '_' + self.ident
+)
 s = set(('%s_Controller.cc' % file_prefix,
  '%s_Controller.hh' % file_prefix,
- '%s_Controller.py' % file_prefix,
+ '%s_Controller.py' % py_prefix,
  '%s_Transitions.cc' % file_prefix,
  '%s_Wakeup.cc' % file_prefix))

diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 2540b0d..3ef6b5b 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -236,7 +236,7 @@
 ident = self.ident

 protocol = self.symtab.slicc.protocol
-py_ident = "%s_Controller" % ident
+py_ident = f"{protocol}_{ident}_Controller"
 c_ident = "%s_Controller" % self.ident
 gen_filename = f"{protocol}/{py_ident}"

@@ -267,6 +267,23 @@
"in StateMachine.py",  
param.type_ast.type.c_ident)


 code.dedent()
+
+# Needed for backwards compatibility while there is only one  
protocol
+# compiled. When moving to multiple protocols in the gem5 binary,  
this

+# will need to change.
+code('''
+
+from m5.defines import buildEnv
+from m5.util import warn
+
+if getRubyProtocol() == "${protocol}":
+warn(
+"${c_indent} is deprecated. Use %s_${c_indent} instead",
+getRubyProtocol()
+)
+${c_ident} = ${py_ident}
+''')
+
 code.write(path, '%s.py' % gen_filename)


@@ -275,8 +292,11 @@
 code = self.symtab.codeFormatter()
 ident = self.ident
 c_ident = "%s_Controller" % self.ident
-header_string = self.symtab.slicc.protocol + '_' + self.ident
-gen_filename = f"{self.symtab.slicc.protocol}/{c_ident}"
+
+protocol = self.symtab.slicc.protocol
+header_string = protocol + '_' + self.ident
+gen_filename = f"{protocol}/{c_ident}"
+py_ident = f"{protocol}_{ident}_Controller"

 code('''
 // Created by slicc definition of Module "${{self.short}}"
@@ -292,7 +312,7 @@
 #include "mem/ruby/protocol/TransitionResult.hh"
 #include "mem/ruby/protocol/${protocol}/Types.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
-#include "params/$c_ident.hh"
+#include "params/$py_ident.hh"

 ''')

@@ -325,7 +345,7 @@
 class $c_ident : public AbstractController
 {
   public:
-typedef ${c_ident}Params Params;
+typedef ${py_ident}Params Params;
 $c_ident(const Params &p);
 static int getNumControllers();
 void init();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2f1b2a541778de5b6316348386927141485

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Move protocol files to subdir

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58433 )



Change subject: mem-ruby: Move protocol files to subdir
..

mem-ruby: Move protocol files to subdir

Move all generated protocol-specific files to a subdirectory with the
protocol's name.

This change also updates SLICC to have separate variables for the
filename, c identifier and python identifier instead of just using
variations of the c identifier.

Change-Id: I62f69a4606b030ee23cb2d96493f3257a6923748
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/ast/EnumDeclAST.py
M src/mem/slicc/ast/MachineAST.py
M src/mem/slicc/ast/StateDeclAST.py
M src/mem/slicc/ast/TypeDeclAST.py
M src/mem/slicc/parser.py
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/SymbolTable.py
M src/mem/slicc/symbols/Type.py
8 files changed, 109 insertions(+), 51 deletions(-)



diff --git a/src/mem/slicc/ast/EnumDeclAST.py  
b/src/mem/slicc/ast/EnumDeclAST.py

index 5a3fd7a..3e71dc0 100644
--- a/src/mem/slicc/ast/EnumDeclAST.py
+++ b/src/mem/slicc/ast/EnumDeclAST.py
@@ -46,6 +46,8 @@
 ident = "%s_%s" % (parent, self.type_ast.ident)
 else:
 ident = self.type_ast.ident
+if not self.shared:
+ident = f"{self.slicc.protocol}/{ident}"
 s = set(("%s.hh" % ident, "%s.cc" % ident))
 return s

diff --git a/src/mem/slicc/ast/MachineAST.py  
b/src/mem/slicc/ast/MachineAST.py

index 7434d6b..4114f01 100644
--- a/src/mem/slicc/ast/MachineAST.py
+++ b/src/mem/slicc/ast/MachineAST.py
@@ -41,11 +41,13 @@
 return "[Machine: %r]" % self.ident

 def files(self, parent=None):
-s = set(('%s_Controller.cc' % self.ident,
- '%s_Controller.hh' % self.ident,
- '%s_Controller.py' % self.ident,
- '%s_Transitions.cc' % self.ident,
- '%s_Wakeup.cc' % self.ident))
+import os
+file_prefix = os.path.join(self.slicc.protocol, self.ident)
+s = set(('%s_Controller.cc' % file_prefix,
+ '%s_Controller.hh' % file_prefix,
+ '%s_Controller.py' % file_prefix,
+ '%s_Transitions.cc' % file_prefix,
+ '%s_Wakeup.cc' % file_prefix))

 s |= self.decls.files(self.ident)
 return s
diff --git a/src/mem/slicc/ast/StateDeclAST.py  
b/src/mem/slicc/ast/StateDeclAST.py

index 4100296..1fffaa1 100644
--- a/src/mem/slicc/ast/StateDeclAST.py
+++ b/src/mem/slicc/ast/StateDeclAST.py
@@ -45,6 +45,8 @@
 ident = "%s_%s" % (parent, self.type_ast.ident)
 else:
 ident = self.type_ast.ident
+if not self.shared:
+ident = f"{self.slicc.protocol}/{ident}"
 s = set(("%s.hh" % ident, "%s.cc" % ident))
 return s

diff --git a/src/mem/slicc/ast/TypeDeclAST.py  
b/src/mem/slicc/ast/TypeDeclAST.py

index 9748178..000d66e 100644
--- a/src/mem/slicc/ast/TypeDeclAST.py
+++ b/src/mem/slicc/ast/TypeDeclAST.py
@@ -46,6 +46,8 @@
 ident = "%s_%s" % (parent, self.type_ast.ident)
 else:
 ident = self.type_ast.ident
+if not self.shared:
+ident = f"{self.slicc.protocol}/{ident}"
 return set(("%s.hh" % ident, "%s.cc" % ident))

 def generate(self):
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index e2b0a64..78a16bf 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -97,7 +97,7 @@
 self.symtab.writeHTMLFiles(html_path)

 def files(self):
-f = set(['Types.hh'])
+f = set([os.path.join(self.protocol, 'Types.hh')])

 f |= self.decl_list.files()

diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index e220731..2540b0d 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -235,8 +235,10 @@
 code = self.symtab.codeFormatter()
 ident = self.ident

+protocol = self.symtab.slicc.protocol
 py_ident = "%s_Controller" % ident
 c_ident = "%s_Controller" % self.ident
+gen_filename = f"{protocol}/{py_ident}"

 code('''
 from m5.params import *
@@ -245,8 +247,8 @@

 class $py_ident(RubyController):
 type = '$py_ident'
-cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
-cxx_class = 'gem5::ruby::$protocol::$py_ident'
+cxx_header = 'mem/ruby/protocol/${protocol}/${c_ident}.hh'
+cxx_class = 'gem5::ruby::$protocol::$c_ident'
 ''')
 code.indent()
 for param in self.config_parameters:
@@ -265,7 +267,7 @@
"in StateMachine.py",  
param.type_ast.type.c_ident)


 code.dedent()
-code.write(path, '%s.py' % py_ident)
+code.write(path, '%s.py' % gen_filename)


 def printControllerHH(self, path):
@@ -273,12 +275,14 @@
 code = self.symtab.codeFormatter()
 i

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby,scons: Split SLICC generic and specific

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58436 )



Change subject: mem-ruby,scons: Split SLICC generic and specific
..

mem-ruby,scons: Split SLICC generic and specific

Update the SLICC generation to be able to generate the shared files and
protocol-specific files separately.

Update the SLICC SConscript to make a separate call to SLICC for the
shared files and the protocol-specific files.

Note: The Scons changes are a bit hacky. Improvements are welcome.

Change-Id: I516a1bbe7f82e57dc4145064170f10b31683b6cd
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/protocol/SConscript
M src/mem/slicc/ast/DeclListAST.py
M src/mem/slicc/main.py
M src/mem/slicc/parser.py
M src/mem/slicc/symbols/SymbolTable.py
5 files changed, 117 insertions(+), 34 deletions(-)



diff --git a/src/mem/ruby/protocol/SConscript  
b/src/mem/ruby/protocol/SConscript

index 162c0db..550dd73 100644
--- a/src/mem/ruby/protocol/SConscript
+++ b/src/mem/ruby/protocol/SConscript
@@ -66,15 +66,23 @@
 assert len(source) == 1
 filepath = source[0].srcnode().abspath

+if filepath.endswith('RubySlicc_interfaces.slicc'):
+# We're working on the shared files
+filepath = None
+shared_only = True
+else:
+shared_only = False
+
 slicc = SLICC(
 filepath,
  
[os.path.join(protocol_base.abspath, 'RubySlicc_interfaces.slicc')],

 protocol_base.abspath,
+shared_only=shared_only,
 verbose=False
 )
 slicc.process()
 slicc.writeCodeFiles(output_dir.abspath, slicc_includes)
-if env['CONF']['SLICC_HTML']:
+if env['CONF']['SLICC_HTML'] and not shared_only:
 slicc.writeHTMLFiles(html_dir.abspath)

 target.extend([output_dir.File(f) for f in sorted(slicc.files())])
@@ -83,35 +91,63 @@
 def slicc_action(target, source, env):
 assert len(source) == 1
 filepath = source[0].srcnode().abspath
+
+if filepath.endswith('RubySlicc_interfaces.slicc'):
+# We're working on the shared files
+filepath = None
+shared_only = True
+else:
+shared_only = False
+
 slicc = SLICC(
 filepath,
  
[os.path.join(protocol_base.abspath, 'RubySlicc_interfaces.slicc')],

 protocol_base.abspath,
+shared_only=shared_only,
 verbose=True
 )
 slicc.process()
 slicc.writeCodeFiles(output_dir.abspath, slicc_includes)
-if env['CONF']['SLICC_HTML']:
+if env['CONF']['SLICC_HTML'] and not shared_only:
 slicc.writeHTMLFiles(html_dir.abspath)

 slicc_builder = Builder(action=MakeAction(slicc_action,  
Transform("SLICC")),

 emitter=slicc_emitter)

-protocol = env['CONF']['PROTOCOL']
-protocol_dir = None
-for path in env['PROTOCOL_DIRS']:
-if os.path.exists(path.File("%s.slicc" % protocol).abspath):
-protocol_dir = Dir(path)
-break
-
-if not protocol_dir:
-raise ValueError("Could not find {}.slicc in PROTOCOL_DIRS".format(
-protocol))
-
-sources = [ protocol_dir.File("%s.slicc" % protocol) ]
-
 env.Append(BUILDERS={'SLICC' : slicc_builder})
-nodes = env.SLICC([], sources)
+
+for protocol in [env['CONF']['PROTOCOL']]:
+if protocol == "None":
+continue
+protocol_dir = None
+for path in env['PROTOCOL_DIRS']:
+if os.path.exists(path.File("%s.slicc" % protocol).abspath):
+protocol_dir = Dir(path)
+break
+
+if not protocol_dir:
+raise ValueError("Could not find {}.slicc in PROTOCOL_DIRS".format(
+protocol))
+
+nodes = env.SLICC([], [protocol_dir.File("%s.slicc" % protocol)])
+env.Depends(nodes, slicc_depends)
+
+append = {}
+if env['CLANG']:
+append['CCFLAGS'] = '-Wno-parentheses'
+for f in nodes:
+s = str(f)
+if s.endswith('.cc'):
+Source(f, append=append)
+elif s.endswith('.py'):
+filename = os.path.basename(s)
+# We currently only expect ${ident}_Controller.py to be  
generated,

+# and for it to contain a single SimObject with the same name +
+# protocol.
+assert(filename.endswith('_Controller.py'))
+SimObject(f, sim_objects=[os.path.splitext(filename)[0]])
+
+nodes = env.SLICC([], [protocol_base.File('RubySlicc_interfaces.slicc')])
 env.Depends(nodes, slicc_depends)

 append = {}
@@ -121,10 +157,3 @@
 s = str(f)
 if s.endswith('.cc'):
 Source(f, append=append)
-elif s.endswith('.py'):
-filename = os.path.basename(s)
-# We currently only expect ${ident}_Controller.py to be generated,  
and
-# for it to contain a single SimObject with the same name +  
protocol.

-assert(filename.endswith('_Controller.py'))
-SimObject(f,  
sim_objects=[protocol+'_'+os.path.splitext(filename)[0]])

-
diff --git a/src/mem/slicc/as

[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: Protocol-spec. in learning gem5

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58438 )



Change subject: configs,mem-ruby: Protocol-spec. in learning gem5
..

configs,mem-ruby: Protocol-spec. in learning gem5

Use protocol-specific names in Learning gem5 configs. Now, we should no
longer use the generic names for the controllers (it's deprecated). This
updates Learning gem5.

Website changes coming soon. (Hopefull before I push this...)

Change-Id: I18fc5b8bb0fef7c3b8b5cea8de4f73fc0f66a1b3
Signed-off-by: Jason Lowe-Power 
---
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
2 files changed, 20 insertions(+), 4 deletions(-)



diff --git a/configs/learning_gem5/part3/msi_caches.py  
b/configs/learning_gem5/part3/msi_caches.py

index 957adf2..5abfff0 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -105,7 +105,7 @@
 self.sequencers[i].connectCpuPorts(cpu)


-class L1Cache(L1Cache_Controller):
+class L1Cache(MSI_L1Cache_Controller):

 _version = 0
 @classmethod
@@ -169,7 +169,7 @@
 self.responseFromDirOrSibling = MessageBuffer(ordered = True)
 self.responseFromDirOrSibling.in_port =  
ruby_system.network.out_port


-class DirController(Directory_Controller):
+class DirController(MSI_Directory_Controller):

 _version = 0
 @classmethod
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py  
b/configs/learning_gem5/part3/ruby_caches_MI_example.py

index b67e6b1..9e5f9cf 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -102,7 +102,7 @@
 for i,cpu in enumerate(cpus):
 self.sequencers[i].connectCpuPorts(cpu)

-class L1Cache(L1Cache_Controller):
+class L1Cache(MI_example_L1Cache_Controller):

 _version = 0
 @classmethod
@@ -157,7 +157,7 @@
 self.responseToCache = MessageBuffer(ordered = True)
 self.responseToCache.in_port = ruby_system.network.out_port

-class DirController(Directory_Controller):
+class DirController(MI_example_Directory_Controller):

 _version = 0
 @classmethod

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I18fc5b8bb0fef7c3b8b5cea8de4f73fc0f66a1b3
Gerrit-Change-Number: 58438
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Use namespaces for protocol types

2022-03-30 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58432 )



Change subject: mem-ruby: Use namespaces for protocol types
..

mem-ruby: Use namespaces for protocol types

Wrap all protocol-specific types in `namespace `. This will
facilitate compiling multiple protocols into one binary.

There is a one-time hack to the generated `MachineType.cc` file to use
the namespace for the protocol until we generalize the machine types.

Change-Id: I5947e8ac69afe6f7ed257d7c5980ad65e9338acf
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/Type.py
2 files changed, 127 insertions(+), 4 deletions(-)



diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index a9f7373..e220731 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -246,7 +246,7 @@
 class $py_ident(RubyController):
 type = '$py_ident'
 cxx_header = 'mem/ruby/protocol/${c_ident}.hh'
-cxx_class = 'gem5::ruby::$py_ident'
+cxx_class = 'gem5::ruby::$protocol::$py_ident'
 ''')
 code.indent()
 for param in self.config_parameters:
@@ -306,6 +306,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 extern std::stringstream ${ident}_transitionComment;

 class $c_ident : public AbstractController
@@ -463,6 +466,7 @@
 code('''
 };

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5

@@ -550,6 +554,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 int $c_ident::m_num_controllers = 0;
 std::vector  $c_ident::eventVec;
 std::vector >  $c_ident::transVec;
@@ -827,7 +834,7 @@
 AbstractController::regStats();

 // For each type of controllers, one controller of that type is picked
-// to aggregate stats of all controllers of that type.
+// to aggregate stats of all controllers of that type.
 if (m_version == 0) {

 Profiler *profiler = params().ruby_system->getProfiler();
@@ -1221,6 +1228,7 @@
 return read;
 }

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5
 ''')
@@ -1282,6 +1290,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 void
 ${ident}_Controller::wakeup()
 {
@@ -1357,6 +1368,7 @@
 }
 }

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5
 ''')
@@ -1395,6 +1407,9 @@
 namespace ruby
 {

+namespace ${protocol}
+{
+
 TransitionResult
 ${ident}_Controller::doTransition(${ident}_Event event,
 ''')
@@ -1623,6 +1638,7 @@
 return TransitionResult_Valid;
 }

+} // namespace ${protocol}
 } // namespace ruby
 } // namespace gem5
 ''')
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index a9c5303..bb8ff0c 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -228,6 +228,16 @@

 namespace ruby
 {
+''')
+# For protocol-specific types, wrap in the protocol namespace
+if not self.shared:
+code('''
+
+namespace ${{protocol}}
+{
+''')
+
+code('''

 $klass ${{self.c_ident}}$parent
 {
@@ -394,7 +404,15 @@
 out << ::std::flush;
 return out;
 }
+''')
+# For protocol-specific types, close the protocol namespace
+if not self.shared:
+code('''

+} // namespace ${{protocol}}
+''')
+
+code('''
 } // namespace ruby
 } // namespace gem5

@@ -418,6 +436,16 @@

 namespace ruby
 {
+''')
+# For protocol-specific types, wrap in the protocol namespace
+if not self.shared:
+code('''
+
+namespace ${{protocol}}
+{
+''')
+
+code('''

 /** \\brief Print the state of this object */
 void
@@ -446,6 +474,13 @@
 for item in self.methods:
 code(self.methods[item].generateCode())

+# For protocol-specific types, close the protocol namespace
+if not self.shared:
+code('''
+
+} // namespace ${{protocol}}
+''')
+
 code('''
 } // namespace ruby
 } // namespace gem5
@@ -480,6 +515,13 @@
 {

 ''')
+# For protocol-specific types, wrap in the protocol namespace
+if not self.shared:
+code('''
+
+namespace ${{protocol}}
+{
+''')

 if self.isMachineType:
 code('struct MachineID;')
@@ -545,7 +587,16 @@

 ::std::ostream&
 operator<<(::std::ostream& out, const ${{self.c_ident}}& obj);
+''')

+# For protocol-specific types, close the protocol namespace
+if not self.shared:
+code('''
+
+} // namespace ${{protocol}}
+''')
+
+code('''
 } // namespace ruby
 } // namespace gem5
 ''')
@@ -594,6 +645,16 @@

 namespace ruby
 {
+''')
+# For protocol-specific types, wrap in the protocol namespace
+if not self.shared:
+code('''
+
+namespace ${{protocol}}
+{
+''')
+
+code('''

 // Code to convert the current state to an access permission
 AccessPermission ${{self.c_ident}}_to

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Reset stats in Ruby correctly

2022-03-02 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57269 )


Change subject: mem-ruby: Reset stats in Ruby correctly
..

mem-ruby: Reset stats in Ruby correctly

Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57269
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M src/mem/ruby/system/RubySystem.cc
1 file changed, 16 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 76d3f25..91c4bc3 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -477,6 +477,7 @@
 for (auto& network : m_networks) {
 network->resetStats();
 }
+ClockedObject::resetStats();
 }

 #ifndef PARTIAL_FUNC_READS

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Gerrit-Change-Number: 57269
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Reset stats in Ruby correctly

2022-03-01 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57269 )



Change subject: mem-ruby: Reset stats in Ruby correctly
..

mem-ruby: Reset stats in Ruby correctly

Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/system/RubySystem.cc
1 file changed, 11 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index 76d3f25..91c4bc3 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -477,6 +477,7 @@
 for (auto& network : m_networks) {
 network->resetStats();
 }
+ClockedObject::resetStats();
 }

 #ifndef PARTIAL_FUNC_READS

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Gerrit-Change-Id: Ie60c6f4be7b2a2705dc6da77b8b3d03717f13188
Gerrit-Change-Number: 57269
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Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Revert 7018c2b34

2022-02-26 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57109 )


Change subject: mem-ruby: Revert 7018c2b34
..

mem-ruby: Revert 7018c2b34

This reverts commit 7018c2b34e83c592843bd4ad714f93bc6179866d. This
commit needs more work which will take a while. Meanwhile the nightly
tests are broken because of this.

Change-Id: I11d01d50ab3a2d8fd649f1a825911e14815b1ca6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57109
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
1 file changed, 81 insertions(+), 94 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm  
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm

index bcac2c1..2496935 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -61,29 +61,26 @@
 {
   // STATES
   state_declaration(State, desc="Directory states",  
default="Directory_State_U") {

-U, AccessPermission:Backing_Store,  desc="unblocked";
+U, AccessPermission:Backing_Store, desc="unblocked";
+BL, AccessPermission:Busy,  desc="got L3 WB request";
 // BL is Busy because it's possible for the data only to be in the  
network
 // in the WB, L3 has sent it and gone on with its business in possibly  
I

 // state.
-BL, AccessPermission:Busy,  desc="got L3 WB request";
-BL_WM, AccessPermission:Busy,   desc="writing L3 WB to  
memory, waiting for ack";
-BDR_M, AccessPermission:Backing_Store,  desc="DMA read, blocked  
waiting for memory";
-BS_M, AccessPermission:Backing_Store,   desc="blocked waiting for  
memory";
-BM_M, AccessPermission:Backing_Store,   desc="blocked waiting for  
memory";
-B_M, AccessPermission:Backing_Store,desc="blocked waiting for  
memory";
-BP, AccessPermission:Backing_Store, desc="blocked waiting for  
probes, no need for memory";
-BDR_PM, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes and memory";
-BS_PM, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes and Memory";
-BM_PM, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes and Memory";
-B_PM, AccessPermission:Backing_Store,   desc="blocked waiting for  
probes and Memory";
-BDW_P, AccessPermission:Backing_Store,  desc="DMA write, blocked  
waiting for probes, no need for memory";
-BDW_WM, AccessPermission:Backing_Store, desc="DMA write, writing  
to memory, waiting for ack";
-BDR_Pm, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes, already got memory";
-BS_Pm, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes, already got memory";
-BM_Pm, AccessPermission:Backing_Store,  desc="blocked waiting for  
probes, already got memory";
-B_Pm, AccessPermission:Backing_Store,   desc="blocked waiting for  
probes, already got memory";
-B_WM, AccessPermission:Backing_Store,   desc="writing to memory,  
waiting for ack";
-B, AccessPermission:Backing_Store,  desc="sent response,  
Blocked til ack";
+BDR_M, AccessPermission:Backing_Store,  desc="DMA read, blocked  
waiting for memory";
+BS_M, AccessPermission:Backing_Store, desc="blocked  
waiting for memory";
+BM_M, AccessPermission:Backing_Store, desc="blocked  
waiting for memory";
+B_M, AccessPermission:Backing_Store, desc="blocked  
waiting for memory";
+BP, AccessPermission:Backing_Store, desc="blocked  
waiting for probes, no need for memory";
+BDR_PM, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes and memory";
+BS_PM, AccessPermission:Backing_Store,desc="blocked  
waiting for probes and Memory";
+BM_PM, AccessPermission:Backing_Store,desc="blocked  
waiting for probes and Memory";
+B_PM, AccessPermission:Backing_Store,desc="blocked  
waiting for probes and Memory";
+BDW_P, AccessPermission:Backing_Store, desc="DMA write, blocked  
waiting for probes, no need for memory";
+BDR_Pm, AccessPermission:Backing_Store, desc="DMA read, blocked  
waiting for probes, already got memory";
+BS_Pm, AccessPermission:Backing_Store,desc="blocked  
waiting for probes, already got memory";
+BM_Pm, AccessPermission:Backing_Store,desc="blocked  
waiting for probes, already got memory";
+B_Pm, AccessPermission:Backing_Store,desc="blocked  
waiting for probes, already got memory";
+B, AccessPermission:Backing_Store,

[gem5-dev] Change in gem5/gem5[release-staging-v21-2]: misc: Add release notes for v21.2

2021-12-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54603 )



Change subject: misc: Add release notes for v21.2
..

misc: Add release notes for v21.2

Signed-off-by: Jason Lowe-Power 
Change-Id: Ia92440b3b2bcd777b75b0c65ab65252b27734ebb
---
M RELEASE-NOTES.md
1 file changed, 69 insertions(+), 0 deletions(-)



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 6f672a8..7f6f327 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -1,3 +1,62 @@
+# Version 21.2.0.0
+
+## API (user-facing) changes
+
+All `SimObject` declarations in SConscript files now require the  
`sim_objects` parameter which is a list of the

+`SimObjects` declared in that file.
+Anyone who has a non-upstream `SimObject` will need to update their  
`SConscript` files.

+
+## Initial release of the "gem5 standard library"
+
+Previous release had an alpha release of the "components library."
+This has now been wrapped in a larger "standard library."
+
+The *gem5 standard library* is a Python package which contains the  
following:

+
+- **Components:** A set of Python classes which wrap gem5's models. Some  
of the components are preconfigured to match real hardware (e.g.,  
`SingleChannelDDR3_1600`) and others are parameterized. Components can be  
combined together onto *boards* which can be simulated.
+- **Resources:** A set of utilities to interact with the gem5-resources  
repository/website. Using this module allows you to *automatically*  
download and use many of gem5's prebuilt resources (e.g., kernels, disk  
images, etc.).
+- **Simulate:** *THIS MODULE IS ALPHA!* A simpler interface to gem5's  
simulation/run capabilities. Expect API changes to this module in future  
releases. Feedback is appreciated.
+- **Prebuilt**: These are fully functioning prebuilt systems. These  
systems are built from the components in `components`, but they have been  
preconfigured with "known-good" parameters. This release has a "demo" board  
to show an example of how to use the prebuilt systems.

+
+## Many Arm improvements
+
+- Improving configurability for Arm architectural extensions  
()
+- Allow Arm TLB to store partial entries (walk cache)  
()
+- Implement a multilevel TLB hierarchy  
()
+- Provide an Arm example script for the gem5-SST integration  
()

+
+## GPU improvements
+
+- Improvements to the VIPER coherence protocol to fix bugs and improve  
performance

+- VEGA GPU support added
+
+## gem5-SST bridges revived
+
+We now support gem5 cores connected to SST memory system for gem5 full  
system mode.

+This has been tested for RISC-V and Arm.
+See `ext/sst/README.md` for details.
+
+## LupIO devices
+
+LupIO devices were developed by Prof. Joel Porquet-Lupine as a set of  
open-source I/O devices to be used for teaching.
+They were designed to model a complete set of I/O devices that are neither  
too complex to teach in a classroom setting, or too simple to translate to  
understanding real-world devices.
+Our collection consists of a real-time clock, random number generator,  
terminal device, block device, system controller, timer device,  
programmable interrupt controller, as well as an inter-processor interrupt  
controller.
+A more detailed outline of LupIO can be found here:  
.
+Within gem5, these devices offer the capability to run simulations with a  
complete set of I/O devices that are both easy to understand and manipulate.

+
+The initial implementation of the LupIO devices are for the RISC-V ISA.
+However, they should be simple to extend to other ISAs through small  
source changes and updating the SConscripts.

+
+## Other improvements
+
+- Remove master/slave terminology: this was a closed ticket which was  
marked as done even if there were multiple references of master/slave in  
the config scripts which we fixed.

+- Armv8.2-A FEAT_UAO implementation
+- Implemented 'at' variants of file syscall in SE mode  
()

+- Improved modularity in SConscripts
+- Arm atomic support in the CHI protocol
+- Many testing improvements
+- New "tester" CPU which mimics GPUS
+
 # Version 21.1.0.2

 **[HOTFIX]** [A commit introduced `std::vector` with `resize()` to  
initialize all  
storages](https://gem5-review.googlesource.com/c/public/gem5/+/27085).


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Gerrit-Branch: release-staging-v21-2
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Gerrit-Change-Number: 54603
Gerrit-PatchSet: 1
Gerrit

[gem5-dev] Change in gem5/gem5[develop]: arch-arm,arch-sparc: Remove legacy stat for faults

2021-12-07 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52504 )


Change subject: arch-arm,arch-sparc: Remove legacy stat for faults
..

arch-arm,arch-sparc: Remove legacy stat for faults

This is a legacy stat that was not easy to tie to a Stats::Group.

In ARM, this stat wasn't actually counting all faults, it was only
counting the faults that occured in 32-bit mode, so it's probably safe
to remove the stat (it was wrong anyway). For SPARC, it's also unlikely
anyone is depending on this stat for their research.

Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52504
Reviewed-by: Gabe Black 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
4 files changed, 22 insertions(+), 8 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 64a07cb..e340d07 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -524,7 +524,6 @@
 FaultBase::invoke(tc);
 if (!FullSystem)
 return;
-countStat()++;

 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
 SCR scr = tc->readMiscReg(MISCREG_SCR);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 139d477..688faad 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -193,7 +193,6 @@
 // (exceptions taken in HYP mode or in AArch64 state)
 const ExceptionClass ec;

-FaultStat count;
 FaultVals(const FaultName& name_, const FaultOffset& offset_,
 const uint16_t& currELTOffset_, const uint16_t&  
currELHOffset_,

 const uint16_t& lowerEL64Offset_,
@@ -237,7 +236,6 @@

 ArmStaticInst *instrAnnotate(const StaticInstPtr &inst);
 virtual void annotate(AnnotationIDs id, uint64_t val) {}
-virtual FaultStat& countStat() = 0;
 virtual FaultOffset offset(ThreadContext *tc) = 0;
 virtual FaultOffset offset64(ThreadContext *tc) = 0;
 virtual OperatingMode nextMode() = 0;
@@ -269,7 +267,6 @@
 ArmFaultVals(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 ArmFault(_machInst, _iss) {}
 FaultName name() const override { return vals.name; }
-FaultStat & countStat() override { return vals.count; }
 FaultOffset offset(ThreadContext *tc) override;

 FaultOffset offset64(ThreadContext *tc) override;
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index ec7386f..421befa 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -503,7 +503,6 @@
 if (!FullSystem)
 return;

-countStat()++;

 // We can refer to this to see what the trap level -was-, but something
 // in the middle could change it in the regfile out from under us.
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index df09dc4..a5fb503 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -65,7 +65,6 @@
 const TrapType trapType;
 const FaultPriority priority;
 const PrivilegeLevelSpec nextPrivilegeLevel;
-FaultStat count;
 FaultVals(const FaultName& name_, const TrapType& trapType_,
 const FaultPriority& priority_, const PrivilegeLevelSpec&  
il)

 : name(name_), trapType(trapType_), priority(priority_),
@@ -76,7 +75,6 @@
 nullStaticInstPtr);
 virtual TrapType trapType() = 0;
 virtual FaultPriority priority() = 0;
-virtual FaultStat & countStat() = 0;
 virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
 };

@@ -89,7 +87,6 @@
 FaultName name() const { return vals.name; }
 TrapType trapType() { return vals.trapType; }
 FaultPriority priority() { return vals.priority; }
-FaultStat & countStat() { return vals.count; }

 PrivilegeLevel
 getNextLevel(PrivilegeLevel current)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Gerrit-Change-Number: 52504
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib,mem-ruby: CHI support in components

2021-11-23 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52463 )


Change subject: stdlib,mem-ruby: CHI support in components
..

stdlib,mem-ruby: CHI support in components

This changeset adds CHI support in the components library. Currently,
only a very simple one level protocol is implemented, but hopefully this
design will be able to scale to other more complex hierarchies.

I've tested this with RISC-V with 1 and 4 cores and with x86 with 1
core. Since we don't have an Arm-compatible board, I haven't tested with
ARM. Note that x86 with more than 1 core boots most of the way, but it
hangs during systemd (the kernel comes up completely).

Change-Id: I56953238c6b0ca5ac754b103a1b6ec05a85a0af5
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52463
Reviewed-by: Tiago Mück 
Reviewed-by: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
A src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
A src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
A  
src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

M src/python/SConscript
A src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py
A src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
A src/python/gem5/components/cachehierarchies/chi/__init__.py
A src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
A  
src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

9 files changed, 759 insertions(+), 0 deletions(-)

Approvals:
  Tiago Mück: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index d210960..f9b74c0 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -50,6 +50,22 @@
 'gem5/components/cachehierarchies/abstract_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies',
 'gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py')
+PySource('gem5.components.cachehierarchies.chi',
+'gem5/components/cachehierarchies/chi/__init__.py')
+PySource('gem5.components.cachehierarchies.chi',
+'gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/__init__.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/abstract_node.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/directory.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/dma_requestor.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/memory_controller.py')
 PySource('gem5.components.cachehierarchies.classic',
 'gem5/components/cachehierarchies/classic/__init__.py')
 PySource('gem5.components.cachehierarchies.classic',
diff --git a/src/python/gem5/components/cachehierarchies/chi/__init__.py  
b/src/python/gem5/components/cachehierarchies/chi/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/components/cachehierarchies/chi/__init__.py
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py

new file mode 100644
index 000..e8797b6
--- /dev/null
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
@@ -0,0 +1,132 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products

[gem5-dev] Change in gem5/gem5[develop]: tests: Fix riscv boot exit tests

2021-11-11 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52644 )


Change subject: tests: Fix riscv boot exit tests
..

tests: Fix riscv boot exit tests

Due to this change:
https://gem5-review.googlesource.com/c/public/gem5/+/52089
full RISCV boot tests were added, which makes the "tick_exit" parameter
optional (left to 'None' if simulating a full boot). However, the
simulation function was not updated to not pass the "tick_exit"
parameter if not set. This cause an error. This patch fixes this.

Change-Id: I9c62a6a46d9334a2e9fbad2221b42a1ff4843a54
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52644
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/configs/riscv_boot_exit_run.py
1 file changed, 24 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index 4f0c49f..8add619 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -159,7 +159,10 @@

 m5.instantiate()

-exit_event = m5.simulate(args.tick_exit)
+if args.tick_exit:
+exit_event = m5.simulate(args.tick_exit)
+else:
+exit_event = m5.simulate()
 print(
 "Exiting @ tick {} because {}.".format(m5.curTick(),  
exit_event.getCause())

 )

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9c62a6a46d9334a2e9fbad2221b42a1ff4843a54
Gerrit-Change-Number: 52644
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Remove 'override-download' flag from insttest

2021-11-11 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52643 )


Change subject: tests: Remove 'override-download' flag from insttest
..

tests: Remove 'override-download' flag from insttest

This flag was previously passed to the 'simple_binary_run.py' to
override downloads. However, since this patch:
https://gem5-review.googlesource.com/c/public/gem5/+/52086
we no longer use the flag. It appears in this patch the insttest test
was not updated and, as such, this test failed:
https://jenkins.gem5.org/job/nightly/38/

This, in part, will fix the nightly build.

Change-Id: I4fb5ab175c73687304c04fe426f81519d23574a7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52643
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/insttest_se/test.py
1 file changed, 22 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py
index 0464a9e..25c8823 100644
--- a/tests/gem5/insttest_se/test.py
+++ b/tests/gem5/insttest_se/test.py
@@ -60,7 +60,6 @@
 config_args=[
 binary,
 cpu,
-"--override-download",
 "--resource-directory",
 resource_path,
 ],

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4fb5ab175c73687304c04fe426f81519d23574a7
Gerrit-Change-Number: 52643
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Update pybind11 to v2.8.1

2021-11-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52523 )


Change subject: ext: Update pybind11 to v2.8.1
..

ext: Update pybind11 to v2.8.1

Change-Id: Ia1c7081377f53fd470addf35526f8b28a949a7b0
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52523
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M ext/pybind11/tools/setup_main.py.in
M ext/pybind11/tests/test_custom_type_casters.py
M ext/pybind11/tests/test_cmake_build/installed_function/CMakeLists.txt
M ext/pybind11/tests/test_numpy_dtypes.py
M ext/pybind11/tests/test_stl_binders.py
M ext/pybind11/tests/CMakeLists.txt
M ext/pybind11/tests/test_enum.py
M ext/pybind11/tests/test_cmake_build/installed_embed/CMakeLists.txt
M ext/pybind11/docs/advanced/embedding.rst
M ext/pybind11/tests/test_stl.cpp
M ext/pybind11/docs/upgrade.rst
M ext/pybind11/tests/test_pickling.cpp
M ext/pybind11/docs/advanced/misc.rst
M ext/pybind11/pybind11/commands.py
M ext/pybind11/include/pybind11/pybind11.h
A ext/pybind11/include/pybind11/stl/filesystem.h
M ext/pybind11/tests/test_numpy_array.cpp
M ext/pybind11/tests/test_tagbased_polymorphic.cpp
M ext/pybind11/tests/test_stl.py
M ext/pybind11/docs/faq.rst
M ext/pybind11/docs/requirements.txt
M ext/pybind11/setup.py
M ext/pybind11/tests/test_multiple_inheritance.cpp
M ext/pybind11/docs/advanced/cast/strings.rst
M ext/pybind11/docs/advanced/cast/overview.rst
M ext/pybind11/pybind11/__init__.py
M ext/pybind11/tests/test_embed/CMakeLists.txt
M ext/pybind11/tests/test_factory_constructors.py
A ext/pybind11/include/pybind11/gil.h
M ext/pybind11/setup.cfg
M ext/pybind11/tests/test_eigen.cpp
M ext/pybind11/include/pybind11/eval.h
M ext/pybind11/tests/test_chrono.py
M ext/pybind11/tests/test_cmake_build/test.py
M ext/pybind11/tests/test_call_policies.py
A ext/pybind11/noxfile.py
M ext/pybind11/CMakeLists.txt
M ext/pybind11/tests/test_numpy_array.py
M ext/pybind11/pybind11/_version.pyi
M ext/pybind11/tools/pybind11Config.cmake.in
M ext/pybind11/tests/test_gil_scoped.cpp
M ext/pybind11/tests/test_pickling.py
M ext/pybind11/tests/test_factory_constructors.cpp
M ext/pybind11/tests/test_eigen.py
M ext/pybind11/tests/test_methods_and_attributes.py
M ext/pybind11/docs/advanced/pycpp/utilities.rst
M ext/pybind11/docs/classes.rst
M ext/pybind11/tests/test_cmake_build/subdirectory_target/CMakeLists.txt
M ext/pybind11/tests/test_virtual_functions.py
M ext/pybind11/docs/advanced/cast/eigen.rst
M ext/pybind11/docs/benchmark.py
M ext/pybind11/tests/test_cmake_build/installed_target/CMakeLists.txt
M ext/pybind11/include/pybind11/buffer_info.h
M ext/pybind11/docs/changelog.rst
M ext/pybind11/tests/test_builtin_casters.cpp
M ext/pybind11/tests/test_opaque_types.py
M ext/pybind11/include/pybind11/detail/descr.h
M ext/pybind11/include/pybind11/chrono.h
M ext/pybind11/include/pybind11/operators.h
M ext/pybind11/pybind11/_version.py
M ext/pybind11/tests/pytest.ini
A ext/pybind11/tests/test_exceptions.h
M ext/pybind11/docs/advanced/pycpp/numpy.rst
M ext/pybind11/tests/test_exceptions.cpp
M ext/pybind11/docs/compiling.rst
M ext/pybind11/tests/test_methods_and_attributes.cpp
M ext/pybind11/tests/test_opaque_types.cpp
M ext/pybind11/README.rst
M ext/pybind11/include/pybind11/detail/class.h
M ext/pybind11/tools/pybind11NewTools.cmake
M ext/pybind11/docs/advanced/exceptions.rst
M ext/pybind11/tests/test_callbacks.py
M ext/pybind11/tests/valgrind-numpy-scipy.supp
M ext/pybind11/tests/pybind11_cross_module_tests.cpp
M ext/pybind11/tests/test_buffers.py
M ext/pybind11/include/pybind11/detail/init.h
M ext/pybind11/include/pybind11/functional.h
M ext/pybind11/tests/test_builtin_casters.py
M ext/pybind11/tests/test_cmake_build/subdirectory_embed/CMakeLists.txt
M ext/pybind11/tests/test_buffers.cpp
M ext/pybind11/tools/make_changelog.py
M ext/pybind11/tools/pybind11Tools.cmake
M ext/pybind11/tests/test_operator_overloading.cpp
M ext/pybind11/include/pybind11/iostream.h
M ext/pybind11/tests/test_local_bindings.cpp
M ext/pybind11/tests/test_local_bindings.py
M ext/pybind11/tests/env.py
M ext/pybind11/tools/libsize.py
M ext/pybind11/tests/test_embed/external_module.cpp
M ext/pybind11/include/pybind11/detail/internals.h
M ext/pybind11/tests/test_operator_overloading.py
M ext/pybind11/include/pybind11/stl_bind.h
M ext/pybind11/tests/test_constants_and_functions.cpp
M ext/pybind11/tests/test_exceptions.py
M ext/pybind11/tests/test_smart_ptr.cpp
M ext/pybind11/tests/test_class.cpp
M ext/pybind11/pyproject.toml
M ext/pybind11/tests/test_kwargs_and_defaults.cpp
M ext/pybind11/include/pybind11/pytypes.h
M ext/pybind11/tools/check-style.sh
M ext/pybind11/tests/local_bindings.h
M ext/pybind11/tests/pybind11_tests.h
M ext/pybind11/tests/test_iostream.py
M ext/pybind11/docs/advanced/classes.rst
M ext/pybind11/tests/test_modules.cpp
M ext/pybind11/pybind11/__main__.py
M ext/pybind11/tests/test_e

[gem5-dev] Change in gem5/gem5[develop]: ext: Update pybind11 to v2.8.1

2021-11-06 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52523 )



Change subject: ext: Update pybind11 to v2.8.1
..

ext: Update pybind11 to v2.8.1

Change-Id: Ia1c7081377f53fd470addf35526f8b28a949a7b0
Signed-off-by: Jason Lowe-Power 
---
M ext/pybind11/tools/setup_main.py.in
M ext/pybind11/tests/test_custom_type_casters.py
M ext/pybind11/tests/test_cmake_build/installed_function/CMakeLists.txt
M ext/pybind11/tests/test_numpy_dtypes.py
M ext/pybind11/tests/test_stl_binders.py
M ext/pybind11/tests/CMakeLists.txt
M ext/pybind11/tests/test_enum.py
M ext/pybind11/tests/test_cmake_build/installed_embed/CMakeLists.txt
M ext/pybind11/docs/advanced/embedding.rst
M ext/pybind11/tests/test_stl.cpp
M ext/pybind11/docs/upgrade.rst
M ext/pybind11/tests/test_pickling.cpp
M ext/pybind11/docs/advanced/misc.rst
M ext/pybind11/pybind11/commands.py
M ext/pybind11/include/pybind11/pybind11.h
A ext/pybind11/include/pybind11/stl/filesystem.h
M ext/pybind11/tests/test_numpy_array.cpp
M ext/pybind11/tests/test_tagbased_polymorphic.cpp
M ext/pybind11/tests/test_stl.py
M ext/pybind11/docs/faq.rst
M ext/pybind11/docs/requirements.txt
M ext/pybind11/setup.py
M ext/pybind11/tests/test_multiple_inheritance.cpp
M ext/pybind11/docs/advanced/cast/strings.rst
M ext/pybind11/docs/advanced/cast/overview.rst
M ext/pybind11/pybind11/__init__.py
M ext/pybind11/tests/test_embed/CMakeLists.txt
M ext/pybind11/tests/test_factory_constructors.py
A ext/pybind11/include/pybind11/gil.h
M ext/pybind11/setup.cfg
M ext/pybind11/tests/test_eigen.cpp
M ext/pybind11/include/pybind11/eval.h
M ext/pybind11/tests/test_chrono.py
M ext/pybind11/tests/test_cmake_build/test.py
M ext/pybind11/tests/test_call_policies.py
A ext/pybind11/noxfile.py
M ext/pybind11/CMakeLists.txt
M ext/pybind11/tests/test_numpy_array.py
M ext/pybind11/pybind11/_version.pyi
M ext/pybind11/tools/pybind11Config.cmake.in
M ext/pybind11/tests/test_gil_scoped.cpp
M ext/pybind11/tests/test_pickling.py
M ext/pybind11/tests/test_factory_constructors.cpp
M ext/pybind11/tests/test_eigen.py
M ext/pybind11/tests/test_methods_and_attributes.py
M ext/pybind11/docs/advanced/pycpp/utilities.rst
M ext/pybind11/docs/classes.rst
M ext/pybind11/tests/test_cmake_build/subdirectory_target/CMakeLists.txt
M ext/pybind11/tests/test_virtual_functions.py
M ext/pybind11/docs/advanced/cast/eigen.rst
M ext/pybind11/docs/benchmark.py
M ext/pybind11/tests/test_cmake_build/installed_target/CMakeLists.txt
M ext/pybind11/include/pybind11/buffer_info.h
M ext/pybind11/docs/changelog.rst
M ext/pybind11/tests/test_builtin_casters.cpp
M ext/pybind11/tests/test_opaque_types.py
M ext/pybind11/include/pybind11/detail/descr.h
M ext/pybind11/include/pybind11/chrono.h
M ext/pybind11/include/pybind11/operators.h
M ext/pybind11/pybind11/_version.py
M ext/pybind11/tests/pytest.ini
A ext/pybind11/tests/test_exceptions.h
M ext/pybind11/docs/advanced/pycpp/numpy.rst
M ext/pybind11/tests/test_exceptions.cpp
M ext/pybind11/docs/compiling.rst
M ext/pybind11/tests/test_methods_and_attributes.cpp
M ext/pybind11/tests/test_opaque_types.cpp
M ext/pybind11/README.rst
M ext/pybind11/include/pybind11/detail/class.h
M ext/pybind11/tools/pybind11NewTools.cmake
M ext/pybind11/docs/advanced/exceptions.rst
M ext/pybind11/tests/test_callbacks.py
M ext/pybind11/tests/valgrind-numpy-scipy.supp
M ext/pybind11/tests/pybind11_cross_module_tests.cpp
M ext/pybind11/tests/test_buffers.py
M ext/pybind11/include/pybind11/detail/init.h
M ext/pybind11/include/pybind11/functional.h
M ext/pybind11/tests/test_builtin_casters.py
M ext/pybind11/tests/test_cmake_build/subdirectory_embed/CMakeLists.txt
M ext/pybind11/tests/test_buffers.cpp
M ext/pybind11/tools/make_changelog.py
M ext/pybind11/tools/pybind11Tools.cmake
M ext/pybind11/tests/test_operator_overloading.cpp
M ext/pybind11/include/pybind11/iostream.h
M ext/pybind11/tests/test_local_bindings.cpp
M ext/pybind11/tests/test_local_bindings.py
M ext/pybind11/tests/env.py
M ext/pybind11/tools/libsize.py
M ext/pybind11/tests/test_embed/external_module.cpp
M ext/pybind11/include/pybind11/detail/internals.h
M ext/pybind11/tests/test_operator_overloading.py
M ext/pybind11/include/pybind11/stl_bind.h
M ext/pybind11/tests/test_constants_and_functions.cpp
M ext/pybind11/tests/test_exceptions.py
M ext/pybind11/tests/test_smart_ptr.cpp
M ext/pybind11/tests/test_class.cpp
M ext/pybind11/pyproject.toml
M ext/pybind11/tests/test_kwargs_and_defaults.cpp
M ext/pybind11/include/pybind11/pytypes.h
M ext/pybind11/tools/check-style.sh
M ext/pybind11/tests/local_bindings.h
M ext/pybind11/tests/pybind11_tests.h
M ext/pybind11/tests/test_iostream.py
M ext/pybind11/docs/advanced/classes.rst
M ext/pybind11/tests/test_modules.cpp
M ext/pybind11/pybind11/__main__.py
M ext/pybind11/tests/test_enum.cpp
M ext/pybind11/tests/test_kwargs_and_defaults.py
M ext/pybind11/include/pybind11/stl.h
M ext/pybind11/tests/test_callbacks.cp

[gem5-dev] Change in gem5/gem5[develop]: mem: Initialize all stats in MemInterface

2021-11-06 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52503 )


Change subject: mem: Initialize all stats in MemInterface
..

mem: Initialize all stats in MemInterface

Change-Id: I1ee9ca14127abb7311ee8282b3fef1051277592c
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52503
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/mem/mem_interface.cc
1 file changed, 20 insertions(+), 0 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index a3e5963..f8cb01a 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -1893,6 +1893,12 @@

 ADD_STAT(bytesPerActivate, statistics::units::Byte::get(),
  "Bytes accessed per row activation"),
+
+ADD_STAT(bytesRead, statistics::units::Byte::get(),
+"Total bytes read"),
+ADD_STAT(bytesWritten, statistics::units::Byte::get(),
+"Total bytes written"),
+
 ADD_STAT(avgRdBW, statistics::units::Rate<
 statistics::units::Byte, statistics::units::Second>::get(),
  "Average DRAM read bandwidth in MiBytes/s"),

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52503
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1ee9ca14127abb7311ee8282b3fef1051277592c
Gerrit-Change-Number: 52503
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm,arch-sparc: Remove legacy stat for faults

2021-11-05 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52504 )



Change subject: arch-arm,arch-sparc: Remove legacy stat for faults
..

arch-arm,arch-sparc: Remove legacy stat for faults

This is a legacy stat that was not easy to tie to a Stats::Group.

In ARM, this stat wasn't actually counting all faults, it was only
counting the faults that occured in 32-bit mode, so it's probably safe
to remove the stat (it was wrong anyway). For SPARC, it's also unlikely
anyone is depending on this stat for their research.

Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Signed-off-by: Jason Lowe-Power 
---
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
4 files changed, 17 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 1e94329..620197e 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -524,7 +524,6 @@
 FaultBase::invoke(tc);
 if (!FullSystem)
 return;
-countStat()++;

 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
 SCR scr = tc->readMiscReg(MISCREG_SCR);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 139d477..688faad 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -193,7 +193,6 @@
 // (exceptions taken in HYP mode or in AArch64 state)
 const ExceptionClass ec;

-FaultStat count;
 FaultVals(const FaultName& name_, const FaultOffset& offset_,
 const uint16_t& currELTOffset_, const uint16_t&  
currELHOffset_,

 const uint16_t& lowerEL64Offset_,
@@ -237,7 +236,6 @@

 ArmStaticInst *instrAnnotate(const StaticInstPtr &inst);
 virtual void annotate(AnnotationIDs id, uint64_t val) {}
-virtual FaultStat& countStat() = 0;
 virtual FaultOffset offset(ThreadContext *tc) = 0;
 virtual FaultOffset offset64(ThreadContext *tc) = 0;
 virtual OperatingMode nextMode() = 0;
@@ -269,7 +267,6 @@
 ArmFaultVals(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 ArmFault(_machInst, _iss) {}
 FaultName name() const override { return vals.name; }
-FaultStat & countStat() override { return vals.count; }
 FaultOffset offset(ThreadContext *tc) override;

 FaultOffset offset64(ThreadContext *tc) override;
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 6ead79a..d38ac12 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -503,7 +503,6 @@
 if (!FullSystem)
 return;

-countStat()++;

 // We can refer to this to see what the trap level -was-, but something
 // in the middle could change it in the regfile out from under us.
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index df09dc4..a5fb503 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -65,7 +65,6 @@
 const TrapType trapType;
 const FaultPriority priority;
 const PrivilegeLevelSpec nextPrivilegeLevel;
-FaultStat count;
 FaultVals(const FaultName& name_, const TrapType& trapType_,
 const FaultPriority& priority_, const PrivilegeLevelSpec&  
il)

 : name(name_), trapType(trapType_), priority(priority_),
@@ -76,7 +75,6 @@
 nullStaticInstPtr);
 virtual TrapType trapType() = 0;
 virtual FaultPriority priority() = 0;
-virtual FaultStat & countStat() = 0;
 virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
 };

@@ -89,7 +87,6 @@
 FaultName name() const { return vals.name; }
 TrapType trapType() { return vals.trapType; }
 FaultPriority priority() { return vals.priority; }
-FaultStat & countStat() { return vals.count; }

 PrivilegeLevel
 getNextLevel(PrivilegeLevel current)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Gerrit-Change-Number: 52504
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Initialize all stats in MemInterface

2021-11-05 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52503 )



Change subject: mem: Initialize all stats in MemInterface
..

mem: Initialize all stats in MemInterface

Change-Id: I1ee9ca14127abb7311ee8282b3fef1051277592c
Signed-off-by: Jason Lowe-Power 
---
M src/mem/mem_interface.cc
1 file changed, 16 insertions(+), 0 deletions(-)



diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index a3e5963..f8cb01a 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -1893,6 +1893,12 @@

 ADD_STAT(bytesPerActivate, statistics::units::Byte::get(),
  "Bytes accessed per row activation"),
+
+ADD_STAT(bytesRead, statistics::units::Byte::get(),
+"Total bytes read"),
+ADD_STAT(bytesWritten, statistics::units::Byte::get(),
+"Total bytes written"),
+
 ADD_STAT(avgRdBW, statistics::units::Rate<
 statistics::units::Byte, statistics::units::Second>::get(),
  "Average DRAM read bandwidth in MiBytes/s"),

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1ee9ca14127abb7311ee8282b3fef1051277592c
Gerrit-Change-Number: 52503
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: stdlib,mem-ruby: CHI support in components

2021-11-04 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52463 )



Change subject: stdlib,mem-ruby: CHI support in components
..

stdlib,mem-ruby: CHI support in components

This changeset adds CHI support in the components library. Currently,
only a very simple one level protocol is implemented, but hopefully this
design will be able to scale to other more complex hierarchies.

I've tested this with RISC-V with 1 and 4 cores and with x86 with 1
core. Since we don't have an Arm-compatible board, I haven't tested with
ARM. Note that x86 with more than 1 core boots most of the way, but it
hangs during systemd (the kernel comes up completely).

Change-Id: I56953238c6b0ca5ac754b103a1b6ec05a85a0af5
Signed-off-by: Jason Lowe-Power 
---
A src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
A src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py
A  
src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

M src/python/SConscript
A src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py
A src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
A src/python/gem5/components/cachehierarchies/chi/__init__.py
A src/python/gem5/components/cachehierarchies/chi/nodes/directory.py
A  
src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

9 files changed, 750 insertions(+), 0 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index e750829..c3c3374 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -46,6 +46,22 @@
 'gem5/components/cachehierarchies/abstract_cache_hierarchy.py')
 PySource('gem5.components.cachehierarchies',
 'gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py')
+PySource('gem5.components.cachehierarchies.chi',
+'gem5/components/cachehierarchies/chi/__init__.py')
+PySource('gem5.components.cachehierarchies.chi',
+'gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/__init__.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/abstract_node.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/directory.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/dma_requestor.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py')
+PySource('gem5.components.cachehierarchies.chi.nodes',
+'gem5/components/cachehierarchies/chi/nodes/memory_controller.py')
 PySource('gem5.components.cachehierarchies.classic',
 'gem5/components/cachehierarchies/classic/__init__.py')
 PySource('gem5.components.cachehierarchies.classic',
diff --git a/src/python/gem5/components/cachehierarchies/chi/__init__.py  
b/src/python/gem5/components/cachehierarchies/chi/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/components/cachehierarchies/chi/__init__.py
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/__init__.py
diff --git  
a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py  
b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py

new file mode 100644
index 000..4702ca0
--- /dev/null
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
@@ -0,0 +1,129 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIA

[gem5-dev] Change in gem5/gem5[develop]: tests: Add RISC-V Ruby boot tests

2021-10-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51450 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Add RISC-V Ruby boot tests
..

tests: Add RISC-V Ruby boot tests

Change-Id: I6a173dcef974fef726991bf3db8b7355838e2d04
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51450
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M tests/gem5/configs/riscv_boot_exit_run.py
2 files changed, 66 insertions(+), 9 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index b97c8ad..1798e4d 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -36,6 +36,7 @@
 import m5
 from m5.objects import Root

+from gem5.components.boards.riscv_board import RiscvBoard
 from gem5.components.memory.single_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
@@ -67,6 +68,15 @@
 )

 parser.add_argument(
+"-m",
+"--mem-system",
+type=str,
+choices=("classic", "mi_example",),
+required=True,
+help="The memory system.",
+)
+
+parser.add_argument(
 "-t",
 "--tick-exit",
 type=int,
@@ -94,15 +104,24 @@
 # Run a check to ensure the right version of gem5 is being used.
 requires(isa_required=ISA.RISCV)

-from gem5.components.cachehierarchies.classic.\
-private_l1_private_l2_cache_hierarchy import \
-PrivateL1PrivateL2CacheHierarchy
-from gem5.components.boards.riscv_board import RiscvBoard
+if args.mem_system == "classic":
+from gem5.components.cachehierarchies.classic.\
+private_l1_private_l2_cache_hierarchy import \
+PrivateL1PrivateL2CacheHierarchy

-# Setup the cache hierarchy.
-cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
-l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
-)
+# Setup the cache hierarchy.
+cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
+)
+elif args.mem_system == "mi_example":
+from gem5.components.cachehierarchies.ruby.\
+mi_example_cache_hierarchy import \
+MIExampleCacheHierarchy
+
+# Setup the cache hierarchy.
+cache_hierarchy = MIExampleCacheHierarchy(
+size="32KiB", assoc=8
+)

 # Setup the system memory.
 memory = SingleChannelDDR3_1600()
diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py  
b/tests/gem5/riscv-boot-tests/test_linux_boot.py

index bdaa1e6..940702a 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -37,10 +37,12 @@
 def test_boot(
 cpu: str,
 num_cpus: int,
+cache_type: str,
 to_tick: int,
 length: str,
 ):
-name = "{}-cpu_{}-cores_riscv-boot-test_to-tick".format(cpu,  
str(num_cpus))

+name = "{}-cpu_{}-{}-cores_riscv-boot-test_to-tick".format(
+cpu, str(num_cpus), cache_type)

 verifiers = []
 exit_regex = re.compile(
@@ -66,6 +68,8 @@
 cpu,
 "--num-cpus",
 str(num_cpus),
+"--mem-system",
+cache_type,
 "--tick-exit",
 str(to_tick),
 "--override-download",
@@ -83,6 +87,7 @@
 test_boot(
 cpu="atomic",
 num_cpus=1,
+cache_type="classic",
 to_tick=100,  # Simulates 1/100th of a second.
 length=constants.quick_tag,
 )
@@ -90,6 +95,15 @@
 test_boot(
 cpu="timing",
 num_cpus=1,
+cache_type="classic",
+to_tick=100,
+length=constants.quick_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=1,
+cache_type="mi_example",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -97,6 +111,7 @@
 test_boot(
 cpu="o3",
 num_cpus=1,
+cache_type="classic",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -104,6 +119,15 @@
 test_boot(
 cpu="timing",
 num_cpus=4,
+cache_type="classic",
+to_tick=100,
+length=constants.quick_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=4,
+cache_type="mi_example",
 to_tick=100,
 length=constants.quick_tag,
 )

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6a173dcef974fef726991bf3db8b7355838e2d04
Gerrit-Change-Number: 51450

[gem5-dev] Change in gem5/gem5[develop]: python,configs: Add Ruby support to RISC-V board

2021-10-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51449 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: python,configs: Add Ruby support to RISC-V board
..

python,configs: Add Ruby support to RISC-V board

Take out guards stopping the RISC-V board from being configured with
Ruby and update the I/O config with a check for Ruby. Also, add a
comment in the example file that Ruby is now supported.

Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51449
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/python/gem5/components/boards/riscv_board.py
M configs/example/components-library/riscv_fs.py
2 files changed, 40 insertions(+), 17 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/components-library/riscv_fs.py  
b/configs/example/components-library/riscv_fs.py

index eadac8b..9b9d5f0 100644
--- a/configs/example/components-library/riscv_fs.py
+++ b/configs/example/components-library/riscv_fs.py
@@ -57,7 +57,9 @@
 PrivateL1PrivateL2CacheHierarchy,
 )

-# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been  
tested.

+# Setup the cache hierarchy.
+# For classic, PrivateL1PrivateL2 and NoCache have been tested.
+# For Ruby, MESI_Two_Level and MI_example have been tested.
 cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
 l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
 )
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index a41f33f..d42cfd5 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -89,9 +89,6 @@

 requires(isa_required=ISA.RISCV)

-if cache_hierarchy.is_ruby():
-raise EnvironmentError("RiscvBoard is not compatible with  
Ruby")

-
 self.workload = RiscvLinux()

 # Contains a CLINT, PLIC, UART, and some functions for the dtb,  
etc.

@@ -124,20 +121,26 @@

 def _setup_io_devices(self) -> None:
 """Connect the I/O devices to the I/O bus"""
-for device in self._off_chip_devices:
-device.pio = self.iobus.mem_side_ports
-for device in self._on_chip_devices:
-device.pio = self.get_cache_hierarchy().get_mem_side_port()

-self.bridge = Bridge(delay="10ns")
-self.bridge.mem_side_port = self.iobus.cpu_side_ports
-self.bridge.cpu_side_port = (
-self.get_cache_hierarchy().get_mem_side_port()
-)
-self.bridge.ranges = [
-AddrRange(dev.pio_addr, size=dev.pio_size)
-for dev in self._off_chip_devices
-]
+if self.get_cache_hierarchy().is_ruby():
+for device in self._off_chip_devices + self._on_chip_devices:
+device.pio = self.iobus.mem_side_ports
+
+else:
+for device in self._off_chip_devices:
+device.pio = self.iobus.mem_side_ports
+for device in self._on_chip_devices:
+device.pio = self.get_cache_hierarchy().get_mem_side_port()
+
+self.bridge = Bridge(delay="10ns")
+self.bridge.mem_side_port = self.iobus.cpu_side_ports
+self.bridge.cpu_side_port = (
+self.get_cache_hierarchy().get_mem_side_port()
+)
+self.bridge.ranges = [
+AddrRange(dev.pio_addr, size=dev.pio_size)
+for dev in self._off_chip_devices
+]

 def _setup_pma(self) -> None:
 """Set the PMA devices on each core"""

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Gerrit-Change-Number: 51449
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add RISC-V atomic support to Ruby

2021-10-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51447 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: mem-ruby: Add RISC-V atomic support to Ruby
..

mem-ruby: Add RISC-V atomic support to Ruby

RISC-V atomics carry a atomic functor that needs to be executed in the
cache hierarchy. To implement this in Ruby, we execute the functor in
the hitCallback function. Note that these functions are slightly
different than the atomic functions used in the GPU model and the GPU
coalescer even though they have similar semantics.

This change was tested with RISC-V Linux boot which has a few atomics
and linux boot finishes successfully. Previously, the boot got stuck
after the incorrect atomic operation.

Change-Id: I47a69c05ad9f4267d0220023289116e62b5231be
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51447
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Maintainer: Matt Sinclair 
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 35 insertions(+), 0 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/system/Sequencer.cc  
b/src/mem/ruby/system/Sequencer.cc

index 77ab170..ac52c5f 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -613,6 +613,15 @@
 data.setData(&overwrite_val[0],
  getOffset(request_address), pkt->getSize());
 DPRINTF(RubySequencer, "swap data %s\n", data);
+} else if (pkt->isAtomicOp()) {
+// Set the data in the packet to the old value in the cache
+pkt->setData(
+data.getData(getOffset(request_address), pkt->getSize()));
+DPRINTF(RubySequencer, "AMO original data %s\n", data);
+// execute AMO operation
+(*(pkt->getAtomicOp()))(
+data.getDataMod(getOffset(request_address)));
+DPRINTF(RubySequencer, "AMO new data %s\n", data);
 } else if (type != RubyRequestType_Store_Conditional ||  
llscSuccess) {

 // Types of stores set the actual data here, apart from
 // failed Store Conditional requests

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I47a69c05ad9f4267d0220023289116e62b5231be
Gerrit-Change-Number: 51447
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bradford Beckmann 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Generalize ruby components in library

2021-10-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51448 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: python: Generalize ruby components in library
..

python: Generalize ruby components in library

The Ruby protocols in the components library had some special cases for
x86 that ended up breaking other ISAs (RISC-V in my testing). This
change generalizes those scripts slightly so they will work with both
x86 and RISC-V

Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51448
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
Reviewed-by: Bobby R. Bruce 
---
M  
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

2 files changed, 33 insertions(+), 28 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

index e5d0353..9d42365 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -110,21 +110,14 @@
 board.get_clock_domain(),
 )

+cache.sequencer = RubySequencer(
+version=i,
+dcache=cache.L1Dcache,
+clk_domain=cache.clk_domain,
+)
+
 if board.has_io_bus():
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.L1Dcache,
-clk_domain=cache.clk_domain,
-pio_request_port=board.get_io_bus().cpu_side_ports,
-mem_request_port=board.get_io_bus().cpu_side_ports,
-pio_response_port=board.get_io_bus().mem_side_ports,
-)
-else:
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.L1Dcache,
-clk_domain=cache.clk_domain,
-)
+cache.sequencer.connectIOPorts(board.get_io_bus())

 cache.ruby_system = self.ruby_system

diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

index 338d1c4..523ba49 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

@@ -97,21 +97,14 @@
 clk_domain=board.get_clock_domain(),
 )

+cache.sequencer = RubySequencer(
+version=i,
+dcache=cache.cacheMemory,
+clk_domain=cache.clk_domain,
+)
+
 if board.has_io_bus():
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.cacheMemory,
-clk_domain=cache.clk_domain,
-pio_request_port=board.get_io_bus().cpu_side_ports,
-mem_request_port=board.get_io_bus().cpu_side_ports,
-pio_response_port=board.get_io_bus().mem_side_ports,
-)
-else:
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.L1Dcache,
-clk_domain=cache.clk_domain,
-)
+cache.sequencer.connectIOPorts(board.get_io_bus())

 cache.ruby_system = self.ruby_system


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Gerrit-Change-Number: 51448
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Updates to improve debugging output

2021-10-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51787 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: python: Updates to improve debugging output
..

python: Updates to improve debugging output

This changeset updates SimObject and Proxy so that certain errors are
easier to diagnose. In SimObject, the warn() statement could cause
another exception, so it's split into two statements. In Proxy, it is
helpful to know which attribute is referenced when there's a mistake.

Change-Id: I3704a247b8b40e18ffc5e4a6241a74829313c07e
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51787
Maintainer: Bobby R. Bruce 
Maintainer: Andreas Sandberg 
Reviewed-by: Andreas Sandberg 
Tested-by: kokoro 
---
M src/python/m5/proxy.py
M src/python/m5/SimObject.py
2 files changed, 24 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index bf5ab54..25bb003 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1534,9 +1534,9 @@
 def add_child(self, name, child):
 child = coerceSimObjectOrVector(child)
 if child.has_parent():
-warn(f"{self}.{name} already has parent (Previously declared  
as "

- f"{child._parent}.{name}), not resetting parent.\n"
+warn(f"{self}.{name} already has parent not resetting  
parent.\n"
  f"\tNote: {name} is not a parameter of  
{type(self).__name__}")

+warn(f"(Previously declared as {child._parent}.{name}")
 return
 if name in self._children:
 # This code path had an undiscovered bug that would make it  
fail

diff --git a/src/python/m5/proxy.py b/src/python/m5/proxy.py
index fe4cb65..2de0ee7 100644
--- a/src/python/m5/proxy.py
+++ b/src/python/m5/proxy.py
@@ -172,7 +172,8 @@
 if attr.startswith('_'):
 return super(AttrProxy, self).__getattr__(self, attr)
 if hasattr(self, '_pdesc'):
-raise AttributeError("Attribute reference on bound proxy")
+raise AttributeError("Attribute reference on bound proxy "
+f"({self}.{attr})")
 # Return a copy of self rather than modifying self in place
 # since self could be an indirect reference via a variable or
 # parameter

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3704a247b8b40e18ffc5e4a6241a74829313c07e
Gerrit-Change-Number: 51787
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Add check to SimObject for init

2021-10-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51568 )


Change subject: python: Add check to SimObject for __init__
..

python: Add check to SimObject for __init__

When extending a SimObject by subclassing, if you don't call
`super().__init__()` you get a confusing infinite recursion error. The
infinite recursion occurs because SimObject overrides `__getattr__`. So,
if an attribute is accessed that is set in SimObject.__init__ but that
function hasn't been called there's a problem.

This patch adds another member variable to track if __init__ has been
called. This member variable is set to False in the *meta class*  so
that it will always be available, even if __init__ has not been called.
There is one check for whether init has been called in the __getattr__
function. This is where I have experienced prior issues. This function
could be called from other SimObject functions, if needed.

With this change, a helpful error is shown telling the user to be sure
to call super().__init__ in the specific class that is missing the call.

Note: I have been bitten by this an embarrassing number of times. A
helpful error message would have saved me many hours.

Change-Id: Id919c540b23fc2783e203ef625bce3000ba808a9
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51568
Maintainer: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Reviewed-by: Andreas Sandberg 
Tested-by: kokoro 
---
M src/python/m5/SimObject.py
1 file changed, 49 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index dec630c..bf5ab54 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -479,6 +479,7 @@
 cls._children = multidict() # SimObject children
 cls._port_refs = multidict() # port ref objects
 cls._instantiated = False # really instantiated, cloned, or  
subclassed

+cls._init_called = False # Used to check if __init__ overridden

 # We don't support multiple inheritance of sim objects.  If you  
want
 # to, you must fix multidict to deal with it properly. Non  
sim-objects

@@ -1323,6 +1324,7 @@
 self._ccObject = None  # pointer to C++ object
 self._ccParams = None
 self._instantiated = False # really "cloned"
+self._init_called = True # Checked so subclasses don't forget  
__init__


 # Clone children specified at class level.  No need for a
 # multidict here since we will be cloning everything.
@@ -1352,6 +1354,14 @@
 for key,val in kwargs.items():
 setattr(self, key, val)

+def _check_init(self):
+"""Utility function to check to make sure that all subclasses call
+__init__
+"""
+if not self._init_called:
+raise RuntimeError(f"{str(self.__class__)} is missing a call "
+"to super().__init__()")
+
 # "Clone" the current instance by creating another instance of
 # this instance's class, but that inherits its parameter values
 # and port mappings from the current instance.  If we're in a
@@ -1385,6 +1395,11 @@
 return ref

 def __getattr__(self, attr):
+# Check for infinite recursion. If this SimObject hasn't been
+# initialized with SimObject.__init__ this function will  
experience an

+# infinite recursion checking for attributes that don't exist.
+self._check_init()
+
 if attr in self._deprecated_params:
 dep_param = self._deprecated_params[attr]
 dep_param.printWarning(self._name, self.__class__.__name__)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id919c540b23fc2783e203ef625bce3000ba808a9
Gerrit-Change-Number: 51568
Gerrit-PatchSet: 4
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Updates to improve debugging output

2021-10-19 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51787 )



Change subject: python: Updates to improve debugging output
..

python: Updates to improve debugging output

This changeset updates SimObject and Proxy so that certain errors are
easier to diagnose. In SimObject, the warn() statement could cause
another exception, so it's split into two statements. In Proxy, it is
helpful to know which attribute is referenced when there's a mistake.

Change-Id: I3704a247b8b40e18ffc5e4a6241a74829313c07e
Signed-off-by: Jason Lowe-Power 
---
M src/python/m5/proxy.py
M src/python/m5/SimObject.py
2 files changed, 19 insertions(+), 3 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 923700d..4dfa2d7 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1525,9 +1525,9 @@
 def add_child(self, name, child):
 child = coerceSimObjectOrVector(child)
 if child.has_parent():
-warn(f"{self}.{name} already has parent (Previously declared  
as "

- f"{child._parent}.{name}), not resetting parent.\n"
+warn(f"{self}.{name} already has parent not resetting  
parent.\n"
  f"\tNote: {name} is not a parameter of  
{type(self).__name__}")

+warn(f"(Previously declared as {child._parent}.{name}")
 return
 if name in self._children:
 # This code path had an undiscovered bug that would make it  
fail

diff --git a/src/python/m5/proxy.py b/src/python/m5/proxy.py
index fe4cb65..2de0ee7 100644
--- a/src/python/m5/proxy.py
+++ b/src/python/m5/proxy.py
@@ -172,7 +172,8 @@
 if attr.startswith('_'):
 return super(AttrProxy, self).__getattr__(self, attr)
 if hasattr(self, '_pdesc'):
-raise AttributeError("Attribute reference on bound proxy")
+raise AttributeError("Attribute reference on bound proxy "
+f"({self}.{attr})")
 # Return a copy of self rather than modifying self in place
 # since self could be an indirect reference via a variable or
 # parameter

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3704a247b8b40e18ffc5e4a6241a74829313c07e
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Gerrit-Owner: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: python: Add check to SimObject for init

2021-10-13 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51568 )



Change subject: python: Add check to SimObject for __init__
..

python: Add check to SimObject for __init__

When extending a SimObject by subclassing, if you don't call
`super().__init__()` you get a confusing infinite recursion error. The
infinite recursion occurs because SimObject overrides `__getattr__`. So,
if an attribute is accessed that is set in SimObject.__init__ but that
function hasn't been called there's a problem.

This patch adds another member variable to track if __init__ has been
called. This member variable is set to False in the *meta class*  so
that it will always be available, even if __init__ has not been called.
There is one check for whether init has been called in the __getattr__
function. This is where I have experienced prior issues. This function
could be called from other SimObject functions, if needed.

With this change, a helpful error is shown telling the user to be sure
to call super().__init__ in the specific class that is missing the call.

Note: I have been bitten by this an embarrassing number of times. A
helpful error message would have saved me many hours.

Change-Id: Id919c540b23fc2783e203ef625bce3000ba808a9
Signed-off-by: Jason Lowe-Power 
---
M src/python/m5/SimObject.py
1 file changed, 41 insertions(+), 0 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index d18d879..923700d 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -479,6 +479,7 @@
 cls._children = multidict() # SimObject children
 cls._port_refs = multidict() # port ref objects
 cls._instantiated = False # really instantiated, cloned, or  
subclassed

+cls._init_called = False # Used to check if __init__ overridden

 # We don't support multiple inheritance of sim objects.  If you  
want
 # to, you must fix multidict to deal with it properly. Non  
sim-objects

@@ -1323,6 +1324,7 @@
 self._ccObject = None  # pointer to C++ object
 self._ccParams = None
 self._instantiated = False # really "cloned"
+self._init_called = True # Checked so subclasses don't forget  
__init__


 # Clone children specified at class level.  No need for a
 # multidict here since we will be cloning everything.
@@ -1352,6 +1354,14 @@
 for key,val in kwargs.items():
 setattr(self, key, val)

+def _check_init(self):
+"""Utility function to check to make sure that all subclasses call
+__init__
+"""
+if not self._init_called:
+raise RuntimeError(f"{str(self.__class__)} is missing a call "
+"to super().__init__()")
+
 # "Clone" the current instance by creating another instance of
 # this instance's class, but that inherits its parameter values
 # and port mappings from the current instance.  If we're in a
@@ -1385,6 +1395,8 @@
 return ref

 def __getattr__(self, attr):
+self._check_init() # Check for inifinite recursion
+
 if attr in self._deprecated_params:
 dep_param = self._deprecated_params[attr]
 dep_param.printWarning(self._name, self.__class__.__name__)

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id919c540b23fc2783e203ef625bce3000ba808a9
Gerrit-Change-Number: 51568
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[gem5-dev] Change in gem5/gem5[develop]: python: Generalize ruby components in library

2021-10-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51448 )



Change subject: python: Generalize ruby components in library
..

python: Generalize ruby components in library

The Ruby protocols in the components library had some special cases for
x86 that ended up breaking other ISAs (RISC-V in my testing). This
change generalizes those scripts slightly so they will work with both
x86 and RISC-V

Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Signed-off-by: Jason Lowe-Power 
---
M  
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M  
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

2 files changed, 29 insertions(+), 28 deletions(-)



diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

index e5d0353..9d42365 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -110,21 +110,14 @@
 board.get_clock_domain(),
 )

+cache.sequencer = RubySequencer(
+version=i,
+dcache=cache.L1Dcache,
+clk_domain=cache.clk_domain,
+)
+
 if board.has_io_bus():
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.L1Dcache,
-clk_domain=cache.clk_domain,
-pio_request_port=board.get_io_bus().cpu_side_ports,
-mem_request_port=board.get_io_bus().cpu_side_ports,
-pio_response_port=board.get_io_bus().mem_side_ports,
-)
-else:
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.L1Dcache,
-clk_domain=cache.clk_domain,
-)
+cache.sequencer.connectIOPorts(board.get_io_bus())

 cache.ruby_system = self.ruby_system

diff --git  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

index 338d1c4..523ba49 100644
---  
a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
+++  
b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

@@ -97,21 +97,14 @@
 clk_domain=board.get_clock_domain(),
 )

+cache.sequencer = RubySequencer(
+version=i,
+dcache=cache.cacheMemory,
+clk_domain=cache.clk_domain,
+)
+
 if board.has_io_bus():
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.cacheMemory,
-clk_domain=cache.clk_domain,
-pio_request_port=board.get_io_bus().cpu_side_ports,
-mem_request_port=board.get_io_bus().cpu_side_ports,
-pio_response_port=board.get_io_bus().mem_side_ports,
-)
-else:
-cache.sequencer = RubySequencer(
-version=i,
-dcache=cache.L1Dcache,
-clk_domain=cache.clk_domain,
-)
+cache.sequencer.connectIOPorts(board.get_io_bus())

 cache.ruby_system = self.ruby_system


--
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Gerrit-Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Gerrit-Change-Number: 51448
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Gerrit-Owner: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: python,configs: Add Ruby support to RISC-V board

2021-10-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51449 )



Change subject: python,configs: Add Ruby support to RISC-V board
..

python,configs: Add Ruby support to RISC-V board

Take out guards stopping the RISC-V board from being configured with
Ruby and update the I/O config with a check for Ruby. Also, add a
comment in the example file that Ruby is now supported.

Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Signed-off-by: Jason Lowe-Power 
---
M src/python/gem5/components/boards/riscv_board.py
M configs/example/components-library/riscv_fs.py
2 files changed, 36 insertions(+), 17 deletions(-)



diff --git a/configs/example/components-library/riscv_fs.py  
b/configs/example/components-library/riscv_fs.py

index eadac8b..9b9d5f0 100644
--- a/configs/example/components-library/riscv_fs.py
+++ b/configs/example/components-library/riscv_fs.py
@@ -57,7 +57,9 @@
 PrivateL1PrivateL2CacheHierarchy,
 )

-# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been  
tested.

+# Setup the cache hierarchy.
+# For classic, PrivateL1PrivateL2 and NoCache have been tested.
+# For Ruby, MESI_Two_Level and MI_example have been tested.
 cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
 l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
 )
diff --git a/src/python/gem5/components/boards/riscv_board.py  
b/src/python/gem5/components/boards/riscv_board.py

index 2cc151d..7ad1b73 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -89,9 +89,6 @@

 requires(isa_required=ISA.RISCV)

-if cache_hierarchy.is_ruby():
-raise EnvironmentError("RiscvBoard is not compatible with  
Ruby")

-
 self.workload = RiscvLinux()

 # Contains a CLINT, PLIC, UART, and some functions for the dtb,  
etc.

@@ -124,20 +121,26 @@

 def _setup_io_devices(self) -> None:
 """Connect the I/O devices to the I/O bus"""
-for device in self._off_chip_devices:
-device.pio = self.iobus.mem_side_ports
-for device in self._on_chip_devices:
-device.pio = self.get_cache_hierarchy().get_mem_side_port()

-self.bridge = Bridge(delay="10ns")
-self.bridge.mem_side_port = self.iobus.cpu_side_ports
-self.bridge.cpu_side_port = (
-self.get_cache_hierarchy().get_mem_side_port()
-)
-self.bridge.ranges = [
-AddrRange(dev.pio_addr, size=dev.pio_size)
-for dev in self._off_chip_devices
-]
+if self.get_cache_hierarchy().is_ruby():
+for device in self._off_chip_devices + self._on_chip_devices:
+device.pio = self.iobus.mem_side_ports
+
+else:
+for device in self._off_chip_devices:
+device.pio = self.iobus.mem_side_ports
+for device in self._on_chip_devices:
+device.pio = self.get_cache_hierarchy().get_mem_side_port()
+
+self.bridge = Bridge(delay="10ns")
+self.bridge.mem_side_port = self.iobus.cpu_side_ports
+self.bridge.cpu_side_port = (
+self.get_cache_hierarchy().get_mem_side_port()
+)
+self.bridge.ranges = [
+AddrRange(dev.pio_addr, size=dev.pio_size)
+for dev in self._off_chip_devices
+]

 def _setup_pma(self) -> None:
 """Set the PMA devices on each core"""

--
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add RISC-V Ruby boot tests

2021-10-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51450 )



Change subject: tests: Add RISC-V Ruby boot tests
..

tests: Add RISC-V Ruby boot tests

Change-Id: I6a173dcef974fef726991bf3db8b7355838e2d04
Signed-off-by: Jason Lowe-Power 
---
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M tests/gem5/configs/riscv_boot_exit_run.py
2 files changed, 62 insertions(+), 9 deletions(-)



diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index b97c8ad..1798e4d 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -36,6 +36,7 @@
 import m5
 from m5.objects import Root

+from gem5.components.boards.riscv_board import RiscvBoard
 from gem5.components.memory.single_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
@@ -67,6 +68,15 @@
 )

 parser.add_argument(
+"-m",
+"--mem-system",
+type=str,
+choices=("classic", "mi_example",),
+required=True,
+help="The memory system.",
+)
+
+parser.add_argument(
 "-t",
 "--tick-exit",
 type=int,
@@ -94,15 +104,24 @@
 # Run a check to ensure the right version of gem5 is being used.
 requires(isa_required=ISA.RISCV)

-from gem5.components.cachehierarchies.classic.\
-private_l1_private_l2_cache_hierarchy import \
-PrivateL1PrivateL2CacheHierarchy
-from gem5.components.boards.riscv_board import RiscvBoard
+if args.mem_system == "classic":
+from gem5.components.cachehierarchies.classic.\
+private_l1_private_l2_cache_hierarchy import \
+PrivateL1PrivateL2CacheHierarchy

-# Setup the cache hierarchy.
-cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
-l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
-)
+# Setup the cache hierarchy.
+cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
+)
+elif args.mem_system == "mi_example":
+from gem5.components.cachehierarchies.ruby.\
+mi_example_cache_hierarchy import \
+MIExampleCacheHierarchy
+
+# Setup the cache hierarchy.
+cache_hierarchy = MIExampleCacheHierarchy(
+size="32KiB", assoc=8
+)

 # Setup the system memory.
 memory = SingleChannelDDR3_1600()
diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py  
b/tests/gem5/riscv-boot-tests/test_linux_boot.py

index bdaa1e6..940702a 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -37,10 +37,12 @@
 def test_boot(
 cpu: str,
 num_cpus: int,
+cache_type: str,
 to_tick: int,
 length: str,
 ):
-name = "{}-cpu_{}-cores_riscv-boot-test_to-tick".format(cpu,  
str(num_cpus))

+name = "{}-cpu_{}-{}-cores_riscv-boot-test_to-tick".format(
+cpu, str(num_cpus), cache_type)

 verifiers = []
 exit_regex = re.compile(
@@ -66,6 +68,8 @@
 cpu,
 "--num-cpus",
 str(num_cpus),
+"--mem-system",
+cache_type,
 "--tick-exit",
 str(to_tick),
 "--override-download",
@@ -83,6 +87,7 @@
 test_boot(
 cpu="atomic",
 num_cpus=1,
+cache_type="classic",
 to_tick=100,  # Simulates 1/100th of a second.
 length=constants.quick_tag,
 )
@@ -90,6 +95,15 @@
 test_boot(
 cpu="timing",
 num_cpus=1,
+cache_type="classic",
+to_tick=100,
+length=constants.quick_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=1,
+cache_type="mi_example",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -97,6 +111,7 @@
 test_boot(
 cpu="o3",
 num_cpus=1,
+cache_type="classic",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -104,6 +119,15 @@
 test_boot(
 cpu="timing",
 num_cpus=4,
+cache_type="classic",
+to_tick=100,
+length=constants.quick_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=4,
+cache_type="mi_example",
 to_tick=100,
 length=constants.quick_tag,
 )

--
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Gerrit-Change-Id: I6a173dcef974fef726991bf3db8b7355838e2d04
Gerrit-Change-Number: 51450
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add RISC-V atomic support to Ruby

2021-10-12 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51447 )



Change subject: mem-ruby: Add RISC-V atomic support to Ruby
..

mem-ruby: Add RISC-V atomic support to Ruby

RISC-V atomics carry a atomic functor that needs to be executed in the
cache hierarchy. To implement this in Ruby, we execute the functor in
the hitCallback function. Note that these functions are slightly
different than the atomic functions used in the GPU model and the GPU
coalescer even though they have similar semantics.

This change was tested with RISC-V Linux boot which has a few atomics
and linux boot finishes successfully. Previously, the boot got stuck
after the incorrect atomic operation.

Change-Id: I47a69c05ad9f4267d0220023289116e62b5231be
Signed-off-by: Jason Lowe-Power 
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 29 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/system/Sequencer.cc  
b/src/mem/ruby/system/Sequencer.cc

index 77ab170..ac52c5f 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -613,6 +613,15 @@
 data.setData(&overwrite_val[0],
  getOffset(request_address), pkt->getSize());
 DPRINTF(RubySequencer, "swap data %s\n", data);
+} else if (pkt->isAtomicOp()) {
+// Set the data in the packet to the old value in the cache
+pkt->setData(
+data.getData(getOffset(request_address), pkt->getSize()));
+DPRINTF(RubySequencer, "AMO original data %s\n", data);
+// execute AMO operation
+(*(pkt->getAtomicOp()))(
+data.getDataMod(getOffset(request_address)));
+DPRINTF(RubySequencer, "AMO new data %s\n", data);
 } else if (type != RubyRequestType_Store_Conditional ||  
llscSuccess) {

 // Types of stores set the actual data here, apart from
 // failed Store Conditional requests

--
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[gem5-dev] Change in gem5/gem5[develop]: cpu-kvm: Fix instruction counter for threading

2021-09-13 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50267 )



Change subject: cpu-kvm: Fix instruction counter for threading
..

cpu-kvm: Fix instruction counter for threading

Previously, the instruction counter was part of a "group" with the cycle
counter. This, in theory, would allow both counters to be read with a
single "read" call. However, as far as I can tell, this feature wasn't
used. Plus, when they were part of a group it was causing EINVAL errors
when detaching and reattching in a different thread.

This change moves the instruction counter to its own group. This
shouldn't cause any functional changes, but it allows multithreaded kvm
to work with the new threading implementation in the next change.

Change-Id: I5a9f55326a5548a0de1d02dded0d7f7817ad19fe
Signed-off-by: Jason Lowe-Power 
---
M src/cpu/kvm/base.cc
1 file changed, 1 insertion(+), 3 deletions(-)



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index c7c72a8..9931f0c 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1352,10 +1352,8 @@
 // sampling settings. See PerfKvmCounter::period() for details.
 if (hwInstructions.attached())
 hwInstructions.detach();
-assert(hwCycles.attached());
 hwInstructions.attach(cfgInstructions,
-  0, // TID (0 => currentThread)
-  hwCycles);
+  0); // TID (0 => currentThread)

 if (period)
 hwInstructions.enableSignals(KVM_KICK_SIGNAL);

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Remove unused stats

2021-09-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50068 )


Change subject: arch-riscv: Remove unused stats
..

arch-riscv: Remove unused stats

These stats were unused and caused a warning about legacy stats. From
what I can tell looking at the blame, they were never used.

Change-Id: If2886e91dd776c34354a79a4cbc447ffe5988982
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50068
Reviewed-by: Hoa Nguyen 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/tlb.hh
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index 26b6afa..f37143d 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -75,11 +75,9 @@

 statistics::Scalar readHits;
 statistics::Scalar readMisses;
-statistics::Scalar read_acv;
 statistics::Scalar readAccesses;
 statistics::Scalar writeHits;
 statistics::Scalar writeMisses;
-statistics::Scalar write_acv;
 statistics::Scalar writeAccesses;

 statistics::Formula hits;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If2886e91dd776c34354a79a4cbc447ffe5988982
Gerrit-Change-Number: 50068
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Remove unused stats

2021-09-07 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50068 )



Change subject: arch-riscv: Remove unused stats
..

arch-riscv: Remove unused stats

These stats were unused and caused a warning about legacy stats. From
what I can tell looking at the blame, they were never used.

Change-Id: If2886e91dd776c34354a79a4cbc447ffe5988982
Signed-off-by: Jason Lowe-Power 
---
M src/arch/riscv/tlb.hh
1 file changed, 0 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index 26b6afa..f37143d 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -75,11 +75,9 @@

 statistics::Scalar readHits;
 statistics::Scalar readMisses;
-statistics::Scalar read_acv;
 statistics::Scalar readAccesses;
 statistics::Scalar writeHits;
 statistics::Scalar writeMisses;
-statistics::Scalar write_acv;
 statistics::Scalar writeAccesses;

 statistics::Formula hits;

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add RISC-V FS example to components

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49433 )


Change subject: configs: Add RISC-V FS example to components
..

configs: Add RISC-V FS example to components

Change-Id: Ib4fe99de7a1fe82c787a8c38d36bf7c7f5cb277c
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49433
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
A configs/example/components-library/riscv_fs.py
1 file changed, 142 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/components-library/riscv_fs.py  
b/configs/example/components-library/riscv_fs.py

new file mode 100644
index 000..10692f6
--- /dev/null
+++ b/configs/example/components-library/riscv_fs.py
@@ -0,0 +1,142 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This example runs a simple linux boot.
+
+Characteristics
+---
+
+* Runs exclusively on the RISC-V ISA with the classic caches
+* Assumes that the kernel is compiled into the bootloader
+* Automatically generates the DTB file
+"""
+
+import m5
+from m5.objects import Root
+
+import sys
+import os
+
+# This is a lame hack to get the imports working correctly.
+# TODO: This needs fixed.
+sys.path.append(
+os.path.join(
+os.path.dirname(os.path.abspath(__file__)),
+os.pardir,
+os.pardir,
+os.pardir,
+)
+)
+
+from components_library.runtime import get_runtime_isa
+from components_library.boards.riscv_board import RiscvBoard
+from components_library.memory.single_channel import SingleChannelDDR3_1600
+from components_library.processors.simple_processor import SimpleProcessor
+from components_library.processors.cpu_types import CPUTypes
+from components_library.isas import ISA
+
+import os
+import subprocess
+import gzip
+import shutil
+
+# Run a check to ensure the right version of gem5 is being used.
+if get_runtime_isa() != ISA.RISCV:
+raise EnvironmentError(
+"The riscv_fs.py should be run with RISCV ISA."
+)
+
+from components_library.cachehierarchies.classic. \
+private_l1_private_l2_cache_hierarchy import (
+PrivateL1PrivateL2CacheHierarchy,
+)
+from components_library.boards.riscv_board import RiscvBoard
+
+# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been  
tested.

+cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+l1d_size='32KiB',
+l1i_size='32KiB',
+l2_size='512KiB'
+)
+
+# Setup the system memory.
+memory = SingleChannelDDR3_1600()
+
+# Setup a single core Processor.
+processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)
+
+# Setup the board.
+board = RiscvBoard(
+clk_freq="1GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+board.connect_things()
+
+# Download the resources as necessary.
+thispath = os.path.dirname(os.path.realpath(__file__))
+
+bootloader_url = (
+"http://dist.gem5.org/dist/develop/kernels/";
+"riscv/static/bootloader-vmlinux-5.10"
+)
+bootloader_path = os.path.join(thispath, "bootloader-vmlinux-5.10")
+if not os.path.exists(bootloader_path):
+subprocess.run(["wget", "-P", thispath, bootloader_url])
+
+boot_img_url = (
+"http://dist.gem5.org/dist/develop/images/riscv/busybox/ris

[gem5-dev] Change in gem5/gem5[develop]: configs: Add RISC-V board to components

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49432 )


Change subject: configs: Add RISC-V board to components
..

configs: Add RISC-V board to components

Change-Id: Ie098e7cd94c8f8b5b4036a478ee8166b1fb9b263
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49432
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
A components_library/boards/riscv_board.py
1 file changed, 378 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/boards/riscv_board.py  
b/components_library/boards/riscv_board.py

new file mode 100644
index 000..97e32f0
--- /dev/null
+++ b/components_library/boards/riscv_board.py
@@ -0,0 +1,378 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+from typing import Optional
+
+from ..utils.override import overrides
+from .simple_board import SimpleBoard
+from .abstract_board import AbstractBoard
+from ..processors.abstract_processor import AbstractProcessor
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

+from ..isas import ISA
+from ..runtime import get_runtime_isa
+
+import m5
+
+from m5.objects import (
+Bridge,
+PMAChecker,
+RiscvLinux,
+AddrRange,
+IOXBar,
+RiscvRTC,
+HiFive,
+CowDiskImage,
+RawDiskImage,
+MmioVirtIO,
+VirtIOBlock,
+Frequency,
+Port,
+)
+
+from m5.util.fdthelper import (
+Fdt,
+FdtNode,
+FdtProperty,
+FdtPropertyStrings,
+FdtPropertyWords,
+FdtState,
+)
+
+
+class RiscvBoard(SimpleBoard):
+"""
+A board capable of full system simulation for RISC-V
+
+At a high-level, this is based on the HiFive Unmatched board from  
SiFive.

+
+This board assumes that you will be booting Linux.
+
+**Limitations**
+* Only works with classic caches
+"""
+
+def __init__(
+self,
+clk_freq: str,
+processor: AbstractProcessor,
+memory: AbstractMemorySystem,
+cache_hierarchy: AbstractCacheHierarchy,
+) -> None:
+super().__init__(clk_freq, processor, memory, cache_hierarchy)
+
+if get_runtime_isa() != ISA.RISCV:
+raise EnvironmentError(
+"RiscvBoard will only work with the RISC-V ISA. Please"
+" recompile gem5 with ISA=RISCV."
+)
+if cache_hierarchy.is_ruby():
+raise EnvironmentError("RiscvBoard is not compatible with  
Ruby")

+
+self.workload = RiscvLinux()
+
+# Contains a CLINT, PLIC, UART, and some functions for the dtb,  
etc.

+self.platform = HiFive()
+# Note: This only works with single threaded cores.
+self.platform.plic.n_contexts = self.processor.get_num_cores() * 2
+self.platform.attachPlic()
+self.platform.clint.num_threads = self.processor.get_num_cores()
+
+# Add the RTC
+# TODO: Why 100MHz? Does something else need to change when this  
does?

+self.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))
+self.platform.clint.int_pin = self.platform.rtc.int_pin
+
+# Incoherent I/O bus
+self.iobus = IOXBar()
+

[gem5-dev] Change in gem5/gem5[develop]: misc,configs: Add gitignore for downloaded files

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49434 )


Change subject: misc,configs: Add gitignore for downloaded files
..

misc,configs: Add gitignore for downloaded files

Change-Id: Idf9aa0e5e3b8490d1e75c8811a8dfad48bbdada3
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49434
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
A configs/example/components-library/.gitignore
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/components-library/.gitignore  
b/configs/example/components-library/.gitignore

new file mode 100644
index 000..8e91cb1
--- /dev/null
+++ b/configs/example/components-library/.gitignore
@@ -0,0 +1,4 @@
+bootloader-vmlinux-*
+riscv-disk.img*
+vmlinux-*
+boot-exit.img*

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idf9aa0e5e3b8490d1e75c8811a8dfad48bbdada3
Gerrit-Change-Number: 49434
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,dev: Explicitly set num CPUs on platform

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49431 )


Change subject: arch-riscv,dev: Explicitly set num CPUs on platform
..

arch-riscv,dev: Explicitly set num CPUs on platform

Previously, the RISC-V devices queried the system object in
SimObject::init() for the number of CPUs and the number of threads.
However, the system object doesn't actually count the number of
CPUs/threads until it runs init(). Therefore, we've just been getting
lucky in the order that the SimObject init() functions were called.

This change instead decouples these two functions and makes the number
of CPUs/threads a parameter for the RISC-V interrupt devices. This
change also updates the example config script.

Change-Id: Ic4da5604156837cfeec05e58d188b42a02420de1
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49431
Maintainer: Bobby R. Bruce 
Reviewed-by: Ayaz Akram 
Tested-by: kokoro 
---
M configs/example/riscv/fs_linux.py
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/clint.cc
M src/dev/riscv/plic.cc
6 files changed, 17 insertions(+), 8 deletions(-)

Approvals:
  Ayaz Akram: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/riscv/fs_linux.py  
b/configs/example/riscv/fs_linux.py

index 55097ba..982dfa4 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -185,6 +185,7 @@
 system.platform.attachOnChipIO(system.membus)
 system.platform.attachOffChipIO(system.iobus)
 system.platform.attachPlic()
+system.platform.setNumCores(np)

 #  Default Setup --- #

diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
index 75c89aa..70ec0ed 100644
--- a/src/dev/riscv/Clint.py
+++ b/src/dev/riscv/Clint.py
@@ -52,6 +52,7 @@
 cxx_class = 'gem5::Clint'
 int_pin = IntSinkPin('Pin to receive RTC signal')
 pio_size = Param.Addr(0xC000, "PIO Size")
+num_threads = Param.Int("Number of threads in the system.")

 def generateDeviceTree(self, state):
 node = self.generateBasicPioDeviceNode(state, "clint",  
self.pio_addr,

diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 8af2ddd..d945590 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -112,9 +112,6 @@
 uart_int_id = Param.Int(0xa, "PLIC Uart interrupt ID")
 terminal = Terminal()

-# Dummy param for generating devicetree
-cpu_count = Param.Int(0, "dummy")
-
 def _on_chip_devices(self):
 """Returns a list of on-chip peripherals
 """
@@ -172,6 +169,13 @@
 for device in self._off_chip_devices():
 device.pio = bus.mem_side_ports

+def setNumCores(self, num_cpu):
+""" Sets the PLIC and CLINT to have the right number of threads and
+contexts. Assumes that the cores have a single hardware thread.
+"""
+self.plic.n_contexts = num_cpu * 2
+self.clint.num_threads = num_cpu
+
 def generateDeviceTree(self, state):
 cpus_node = FdtNode("cpus")
 cpus_node.append(FdtPropertyWords("timebase-frequency",  
[1000]))

@@ -189,6 +193,8 @@

 yield node

+# For generating devicetree
+_cpu_count = 0
 def annotateCpuDeviceNode(self, cpu, state):
 cpu.append(FdtPropertyStrings('mmu-type', 'riscv,sv48'))
 cpu.append(FdtPropertyStrings('status', 'okay'))
@@ -202,8 +208,8 @@
 int_node.appendCompatible("riscv,cpu-intc")

 cpus = self.system.unproxy(self).cpu
-phandle = int_state.phandle(cpus[self.cpu_count])
-self.cpu_count += 1
+phandle = int_state.phandle(cpus[self._cpu_count])
+self._cpu_count += 1
 int_node.append(FdtPropertyWords("phandle", [phandle]))

 cpu.append(int_node)
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 24ed5a5..be0b629 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -51,6 +51,8 @@
 cxx_class = 'gem5::Plic'
 pio_size = Param.Addr(0x400, "PIO Size")
 n_src = Param.Int("Number of interrupt sources")
+n_contexts = Param.Int("Number of interrupt contexts. Usually the  
number "
+   "of threads * 2. One for M mode, one for S  
mode")


 def generateDeviceTree(self, state):
 node = self.generateBasicPioDeviceNode(state, "plic",  
self.pio_addr,

diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 0356af0..b27b9bf 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -52,6 +52,7 @@
 Clint::Clint(const Params ¶ms) :
 BasicPioDevice(params, params.pio_size),
 system(params.system),
+nThread(params.num_threads),
 signal(params.name + ".signal", 0, this),
 registers(params.name + ".registers", params.

[gem5-dev] Change in gem5/gem5[develop]: configs: Create interrupts for ISAs other than x86

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49344 )


Change subject: configs: Create interrupts for ISAs other than x86
..

configs: Create interrupts for ISAs other than x86

All CPUs need to have `createInterrupts()` called. Add a switch to check
for that in the caches and make the ports optional parameters.

Change-Id: I38310c57a68ef18fbe1c28844dcda515eca3170e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49344
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M components_library/cachehierarchies/classic/no_cache.py
M  
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

M components_library/processors/abstract_core.py
M components_library/processors/simple_core.py
4 files changed, 15 insertions(+), 2 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/cachehierarchies/classic/no_cache.py  
b/components_library/cachehierarchies/classic/no_cache.py

index 9b8a49c..44933bf 100644
--- a/components_library/cachehierarchies/classic/no_cache.py
+++ b/components_library/cachehierarchies/classic/no_cache.py
@@ -113,6 +113,8 @@
 int_req_port = self.membus.mem_side_ports
 int_resp_port = self.membus.cpu_side_ports
 core.connect_interrupt(int_req_port, int_resp_port)
+else:
+core.connect_interrupt()

 # Set up the system port for functional access from the simulator.
 board.connect_system_port(self.membus.cpu_side_ports)
diff --git  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

index bf357c5..012743e 100644
---  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -157,3 +157,5 @@
 int_req_port = self.membus.mem_side_ports
 int_resp_port = self.membus.cpu_side_ports
 cpu.connect_interrupt(int_req_port, int_resp_port)
+else:
+cpu.connect_interrupt()
diff --git a/components_library/processors/abstract_core.py  
b/components_library/processors/abstract_core.py

index 68f8db1..35225c1 100644
--- a/components_library/processors/abstract_core.py
+++ b/components_library/processors/abstract_core.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from abc import ABCMeta, abstractmethod
+from typing import Optional
 from .cpu_types import CPUTypes

 from m5.objects import Port, SubSystem
@@ -81,6 +82,12 @@

 @abstractmethod
 def connect_interrupt(
-self, interrupt_requestor: Port, interrupt_responce: Port
+self, interrupt_requestor: Optional[Port] = None,
+interrupt_responce: Optional[Port] = None
 ) -> None:
+""" Connect the core interrupts to the interrupt controller
+
+This function is usually called from the cache hierarchy since the
+optional ports can be implemented as cache ports.
+"""
 raise NotImplementedError
diff --git a/components_library/processors/simple_core.py  
b/components_library/processors/simple_core.py

index 4f8a4a6..c093856 100644
--- a/components_library/processors/simple_core.py
+++ b/components_library/processors/simple_core.py
@@ -24,6 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+from typing import Optional
 from components_library.runtime import get_runtime_isa
 from components_library.processors.abstract_core import AbstractCore

@@ -83,7 +84,8 @@

 @overrides(AbstractCore)
 def connect_interrupt(
-self, interrupt_requestor: Port, interrupt_responce: Port
+self, interrupt_requestor: Optional[Port] = None,
+interrupt_responce: Optional[Port] = None
 ) -> None:

 # TODO: This model assumes that we will only create an interrupt

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49344
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I38310c57a68ef18fbe1c28844dcda515eca3170e
Gerrit-Change-Number: 49344
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove unneeded ddr3 memory component

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49347 )


Change subject: configs: Remove unneeded ddr3 memory component
..

configs: Remove unneeded ddr3 memory component

Change-Id: Id0228b4628c1be6dce3d7092731798bfa07de815
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49347
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
D components_library/memory/ddr3_1600_8x8.py
M configs/example/components-library/boot_exit_disk_run.py
M configs/example/components-library/parsec_disk_run.py
3 files changed, 4 insertions(+), 70 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/memory/ddr3_1600_8x8.py  
b/components_library/memory/ddr3_1600_8x8.py

deleted file mode 100644
index 918617b..000
--- a/components_library/memory/ddr3_1600_8x8.py
+++ /dev/null
@@ -1,66 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import abstractmethod
-from typing import Optional
-
-from m5.objects import DDR3_1600_8x8 as DIMM
-from m5.objects import MemCtrl
-from m5.params import Port, AddrRange
-
-from .abstract_memory_system import AbstractMemorySystem
-from ..boards.abstract_board import AbstractBoard
-
-from ..utils.override import *
-
-from typing import Tuple, Sequence, List
-
-
-class DDR3_1600_8x8(AbstractMemorySystem):
-def __init__(self, size: Optional[str] = "512MiB") -> None:
-super(DDR3_1600_8x8, self).__init__()
-
-# The DDR3_1600_8x8 has a lot of variables with sensible defaults  
that

-# make sense for a DDR3_1600_8x8 device. Only the size has been
-# exposed.
-self._dram = DIMM(range=size)
-self.mem_cntrls = [MemCtrl(dram=self._dram)]
-
-@overrides(AbstractMemorySystem)
-def incorporate_memory(self, board: AbstractBoard) -> None:
-pass
-
-@overrides(AbstractMemorySystem)
-def get_mem_ports(self) -> Tuple[Sequence[AddrRange], Port]:
-return [(self._dram.range, ctrl.port) for ctrl in self.mem_cntrls]
-
-@overrides(AbstractMemorySystem)
-def get_memory_controllers(self) -> List[MemCtrl]:
-return self.mem_cntrls
-
-@overrides(AbstractMemorySystem)
-def get_memory_ranges(self):
-return [self._dram.range]
diff --git a/configs/example/components-library/boot_exit_disk_run.py  
b/configs/example/components-library/boot_exit_disk_run.py

index d64e2e6..67b0fea 100644
--- a/configs/example/components-library/boot_exit_disk_run.py
+++ b/configs/example/components-library/boot_exit_disk_run.py
@@ -55,7 +55,7 @@
 get_runtime_isa,
 )
 from components_library.boards.x86_board import X86Board
-from components_library.memory.ddr3_1600_8x8 import DDR3_1600_8x8
+from components_library.memory.single_channel import SingleChannelDDR3_1600
 from components_library.processors.simple_processor import SimpleProcessor
 from components_library.processors.cpu_types import CPUTypes
 from components_library.isas import ISA
@@ -94,7 +94,7 @@
 # Setup the system memory.
 # Warning: This must be kept at 3GB for now. X86Motherboard does not  
support

 # anything else right now!
-memory = DDR3_1600_8x8(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GB")

 # Setup a single core Timing Processor.
 proc

[gem5-dev] Change in gem5/gem5[develop]: configs: Update component API for I/O

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49363 )


Change subject: configs: Update component API for I/O
..

configs: Update component API for I/O

This change adds a check for coherent I/O ports from the board. This
change allows us to move some of the cache hierarchy specific code out
of the board and into the cache hierarchies.

Change-Id: Ib8144b6d8579ee71e86e4823d2cd396f9cb254ba
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49363
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M components_library/boards/abstract_board.py
M components_library/boards/simple_board.py
M components_library/boards/test_board.py
M components_library/boards/x86_board.py
M components_library/cachehierarchies/classic/no_cache.py
M  
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

6 files changed, 75 insertions(+), 20 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/boards/abstract_board.py  
b/components_library/boards/abstract_board.py

index 3eae0e0..c83668b 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -145,6 +145,24 @@
 raise NotImplementedError

 @abstractmethod
+def has_coherent_io(self) -> bool:
+"""Determine whether the board needs coherent I/O
+
+:returns: True if the board needs coherent I/O, false otherwise
+"""
+raise NotImplementedError
+
+@abstractmethod
+def get_mem_side_coherent_io_port(self):
+"""Get the memory-side coherent I/O port.
+This abstract method must be implemented if has_coherent_io is  
true.

+
+This returns a *port* (not a bus) that should be connected to a
+CPU-side port for which coherent I/O (DMA) is issued.
+"""
+raise NotImplementedError
+
+@abstractmethod
 def get_clock_domain(self) -> ClockDomain:
 """Get the clock domain.

diff --git a/components_library/boards/simple_board.py  
b/components_library/boards/simple_board.py

index fdba342..8ecaefc 100644
--- a/components_library/boards/simple_board.py
+++ b/components_library/boards/simple_board.py
@@ -126,6 +126,17 @@
 )

 @overrides(AbstractBoard)
+def has_coherent_io(self) -> bool:
+return False
+
+@overrides(AbstractBoard)
+def get_mem_side_coherent_io_port(self) -> Port:
+raise NotImplementedError(
+"SimpleBoard does not have any I/O ports. Use has_coherent_io  
to "

+"check this."
+)
+
+@overrides(AbstractBoard)
 def setup_memory_ranges(self) -> None:
 memory = self.get_memory()

diff --git a/components_library/boards/test_board.py  
b/components_library/boards/test_board.py

index 567a4ad..b64e514 100644
--- a/components_library/boards/test_board.py
+++ b/components_library/boards/test_board.py
@@ -106,6 +106,17 @@
 )

 @overrides(AbstractBoard)
+def has_coherent_io(self) -> bool:
+return False
+
+@overrides(AbstractBoard)
+def get_mem_side_coherent_io_port(self):
+raise NotImplementedError(
+"SimpleBoard does not have any I/O ports. Use has_coherent_io  
to "

+"check this."
+)
+
+@overrides(AbstractBoard)
 def set_mem_mode(self, mem_mode: MemMode) -> None:
 self.mem_mode = mem_mode_to_string(mem_mode=mem_mode)

diff --git a/components_library/boards/x86_board.py  
b/components_library/boards/x86_board.py

index 11a223f..dd9ad13 100644
--- a/components_library/boards/x86_board.py
+++ b/components_library/boards/x86_board.py
@@ -99,6 +99,9 @@

 self.workload = X86FsLinux()

+# North Bridge
+self.iobus = IOXBar()
+
 def _setup_io_devices(self):
 """ Sets up the x86 IO devices.

@@ -112,9 +115,6 @@
 interrupts_address_space_base = 0xA000
 APIC_range_size = 1 << 12

-# North Bridge
-self.iobus = IOXBar()
-
 # Setup memory system specific settings.
 if self.get_cache_hierarchy().is_ruby():
 self.pc.attachIO(self.get_io_bus(),  
[self.pc.south_bridge.ide.dma])

@@ -154,22 +154,6 @@
 ]
 self.pc.attachIO(self.get_io_bus())

-self.iocache = Cache(
-assoc=8,
-tag_latency=50,
-data_latency=50,
-response_latency=50,
-mshrs=20,
-size="1kB",
-tgts_per_mshr=12,
-addr_ranges=self.mem_ranges,
-)
-
-self.iocache.cpu_side = self.get_io_bus().mem_side_ports
-self.iocache.mem_side = (
-self.get_cache_hierarchy().get_cpu_side

[gem5-dev] Change in gem5/gem5[develop]: configs: Update how private L1/L2 cache handles MMU

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49364 )


Change subject: configs: Update how private L1/L2 cache handles MMU
..

configs: Update how private L1/L2 cache handles MMU

This change makes an MMU cache per TLB port as is required by x86 and
RISC-V.

Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49364
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M components_library/cachehierarchies/classic/caches/mmu_cache.py
M  
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

2 files changed, 19 insertions(+), 4 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/components_library/cachehierarchies/classic/caches/mmu_cache.py  
b/components_library/cachehierarchies/classic/caches/mmu_cache.py

index 23707e0..8c72674 100644
--- a/components_library/cachehierarchies/classic/caches/mmu_cache.py
+++ b/components_library/cachehierarchies/classic/caches/mmu_cache.py
@@ -46,7 +46,6 @@
 mshrs: Optional[int] = 20,
 tgts_per_mshr: Optional[int] = 12,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
 ):
 super(MMUCache, self).__init__()
 self.size = size
@@ -57,4 +56,3 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
diff --git  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

index a2a10fc..6d9c603 100644
---  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -30,11 +30,12 @@
 from .caches.l1dcache import L1DCache
 from .caches.l1icache import L1ICache
 from .caches.l2cache import L2Cache
+from .caches.mmu_cache import MMUCache
 from ...boards.abstract_board import AbstractBoard
 from ...isas import ISA
 from ...runtime import get_runtime_isa

-from m5.objects import L2XBar, BaseXBar, SystemXBar, BadAddr, Port
+from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port

 from ...utils.override import *

@@ -136,6 +137,19 @@
 L2Cache(size=self._l2_size)
 for i in range(board.get_processor().get_num_cores())
 ]
+# ITLB Page walk caches
+self.iptw_caches = [
+MMUCache(size='8KiB')
+for _ in range(board.get_processor().get_num_cores())
+]
+# DTLB Page walk caches
+self.dptw_caches = [
+MMUCache(size='8KiB')
+for _ in range(board.get_processor().get_num_cores())
+]
+
+if board.has_coherent_io():
+self._setup_io_cache(board)

 for i, cpu in enumerate(board.get_processor().get_cores()):

@@ -144,13 +158,15 @@

 self.l1icaches[i].mem_side = self.l2buses[i].cpu_side_ports
 self.l1dcaches[i].mem_side = self.l2buses[i].cpu_side_ports
+self.iptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports
+self.dptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports

 self.l2buses[i].mem_side_ports = self.l2caches[i].cpu_side

 self.membus.cpu_side_ports = self.l2caches[i].mem_side

 cpu.connect_walker_ports(
-self.membus.cpu_side_ports, self.membus.cpu_side_ports
+self.iptw_caches[i].cpu_side, self.dptw_caches[i].cpu_side
 )

 if get_runtime_isa() == ISA.X86:
@@ -159,6 +175,7 @@
 cpu.connect_interrupt(int_req_port, int_resp_port)
 else:
 cpu.connect_interrupt()
+
 def _setup_io_cache(self, board: AbstractBoard) -> None:
 """Create a cache for coherent I/O connections"""
 self.iocache = Cache(

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b
Gerrit-Change-Number: 49364
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Update component API for memory size

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49348 )


Change subject: configs: Update component API for memory size
..

configs: Update component API for memory size

This change updates the API in the component library for setting the
size of memory. Now, you can set the size of the memory system as an
argument to the memory object. Then, the board is responsible for
figuring out what the overall memory ranges should be which it
communicates back to the memory system.

This should make multi-channel memories easier to implement and it fixes
some confusion around things like the HiFive platform starting at
0x800.

Change-Id: Ibef5aafbbb1177a992950cdc2bd2634dcfb81eec
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49348
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M components_library/boards/abstract_board.py
M components_library/boards/simple_board.py
M components_library/boards/test_board.py
M components_library/boards/x86_board.py
M components_library/memory/abstract_memory_system.py
M components_library/memory/dramsim_3.py
M components_library/memory/single_channel.py
7 files changed, 143 insertions(+), 26 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/boards/abstract_board.py  
b/components_library/boards/abstract_board.py

index 4bece04..3eae0e0 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from abc import ABCMeta, abstractmethod
+
 from .mem_mode import MemMode

 from m5.objects import System, Port, IOXBar, ClockDomain
@@ -165,6 +166,22 @@
 raise NotImplementedError

 @abstractmethod
+def setup_memory_ranges(self) -> None:
+"""
+Set the memory ranges for this board.
+
+This is called by `connect_things`. It can query the board's memory
+to determine the size and the set the memory ranges on the memory  
if

+it needs to move the memory devices.
+
+The simplest implementation just sets the board's memory range to  
be

+the size of memory and memory's memory range to be the same as the
+board. Full system implementations will likely need something more
+complicated.
+"""
+raise NotImplementedError
+
+@abstractmethod
 def connect_things(self) -> None:
 """Connects all the components to the board.

diff --git a/components_library/boards/simple_board.py  
b/components_library/boards/simple_board.py

index 7d67e08..fdba342 100644
--- a/components_library/boards/simple_board.py
+++ b/components_library/boards/simple_board.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.objects import (
+AddrRange,
 SrcClockDomain,
 VoltageDomain,
 Process,
@@ -74,8 +75,6 @@
 self.clk_domain.clock = clk_freq
 self.clk_domain.voltage_domain = VoltageDomain()

-self.mem_ranges = memory.get_memory_ranges()
-
 self.exit_on_work_items = exit_on_work_items

 @overrides(AbstractBoard)
@@ -92,6 +91,9 @@

 @overrides(AbstractBoard)
 def connect_things(self) -> None:
+# Before incorporating the memory, set up the memory ranges
+self.setup_memory_ranges()
+
 # Incorporate the cache hierarchy for the motherboard.
 self.get_cache_hierarchy().incorporate_cache(self)

@@ -123,6 +125,15 @@
 "Use `has_dma_ports()` to check this."
 )

+@overrides(AbstractBoard)
+def setup_memory_ranges(self) -> None:
+memory = self.get_memory()
+
+# The simple board just has one memory range that is the size of  
the

+# memory.
+self.mem_ranges = [AddrRange(memory.get_size())]
+memory.set_memory_range(self.mem_ranges)
+
 def set_workload(self, binary: str) -> None:
 """Set up the system to run a specific binary.

diff --git a/components_library/boards/test_board.py  
b/components_library/boards/test_board.py

index 74bd91a..567a4ad 100644
--- a/components_library/boards/test_board.py
+++ b/components_library/boards/test_board.py
@@ -24,7 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from m5.objects import SrcClockDomain, ClockDomain, VoltageDomain, Port,  
IOXBar

+from m5.objects import (
+SrcClockDomain,
+ClockDomain,
+VoltageDomain,
+Port,
+IOXBar,
+AddrRange,
+)

 from .mem_mode import MemMode, mem_mode_to_string
 from ..utils.override import overrides
@@ -61,12 +68,12 @@
 clock=clk_freq, voltage

[gem5-dev] Change in gem5/gem5[develop]: configs: Move some runtime checks in components

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49345 )


Change subject: configs: Move some runtime checks in components
..

configs: Move some runtime checks in components

The runtime coherence check should check the cache heirarchy, not the
global protocol so it can differentiate between Ruby and classic.
This patch also removes some unnecessary includes and fails earlier in
MESI_Two_Level if that protocol isn't built.

Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49345
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M components_library/boards/abstract_board.py
M components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M components_library/processors/simple_processor.py
3 files changed, 11 insertions(+), 15 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/boards/abstract_board.py  
b/components_library/boards/abstract_board.py

index 653c589..4bece04 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -29,9 +29,6 @@

 from m5.objects import System, Port, IOXBar, ClockDomain

-from ..isas import ISA
-from ..coherence_protocol import CoherenceProtocol
-
 from typing import List


diff --git  
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py  
b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

index cc643e5..0650613 100644
---  
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++  
b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -67,6 +67,16 @@
 l2_assoc: str,
 num_l2_banks: int,
 ):
+
+if (
+get_runtime_coherence_protocol()
+!= CoherenceProtocol.MESI_TWO_LEVEL
+):
+raise EnvironmentError(
+"The MESITwoLevelCacheHierarchy must be used with with  
the "

+"MESI_Two_Level coherence protocol."
+)
+
 AbstractRubyCacheHierarchy.__init__(self=self)
 AbstractTwoLevelCacheHierarchy.__init__(
 self,
@@ -81,15 +91,6 @@
 self._num_l2_banks = num_l2_banks

 def incorporate_cache(self, board: AbstractBoard) -> None:
-if (
-get_runtime_coherence_protocol()
-!= CoherenceProtocol.MESI_TWO_LEVEL
-):
-raise EnvironmentError(
-"The MESITwoLevelCacheHierarchy must be used with with  
the "

-"MESI_Two_Level coherence protocol."
-)
-
 cache_line_size = board.get_cache_line_size()

 self.ruby_system = RubySystem()
diff --git a/components_library/processors/simple_processor.py  
b/components_library/processors/simple_processor.py

index 4b45171..e449173 100644
--- a/components_library/processors/simple_processor.py
+++ b/components_library/processors/simple_processor.py
@@ -34,8 +34,6 @@
 from .abstract_processor import AbstractProcessor
 from .cpu_types import CPUTypes
 from ..boards.abstract_board import AbstractBoard
-from ..coherence_protocol import is_ruby
-from ..runtime import get_runtime_coherence_protocol

 from typing import List

@@ -79,7 +77,7 @@
 elif self._cpu_type == CPUTypes.KVM:
 board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
 elif self._cpu_type == CPUTypes.ATOMIC:
-if is_ruby(get_runtime_coherence_protocol()):
+if board.get_cache_hierarchy().is_ruby():
 warn(
 "Using an atomic core with Ruby will result in "
 "'atomic_noncaching' memory mode. This will skip  
caching "


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Gerrit-Change-Number: 49345
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix component classic cache prefetchers

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49430 )


Change subject: configs: Fix component classic cache prefetchers
..

configs: Fix component classic cache prefetchers

The prefetchers were instatiated as class variables instead of
instance variables. This change fixes the problem

Change-Id: I7263c9e7ddb138d2f9ad10024ea7f0e7d860dda9
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49430
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M components_library/cachehierarchies/classic/caches/l1dcache.py
M components_library/cachehierarchies/classic/caches/l1icache.py
M components_library/cachehierarchies/classic/caches/l2cache.py
3 files changed, 9 insertions(+), 9 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/cachehierarchies/classic/caches/l1dcache.py  
b/components_library/cachehierarchies/classic/caches/l1dcache.py

index 207692f..2f83905 100644
--- a/components_library/cachehierarchies/classic/caches/l1dcache.py
+++ b/components_library/cachehierarchies/classic/caches/l1dcache.py
@@ -28,7 +28,7 @@

 from m5.objects import Cache, BasePrefetcher, StridePrefetcher

-from typing import Optional
+from typing import Optional, Type


 class L1DCache(Cache):
@@ -46,7 +46,7 @@
 mshrs: Optional[int] = 16,
 tgts_per_mshr: Optional[int] = 20,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
+PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
 ):
 super(L1DCache, self).__init__()
 self.size = size
@@ -57,4 +57,4 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
+self.prefetcher = PrefetcherCls()
diff --git a/components_library/cachehierarchies/classic/caches/l1icache.py  
b/components_library/cachehierarchies/classic/caches/l1icache.py

index 960b6dc..214de41 100644
--- a/components_library/cachehierarchies/classic/caches/l1icache.py
+++ b/components_library/cachehierarchies/classic/caches/l1icache.py
@@ -24,7 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from typing import Optional
+from typing import Optional, Type

 from m5.objects import Cache, BasePrefetcher, StridePrefetcher

@@ -46,7 +46,7 @@
 mshrs: Optional[int] = 16,
 tgts_per_mshr: Optional[int] = 20,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
+PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
 ):
 super(L1ICache, self).__init__()
 self.size = size
@@ -57,4 +57,4 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
+self.prefetcher = PrefetcherCls()
diff --git a/components_library/cachehierarchies/classic/caches/l2cache.py  
b/components_library/cachehierarchies/classic/caches/l2cache.py

index 2437088..bd48919 100644
--- a/components_library/cachehierarchies/classic/caches/l2cache.py
+++ b/components_library/cachehierarchies/classic/caches/l2cache.py
@@ -28,7 +28,7 @@

 from m5.objects import Cache, BasePrefetcher, StridePrefetcher

-from typing import Optional
+from typing import Optional, Type


 class L2Cache(Cache):
@@ -46,7 +46,7 @@
 mshrs: Optional[int] = 20,
 tgts_per_mshr: Optional[int] = 12,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
+PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
 ):
 super(L2Cache, self).__init__()
 self.size = size
@@ -57,4 +57,4 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
+self.prefetcher = PrefetcherCls()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7263c9e7ddb138d2f9ad10024ea7f0e7d860dda9
Gerrit-Change-Number: 49430
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove KVM from default imports in components

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49343 )


Change subject: configs: Remove KVM from default imports in components
..

configs: Remove KVM from default imports in components

Change-Id: I74028df1f775564ff16a41ab367ddad512db524c
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49343
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M components_library/processors/simple_core.py
M components_library/processors/simple_processor.py
2 files changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/processors/simple_core.py  
b/components_library/processors/simple_core.py

index e660fa4..4f8a4a6 100644
--- a/components_library/processors/simple_core.py
+++ b/components_library/processors/simple_core.py
@@ -36,7 +36,6 @@
 AtomicSimpleCPU,
 DerivO3CPU,
 TimingSimpleCPU,
-X86KvmCPU,
 BaseCPU,
 Process,
 )
diff --git a/components_library/processors/simple_processor.py  
b/components_library/processors/simple_processor.py

index 3aaa606..4b45171 100644
--- a/components_library/processors/simple_processor.py
+++ b/components_library/processors/simple_processor.py
@@ -28,7 +28,6 @@
 from components_library.utils.override import overrides
 from components_library.boards.mem_mode import MemMode
 from components_library.processors.simple_core import SimpleCore
-from m5.objects import KvmVM

 from m5.util import warn


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I74028df1f775564ff16a41ab367ddad512db524c
Gerrit-Change-Number: 49343
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Expose the MMU to the board in components

2021-08-24 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49346 )


Change subject: configs: Expose the MMU to the board in components
..

configs: Expose the MMU to the board in components

Change-Id: I30b4736ebe44b8429a32c8951af6e654a1238ae6
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49346
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M components_library/processors/abstract_core.py
M components_library/processors/simple_core.py
2 files changed, 14 insertions(+), 1 deletion(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/components_library/processors/abstract_core.py  
b/components_library/processors/abstract_core.py

index 35225c1..83060db 100644
--- a/components_library/processors/abstract_core.py
+++ b/components_library/processors/abstract_core.py
@@ -28,7 +28,7 @@
 from typing import Optional
 from .cpu_types import CPUTypes

-from m5.objects import Port, SubSystem
+from m5.objects import BaseMMU, Port, SubSystem


 class AbstractCore(SubSystem):
@@ -91,3 +91,11 @@
 optional ports can be implemented as cache ports.
 """
 raise NotImplementedError
+
+@abstractmethod
+def get_mmu(self) -> BaseMMU:
+""" Return the MMU for this core.
+
+This is used in the board to setup system-specific MMU settings.
+"""
+raise NotImplementedError
diff --git a/components_library/processors/simple_core.py  
b/components_library/processors/simple_core.py

index c093856..8f510e9 100644
--- a/components_library/processors/simple_core.py
+++ b/components_library/processors/simple_core.py
@@ -33,6 +33,7 @@
 from ..utils.override import overrides

 from m5.objects import (
+BaseMMU,
 Port,
 AtomicSimpleCPU,
 DerivO3CPU,
@@ -96,3 +97,7 @@
 self.core.interrupts[0].pio = interrupt_requestor
 self.core.interrupts[0].int_requestor = interrupt_responce
 self.core.interrupts[0].int_responder = interrupt_requestor
+
+@overrides(AbstractCore)
+def get_mmu(self) -> BaseMMU:
+return self.core.mmu

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30b4736ebe44b8429a32c8951af6e654a1238ae6
Gerrit-Change-Number: 49346
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: emit python stubfiles

2021-08-20 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49470 )



Change subject: scons: emit python stubfiles
..

scons: emit python stubfiles

Stubfiles in python allow you or your IDE to track the types of python
objects even without the full source code. This is useful for many of
gem5's objects since the source code is embedded in the gem5 binary
where IDEs can't easily see it.

This changeset adds a way to generate the stubfiles as gem5 is being
built. The files are generated to a directory under build/ and after they
are generated, you can point your IDE to that path. This requires the
stubgen program (from mypy) to be installed and does nothing if it's
not available.

Change-Id: I73966c8621d0a7a14060758d322c45df57b71102
Signed-off-by: Jason Lowe-Power 
---
M SConstruct
M src/SConscript
2 files changed, 45 insertions(+), 0 deletions(-)



diff --git a/SConstruct b/SConstruct
index 4091d4b..7d85b4d 100755
--- a/SConstruct
+++ b/SConstruct
@@ -246,6 +246,9 @@
 ('PYTHON_CONFIG', 'Python config binary to use',
  [ 'python3-config', 'python-config']
 ),
+('PYTYPES_PATH', 'Path to output the python types stubfiles relative  
to '

+ 'the build directory', 'py_types'),
+('PYTHON_STUBGEN', 'Path to the stubgen utility', 'stubgen'),
 ('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
 ('BATCH', 'Use batch pool for build and tests', False),
 ('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
@@ -491,6 +494,18 @@
 if conf.TryAction('@%s --embed' % python_config)[0]:
 cmd.append('--embed')

+# Check for stubgen to generate stubfiles
+pytypes_path = main['PYTYPES_PATH']
+python_stubgen = main.Detect(main['PYTHON_STUBGEN'])
+if not python_stubgen:
+warning("Can't find python's stubgen. Install mypy to generate  
python "

+"stubfiles for type annoations.")
+stubgen_path = None
+else:
+stubgen_path = main['PYTHON_STUBGEN']
+Export('pytypes_path')
+Export('stubgen_path')
+
 def flag_filter(env, cmd_output):
 flags = cmd_output.split()
 prefixes = ('-l', '-L', '-I')
diff --git a/src/SConscript b/src/SConscript
index 465b14a..57e8e19 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -372,6 +372,8 @@
 path = []

 modpath = path[:]
+type_path = '/'.join(modpath + [ modname ])
+
 if modname != '__init__':
 modpath += [ modname ]
 modpath = '.'.join(modpath)
@@ -388,6 +390,8 @@
 self.abspath = abspath
 self.compiled = File(self.filename + 'c')
 self.cpp = File(self.filename + '.cc')
+self.stubfile = f'{pytypes_path}/{type_path}.pyi'
+
 self.symname = PySource.invalid_sym_char.sub('_', modpath)

 PySource.modules[modpath] = self
@@ -1243,6 +1247,27 @@
 ''')
 code.write(str(target[0]))

+def stubgenPyFile(target, source, env):
+""" Generate a stubfile (.pyi) for the python source
+"""
+import subprocess
+import pathlib
+
+py_path = pathlib.Path(str(source[0]))
+
+# The python modules in the m5 directory are correctly grouped into
+# packages so we can use the base output path. However, the "special"
+# modules that are outside of the src/python directory (e.g.,  
SimObjects)

+# should use their module name as the output directory.
+if 'python/m5' in str(source[0]):
+output_dir = env['BUILDDIR'] + '/' + pytypes_path
+else:
+output_dir = pathlib.Path(str(target[0])).parent
+
+subprocess.check_call(['stubgen', py_path,
+'--search-path', py_path.parent, '--output', output_dir],
+stdout=subprocess.DEVNULL)
+
 if main['USE_PYTHON']:
 # Build a small helper that marshals the Python code using the same
 # version of Python as gem5. This is in an unorthodox location to
@@ -1254,6 +1279,11 @@
 MakeAction(embedPyFile, Transform("EMBED PY")))
 Source(source.cpp, tags=source.tags, add_tags='python')

+# Generate the stubfiles
+if stubgen_path:
+env.Command(source.stubfile, source.tnode,
+MakeAction(stubgenPyFile, Transform("STUBGEN PY")))
+
 
 #
 # Define binaries.  Each different build type (debug, opt, etc.) gets

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I73966c8621d0a7a14060758d322c45df57b71102
Gerrit-Change-Number: 49470
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix component classic cache prefetchers

2021-08-19 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49430 )



Change subject: configs: Fix component classic cache prefetchers
..

configs: Fix component classic cache prefetchers

The prefetchers were instatiated as class variables instead of
instance variables. This change fixes the problem

Change-Id: I7263c9e7ddb138d2f9ad10024ea7f0e7d860dda9
Signed-off-by: Jason Lowe-Power 
---
M components_library/cachehierarchies/classic/caches/l1dcache.py
M components_library/cachehierarchies/classic/caches/l1icache.py
M components_library/cachehierarchies/classic/caches/l2cache.py
3 files changed, 9 insertions(+), 9 deletions(-)



diff --git a/components_library/cachehierarchies/classic/caches/l1dcache.py  
b/components_library/cachehierarchies/classic/caches/l1dcache.py

index 207692f..2f83905 100644
--- a/components_library/cachehierarchies/classic/caches/l1dcache.py
+++ b/components_library/cachehierarchies/classic/caches/l1dcache.py
@@ -28,7 +28,7 @@

 from m5.objects import Cache, BasePrefetcher, StridePrefetcher

-from typing import Optional
+from typing import Optional, Type


 class L1DCache(Cache):
@@ -46,7 +46,7 @@
 mshrs: Optional[int] = 16,
 tgts_per_mshr: Optional[int] = 20,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
+PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
 ):
 super(L1DCache, self).__init__()
 self.size = size
@@ -57,4 +57,4 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
+self.prefetcher = PrefetcherCls()
diff --git a/components_library/cachehierarchies/classic/caches/l1icache.py  
b/components_library/cachehierarchies/classic/caches/l1icache.py

index 960b6dc..214de41 100644
--- a/components_library/cachehierarchies/classic/caches/l1icache.py
+++ b/components_library/cachehierarchies/classic/caches/l1icache.py
@@ -24,7 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from typing import Optional
+from typing import Optional, Type

 from m5.objects import Cache, BasePrefetcher, StridePrefetcher

@@ -46,7 +46,7 @@
 mshrs: Optional[int] = 16,
 tgts_per_mshr: Optional[int] = 20,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
+PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
 ):
 super(L1ICache, self).__init__()
 self.size = size
@@ -57,4 +57,4 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
+self.prefetcher = PrefetcherCls()
diff --git a/components_library/cachehierarchies/classic/caches/l2cache.py  
b/components_library/cachehierarchies/classic/caches/l2cache.py

index 2437088..bd48919 100644
--- a/components_library/cachehierarchies/classic/caches/l2cache.py
+++ b/components_library/cachehierarchies/classic/caches/l2cache.py
@@ -28,7 +28,7 @@

 from m5.objects import Cache, BasePrefetcher, StridePrefetcher

-from typing import Optional
+from typing import Optional, Type


 class L2Cache(Cache):
@@ -46,7 +46,7 @@
 mshrs: Optional[int] = 20,
 tgts_per_mshr: Optional[int] = 12,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
+PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher,
 ):
 super(L2Cache, self).__init__()
 self.size = size
@@ -57,4 +57,4 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
+self.prefetcher = PrefetcherCls()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7263c9e7ddb138d2f9ad10024ea7f0e7d860dda9
Gerrit-Change-Number: 49430
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add RISC-V FS example to components

2021-08-19 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49433 )



Change subject: configs: Add RISC-V FS example to components
..

configs: Add RISC-V FS example to components

Change-Id: Ib4fe99de7a1fe82c787a8c38d36bf7c7f5cb277c
Signed-off-by: Jason Lowe-Power 
---
A configs/example/components-library/riscv_fs.py
1 file changed, 142 insertions(+), 0 deletions(-)



diff --git a/configs/example/components-library/riscv_fs.py  
b/configs/example/components-library/riscv_fs.py

new file mode 100644
index 000..10692f6
--- /dev/null
+++ b/configs/example/components-library/riscv_fs.py
@@ -0,0 +1,142 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This example runs a simple linux boot.
+
+Characteristics
+---
+
+* Runs exclusively on the RISC-V ISA with the classic caches
+* Assumes that the kernel is compiled into the bootloader
+* Automatically generates the DTB file
+"""
+
+import m5
+from m5.objects import Root
+
+import sys
+import os
+
+# This is a lame hack to get the imports working correctly.
+# TODO: This needs fixed.
+sys.path.append(
+os.path.join(
+os.path.dirname(os.path.abspath(__file__)),
+os.pardir,
+os.pardir,
+os.pardir,
+)
+)
+
+from components_library.runtime import get_runtime_isa
+from components_library.boards.riscv_board import RiscvBoard
+from components_library.memory.single_channel import SingleChannelDDR3_1600
+from components_library.processors.simple_processor import SimpleProcessor
+from components_library.processors.cpu_types import CPUTypes
+from components_library.isas import ISA
+
+import os
+import subprocess
+import gzip
+import shutil
+
+# Run a check to ensure the right version of gem5 is being used.
+if get_runtime_isa() != ISA.RISCV:
+raise EnvironmentError(
+"The riscv_fs.py should be run with RISCV ISA."
+)
+
+from components_library.cachehierarchies.classic. \
+private_l1_private_l2_cache_hierarchy import (
+PrivateL1PrivateL2CacheHierarchy,
+)
+from components_library.boards.riscv_board import RiscvBoard
+
+# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been  
tested.

+cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+l1d_size='32KiB',
+l1i_size='32KiB',
+l2_size='512KiB'
+)
+
+# Setup the system memory.
+memory = SingleChannelDDR3_1600()
+
+# Setup a single core Processor.
+processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)
+
+# Setup the board.
+board = RiscvBoard(
+clk_freq="1GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+board.connect_things()
+
+# Download the resources as necessary.
+thispath = os.path.dirname(os.path.realpath(__file__))
+
+bootloader_url = (
+"http://dist.gem5.org/dist/develop/kernels/";
+"riscv/static/bootloader-vmlinux-5.10"
+)
+bootloader_path = os.path.join(thispath, "bootloader-vmlinux-5.10")
+if not os.path.exists(bootloader_path):
+subprocess.run(["wget", "-P", thispath, bootloader_url])
+
+boot_img_url = (
+"http://dist.gem5.org/dist/develop/images/riscv/busybox/riscv-disk.img.gz";
+)
+boot_img_path_gz = os.path.join(thispath, "riscv-disk.img.gz")
+boot_img_path = os.path.join(thispath, "riscv-disk.img")
+
+if not os.path.exists(boot_img_path):
+subprocess.run(["wget", "-P", thispath, boot_img_url])
+wi

[gem5-dev] Change in gem5/gem5[develop]: configs: Add RISC-V board to components

2021-08-19 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49432 )



Change subject: configs: Add RISC-V board to components
..

configs: Add RISC-V board to components

Change-Id: Ie098e7cd94c8f8b5b4036a478ee8166b1fb9b263
Signed-off-by: Jason Lowe-Power 
---
A components_library/boards/riscv_board.py
1 file changed, 378 insertions(+), 0 deletions(-)



diff --git a/components_library/boards/riscv_board.py  
b/components_library/boards/riscv_board.py

new file mode 100644
index 000..97e32f0
--- /dev/null
+++ b/components_library/boards/riscv_board.py
@@ -0,0 +1,378 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+from typing import Optional
+
+from ..utils.override import overrides
+from .simple_board import SimpleBoard
+from .abstract_board import AbstractBoard
+from ..processors.abstract_processor import AbstractProcessor
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..cachehierarchies.abstract_cache_hierarchy import  
AbstractCacheHierarchy

+from ..isas import ISA
+from ..runtime import get_runtime_isa
+
+import m5
+
+from m5.objects import (
+Bridge,
+PMAChecker,
+RiscvLinux,
+AddrRange,
+IOXBar,
+RiscvRTC,
+HiFive,
+CowDiskImage,
+RawDiskImage,
+MmioVirtIO,
+VirtIOBlock,
+Frequency,
+Port,
+)
+
+from m5.util.fdthelper import (
+Fdt,
+FdtNode,
+FdtProperty,
+FdtPropertyStrings,
+FdtPropertyWords,
+FdtState,
+)
+
+
+class RiscvBoard(SimpleBoard):
+"""
+A board capable of full system simulation for RISC-V
+
+At a high-level, this is based on the HiFive Unmatched board from  
SiFive.

+
+This board assumes that you will be booting Linux.
+
+**Limitations**
+* Only works with classic caches
+"""
+
+def __init__(
+self,
+clk_freq: str,
+processor: AbstractProcessor,
+memory: AbstractMemorySystem,
+cache_hierarchy: AbstractCacheHierarchy,
+) -> None:
+super().__init__(clk_freq, processor, memory, cache_hierarchy)
+
+if get_runtime_isa() != ISA.RISCV:
+raise EnvironmentError(
+"RiscvBoard will only work with the RISC-V ISA. Please"
+" recompile gem5 with ISA=RISCV."
+)
+if cache_hierarchy.is_ruby():
+raise EnvironmentError("RiscvBoard is not compatible with  
Ruby")

+
+self.workload = RiscvLinux()
+
+# Contains a CLINT, PLIC, UART, and some functions for the dtb,  
etc.

+self.platform = HiFive()
+# Note: This only works with single threaded cores.
+self.platform.plic.n_contexts = self.processor.get_num_cores() * 2
+self.platform.attachPlic()
+self.platform.clint.num_threads = self.processor.get_num_cores()
+
+# Add the RTC
+# TODO: Why 100MHz? Does something else need to change when this  
does?

+self.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))
+self.platform.clint.int_pin = self.platform.rtc.int_pin
+
+# Incoherent I/O bus
+self.iobus = IOXBar()
+
+# The virtio disk
+self.disk = MmioVirtIO(
+vio=VirtIOBlock(),
+interrupt_id=0x8,
+pio_size=4096,
+pio_addr=0x10008000,
+)
+
+# Note: This overrides the platform's code

[gem5-dev] Change in gem5/gem5[develop]: misc,configs: Add gitignore for downloaded files

2021-08-19 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49434 )



Change subject: misc,configs: Add gitignore for downloaded files
..

misc,configs: Add gitignore for downloaded files

Change-Id: Idf9aa0e5e3b8490d1e75c8811a8dfad48bbdada3
Signed-off-by: Jason Lowe-Power 
---
A configs/example/components-library/.gitignore
1 file changed, 4 insertions(+), 0 deletions(-)



diff --git a/configs/example/components-library/.gitignore  
b/configs/example/components-library/.gitignore

new file mode 100644
index 000..8e91cb1
--- /dev/null
+++ b/configs/example/components-library/.gitignore
@@ -0,0 +1,4 @@
+bootloader-vmlinux-*
+riscv-disk.img*
+vmlinux-*
+boot-exit.img*

--
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Gerrit-Change-Id: Idf9aa0e5e3b8490d1e75c8811a8dfad48bbdada3
Gerrit-Change-Number: 49434
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Gerrit-Owner: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,dev: Explicitly set num CPUs on platform

2021-08-19 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49431 )



Change subject: arch-riscv,dev: Explicitly set num CPUs on platform
..

arch-riscv,dev: Explicitly set num CPUs on platform

Previously, the RISC-V devices queried the system object in
SimObject::init() for the number of CPUs and the number of threads.
However, the system object doesn't actually count the number of
CPUs/threads until it runs init(). Therefore, we've just been getting
lucky in the order that the SimObject init() functions were called.

This change instead decouples these two functions and makes the number
of CPUs/threads a parameter for the RISC-V interrupt devices. This
change also updates the example config script.

Change-Id: Ic4da5604156837cfeec05e58d188b42a02420de1
Signed-off-by: Jason Lowe-Power 
---
M configs/example/riscv/fs_linux.py
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/clint.cc
M src/dev/riscv/plic.cc
6 files changed, 17 insertions(+), 8 deletions(-)



diff --git a/configs/example/riscv/fs_linux.py  
b/configs/example/riscv/fs_linux.py

index 55097ba..982dfa4 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -185,6 +185,7 @@
 system.platform.attachOnChipIO(system.membus)
 system.platform.attachOffChipIO(system.iobus)
 system.platform.attachPlic()
+system.platform.setNumCores(np)

 #  Default Setup --- #

diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
index 75c89aa..70ec0ed 100644
--- a/src/dev/riscv/Clint.py
+++ b/src/dev/riscv/Clint.py
@@ -52,6 +52,7 @@
 cxx_class = 'gem5::Clint'
 int_pin = IntSinkPin('Pin to receive RTC signal')
 pio_size = Param.Addr(0xC000, "PIO Size")
+num_threads = Param.Int("Number of threads in the system.")

 def generateDeviceTree(self, state):
 node = self.generateBasicPioDeviceNode(state, "clint",  
self.pio_addr,

diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 8af2ddd..d945590 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -112,9 +112,6 @@
 uart_int_id = Param.Int(0xa, "PLIC Uart interrupt ID")
 terminal = Terminal()

-# Dummy param for generating devicetree
-cpu_count = Param.Int(0, "dummy")
-
 def _on_chip_devices(self):
 """Returns a list of on-chip peripherals
 """
@@ -172,6 +169,13 @@
 for device in self._off_chip_devices():
 device.pio = bus.mem_side_ports

+def setNumCores(self, num_cpu):
+""" Sets the PLIC and CLINT to have the right number of threads and
+contexts. Assumes that the cores have a single hardware thread.
+"""
+self.plic.n_contexts = num_cpu * 2
+self.clint.num_threads = num_cpu
+
 def generateDeviceTree(self, state):
 cpus_node = FdtNode("cpus")
 cpus_node.append(FdtPropertyWords("timebase-frequency",  
[1000]))

@@ -189,6 +193,8 @@

 yield node

+# For generating devicetree
+_cpu_count = 0
 def annotateCpuDeviceNode(self, cpu, state):
 cpu.append(FdtPropertyStrings('mmu-type', 'riscv,sv48'))
 cpu.append(FdtPropertyStrings('status', 'okay'))
@@ -202,8 +208,8 @@
 int_node.appendCompatible("riscv,cpu-intc")

 cpus = self.system.unproxy(self).cpu
-phandle = int_state.phandle(cpus[self.cpu_count])
-self.cpu_count += 1
+phandle = int_state.phandle(cpus[self._cpu_count])
+self._cpu_count += 1
 int_node.append(FdtPropertyWords("phandle", [phandle]))

 cpu.append(int_node)
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 24ed5a5..be0b629 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -51,6 +51,8 @@
 cxx_class = 'gem5::Plic'
 pio_size = Param.Addr(0x400, "PIO Size")
 n_src = Param.Int("Number of interrupt sources")
+n_contexts = Param.Int("Number of interrupt contexts. Usually the  
number "
+   "of threads * 2. One for M mode, one for S  
mode")


 def generateDeviceTree(self, state):
 node = self.generateBasicPioDeviceNode(state, "plic",  
self.pio_addr,

diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 0356af0..b27b9bf 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -52,6 +52,7 @@
 Clint::Clint(const Params ¶ms) :
 BasicPioDevice(params, params.pio_size),
 system(params.system),
+nThread(params.num_threads),
 signal(params.name + ".signal", 0, this),
 registers(params.name + ".registers", params.pio_addr, this)
 {
@@ -194,7 +195,6 @@
 void
 Clint::init()
 {
-nThread = system->threads.size();
 registers.init();
 BasicPioDevice::init();
 }
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index 4dea475..b8f765a 100644
--- a/src/dev

[gem5-dev] Change in gem5/gem5[develop]: configs: Update component API for I/O

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49363 )



Change subject: configs: Update component API for I/O
..

configs: Update component API for I/O

This change adds a check for coherent I/O ports from the board. This
change allows us to move some of the cache hierarchy specific code out
of the board and into the cache hierarchies.

Change-Id: Ib8144b6d8579ee71e86e4823d2cd396f9cb254ba
Signed-off-by: Jason Lowe-Power 
---
M components_library/boards/abstract_board.py
M components_library/boards/simple_board.py
M components_library/boards/test_board.py
M components_library/boards/x86_board.py
M components_library/cachehierarchies/classic/no_cache.py
M  
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

6 files changed, 75 insertions(+), 20 deletions(-)



diff --git a/components_library/boards/abstract_board.py  
b/components_library/boards/abstract_board.py

index 3eae0e0..c83668b 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -145,6 +145,24 @@
 raise NotImplementedError

 @abstractmethod
+def has_coherent_io(self) -> bool:
+"""Determine whether the board needs coherent I/O
+
+:returns: True if the board needs coherent I/O, false otherwise
+"""
+raise NotImplementedError
+
+@abstractmethod
+def get_mem_side_coherent_io_port(self):
+"""Get the memory-side coherent I/O port.
+This abstract method must be implemented if has_coherent_io is  
true.

+
+This returns a *port* (not a bus) that should be connected to a
+CPU-side port for which coherent I/O (DMA) is issued.
+"""
+raise NotImplementedError
+
+@abstractmethod
 def get_clock_domain(self) -> ClockDomain:
 """Get the clock domain.

diff --git a/components_library/boards/simple_board.py  
b/components_library/boards/simple_board.py

index fdba342..8ecaefc 100644
--- a/components_library/boards/simple_board.py
+++ b/components_library/boards/simple_board.py
@@ -126,6 +126,17 @@
 )

 @overrides(AbstractBoard)
+def has_coherent_io(self) -> bool:
+return False
+
+@overrides(AbstractBoard)
+def get_mem_side_coherent_io_port(self) -> Port:
+raise NotImplementedError(
+"SimpleBoard does not have any I/O ports. Use has_coherent_io  
to "

+"check this."
+)
+
+@overrides(AbstractBoard)
 def setup_memory_ranges(self) -> None:
 memory = self.get_memory()

diff --git a/components_library/boards/test_board.py  
b/components_library/boards/test_board.py

index 567a4ad..b64e514 100644
--- a/components_library/boards/test_board.py
+++ b/components_library/boards/test_board.py
@@ -106,6 +106,17 @@
 )

 @overrides(AbstractBoard)
+def has_coherent_io(self) -> bool:
+return False
+
+@overrides(AbstractBoard)
+def get_mem_side_coherent_io_port(self):
+raise NotImplementedError(
+"SimpleBoard does not have any I/O ports. Use has_coherent_io  
to "

+"check this."
+)
+
+@overrides(AbstractBoard)
 def set_mem_mode(self, mem_mode: MemMode) -> None:
 self.mem_mode = mem_mode_to_string(mem_mode=mem_mode)

diff --git a/components_library/boards/x86_board.py  
b/components_library/boards/x86_board.py

index 11a223f..dd9ad13 100644
--- a/components_library/boards/x86_board.py
+++ b/components_library/boards/x86_board.py
@@ -99,6 +99,9 @@

 self.workload = X86FsLinux()

+# North Bridge
+self.iobus = IOXBar()
+
 def _setup_io_devices(self):
 """ Sets up the x86 IO devices.

@@ -112,9 +115,6 @@
 interrupts_address_space_base = 0xA000
 APIC_range_size = 1 << 12

-# North Bridge
-self.iobus = IOXBar()
-
 # Setup memory system specific settings.
 if self.get_cache_hierarchy().is_ruby():
 self.pc.attachIO(self.get_io_bus(),  
[self.pc.south_bridge.ide.dma])

@@ -154,22 +154,6 @@
 ]
 self.pc.attachIO(self.get_io_bus())

-self.iocache = Cache(
-assoc=8,
-tag_latency=50,
-data_latency=50,
-response_latency=50,
-mshrs=20,
-size="1kB",
-tgts_per_mshr=12,
-addr_ranges=self.mem_ranges,
-)
-
-self.iocache.cpu_side = self.get_io_bus().mem_side_ports
-self.iocache.mem_side = (
-self.get_cache_hierarchy().get_cpu_side_port()
-)
-
 # Add in a Bios information structure.
 self.workload.smbios_table.structures =  
[X86SMBiosBiosInformation()]


@@ -361,6 +345,14 @@
 return [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports]

[gem5-dev] Change in gem5/gem5[develop]: configs: Update how private L1/L2 cache handles MMU

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49364 )



Change subject: configs: Update how private L1/L2 cache handles MMU
..

configs: Update how private L1/L2 cache handles MMU

This change makes an MMU cache per TLB port as is required by x86 and
RISC-V.

Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b
Signed-off-by: Jason Lowe-Power 
---
M components_library/cachehierarchies/classic/caches/mmu_cache.py
M  
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

2 files changed, 19 insertions(+), 4 deletions(-)



diff --git  
a/components_library/cachehierarchies/classic/caches/mmu_cache.py  
b/components_library/cachehierarchies/classic/caches/mmu_cache.py

index 23707e0..8c72674 100644
--- a/components_library/cachehierarchies/classic/caches/mmu_cache.py
+++ b/components_library/cachehierarchies/classic/caches/mmu_cache.py
@@ -46,7 +46,6 @@
 mshrs: Optional[int] = 20,
 tgts_per_mshr: Optional[int] = 12,
 writeback_clean: Optional[bool] = True,
-prefetcher: BasePrefetcher = StridePrefetcher(),
 ):
 super(MMUCache, self).__init__()
 self.size = size
@@ -57,4 +56,3 @@
 self.mshrs = mshrs
 self.tgts_per_mshr = tgts_per_mshr
 self.writeback_clean = writeback_clean
-self.prefetcher = prefetcher
diff --git  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

index a2a10fc..6d9c603 100644
---  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -30,11 +30,12 @@
 from .caches.l1dcache import L1DCache
 from .caches.l1icache import L1ICache
 from .caches.l2cache import L2Cache
+from .caches.mmu_cache import MMUCache
 from ...boards.abstract_board import AbstractBoard
 from ...isas import ISA
 from ...runtime import get_runtime_isa

-from m5.objects import L2XBar, BaseXBar, SystemXBar, BadAddr, Port
+from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port

 from ...utils.override import *

@@ -136,6 +137,19 @@
 L2Cache(size=self._l2_size)
 for i in range(board.get_processor().get_num_cores())
 ]
+# ITLB Page walk caches
+self.iptw_caches = [
+MMUCache(size='8KiB')
+for _ in range(board.get_processor().get_num_cores())
+]
+# DTLB Page walk caches
+self.dptw_caches = [
+MMUCache(size='8KiB')
+for _ in range(board.get_processor().get_num_cores())
+]
+
+if board.has_coherent_io():
+self._setup_io_cache(board)

 for i, cpu in enumerate(board.get_processor().get_cores()):

@@ -144,13 +158,15 @@

 self.l1icaches[i].mem_side = self.l2buses[i].cpu_side_ports
 self.l1dcaches[i].mem_side = self.l2buses[i].cpu_side_ports
+self.iptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports
+self.dptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports

 self.l2buses[i].mem_side_ports = self.l2caches[i].cpu_side

 self.membus.cpu_side_ports = self.l2caches[i].mem_side

 cpu.connect_walker_ports(
-self.membus.cpu_side_ports, self.membus.cpu_side_ports
+self.iptw_caches[i].cpu_side, self.dptw_caches[i].cpu_side
 )

 if get_runtime_isa() == ISA.X86:
@@ -159,6 +175,7 @@
 cpu.connect_interrupt(int_req_port, int_resp_port)
 else:
 cpu.connect_interrupt()
+
 def _setup_io_cache(self, board: AbstractBoard) -> None:
 """Create a cache for coherent I/O connections"""
 self.iocache = Cache(

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b
Gerrit-Change-Number: 49364
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove unneeded ddr3 memory component

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49347 )



Change subject: configs: Remove unneeded ddr3 memory component
..

configs: Remove unneeded ddr3 memory component

Change-Id: Id0228b4628c1be6dce3d7092731798bfa07de815
Signed-off-by: Jason Lowe-Power 
---
D components_library/memory/ddr3_1600_8x8.py
M configs/example/components-library/boot_exit_disk_run.py
M configs/example/components-library/parsec_disk_run.py
3 files changed, 4 insertions(+), 70 deletions(-)



diff --git a/components_library/memory/ddr3_1600_8x8.py  
b/components_library/memory/ddr3_1600_8x8.py

deleted file mode 100644
index 918617b..000
--- a/components_library/memory/ddr3_1600_8x8.py
+++ /dev/null
@@ -1,66 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import abstractmethod
-from typing import Optional
-
-from m5.objects import DDR3_1600_8x8 as DIMM
-from m5.objects import MemCtrl
-from m5.params import Port, AddrRange
-
-from .abstract_memory_system import AbstractMemorySystem
-from ..boards.abstract_board import AbstractBoard
-
-from ..utils.override import *
-
-from typing import Tuple, Sequence, List
-
-
-class DDR3_1600_8x8(AbstractMemorySystem):
-def __init__(self, size: Optional[str] = "512MiB") -> None:
-super(DDR3_1600_8x8, self).__init__()
-
-# The DDR3_1600_8x8 has a lot of variables with sensible defaults  
that

-# make sense for a DDR3_1600_8x8 device. Only the size has been
-# exposed.
-self._dram = DIMM(range=size)
-self.mem_cntrls = [MemCtrl(dram=self._dram)]
-
-@overrides(AbstractMemorySystem)
-def incorporate_memory(self, board: AbstractBoard) -> None:
-pass
-
-@overrides(AbstractMemorySystem)
-def get_mem_ports(self) -> Tuple[Sequence[AddrRange], Port]:
-return [(self._dram.range, ctrl.port) for ctrl in self.mem_cntrls]
-
-@overrides(AbstractMemorySystem)
-def get_memory_controllers(self) -> List[MemCtrl]:
-return self.mem_cntrls
-
-@overrides(AbstractMemorySystem)
-def get_memory_ranges(self):
-return [self._dram.range]
diff --git a/configs/example/components-library/boot_exit_disk_run.py  
b/configs/example/components-library/boot_exit_disk_run.py

index d64e2e6..67b0fea 100644
--- a/configs/example/components-library/boot_exit_disk_run.py
+++ b/configs/example/components-library/boot_exit_disk_run.py
@@ -55,7 +55,7 @@
 get_runtime_isa,
 )
 from components_library.boards.x86_board import X86Board
-from components_library.memory.ddr3_1600_8x8 import DDR3_1600_8x8
+from components_library.memory.single_channel import SingleChannelDDR3_1600
 from components_library.processors.simple_processor import SimpleProcessor
 from components_library.processors.cpu_types import CPUTypes
 from components_library.isas import ISA
@@ -94,7 +94,7 @@
 # Setup the system memory.
 # Warning: This must be kept at 3GB for now. X86Motherboard does not  
support

 # anything else right now!
-memory = DDR3_1600_8x8(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GB")

 # Setup a single core Timing Processor.
 processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)
diff --git a/configs/example/components-library/parsec_disk_run.py  
b/configs/example/components-library/parsec_disk_run.py

index f1d9237..9285d6d 100644
--- a/configs/example/component

[gem5-dev] Change in gem5/gem5[develop]: configs: Move some runtime checks in components

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49345 )



Change subject: configs: Move some runtime checks in components
..

configs: Move some runtime checks in components

The runtime coherence check should check the cache heirarchy, not the
global protocol so it can differentiate between Ruby and classic.
This patch also removes some unnecessary includes and fails earlier in
MESI_Two_Level if that protocol isn't built.

Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Signed-off-by: Jason Lowe-Power 
---
M components_library/boards/abstract_board.py
M components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
M components_library/processors/simple_processor.py
3 files changed, 11 insertions(+), 15 deletions(-)



diff --git a/components_library/boards/abstract_board.py  
b/components_library/boards/abstract_board.py

index 653c589..4bece04 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -29,9 +29,6 @@

 from m5.objects import System, Port, IOXBar, ClockDomain

-from ..isas import ISA
-from ..coherence_protocol import CoherenceProtocol
-
 from typing import List


diff --git  
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py  
b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

index cc643e5..0650613 100644
---  
a/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++  
b/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -67,6 +67,16 @@
 l2_assoc: str,
 num_l2_banks: int,
 ):
+
+if (
+get_runtime_coherence_protocol()
+!= CoherenceProtocol.MESI_TWO_LEVEL
+):
+raise EnvironmentError(
+"The MESITwoLevelCacheHierarchy must be used with with  
the "

+"MESI_Two_Level coherence protocol."
+)
+
 AbstractRubyCacheHierarchy.__init__(self=self)
 AbstractTwoLevelCacheHierarchy.__init__(
 self,
@@ -81,15 +91,6 @@
 self._num_l2_banks = num_l2_banks

 def incorporate_cache(self, board: AbstractBoard) -> None:
-if (
-get_runtime_coherence_protocol()
-!= CoherenceProtocol.MESI_TWO_LEVEL
-):
-raise EnvironmentError(
-"The MESITwoLevelCacheHierarchy must be used with with  
the "

-"MESI_Two_Level coherence protocol."
-)
-
 cache_line_size = board.get_cache_line_size()

 self.ruby_system = RubySystem()
diff --git a/components_library/processors/simple_processor.py  
b/components_library/processors/simple_processor.py

index 4b45171..e449173 100644
--- a/components_library/processors/simple_processor.py
+++ b/components_library/processors/simple_processor.py
@@ -34,8 +34,6 @@
 from .abstract_processor import AbstractProcessor
 from .cpu_types import CPUTypes
 from ..boards.abstract_board import AbstractBoard
-from ..coherence_protocol import is_ruby
-from ..runtime import get_runtime_coherence_protocol

 from typing import List

@@ -79,7 +77,7 @@
 elif self._cpu_type == CPUTypes.KVM:
 board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
 elif self._cpu_type == CPUTypes.ATOMIC:
-if is_ruby(get_runtime_coherence_protocol()):
+if board.get_cache_hierarchy().is_ruby():
 warn(
 "Using an atomic core with Ruby will result in "
 "'atomic_noncaching' memory mode. This will skip  
caching "


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545
Gerrit-Change-Number: 49345
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Create interrupts for ISAs other than x86

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49344 )



Change subject: configs: Create interrupts for ISAs other than x86
..

configs: Create interrupts for ISAs other than x86

All CPUs need to have `createInterrupts()` called. Add a switch to check
for that in the caches and make the ports optional parameters.

Change-Id: I38310c57a68ef18fbe1c28844dcda515eca3170e
---
M components_library/cachehierarchies/classic/no_cache.py
M  
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

M components_library/processors/abstract_core.py
M components_library/processors/simple_core.py
4 files changed, 15 insertions(+), 2 deletions(-)



diff --git a/components_library/cachehierarchies/classic/no_cache.py  
b/components_library/cachehierarchies/classic/no_cache.py

index 9b8a49c..44933bf 100644
--- a/components_library/cachehierarchies/classic/no_cache.py
+++ b/components_library/cachehierarchies/classic/no_cache.py
@@ -113,6 +113,8 @@
 int_req_port = self.membus.mem_side_ports
 int_resp_port = self.membus.cpu_side_ports
 core.connect_interrupt(int_req_port, int_resp_port)
+else:
+core.connect_interrupt()

 # Set up the system port for functional access from the simulator.
 board.connect_system_port(self.membus.cpu_side_ports)
diff --git  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

index bf357c5..012743e 100644
---  
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++  
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -157,3 +157,5 @@
 int_req_port = self.membus.mem_side_ports
 int_resp_port = self.membus.cpu_side_ports
 cpu.connect_interrupt(int_req_port, int_resp_port)
+else:
+cpu.connect_interrupt()
diff --git a/components_library/processors/abstract_core.py  
b/components_library/processors/abstract_core.py

index 68f8db1..35225c1 100644
--- a/components_library/processors/abstract_core.py
+++ b/components_library/processors/abstract_core.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from abc import ABCMeta, abstractmethod
+from typing import Optional
 from .cpu_types import CPUTypes

 from m5.objects import Port, SubSystem
@@ -81,6 +82,12 @@

 @abstractmethod
 def connect_interrupt(
-self, interrupt_requestor: Port, interrupt_responce: Port
+self, interrupt_requestor: Optional[Port] = None,
+interrupt_responce: Optional[Port] = None
 ) -> None:
+""" Connect the core interrupts to the interrupt controller
+
+This function is usually called from the cache hierarchy since the
+optional ports can be implemented as cache ports.
+"""
 raise NotImplementedError
diff --git a/components_library/processors/simple_core.py  
b/components_library/processors/simple_core.py

index 4f8a4a6..c093856 100644
--- a/components_library/processors/simple_core.py
+++ b/components_library/processors/simple_core.py
@@ -24,6 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+from typing import Optional
 from components_library.runtime import get_runtime_isa
 from components_library.processors.abstract_core import AbstractCore

@@ -83,7 +84,8 @@

 @overrides(AbstractCore)
 def connect_interrupt(
-self, interrupt_requestor: Port, interrupt_responce: Port
+self, interrupt_requestor: Optional[Port] = None,
+interrupt_responce: Optional[Port] = None
 ) -> None:

 # TODO: This model assumes that we will only create an interrupt

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove KVM from default imports in components

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49343 )



Change subject: configs: Remove KVM from default imports in components
..

configs: Remove KVM from default imports in components

Change-Id: I74028df1f775564ff16a41ab367ddad512db524c
Signed-off-by: Jason Lowe-Power 
---
M components_library/processors/simple_core.py
M components_library/processors/simple_processor.py
2 files changed, 0 insertions(+), 2 deletions(-)



diff --git a/components_library/processors/simple_core.py  
b/components_library/processors/simple_core.py

index e660fa4..4f8a4a6 100644
--- a/components_library/processors/simple_core.py
+++ b/components_library/processors/simple_core.py
@@ -36,7 +36,6 @@
 AtomicSimpleCPU,
 DerivO3CPU,
 TimingSimpleCPU,
-X86KvmCPU,
 BaseCPU,
 Process,
 )
diff --git a/components_library/processors/simple_processor.py  
b/components_library/processors/simple_processor.py

index 3aaa606..4b45171 100644
--- a/components_library/processors/simple_processor.py
+++ b/components_library/processors/simple_processor.py
@@ -28,7 +28,6 @@
 from components_library.utils.override import overrides
 from components_library.boards.mem_mode import MemMode
 from components_library.processors.simple_core import SimpleCore
-from m5.objects import KvmVM

 from m5.util import warn


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Gerrit-Change-Id: I74028df1f775564ff16a41ab367ddad512db524c
Gerrit-Change-Number: 49343
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[gem5-dev] Change in gem5/gem5[develop]: configs: Expose the MMU to the board in components

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49346 )



Change subject: configs: Expose the MMU to the board in components
..

configs: Expose the MMU to the board in components

Change-Id: I30b4736ebe44b8429a32c8951af6e654a1238ae6
Signed-off-by: Jason Lowe-Power 
---
M components_library/processors/abstract_core.py
M components_library/processors/simple_core.py
2 files changed, 14 insertions(+), 1 deletion(-)



diff --git a/components_library/processors/abstract_core.py  
b/components_library/processors/abstract_core.py

index 35225c1..83060db 100644
--- a/components_library/processors/abstract_core.py
+++ b/components_library/processors/abstract_core.py
@@ -28,7 +28,7 @@
 from typing import Optional
 from .cpu_types import CPUTypes

-from m5.objects import Port, SubSystem
+from m5.objects import BaseMMU, Port, SubSystem


 class AbstractCore(SubSystem):
@@ -91,3 +91,11 @@
 optional ports can be implemented as cache ports.
 """
 raise NotImplementedError
+
+@abstractmethod
+def get_mmu(self) -> BaseMMU:
+""" Return the MMU for this core.
+
+This is used in the board to setup system-specific MMU settings.
+"""
+raise NotImplementedError
diff --git a/components_library/processors/simple_core.py  
b/components_library/processors/simple_core.py

index c093856..8f510e9 100644
--- a/components_library/processors/simple_core.py
+++ b/components_library/processors/simple_core.py
@@ -33,6 +33,7 @@
 from ..utils.override import overrides

 from m5.objects import (
+BaseMMU,
 Port,
 AtomicSimpleCPU,
 DerivO3CPU,
@@ -96,3 +97,7 @@
 self.core.interrupts[0].pio = interrupt_requestor
 self.core.interrupts[0].int_requestor = interrupt_responce
 self.core.interrupts[0].int_responder = interrupt_requestor
+
+@overrides(AbstractCore)
+def get_mmu(self) -> BaseMMU:
+return self.core.mmu

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Update component API for memory size

2021-08-18 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49348 )



Change subject: configs: Update component API for memory size
..

configs: Update component API for memory size

This change updates the API in the component library for setting the
size of memory. Now, you can set the size of the memory system as an
argument to the memory object. Then, the board is responsible for
figuring out what the overall memory ranges should be which it
communicates back to the memory system.

This should make multi-channel memories easier to implement and it fixes
some confusion around things like the HiFive platform starting at
0x800.

Change-Id: Ibef5aafbbb1177a992950cdc2bd2634dcfb81eec
Signed-off-by: Jason Lowe-Power 
---
M components_library/boards/abstract_board.py
M components_library/boards/simple_board.py
M components_library/boards/test_board.py
M components_library/boards/x86_board.py
M components_library/memory/abstract_memory_system.py
M components_library/memory/dramsim_3.py
M components_library/memory/single_channel.py
7 files changed, 143 insertions(+), 26 deletions(-)



diff --git a/components_library/boards/abstract_board.py  
b/components_library/boards/abstract_board.py

index 4bece04..3eae0e0 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from abc import ABCMeta, abstractmethod
+
 from .mem_mode import MemMode

 from m5.objects import System, Port, IOXBar, ClockDomain
@@ -165,6 +166,22 @@
 raise NotImplementedError

 @abstractmethod
+def setup_memory_ranges(self) -> None:
+"""
+Set the memory ranges for this board.
+
+This is called by `connect_things`. It can query the board's memory
+to determine the size and the set the memory ranges on the memory  
if

+it needs to move the memory devices.
+
+The simplest implementation just sets the board's memory range to  
be

+the size of memory and memory's memory range to be the same as the
+board. Full system implementations will likely need something more
+complicated.
+"""
+raise NotImplementedError
+
+@abstractmethod
 def connect_things(self) -> None:
 """Connects all the components to the board.

diff --git a/components_library/boards/simple_board.py  
b/components_library/boards/simple_board.py

index 7d67e08..fdba342 100644
--- a/components_library/boards/simple_board.py
+++ b/components_library/boards/simple_board.py
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.objects import (
+AddrRange,
 SrcClockDomain,
 VoltageDomain,
 Process,
@@ -74,8 +75,6 @@
 self.clk_domain.clock = clk_freq
 self.clk_domain.voltage_domain = VoltageDomain()

-self.mem_ranges = memory.get_memory_ranges()
-
 self.exit_on_work_items = exit_on_work_items

 @overrides(AbstractBoard)
@@ -92,6 +91,9 @@

 @overrides(AbstractBoard)
 def connect_things(self) -> None:
+# Before incorporating the memory, set up the memory ranges
+self.setup_memory_ranges()
+
 # Incorporate the cache hierarchy for the motherboard.
 self.get_cache_hierarchy().incorporate_cache(self)

@@ -123,6 +125,15 @@
 "Use `has_dma_ports()` to check this."
 )

+@overrides(AbstractBoard)
+def setup_memory_ranges(self) -> None:
+memory = self.get_memory()
+
+# The simple board just has one memory range that is the size of  
the

+# memory.
+self.mem_ranges = [AddrRange(memory.get_size())]
+memory.set_memory_range(self.mem_ranges)
+
 def set_workload(self, binary: str) -> None:
 """Set up the system to run a specific binary.

diff --git a/components_library/boards/test_board.py  
b/components_library/boards/test_board.py

index 74bd91a..567a4ad 100644
--- a/components_library/boards/test_board.py
+++ b/components_library/boards/test_board.py
@@ -24,7 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from m5.objects import SrcClockDomain, ClockDomain, VoltageDomain, Port,  
IOXBar

+from m5.objects import (
+SrcClockDomain,
+ClockDomain,
+VoltageDomain,
+Port,
+IOXBar,
+AddrRange,
+)

 from .mem_mode import MemMode, mem_mode_to_string
 from ..utils.override import overrides
@@ -61,12 +68,12 @@
 clock=clk_freq, voltage_domain=VoltageDomain()
 )

-self.mem_ranges = memory.get_memory_ranges()
-
 def connect_system_port(self, port: Port) -> None:
 self.system_port = port

 def connect_things(self) -> None:
+self.set_memory_rang

[gem5-dev] Change in gem5/gem5[develop]: docker-util: Revert gcn-gpu docker bucket URL to develop

2021-07-29 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48811 )


Change subject: docker-util: Revert gcn-gpu docker bucket URL to develop
..

docker-util: Revert gcn-gpu docker bucket URL to develop

This reverts commit 87c121fd954ea5a6e6b0760d693a2e744c2200de,
https://gem5-review.googlesource.com/c/public/gem5/+/48663

Change-Id: I688e456d5aeec9b91d8f2c7b734eb02c8bdce651
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48811
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M util/dockerfiles/gcn-gpu/Dockerfile
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index b307996..360ab1f 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -70,7 +70,7 @@

 WORKDIR /ROCclr
 # The patch allows us to avoid building blit kernels on-the-fly in gem5
-RUN wget -q -O - dist.gem5.org/dist/v21-1/rocm_patches/ROCclr.patch | git  
apply -v
+RUN wget -q -O - dist.gem5.org/dist/develop/rocm_patches/ROCclr.patch |  
git apply -v


 WORKDIR /ROCclr/build
 RUN cmake -DOPENCL_DIR="/ROCm-OpenCL-Runtime" \

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Gerrit-Change-Id: I688e456d5aeec9b91d8f2c7b734eb02c8bdce651
Gerrit-Change-Number: 48811
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: scons: Re-add -Werror for the gem5 develop branch

2021-07-29 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48812 )


Change subject: scons: Re-add -Werror for the gem5 develop branch
..

scons: Re-add -Werror for the gem5 develop branch

This reverts commit 3c61200c2bbb1cf9ca216d7197b8c0fe6e210d56,
https://gem5-review.googlesource.com/c/public/gem5/+/48584

Change-Id: Idc071168857746f4c8d3e577949939ecf1761cda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48812
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 117a192..617c7b4 100755
--- a/SConstruct
+++ b/SConstruct
@@ -330,6 +330,12 @@
 if GetOption('gold_linker'):
 main.Append(LINKFLAGS='-fuse-ld=gold')

+# Treat warnings as errors but white list some warnings that we
+# want to allow (e.g., deprecation warnings).
+main.Append(CCFLAGS=['-Werror',
+ '-Wno-error=deprecated-declarations',
+ '-Wno-error=deprecated',
+])
 else:
 error('\n'.join((
   "Don't know what compiler options to use for your compiler.",

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Gerrit-Change-Number: 48812
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: misc: Merge branch 'release-staging-v21-1' into develop

2021-07-29 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48814 )


Change subject: misc: Merge branch 'release-staging-v21-1' into develop
..

misc: Merge branch 'release-staging-v21-1' into develop

Change-Id: I0f69d3d0863f77c02ac8089fb4dccee3aa70a4ea
---
1 file changed, 0 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved
  kokoro: Regressions pass




--
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Gerrit-Change-Id: I0f69d3d0863f77c02ac8089fb4dccee3aa70a4ea
Gerrit-Change-Number: 48814
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Updated gem5 versioning information for develop branch

2021-07-29 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48813 )


Change subject: misc: Updated gem5 versioning information for develop branch
..

misc: Updated gem5 versioning information for develop branch

Change-Id: I17382ac18dcdce4cdf8c3366886cd41fbcd7d946
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48813
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M ext/testlib/configuration.py
M src/Doxyfile
M src/base/version.cc
3 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index c3d328d..1fffab4 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -213,7 +213,7 @@
   os.pardir,
   os.pardir))
 defaults.result_path = os.path.join(os.getcwd(), 'testing-results')
-defaults.resource_url = 'http://dist.gem5.org/dist/v21-1'
+defaults.resource_url = 'http://dist.gem5.org/dist/develop'
 defaults.resource_path =  
os.path.abspath(os.path.join(defaults.base_dir,

 'tests',
 'gem5',
diff --git a/src/Doxyfile b/src/Doxyfile
index ef70b54..1ff46c8 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,7 +31,7 @@
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.

-PROJECT_NUMBER = v21.1.0.0
+PROJECT_NUMBER = DEVELOP-FOR-V21-2

 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.
diff --git a/src/base/version.cc b/src/base/version.cc
index 50ffd40..078a2f9 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -32,6 +32,6 @@
 /**
  * @ingroup api_base_utils
  */
-const char *gem5Version = "21.1.0.0";
+const char *gem5Version = "[DEVELOP-FOR-V21.2]";

 } // namespace gem5

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I17382ac18dcdce4cdf8c3366886cd41fbcd7d946
Gerrit-Change-Number: 48813
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Decouple artifacts from mongodb

2021-07-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47463 )


Change subject: util-gem5art: Decouple artifacts from mongodb
..

util-gem5art: Decouple artifacts from mongodb

This commit does a few things to decouple the artifacts from mongodb.
- Creates an ArtifactFileDB which stores artifacts in a json file on the
local machine
- Adds tests fro the artifact file DB
- Sets the file database to be default if pymongo isn't installed
- Extends the Artifact class to prepare for downloading artifacts from
gem5-resources

Change-Id: I1bceef94dc53c066d1c0475e79c9a1ad1f1a6202
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47463
Reviewed-by: Hoa Nguyen 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M util/gem5art/artifact/gem5art/artifact/_artifactdb.py
M util/gem5art/artifact/gem5art/artifact/artifact.py
M util/gem5art/artifact/tests/test_artifact.py
A util/gem5art/artifact/tests/test_filedb.py
4 files changed, 425 insertions(+), 32 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/gem5art/artifact/gem5art/artifact/_artifactdb.py  
b/util/gem5art/artifact/gem5art/artifact/_artifactdb.py

index 4ffb0a0..6714c9c 100644
--- a/util/gem5art/artifact/gem5art/artifact/_artifactdb.py
+++ b/util/gem5art/artifact/gem5art/artifact/_artifactdb.py
@@ -36,14 +36,24 @@

 from abc import ABC, abstractmethod

-import gridfs  # type: ignore
+import copy
+import json
 import os
 from pathlib import Path
-from pymongo import MongoClient  # type: ignore
-from typing import Any, Dict, Iterable, Union, Type
+import shutil
+from typing import Any, Dict, Iterable, Union, Type, List, Tuple
 from urllib.parse import urlparse
 from uuid import UUID

+try:
+import gridfs  # type: ignore
+from pymongo import MongoClient  # type: ignore
+
+MONGO_SUPPORT = True
+except ModuleNotFoundError:
+# If pymongo isn't installed, then disable support for it
+MONGO_SUPPORT = False
+

 class ArtifactDB(ABC):
 """
@@ -51,7 +61,7 @@
 """

 @abstractmethod
-def __init__(self, uri: str):
+def __init__(self, uri: str) -> None:
 """Initialize the database with a URI"""
 pass

@@ -205,11 +215,194 @@
 yield d


+class ArtifactFileDB(ArtifactDB):
+"""
+This is a file-based database where Artifacts (as defined in  
artifacts.py)

+are stored in a JSON file.
+
+This database stores a list of serialized artifacts in a JSON file.
+This database is not thread-safe.
+
+If the user specifies a valid path in the environment variable
+GEM5ART_STORAGE then this database will copy all artifacts to that
+directory named with their UUIDs.
+"""
+
+class ArtifactEncoder(json.JSONEncoder):
+def default(self, obj):
+if isinstance(obj, UUID):
+return str(obj)
+return ArtifactFileDB.ArtifactEncoder(self, obj)
+
+_json_file: Path
+_uuid_artifact_map: Dict[str, Dict[str, str]]
+_hash_uuid_map: Dict[str, List[str]]
+_storage_enabled: bool
+_storage_path: Path
+
+def __init__(self, uri: str) -> None:
+"""Initialize the file-driven database from a JSON file.
+If the file doesn't exist, a new file will be created.
+"""
+parsed_uri = urlparse(uri)
+# using urlparse to parse relative/absolute file path
+# abs path: urlparse("file:///path/to/file") ->
+#   (netloc='', path='/path/to/file')
+# rel path: urlparse("file://path/to/file") ->
+#   (netloc='path', path='/to/file')
+# so, the filepath would be netloc+path for both cases
+self._json_file = Path(parsed_uri.netloc) / Path(parsed_uri.path)
+storage_path = os.environ.get("GEM5ART_STORAGE", "")
+self._storage_enabled = True if storage_path else False
+self._storage_path = Path(storage_path)
+if (
+self._storage_enabled
+and self._storage_path.exists()
+and not self._storage_path.is_dir()
+):
+raise Exception(
+f"GEM5ART_STORAGE={storage_path} exists and is not a  
directory"

+)
+if self._storage_enabled:
+os.makedirs(self._storage_path, exist_ok=True)
+
+self._uuid_artifact_map, self._hash_uuid_map =  
self._load_from_file(

+self._json_file
+)
+
+def put(self, key: UUID, artifact: Dict[str, Union[str, UUID]]) ->  
None:

+"""Insert the artifact into the database with the key."""
+assert artifact["_id"] == key
+assert isinstance(artifact["hash"], str)
+self.insert_artifact(key, artifact["hash"], artifact)
+
+def upload(self, key: UUID, path: Path) -> None:
+"""Copy the artif

[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Simplify rerunning failing runs

2021-07-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47464 )


Change subject: util-gem5art: Simplify rerunning failing runs
..

util-gem5art: Simplify rerunning failing runs

Often, a gem5 experiment will fail for some reason. This happens
non-deterministically when fastforwarding with KVM making it more
difficult to handle.

This change allows the user to specify a function `check_failure` to
check to see if the test has failed. An example would be to open the
terminal and check to see if the kernel has panicked.

Additionally, this change adds a rerun function to rerun a particular
run that has failed.

Change-Id: Ib4a8d47c824254ae89ac9e1593ebd2710e263146
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47464
Reviewed-by: Hoa Nguyen 
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M util/gem5art/run/gem5art/run.py
1 file changed, 88 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Hoa Nguyen: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/gem5art/run/gem5art/run.py  
b/util/gem5art/run/gem5art/run.py

index c367f6d..a32d899 100644
--- a/util/gem5art/run/gem5art/run.py
+++ b/util/gem5art/run/gem5art/run.py
@@ -39,7 +39,7 @@
 import signal
 import subprocess
 import time
-from typing import Any, Dict, Iterable, List, Optional, Tuple, Union
+from typing import Any, Callable, Dict, Iterable, List, Optional, Tuple,  
Union

 from uuid import UUID, uuid4
 import zipfile

@@ -64,6 +64,7 @@
 run_script_git_artifact: Artifact
 params: Tuple[str, ...]
 timeout: int
+check_failure: Callable[["gem5Run"], bool]

 gem5_name: str
 script_name: str
@@ -93,6 +94,8 @@
 results: Optional[Artifact]
 artifacts: List[Artifact]

+rerunnable: bool
+
 @classmethod
 def _create(
 cls,
@@ -105,6 +108,7 @@
 run_script_git_artifact: Artifact,
 params: Tuple[str, ...],
 timeout: int,
+check_failure: Callable[["gem5Run"], bool],
 ) -> "gem5Run":
 """
 Shared code between SE and FS when creating a run object.
@@ -119,6 +123,9 @@
 run.params = params
 run.timeout = timeout

+# Note: Mypy doesn't support monkey patching like this
+run.check_failure = check_failure  # type: ignore
+
 run._id = uuid4()

 run.outdir = outdir.resolve()  # ensure this is absolute
@@ -142,6 +149,8 @@
 # Initially, there are no results
 run.results = None

+run.rerunnable = False
+
 return run

 @classmethod
@@ -156,6 +165,7 @@
 run_script_git_artifact: Artifact,
 *params: str,
 timeout: int = 60 * 15,
+check_failure: Callable[["gem5Run"], bool] = lambda run: False,
 ) -> "gem5Run":
 """
 name is the name of the run. The name is not necessarily unique.  
The

@@ -186,6 +196,7 @@
 run_script_git_artifact,
 params,
 timeout,
+check_failure,
 )

 run.artifacts = [
@@ -230,6 +241,7 @@
 disk_image_artifact: Artifact,
 *params: str,
 timeout: int = 60 * 15,
+check_failure: Callable[["gem5Run"], bool] = lambda run: False,
 ) -> "gem5Run":
 """
 name is the name of the run. The name is not necessarily unique.  
The

@@ -244,6 +256,10 @@
 Further parameters can be passed via extra arguments. These
 parameters will be passed in order to the gem5 run script.

+check_failure is a user-defined function that will be executed
+periodically (e.g., every 10 seconds) to check the health of the
+simulation. When it returns True, the simulation will be killed
+
 Note: When instantiating this class for the first time, it will  
create
 a file `info.json` in the outdir which contains a serialized  
version

 of this class.
@@ -259,6 +275,7 @@
 run_script_git_artifact,
 params,
 timeout,
+check_failure,
 )
 run.linux_binary = Path(linux_binary)
 run.disk_image = Path(disk_image)
@@ -397,6 +414,10 @@
 # Remove list of artifacts
 del d["artifacts"]

+# Doesn't make sense to serialize the user-specified fail function
+if "check_failure" in d.keys():
+del d["check_failure"]
+
 # Replace the artifacts with their UUIDs
 for k, v in d.items():
 if isinstance(v, Artifact):
@@ -438,7 +459,7 @@
 d = self._convertForJson(self._getSerializable())
 return json.dumps(d)

-def run(self, task: Any = None, cwd: str = ".") -> None:
+def _run(self, task: Any = None, cwd: str = ".") -> None:

[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Simplify gem5art Run

2021-07-09 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47465 )


Change subject: util-gem5art: Simplify gem5art Run
..

util-gem5art: Simplify gem5art Run

This changeset removes some of the duplicate information in the gem5 run
object making it a little simpler to use the createRun functions.

Change-Id: I36ee105166e41407c21e36d9bc71fd4db89fb1e8
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47465
Reviewed-by: Hoa Nguyen 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M util/gem5art/run/gem5art/run.py
M util/gem5art/run/tests/test_run.py
2 files changed, 16 insertions(+), 31 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/gem5art/run/gem5art/run.py  
b/util/gem5art/run/gem5art/run.py

index a32d899..89bd463 100644
--- a/util/gem5art/run/gem5art/run.py
+++ b/util/gem5art/run/gem5art/run.py
@@ -57,7 +57,7 @@
 hash: str
 type: str
 name: str
-gem5_binary: Path
+gem5_binary_path: Path
 run_script: Path
 gem5_artifact: Artifact
 gem5_git_artifact: Artifact
@@ -74,8 +74,8 @@

 outdir: Path

-linux_binary: Path
-disk_image: Path
+linux_binary_path: Path
+disk_image_path: Path
 linux_binary_artifact: Artifact
 disk_image_artifact: Artifact

@@ -100,7 +100,6 @@
 def _create(
 cls,
 name: str,
-gem5_binary: Path,
 run_script: Path,
 outdir: Path,
 gem5_artifact: Artifact,
@@ -115,7 +114,7 @@
 """
 run = cls()
 run.name = name
-run.gem5_binary = gem5_binary
+run.gem5_binary_path = gem5_artifact.path
 run.run_script = run_script
 run.gem5_artifact = gem5_artifact
 run.gem5_git_artifact = gem5_git_artifact
@@ -131,7 +130,7 @@
 run.outdir = outdir.resolve()  # ensure this is absolute

 # Assumes **//gem5.
-run.gem5_name = run.gem5_binary.parent.name
+run.gem5_name = run.gem5_binary_path.parent.name
 # Assumes **/.py
 run.script_name = run.run_script.stem

@@ -157,7 +156,6 @@
 def createSERun(
 cls,
 name: str,
-gem5_binary: str,
 run_script: str,
 outdir: str,
 gem5_artifact: Artifact,
@@ -171,8 +169,7 @@
 name is the name of the run. The name is not necessarily unique.  
The

 name could be used to query the results of the run.

-gem5_binary and run_script are the paths to the binary to run
-and the script to pass to gem5. Full paths are better.
+run_script is the path to the run script to pass to gem5.

 The artifact parameters (gem5_artifact, gem5_git_artifact, and
 run_script_git_artifact) are used to ensure this is reproducible  
run.

@@ -188,7 +185,6 @@

 run = cls._create(
 name,
-Path(gem5_binary),
 Path(run_script),
 Path(outdir),
 gem5_artifact,
@@ -209,7 +205,7 @@
 run.string += " ".join(run.params)

 run.command = [
-str(run.gem5_binary),
+str(run.gem5_binary_path),
 "-re",
 f"--outdir={run.outdir}",
 str(run.run_script),
@@ -229,14 +225,11 @@
 def createFSRun(
 cls,
 name: str,
-gem5_binary: str,
 run_script: str,
 outdir: str,
 gem5_artifact: Artifact,
 gem5_git_artifact: Artifact,
 run_script_git_artifact: Artifact,
-linux_binary: str,
-disk_image: str,
 linux_binary_artifact: Artifact,
 disk_image_artifact: Artifact,
 *params: str,
@@ -247,11 +240,7 @@
 name is the name of the run. The name is not necessarily unique.  
The

 name could be used to query the results of the run.

-gem5_binary and run_script are the paths to the binary to run
-and the script to pass to gem5.
-
-The linux_binary is the kernel to run and the disk_image is the  
path

-to the disk image to use.
+run_script is the path to the run script to pass to gem5.

 Further parameters can be passed via extra arguments. These
 parameters will be passed in order to the gem5 run script.
@@ -264,10 +253,8 @@
 a file `info.json` in the outdir which contains a serialized  
version

 of this class.
 """
-
 run = cls._create(
 name,
-Path(gem5_binary),
 Path(run_script),
 Path(outdir),
 gem5_artifact,
@@ -277,15 +264,15 @@
 timeout,
 check_failure,
 )
-run.linux_binary = Path(linux_binary)
-run.disk_image = Path(

[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Simplify gem5art Run

2021-07-01 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47465 )



Change subject: util-gem5art: Simplify gem5art Run
..

util-gem5art: Simplify gem5art Run

This changeset removes some of the duplicate information in the gem5 run
object making it a little simpler to use the createRun functions.

Change-Id: I36ee105166e41407c21e36d9bc71fd4db89fb1e8
Signed-off-by: Jason Lowe-Power 
---
M util/gem5art/run/gem5art/run.py
M util/gem5art/run/tests/test_run.py
2 files changed, 16 insertions(+), 31 deletions(-)



diff --git a/util/gem5art/run/gem5art/run.py  
b/util/gem5art/run/gem5art/run.py

index a32d899..89bd463 100644
--- a/util/gem5art/run/gem5art/run.py
+++ b/util/gem5art/run/gem5art/run.py
@@ -57,7 +57,7 @@
 hash: str
 type: str
 name: str
-gem5_binary: Path
+gem5_binary_path: Path
 run_script: Path
 gem5_artifact: Artifact
 gem5_git_artifact: Artifact
@@ -74,8 +74,8 @@

 outdir: Path

-linux_binary: Path
-disk_image: Path
+linux_binary_path: Path
+disk_image_path: Path
 linux_binary_artifact: Artifact
 disk_image_artifact: Artifact

@@ -100,7 +100,6 @@
 def _create(
 cls,
 name: str,
-gem5_binary: Path,
 run_script: Path,
 outdir: Path,
 gem5_artifact: Artifact,
@@ -115,7 +114,7 @@
 """
 run = cls()
 run.name = name
-run.gem5_binary = gem5_binary
+run.gem5_binary_path = gem5_artifact.path
 run.run_script = run_script
 run.gem5_artifact = gem5_artifact
 run.gem5_git_artifact = gem5_git_artifact
@@ -131,7 +130,7 @@
 run.outdir = outdir.resolve()  # ensure this is absolute

 # Assumes **//gem5.
-run.gem5_name = run.gem5_binary.parent.name
+run.gem5_name = run.gem5_binary_path.parent.name
 # Assumes **/.py
 run.script_name = run.run_script.stem

@@ -157,7 +156,6 @@
 def createSERun(
 cls,
 name: str,
-gem5_binary: str,
 run_script: str,
 outdir: str,
 gem5_artifact: Artifact,
@@ -171,8 +169,7 @@
 name is the name of the run. The name is not necessarily unique.  
The

 name could be used to query the results of the run.

-gem5_binary and run_script are the paths to the binary to run
-and the script to pass to gem5. Full paths are better.
+run_script is the path to the run script to pass to gem5.

 The artifact parameters (gem5_artifact, gem5_git_artifact, and
 run_script_git_artifact) are used to ensure this is reproducible  
run.

@@ -188,7 +185,6 @@

 run = cls._create(
 name,
-Path(gem5_binary),
 Path(run_script),
 Path(outdir),
 gem5_artifact,
@@ -209,7 +205,7 @@
 run.string += " ".join(run.params)

 run.command = [
-str(run.gem5_binary),
+str(run.gem5_binary_path),
 "-re",
 f"--outdir={run.outdir}",
 str(run.run_script),
@@ -229,14 +225,11 @@
 def createFSRun(
 cls,
 name: str,
-gem5_binary: str,
 run_script: str,
 outdir: str,
 gem5_artifact: Artifact,
 gem5_git_artifact: Artifact,
 run_script_git_artifact: Artifact,
-linux_binary: str,
-disk_image: str,
 linux_binary_artifact: Artifact,
 disk_image_artifact: Artifact,
 *params: str,
@@ -247,11 +240,7 @@
 name is the name of the run. The name is not necessarily unique.  
The

 name could be used to query the results of the run.

-gem5_binary and run_script are the paths to the binary to run
-and the script to pass to gem5.
-
-The linux_binary is the kernel to run and the disk_image is the  
path

-to the disk image to use.
+run_script is the path to the run script to pass to gem5.

 Further parameters can be passed via extra arguments. These
 parameters will be passed in order to the gem5 run script.
@@ -264,10 +253,8 @@
 a file `info.json` in the outdir which contains a serialized  
version

 of this class.
 """
-
 run = cls._create(
 name,
-Path(gem5_binary),
 Path(run_script),
 Path(outdir),
 gem5_artifact,
@@ -277,15 +264,15 @@
 timeout,
 check_failure,
 )
-run.linux_binary = Path(linux_binary)
-run.disk_image = Path(disk_image)
+run.linux_binary_path = Path(linux_binary_artifact.path)
+run.disk_image_path = Path(disk_image_artifact.path)
 run.linux_binary_artifact = linux_binary_artifact
 run.disk_image_artifact = disk_image_artifact

 # Assumes **/
-run.linux_name = run.linux_binary.name
+r

[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Simplify rerunning failing runs

2021-07-01 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47464 )



Change subject: util-gem5art: Simplify rerunning failing runs
..

util-gem5art: Simplify rerunning failing runs

Often, a gem5 experiment will fail for some reason. This happens
non-deterministically when fastforwarding with KVM making it more
difficult to handle.

This change allows the user to specify a function `check_failure` to
check to see if the test has failed. An example would be to open the
terminal and check to see if the kernel has panicked.

Additionally, this change adds a rerun function to rerun a particular
run that has failed.

Change-Id: Ib4a8d47c824254ae89ac9e1593ebd2710e263146
Signed-off-by: Jason Lowe-Power 
---
M util/gem5art/run/gem5art/run.py
1 file changed, 88 insertions(+), 6 deletions(-)



diff --git a/util/gem5art/run/gem5art/run.py  
b/util/gem5art/run/gem5art/run.py

index c367f6d..a32d899 100644
--- a/util/gem5art/run/gem5art/run.py
+++ b/util/gem5art/run/gem5art/run.py
@@ -39,7 +39,7 @@
 import signal
 import subprocess
 import time
-from typing import Any, Dict, Iterable, List, Optional, Tuple, Union
+from typing import Any, Callable, Dict, Iterable, List, Optional, Tuple,  
Union

 from uuid import UUID, uuid4
 import zipfile

@@ -64,6 +64,7 @@
 run_script_git_artifact: Artifact
 params: Tuple[str, ...]
 timeout: int
+check_failure: Callable[["gem5Run"], bool]

 gem5_name: str
 script_name: str
@@ -93,6 +94,8 @@
 results: Optional[Artifact]
 artifacts: List[Artifact]

+rerunnable: bool
+
 @classmethod
 def _create(
 cls,
@@ -105,6 +108,7 @@
 run_script_git_artifact: Artifact,
 params: Tuple[str, ...],
 timeout: int,
+check_failure: Callable[["gem5Run"], bool],
 ) -> "gem5Run":
 """
 Shared code between SE and FS when creating a run object.
@@ -119,6 +123,9 @@
 run.params = params
 run.timeout = timeout

+# Note: Mypy doesn't support monkey patching like this
+run.check_failure = check_failure  # type: ignore
+
 run._id = uuid4()

 run.outdir = outdir.resolve()  # ensure this is absolute
@@ -142,6 +149,8 @@
 # Initially, there are no results
 run.results = None

+run.rerunnable = False
+
 return run

 @classmethod
@@ -156,6 +165,7 @@
 run_script_git_artifact: Artifact,
 *params: str,
 timeout: int = 60 * 15,
+check_failure: Callable[["gem5Run"], bool] = lambda run: False,
 ) -> "gem5Run":
 """
 name is the name of the run. The name is not necessarily unique.  
The

@@ -186,6 +196,7 @@
 run_script_git_artifact,
 params,
 timeout,
+check_failure,
 )

 run.artifacts = [
@@ -230,6 +241,7 @@
 disk_image_artifact: Artifact,
 *params: str,
 timeout: int = 60 * 15,
+check_failure: Callable[["gem5Run"], bool] = lambda run: False,
 ) -> "gem5Run":
 """
 name is the name of the run. The name is not necessarily unique.  
The

@@ -244,6 +256,10 @@
 Further parameters can be passed via extra arguments. These
 parameters will be passed in order to the gem5 run script.

+check_failure is a user-defined function that will be executed
+periodically (e.g., every 10 seconds) to check the health of the
+simulation. When it returns True, the simulation will be killed
+
 Note: When instantiating this class for the first time, it will  
create
 a file `info.json` in the outdir which contains a serialized  
version

 of this class.
@@ -259,6 +275,7 @@
 run_script_git_artifact,
 params,
 timeout,
+check_failure,
 )
 run.linux_binary = Path(linux_binary)
 run.disk_image = Path(disk_image)
@@ -397,6 +414,10 @@
 # Remove list of artifacts
 del d["artifacts"]

+# Doesn't make sense to serialize the user-specified fail function
+if "check_failure" in d.keys():
+del d["check_failure"]
+
 # Replace the artifacts with their UUIDs
 for k, v in d.items():
 if isinstance(v, Artifact):
@@ -438,7 +459,7 @@
 d = self._convertForJson(self._getSerializable())
 return json.dumps(d)

-def run(self, task: Any = None, cwd: str = ".") -> None:
+def _run(self, task: Any = None, cwd: str = ".") -> None:
 """Actually run the test.

 Calls Popen with the command to fork a new process.
@@ -452,11 +473,8 @@
 process to run in a different directory than the running process.  
Note

 that only the spawned process runs in the new directory.
 """
-# Check if the run is already in the database
+# Connect to the

[gem5-dev] Change in gem5/gem5[develop]: util-gem5art: Decouple artifacts from mongodb

2021-07-01 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47463 )



Change subject: util-gem5art: Decouple artifacts from mongodb
..

util-gem5art: Decouple artifacts from mongodb

This commit does a few things to decouple the artifacts from mongodb.
- Creates an ArtifactFileDB which stores artifacts in a json file on the
local machine
- Adds tests fro the artifact file DB
- Sets the file database to be default if pymongo isn't installed
- Extends the Artifact class to prepare for downloading artifacts from
gem5-resources

Change-Id: I1bceef94dc53c066d1c0475e79c9a1ad1f1a6202
Signed-off-by: Jason Lowe-Power 
---
M util/gem5art/artifact/gem5art/artifact/_artifactdb.py
M util/gem5art/artifact/gem5art/artifact/artifact.py
M util/gem5art/artifact/tests/test_artifact.py
A util/gem5art/artifact/tests/test_filedb.py
4 files changed, 425 insertions(+), 32 deletions(-)



diff --git a/util/gem5art/artifact/gem5art/artifact/_artifactdb.py  
b/util/gem5art/artifact/gem5art/artifact/_artifactdb.py

index 4ffb0a0..6714c9c 100644
--- a/util/gem5art/artifact/gem5art/artifact/_artifactdb.py
+++ b/util/gem5art/artifact/gem5art/artifact/_artifactdb.py
@@ -36,14 +36,24 @@

 from abc import ABC, abstractmethod

-import gridfs  # type: ignore
+import copy
+import json
 import os
 from pathlib import Path
-from pymongo import MongoClient  # type: ignore
-from typing import Any, Dict, Iterable, Union, Type
+import shutil
+from typing import Any, Dict, Iterable, Union, Type, List, Tuple
 from urllib.parse import urlparse
 from uuid import UUID

+try:
+import gridfs  # type: ignore
+from pymongo import MongoClient  # type: ignore
+
+MONGO_SUPPORT = True
+except ModuleNotFoundError:
+# If pymongo isn't installed, then disable support for it
+MONGO_SUPPORT = False
+

 class ArtifactDB(ABC):
 """
@@ -51,7 +61,7 @@
 """

 @abstractmethod
-def __init__(self, uri: str):
+def __init__(self, uri: str) -> None:
 """Initialize the database with a URI"""
 pass

@@ -205,11 +215,194 @@
 yield d


+class ArtifactFileDB(ArtifactDB):
+"""
+This is a file-based database where Artifacts (as defined in  
artifacts.py)

+are stored in a JSON file.
+
+This database stores a list of serialized artifacts in a JSON file.
+This database is not thread-safe.
+
+If the user specifies a valid path in the environment variable
+GEM5ART_STORAGE then this database will copy all artifacts to that
+directory named with their UUIDs.
+"""
+
+class ArtifactEncoder(json.JSONEncoder):
+def default(self, obj):
+if isinstance(obj, UUID):
+return str(obj)
+return ArtifactFileDB.ArtifactEncoder(self, obj)
+
+_json_file: Path
+_uuid_artifact_map: Dict[str, Dict[str, str]]
+_hash_uuid_map: Dict[str, List[str]]
+_storage_enabled: bool
+_storage_path: Path
+
+def __init__(self, uri: str) -> None:
+"""Initialize the file-driven database from a JSON file.
+If the file doesn't exist, a new file will be created.
+"""
+parsed_uri = urlparse(uri)
+# using urlparse to parse relative/absolute file path
+# abs path: urlparse("file:///path/to/file") ->
+#   (netloc='', path='/path/to/file')
+# rel path: urlparse("file://path/to/file") ->
+#   (netloc='path', path='/to/file')
+# so, the filepath would be netloc+path for both cases
+self._json_file = Path(parsed_uri.netloc) / Path(parsed_uri.path)
+storage_path = os.environ.get("GEM5ART_STORAGE", "")
+self._storage_enabled = True if storage_path else False
+self._storage_path = Path(storage_path)
+if (
+self._storage_enabled
+and self._storage_path.exists()
+and not self._storage_path.is_dir()
+):
+raise Exception(
+f"GEM5ART_STORAGE={storage_path} exists and is not a  
directory"

+)
+if self._storage_enabled:
+os.makedirs(self._storage_path, exist_ok=True)
+
+self._uuid_artifact_map, self._hash_uuid_map =  
self._load_from_file(

+self._json_file
+)
+
+def put(self, key: UUID, artifact: Dict[str, Union[str, UUID]]) ->  
None:

+"""Insert the artifact into the database with the key."""
+assert artifact["_id"] == key
+assert isinstance(artifact["hash"], str)
+self.insert_artifact(key, artifact["hash"], artifact)
+
+def upload(self, key: UUID, path: Path) -> None:
+"""Copy the artifact to the folder specified by GEM5ART_STORAGE."""
+if not self._storage_enabled:
+return
+src_path = path
+dst_path = self._storage_path / str(key)
+if not dst_path.exists():
+shutil.copy2(src_path, ds

[gem5-dev] Change in gem5/gem5[develop]: scons,python: revert Always generate default create() methods.

2021-06-11 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46819 )



Change subject: scons,python: revert Always generate default create()  
methods.

..

scons,python: revert Always generate default create() methods.

This reverts commit 7bb690c1ee70b1c82b23eeb68dcda3dc6e5c97f7.

Change-Id: If1b44162b24409fb44daec0159852fa44937184d
---
M src/SConscript
M src/python/m5/SimObject.py
2 files changed, 72 insertions(+), 94 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index cc51b9f..d8e8249 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -976,7 +976,7 @@
 # Create all of the SimObject param headers and enum headers
 #

-def createSimObjectParamDecl(target, source, env):
+def createSimObjectParamStruct(target, source, env):
 assert len(target) == 1 and len(source) == 1

 name = source[0].get_text_contents()
@@ -986,16 +986,6 @@
 obj.cxx_param_decl(code)
 code.write(target[0].abspath)

-def createSimObjectParamDef(target, source, env):
-assert len(target) == 1 and len(source) == 1
-
-name = source[0].get_text_contents()
-obj = sim_objects[name]
-
-code = code_formatter()
-obj.cxx_param_def(code)
-code.write(target[0].abspath)
-
 def createSimObjectCxxConfig(is_header):
 def body(target, source, env):
 assert len(target) == 1 and len(source) == 1
@@ -1056,16 +1046,9 @@
 hh_file = File('params/%s.hh' % name)
 params_hh_files.append(hh_file)
 env.Command(hh_file, Value(name),
-MakeAction(createSimObjectParamDecl,  
Transform("SOPARMHH")))
+MakeAction(createSimObjectParamStruct, Transform("SO  
PARAM")))

 env.Depends(hh_file, depends + extra_deps)

-if not getattr(simobj, 'abstract', False) and hasattr(simobj, 'type'):
-cc_file = File('params/%s.cc' % name)
-env.Command(cc_file, Value(name),
-MakeAction(createSimObjectParamDef,  
Transform("SOPARMCC")))

-env.Depends(cc_file, depends + extra_deps)
-Source(cc_file)
-
 # C++ parameter description files
 if GetOption('with_cxx_config'):
 for name,simobj in sorted(sim_objects.items()):
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index bb17a38..88abc43 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -368,7 +368,7 @@

 if not is_header:
 code('{')
-if getattr(simobj, 'abstract', False):
+if hasattr(simobj, 'abstract') and simobj.abstract:
 code('return NULL;')
 else:
 code('return this->create();')
@@ -700,80 +700,6 @@
 def pybind_predecls(cls, code):
 code('#include "${{cls.cxx_header}}"')

-def cxx_param_def(cls, code):
-code('''
-#include 
-
-#include "base/compiler.hh"
-
-#include "${{cls.cxx_header}}"
-#include "params/${cls}.hh"
-
-''')
-code()
-code('namespace')
-code('{')
-code()
-# If we can't define a default create() method for this params  
struct

-# because the SimObject doesn't have the right constructor, use
-# template magic to make it so we're actually defining a create  
method

-# for this class instead.
-code('class Dummy${cls}ParamsClass')
-code('{')
-code('  public:')
-code('${{cls.cxx_class}} *create() const;')
-code('};')
-code()
-code('template ')
-code('class Dummy${cls}Shunt;')
-code()
-# This version directs to the real Params struct and the default
-# behavior of create if there's an appropriate constructor.
-code('template ')
-code('class Dummy${cls}Shunt::value>>')
-code('{')
-code('  public:')
-code('using Params = ${cls}Params;')
-code('static ${{cls.cxx_class}} *')
-code('create(const Params &p)')
-code('{')
-code('return new CxxClass(p);')
-code('}')
-code('};')
-code()
-# This version diverts to the DummyParamsClass and a dummy
-# implementation of create if the appropriate constructor does not
-# exist.
-code('template ')
-code('class Dummy${cls}Shunt::value>>')
-code('{')
-code('  public:')
-code('using Params = Dummy${cls}ParamsClass;')
-code('static ${{cls.cxx_class}} *')
-code('create(const Params &p)')
-code('{')
-code('return nullptr;')
-code('}')
-code('};')
-code()
-code('} // anonymous namespace')
-code()
-# An implementation of either the real Params struct's create
-# method, or the Dummy one. Either an implementation is
-# mandantory since this was shunted off to the dummy class, or
-# one is optional which will overri

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