[gem5-dev] Change in public/gem5[master]: configs: fix cpu names in big.LITTLE example
Pierre-Yves Péneau has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3300 )
Change subject: configs: fix cpu names in big.LITTLE example
..
configs: fix cpu names in big.LITTLE example
CPU aliases have been dropped, this change fixes the big.LITTLE example.
Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/3300
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 3e7ac2f..4f548b1 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -84,7 +84,7 @@
class BigCluster(devices.CpuCluster):
def __init__(self, system, num_cpus, cpu_clock,
cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("arm_detailed"), devices.L1I,
devices.L1D,
+cpu_config = [ CpuConfig.get("O3_ARM_v7a_3"), devices.L1I,
devices.L1D,
devices.WalkCache, devices.L2 ]
super(BigCluster, self).__init__(system, num_cpus, cpu_clock,
cpu_voltage, *cpu_config)
@@ -92,7 +92,7 @@
class LittleCluster(devices.CpuCluster):
def __init__(self, system, num_cpus, cpu_clock,
cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("minor"), devices.L1I, devices.L1D,
+cpu_config = [ CpuConfig.get("MinorCPU"), devices.L1I, devices.L1D,
devices.WalkCache, devices.L2 ]
super(LittleCluster, self).__init__(system, num_cpus, cpu_clock,
cpu_voltage, *cpu_config)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Gerrit-Change-Number: 3300
Gerrit-PatchSet: 3
Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
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[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE
Pierre-Yves Péneau has submitted this change and it was merged. ( https://gem5-review.googlesource.com/2464 ) Change subject: arm, config: added support for ex5 model of big.LITTLE .. arm, config: added support for ex5 model of big.LITTLE This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abu...@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.do...@arm.com> Maintainer: Jason Lowe-Power <ja...@lowepower.com> --- M configs/common/CpuConfig.py A configs/common/ex5_LITTLE.py A configs/common/ex5_big.py M configs/example/arm/fs_bigLITTLE.py 4 files changed, 392 insertions(+), 0 deletions(-) Approvals: Gabor Dozsa: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py index 8810622..28267c7 100644 --- a/configs/common/CpuConfig.py +++ b/configs/common/CpuConfig.py @@ -117,6 +117,20 @@ except: pass +# The calibrated ex5-model cores +try: +from ex5_LITTLE import ex5_LITTLE +_cpu_classes["ex5_LITTLE"] = ex5_LITTLE +except: + pass + +try: +from ex5_big import ex5_big +_cpu_classes["ex5_big"] = ex5_big +except: + pass + + # Add all CPUs in the object hierarchy. for name, cls in inspect.getmembers(m5.objects, is_cpu_class): _cpu_classes[name] = cls diff --git a/configs/common/ex5_LITTLE.py b/configs/common/ex5_LITTLE.py new file mode 100644 index 000..c9c419f --- /dev/null +++ b/configs/common/ex5_LITTLE.py @@ -0,0 +1,154 @@ +# Copyright (c) 2012 The Regents of The University of Michigan +# Copyright (c) 2016 Centre National de la Recherche Scientifique +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski +# Anastasiia Butko +# Louisa Bessad + +from m5.objects import * +from O3_ARM_v7a import * +from Caches import * + +#--- +#ex5 LITTLE core (based on the ARM Cortex-A7) +#--- + +# Simple ALU Instructions have a latency of 3 +class ex5_LITTLE_Simple_Int(MinorDefaultIntFU): +opList = [ OpDesc(opClass='IntAlu', opLat=4) ] + +# Complex ALU instructions have a variable latencies +class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU): +opList = [ OpDesc(opClass='IntMult', opLat=7) ] + +class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU): +opList = [ OpDesc(opClass='IntDiv', opLat=9) ] + +# Floating point and SIMD instructions +class ex5_LITTLE_FP(MinorDefaultFloatSimdFU): +opList = [ OpDesc(opClass='SimdAdd', opLat=6), + OpDesc(opClass='SimdAddAcc', opLat
[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE
Hello Jason Lowe-Power, Gabor Dozsa, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/2464 to look at the new patch set (#3). Change subject: arm, config: added support for ex5 model of big.LITTLE .. arm, config: added support for ex5 model of big.LITTLE This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abu...@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> --- M configs/common/CpuConfig.py A configs/common/ex5_LITTLE.py A configs/common/ex5_big.py M configs/example/arm/fs_bigLITTLE.py 4 files changed, 392 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/2464 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Gerrit-Change-Number: 2464 Gerrit-PatchSet: 3 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com> Gerrit-Reviewer: Gabor Dozsa <gabor.do...@arm.com> Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com> Gerrit-Reviewer: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: configs: fix cpu names in big.LITTLE example
Pierre-Yves Péneau has uploaded this change for review. (
https://gem5-review.googlesource.com/3300
Change subject: configs: fix cpu names in big.LITTLE example
..
configs: fix cpu names in big.LITTLE example
CPU aliases have been dropped, this change fixes the big.LITTLE example.
Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 3ebc91d..92173e5 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -82,7 +82,7 @@
class BigCluster(devices.CpuCluster):
def __init__(self, system, num_cpus, cpu_clock,
cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("arm_detailed"), devices.L1I,
devices.L1D,
+cpu_config = [ CpuConfig.get("O3_ARM_v7a_3"), devices.L1I,
devices.L1D,
devices.WalkCache, devices.L2 ]
super(BigCluster, self).__init__(system, num_cpus, cpu_clock,
cpu_voltage, *cpu_config)
@@ -90,7 +90,7 @@
class LittleCluster(devices.CpuCluster):
def __init__(self, system, num_cpus, cpu_clock,
cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("minor"), devices.L1I, devices.L1D,
+cpu_config = [ CpuConfig.get("MinorCPU"), devices.L1I, devices.L1D,
devices.WalkCache, devices.L2 ]
super(LittleCluster, self).__init__(system, num_cpus, cpu_clock,
cpu_voltage, *cpu_config)
--
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Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Gerrit-Change-Number: 3300
Gerrit-PatchSet: 1
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[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE
Hello Jason Lowe-Power, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/2464 to look at the new patch set (#2). Change subject: arm, config: added support for ex5 model of big.LITTLE .. arm, config: added support for ex5 model of big.LITTLE This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abu...@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> --- M configs/common/CpuConfig.py A configs/common/ex5_LITTLE.py A configs/common/ex5_big.py M configs/example/arm/fs_bigLITTLE.py 4 files changed, 390 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/2464 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Gerrit-Change-Number: 2464 Gerrit-PatchSet: 2 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com> Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com> Gerrit-Reviewer: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: arm, config: Enabled MemConfig usage for the big.LITTLE example
Pierre-Yves Péneau has uploaded this change for review. (
https://gem5-review.googlesource.com/2463
Change subject: arm, config: Enabled MemConfig usage for the big.LITTLE
example
..
arm, config: Enabled MemConfig usage for the big.LITTLE example
This patch replaces the SimpleMemory with the MemConfig function. Additional
parser arguments are added (TODO: improve with addCommonOptions &
addFSOptions).
From http://reviews.gem5.org/r/3665
Change-Id: I7bd4e58a01da22646ace4a8a7709b02672ecf156
Signed-off-by: Anastasiia Butko <abu...@lbl.gov>
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index c542b85..bc80d4b 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -50,9 +50,9 @@
from common import SysPaths
from common import CpuConfig
+from common import MemConfig
import devices
-
default_dtb = 'armv8_gem5_v1_big_little_2_2.dtb'
default_kernel = 'vmlinux4.3.aarch64'
@@ -79,14 +79,15 @@
cpu_voltage, *cpu_config)
-def createSystem(caches, kernel, bootscript, disks=[]):
-sys = devices.SimpleSystem(caches, default_mem_size,
- kernel=SysPaths.binary(kernel),
- readfile=bootscript,
+def createSystem(options, disks=[]):
+sys = devices.SimpleSystem(options.caches, default_mem_size,
+ kernel=SysPaths.binary(options.kernel),
+ readfile=options.bootscript,
machine_type="DTOnly")
-sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
-sys.mem_ctrls.port = sys.membus.master
+mem_region = sys.realview._mem_regions[0]
+sys.mem_ranges = AddrRange(start=mem_region[0], size=default_mem_size)
+MemConfig.config_mem(options, sys)
sys.connect()
@@ -135,6 +136,21 @@
help="Big CPU clock frequency")
parser.add_argument("--little-cpu-clock", type=str, default="1GHz",
help="Little CPU clock frequency")
+parser.add_argument("--mem-type", type=str, default="DDR3_1600_8x8",
+help="memory controller type")
+parser.add_argument("--mem-channels", type=int, default=1,
+help = "number of memory channels")
+parser.add_argument("--mem-ranks", type=int, default=None,
+help = "number of memory ranks per channel")
+parser.add_argument("--mem-size", action="store", type=str,
+default="512MB",
+help="Specify the physical memory size")
+parser.add_argument("--tlm-memory", type=str,
+help="use external port for SystemC TLM ")
+parser.add_argument("--external-memory-system", type=str,
+help="use external ports of this port_type for
caches")
+parser.add_argument("--elastic-trace-en", action="store_true",
+help="Enable capture of elastic trace probe.")
return parser
@@ -157,9 +173,7 @@
root = Root(full_system=True)
disks = [default_disk] if len(options.disk) == 0 else options.disk
-system = createSystem(options.caches,
- options.kernel,
- options.bootscript,
+system = createSystem(options,
disks=disks)
root.system = system
--
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To unsubscribe, visit https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7bd4e58a01da22646ace4a8a7709b02672ecf156
Gerrit-Change-Number: 2463
Gerrit-PatchSet: 1
Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
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[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE
Pierre-Yves Péneau has uploaded this change for review. ( https://gem5-review.googlesource.com/2464 Change subject: arm, config: added support for ex5 model of big.LITTLE .. arm, config: added support for ex5 model of big.LITTLE This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abu...@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> --- M configs/common/CpuConfig.py A configs/common/ex5_LITTLE.py A configs/common/ex5_big.py M configs/example/arm/fs_bigLITTLE.py 4 files changed, 402 insertions(+), 9 deletions(-) diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py index 757ec2d..77d523a 100644 --- a/configs/common/CpuConfig.py +++ b/configs/common/CpuConfig.py @@ -141,6 +141,20 @@ except: pass +# The calibrated ex5-model cores +try: +from ex5_LITTLE import ex5_LITTLE +_cpu_classes["ex5_LITTLE"] = ex5_LITTLE +except: + pass + +try: +from ex5_big import ex5_big +_cpu_classes["ex5_big"] = ex5_big +except: + pass + + # Add all CPUs in the object hierarchy. for name, cls in inspect.getmembers(m5.objects, is_cpu_class): _cpu_classes[name] = cls diff --git a/configs/common/ex5_LITTLE.py b/configs/common/ex5_LITTLE.py new file mode 100644 index 000..c9c419f --- /dev/null +++ b/configs/common/ex5_LITTLE.py @@ -0,0 +1,154 @@ +# Copyright (c) 2012 The Regents of The University of Michigan +# Copyright (c) 2016 Centre National de la Recherche Scientifique +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski +# Anastasiia Butko +# Louisa Bessad + +from m5.objects import * +from O3_ARM_v7a import * +from Caches import * + +#--- +#ex5 LITTLE core (based on the ARM Cortex-A7) +#--- + +# Simple ALU Instructions have a latency of 3 +class ex5_LITTLE_Simple_Int(MinorDefaultIntFU): +opList = [ OpDesc(opClass='IntAlu', opLat=4) ] + +# Complex ALU instructions have a variable latencies +class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU): +opList = [ OpDesc(opClass='IntMult', opLat=7) ] + +class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU): +opList = [ OpDesc(opClass='IntDiv', opLat=9) ] + +# Floating point and SIMD instructions +class ex5_LITTLE_FP(MinorDefaultFloatSimdFU): +opList = [ OpDesc(opClass='SimdAdd', opLat=6), + OpDesc(opClass='SimdAddAcc', opLat=4), + OpDesc(opClass='SimdAlu', opLat=4), + OpDesc(opClass='SimdCmp', opLat=1), + OpDesc(opClass='SimdCvt', opLat=3), + OpDesc(opClass='SimdMisc', opLat=3), + OpDesc(opClass='SimdMult',opLat=4), +
[gem5-dev] Change in public/gem5[master]: config, mem: l3 cache support
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/2462
to look at the new patch set (#2).
Change subject: config, mem: l3 cache support
..
config, mem: l3 cache support
Change-Id: I78e3c055d5f312647c4ab4f0c937d6dc4841fb57
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/Options.py
M configs/example/fs.py
M configs/example/se.py
5 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 52659e8..d85a69b 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -60,12 +60,12 @@
print "arm_detailed is unavailable. Did you compile the O3
model?"
sys.exit(1)
-dcache_class, icache_class, l2_cache_class, walk_cache_class = \
-O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
-O3_ARM_v7aWalkCache
+dcache_class, icache_class, l2_cache_class, l3_cache_class, \
+walk_cache_class = O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, \
+O3_ARM_v7aL2, L3Cache, O3_ARM_v7aWalkCache
else:
-dcache_class, icache_class, l2_cache_class, walk_cache_class = \
-L1_DCache, L1_ICache, L2Cache, None
+dcache_class, icache_class, l2_cache_class, l3_cache_class, \
+walk_cache_class = L1_DCache, L1_ICache, L2Cache, L3Cache,
None
if buildEnv['TARGET_ISA'] == 'x86':
walk_cache_class = PageTableWalkerCache
@@ -77,8 +77,21 @@
# minimal so that compute delays do not include memory access
latencies.
# Configure the compulsory L1 caches for the O3CPU, do not configure
# any more caches.
-if options.l2cache and options.elastic_trace_en:
-fatal("When elastic trace is enabled, do not configure L2 caches.")
+if (options.l2cache or options.l3cache) and options.elastic_trace_en:
+fatal("When elastic trace is enabled, do not configure L2/L3
caches.")
+
+if options.l3cache:
+# Provide a clock for the L3 and the L2-to-L3 bus here as they
+# are not connected using addTwoLevelCacheHierarchy. Use the
+# same clock as the CPUs.
+system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
+ size=options.l3_size,
+ assoc=options.l3_assoc)
+
+system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain,
width=64)
+system.l3.cpu_side = system.tol3bus.master
+system.l3.mem_side = system.membus.slave
+
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
@@ -90,7 +103,11 @@
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
-system.l2.mem_side = system.membus.slave
+
+if options.l3cache:
+system.l2.mem_side = system.tol3bus.slave
+else:
+system.l2.mem_side = system.membus.slave
if options.memchecker:
system.memchecker = MemChecker()
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 926a41d..d0ff57e 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -72,6 +72,21 @@
tgts_per_mshr = 12
write_buffers = 8
+class L3Cache(Cache):
+assoc = 16
+tag_latency = 30
+data_latency = 30
+response_latency = 30
+mshrs = 30
+tgts_per_mshr = 8
+write_buffers = 10
+size = '16MB'
+prefetch_on_access = True
+clusivity = 'mostly_excl'
+# Simple stride prefetcher
+prefetcher = StridePrefetcher(degree=8, latency = 1)
+tags = RandomRepl()
+
class IOCache(Cache):
assoc = 8
tag_latency = 50
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 9af15ff..49d4af8 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -98,6 +98,7 @@
help="use external port for SystemC TLM
cosimulation")
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
+parser.add_option("--l3cache", action="store_true")
parser.add_option("--num-dirs", type="int", default=1)
parser.add_option("--num-l2caches", type="int", default=1)
parser.add_option("--num-l3caches", type="int", default=1)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 8102edc..c3aa495 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -183,7 +183,7 @@
cpu.interrupts[0].int_slave =
test_sys.ruby._cpu_ports[i].master
else:
-
[gem5-dev] Change in public/gem5[master]: config, mem: l3 cache support
Pierre-Yves Péneau has uploaded this change for review. (
https://gem5-review.googlesource.com/2462
Change subject: config, mem: l3 cache support
..
config, mem: l3 cache support
Change-Id: I78e3c055d5f312647c4ab4f0c937d6dc4841fb57
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/O3_ARM_v7a.py
M configs/common/Options.py
M configs/example/fs.py
M configs/example/se.py
6 files changed, 54 insertions(+), 11 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 52659e8..dd1098d 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -60,12 +60,12 @@
print "arm_detailed is unavailable. Did you compile the O3
model?"
sys.exit(1)
-dcache_class, icache_class, l2_cache_class, walk_cache_class = \
-O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
-O3_ARM_v7aWalkCache
+dcache_class, icache_class, l2_cache_class, l3_cache_class, \
+walk_cache_class = O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, \
+O3_ARM_v7aL2, O3_ARM_v7aL3, O3_ARM_v7aWalkCache
else:
-dcache_class, icache_class, l2_cache_class, walk_cache_class = \
-L1_DCache, L1_ICache, L2Cache, None
+dcache_class, icache_class, l2_cache_class, l3_cache_class, \
+walk_cache_class = L1_DCache, L1_ICache, L2Cache, L3Cache,
None
if buildEnv['TARGET_ISA'] == 'x86':
walk_cache_class = PageTableWalkerCache
@@ -77,8 +77,21 @@
# minimal so that compute delays do not include memory access
latencies.
# Configure the compulsory L1 caches for the O3CPU, do not configure
# any more caches.
-if options.l2cache and options.elastic_trace_en:
-fatal("When elastic trace is enabled, do not configure L2 caches.")
+if (options.l2cache or options.l3cache) and options.elastic_trace_en:
+fatal("When elastic trace is enabled, do not configure L2/L3
caches.")
+
+if options.l3cache:
+# Provide a clock for the L3 and the L2-to-L3 bus here as they
+# are not connected using addTwoLevelCacheHierarchy. Use the
+# same clock as the CPUs.
+system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
+ size=options.l3_size,
+ assoc=options.l3_assoc)
+
+system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain,
width=64)
+system.l3.cpu_side = system.tol3bus.master
+system.l3.mem_side = system.membus.slave
+
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
@@ -90,7 +103,11 @@
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
-system.l2.mem_side = system.membus.slave
+
+if options.l3cache:
+system.l2.mem_side = system.tol3bus.slave
+else:
+system.l2.mem_side = system.membus.slave
if options.memchecker:
system.memchecker = MemChecker()
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 926a41d..86cbc52 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -72,6 +72,15 @@
tgts_per_mshr = 12
write_buffers = 8
+class L3Cache(Cache):
+assoc = 16
+tag_latency = 30
+data_latency = 30
+response_latency = 30
+mshrs = 30
+tgts_per_mshr = 8
+write_buffers = 10
+
class IOCache(Cache):
assoc = 8
tag_latency = 50
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index f5c2c71..a2a6f94 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -201,3 +201,19 @@
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
tags = RandomRepl()
+
+# L3 Cache
+class O3_ARM_v7aL3(Cache):
+tag_latency = 30
+data_latency = 30
+response_latency = 30
+mshrs = 30
+tgts_per_mshr = 8
+size = '16MB'
+assoc = 16
+write_buffers = 10
+prefetch_on_access = True
+clusivity = 'mostly_excl'
+# Simple stride prefetcher
+prefetcher = StridePrefetcher(degree=8, latency = 1)
+tags = RandomRepl()
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 9af15ff..49d4af8 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -98,6 +98,7 @@
help="use external port for SystemC TLM
cosimulation")
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
+parser.add_option("--l3cache", action="store_true")
parser.add_option("--num-dirs",
[gem5-dev] Change in public/gem5[master]: misc: add copyright/name information for contribution
Pierre-Yves Péneau has submitted this change and it was merged. ( https://gem5-review.googlesource.com/2328 ) Change subject: misc: add copyright/name information for contribution .. misc: add copyright/name information for contribution Change-Id: I9242ce50b86b02ec1880d411627da11265cb8961 Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2328 Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com> Reviewed-by: Brandon Potter <brandon.pot...@amd.com> Reviewed-by: Jason Lowe-Power <ja...@lowepower.com> Maintainer: Jason Lowe-Power <ja...@lowepower.com> --- M CONTRIBUTING.md 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Andreas Sandberg: Looks good to me, approved Brandon Potter: Looks good to me, approved diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 8e82798..a9781a3 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -186,6 +186,11 @@ It is imperative that you use your real name and your real email address in both tags and in the author field of the changeset. +For significant changes, authors are encouraged to add copyright information +and their names at the beginning of the file. The main purpose of the author +names on the file is to track who is most knowledgeable about the file (e.g., +who has contributed a significant amount of code to the file). + Note: If you do not follow these guidelines, the gerrit review site will automatically reject your patch. If this happens, update your changeset descriptions to match the required style -- To view, visit https://gem5-review.googlesource.com/2328 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9242ce50b86b02ec1880d411627da11265cb8961 Gerrit-Change-Number: 2328 Gerrit-PatchSet: 3 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com> Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com> Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com> Gerrit-Reviewer: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: misc: add copyright/name information for contribution
Hello Jason Lowe-Power, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/2328 to look at the new patch set (#2). Change subject: misc: add copyright/name information for contribution .. misc: add copyright/name information for contribution Change-Id: I9242ce50b86b02ec1880d411627da11265cb8961 Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> --- M CONTRIBUTING.md 1 file changed, 5 insertions(+), 0 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 8e82798..a9781a3 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -186,6 +186,11 @@ It is imperative that you use your real name and your real email address in both tags and in the author field of the changeset. +For significant changes, authors are encouraged to add copyright information +and their names at the beginning of the file. The main purpose of the author +names on the file is to track who is most knowledgeable about the file (e.g., +who has contributed a significant amount of code to the file). + Note: If you do not follow these guidelines, the gerrit review site will automatically reject your patch. If this happens, update your changeset descriptions to match the required style -- To view, visit https://gem5-review.googlesource.com/2328 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9242ce50b86b02ec1880d411627da11265cb8961 Gerrit-Change-Number: 2328 Gerrit-PatchSet: 2 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com> Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: misc: add copyright/name information for contribution
Pierre-Yves Péneau has uploaded this change for review. ( https://gem5-review.googlesource.com/2328 Change subject: misc: add copyright/name information for contribution .. misc: add copyright/name information for contribution Change-Id: I9242ce50b86b02ec1880d411627da11265cb8961 --- M CONTRIBUTING.md 1 file changed, 3 insertions(+), 0 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 8e82798..ecaafb3 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -186,6 +186,9 @@ It is imperative that you use your real name and your real email address in both tags and in the author field of the changeset. +For significant changes, authors are encouraged to add copyright information +and their names at the beginning of the file. + Note: If you do not follow these guidelines, the gerrit review site will automatically reject your patch. If this happens, update your changeset descriptions to match the required style -- To view, visit https://gem5-review.googlesource.com/2328 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9242ce50b86b02ec1880d411627da11265cb8961 Gerrit-Change-Number: 2328 Gerrit-PatchSet: 1 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: config: exit with fatal() if error
Pierre-Yves Péneau has submitted this change and it was merged. (
https://gem5-review.googlesource.com/2221 )
Change subject: config: exit with fatal() if error
..
config: exit with fatal() if error
If output redirection is activated, the error message is printed in
simout. This change ensure it will be printed in simerr.
Change-Id: Ie661ac6b6978bf2e4aaaccdf23134795d764d459
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/2221
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M configs/common/PlatformConfig.py
1 file changed, 5 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/configs/common/PlatformConfig.py
b/configs/common/PlatformConfig.py
index 3541c07..e2589c0 100644
--- a/configs/common/PlatformConfig.py
+++ b/configs/common/PlatformConfig.py
@@ -1,6 +1,8 @@
# Copyright (c) 2012, 2015 ARM Limited
# All rights reserved.
#
+# Copyright (c) 2017, Centre National de la Recherche Scientifique (CNRS)
+#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
@@ -34,10 +36,12 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
+# Pierre-Yves Peneau
import m5.objects
import inspect
import sys
+from m5.util import fatal
from textwrap import TextWrapper
# Dictionary of mapping names of real CPU models to classes.
@@ -74,8 +78,7 @@
try:
return _platform_classes[real_name]
except KeyError:
-print "%s is not a valid Platform model." % (name,)
-sys.exit(1)
+fatal("%s is not a valid Platform model." % (name,))
def print_platform_list():
"""Print a list of available Platform classes including their
aliases."""
--
To view, visit https://gem5-review.googlesource.com/2221
To unsubscribe, visit https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ie661ac6b6978bf2e4aaaccdf23134795d764d459
Gerrit-Change-Number: 2221
Gerrit-PatchSet: 2
Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
___
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[gem5-dev] Change in public/gem5[master]: cpu: check cpu ports status before connecting
Pierre-Yves Péneau has uploaded this change for review. ( https://gem5-review.googlesource.com/2223 Change subject: cpu: check cpu ports status before connecting .. cpu: check cpu ports status before connecting Connecting a ComMonitor between cpu port and L1 cache needs to assign this port to the monitor slave. This assignement has to be done before connecting cached ports. However, connecting cached ports does not check if cpu ports are already connected, which raises an error when it is true. This change fixes this assumption by checking the port status before the connection. Change-Id: I77b5b6ee7c8a8910f3f66103f2f6f4df3af2054b Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> --- M src/cpu/BaseCPU.py 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 7b8a615..8bac998 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -12,6 +12,7 @@ # # Copyright (c) 2005-2008 The Regents of The University of Michigan # Copyright (c) 2011 Regents of the University of California +# Copyright (c) 2017 Centre National de la Recherche Scientifique # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -40,6 +41,7 @@ # Authors: Nathan Binkert # Rick Strong # Andreas Hansson +# Pierre-Yves Peneau import sys @@ -282,8 +284,11 @@ def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): self.icache = ic self.dcache = dc -self.icache_port = ic.cpu_side -self.dcache_port = dc.cpu_side +if not self.icache_port: +self.icache_port = ic.cpu_side +if not self.dcache_port: +self.dcache_port = dc.cpu_side + self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: -- To view, visit https://gem5-review.googlesource.com/2223 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I77b5b6ee7c8a8910f3f66103f2f6f4df3af2054b Gerrit-Change-Number: 2223 Gerrit-PatchSet: 2 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: misc: add missing copyright/author information in previous c...
Pierre-Yves Péneau has uploaded this change for review. ( https://gem5-review.googlesource.com/2224 Change subject: misc: add missing copyright/author information in previous commit .. misc: add missing copyright/author information in previous commit See a06a46f and a854373. Change-Id: Id66427db22b7d7764c218b9cd78d95db929f4127 Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> --- M src/base/statistics.hh M src/mem/comm_monitor.cc M src/mem/comm_monitor.hh 3 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/base/statistics.hh b/src/base/statistics.hh index cdb5a0b..d0f7729 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2017, Centre National de la Recherche Scientifique * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,6 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Nathan Binkert + * Pierre-Yves Peneau */ /** @file diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc index d5800e5..0914f34 100644 --- a/src/mem/comm_monitor.cc +++ b/src/mem/comm_monitor.cc @@ -1,6 +1,7 @@ /* * Copyright (c) 2012-2013, 2015 ARM Limited * Copyright (c) 2016 Google Inc. + * Copyright (c) 2017, Centre National de la Recherche Scientifique * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -38,6 +39,7 @@ * Authors: Thomas Grass * Andreas Hansson * Rahul Thakur + * Pierre-Yves Peneau */ #include "mem/comm_monitor.hh" diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh index d46f75f..fa28eae 100644 --- a/src/mem/comm_monitor.hh +++ b/src/mem/comm_monitor.hh @@ -1,6 +1,7 @@ /* * Copyright (c) 2012-2013, 2015 ARM Limited * Copyright (c) 2016 Google Inc. + * Copyright (c) 2017, Centre National de la Recherche Scientifique * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -38,6 +39,7 @@ * Authors: Thomas Grass * Andreas Hansson * Rahul Thakur + * Pierre-Yves Peneau */ #ifndef __MEM_COMM_MONITOR_HH__ -- To view, visit https://gem5-review.googlesource.com/2224 To unsubscribe, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id66427db22b7d7764c218b9cd78d95db929f4127 Gerrit-Change-Number: 2224 Gerrit-PatchSet: 2 Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3830: syscall_emul: remove unused class and member
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3830/#review9461 --- Ship it! Ship It! - Pierre-Yves Péneau On Feb. 23, 2017, 8:33 p.m., Brandon Potter wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3830/ > --- > > (Updated Feb. 23, 2017, 8:33 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11880:770add1a79a8 > --- > syscall_emul: remove unused class and member > > > Diffs > - > > src/sim/process.hh 5ea85692a53ea437c95e5a199884bd3a5266f820 > > Diff: http://reviews.gem5.org/r/3830/diff/ > > > Testing > --- > > > Thanks, > > Brandon Potter > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in public/gem5[master]: config: exit with fatal() if error
Pierre-Yves Péneau has uploaded this change for review. (
https://gem5-review.googlesource.com/2221
Change subject: config: exit with fatal() if error
..
config: exit with fatal() if error
If output redirection is activated, the error message is printed in
simout. This change ensure it will be printed in simerr.
Change-Id: Ie661ac6b6978bf2e4aaaccdf23134795d764d459
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
---
M configs/common/PlatformConfig.py
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/configs/common/PlatformConfig.py
b/configs/common/PlatformConfig.py
index 3541c07..e2589c0 100644
--- a/configs/common/PlatformConfig.py
+++ b/configs/common/PlatformConfig.py
@@ -1,6 +1,8 @@
# Copyright (c) 2012, 2015 ARM Limited
# All rights reserved.
#
+# Copyright (c) 2017, Centre National de la Recherche Scientifique (CNRS)
+#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
@@ -34,10 +36,12 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
+# Pierre-Yves Peneau
import m5.objects
import inspect
import sys
+from m5.util import fatal
from textwrap import TextWrapper
# Dictionary of mapping names of real CPU models to classes.
@@ -74,8 +78,7 @@
try:
return _platform_classes[real_name]
except KeyError:
-print "%s is not a valid Platform model." % (name,)
-sys.exit(1)
+fatal("%s is not a valid Platform model." % (name,))
def print_platform_list():
"""Print a list of available Platform classes including their
aliases."""
--
To view, visit https://gem5-review.googlesource.com/2221
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie661ac6b6978bf2e4aaaccdf23134795d764d459
Gerrit-Change-Number: 2221
Gerrit-PatchSet: 1
Gerrit-Owner: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
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Re: [gem5-dev] Review Request 3814: misc: Add a CONTRIBUTING document
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3814/#review9456 --- Ship it! Ship It! - Pierre-Yves Péneau On Feb. 21, 2017, 6:34 p.m., Jason Lowe-Power wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3814/ > --- > > (Updated Feb. 21, 2017, 6:34 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > changesets: > 11849:b5f456096b51 "misc: Add a CONTRIBUTING document > > This document details how to contribute to gem5 based on our new > contribution flow with git and gerrit. > > Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>" > > > Diffs > - > > CONTRIBUTING.md PRE-CREATION > > Diff: http://reviews.gem5.org/r/3814/diff/ > > > Testing > --- > > > Thanks, > > Jason Lowe-Power > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] changeset in gem5: mem, stats: fix typos in CommMonitor and Stats
changeset f438fcbab00e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f438fcbab00e
description:
mem, stats: fix typos in CommMonitor and Stats
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
Reviewed-by: Tony Gutierrez <anthony.gutier...@amd.com>
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed at http://reviews.gem5.org/r/3802/
diffstat:
src/base/statistics.hh | 4 ++--
src/mem/comm_monitor.cc | 2 +-
src/mem/comm_monitor.hh | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diffs (45 lines):
diff -r 22d08b519cb0 -r f438fcbab00e src/base/statistics.hh
--- a/src/base/statistics.hhWed Feb 15 14:56:54 2017 -0600
+++ b/src/base/statistics.hhWed Feb 15 14:59:06 2017 -0600
@@ -1359,7 +1359,7 @@
};
/**
- * Templatized storage and interface for a distrbution stat.
+ * Templatized storage and interface for a distribution stat.
*/
class DistStor
{
@@ -1894,7 +1894,7 @@
}
/**
- * Add the argument distribution to the this distibution.
+ * Add the argument distribution to the this distribution.
*/
void add(DistBase ) { data()->add(d.data()); }
diff -r 22d08b519cb0 -r f438fcbab00e src/mem/comm_monitor.cc
--- a/src/mem/comm_monitor.cc Wed Feb 15 14:56:54 2017 -0600
+++ b/src/mem/comm_monitor.cc Wed Feb 15 14:59:06 2017 -0600
@@ -490,7 +490,7 @@
stats.writeTransHist
.init(params()->transaction_bins)
.name(name() + ".writeTransHist")
-.desc("Histogram of read transactions per sample period")
+.desc("Histogram of write transactions per sample period")
.flags(stats.disableTransactionHists ? nozero : pdf);
stats.readAddrDist
diff -r 22d08b519cb0 -r f438fcbab00e src/mem/comm_monitor.hh
--- a/src/mem/comm_monitor.hh Wed Feb 15 14:56:54 2017 -0600
+++ b/src/mem/comm_monitor.hh Wed Feb 15 14:59:06 2017 -0600
@@ -271,7 +271,7 @@
struct MonitorStats
{
-/** Disable flag for burst length historgrams **/
+/** Disable flag for burst length histograms **/
bool disableBurstLengthHists;
/** Histogram of read burst lengths */
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[gem5-dev] changeset in gem5: mem, misc: fix building issue with CommMonito...
changeset 22d08b519cb0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=22d08b519cb0
description:
mem, misc: fix building issue with CommMonitor (unused variables)
Signed-off-by: Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr>
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed at http://reviews.gem5.org/r/3801/
diffstat:
src/mem/comm_monitor.cc | 12
1 files changed, 4 insertions(+), 8 deletions(-)
diffs (43 lines):
diff -r b9436a49 -r 22d08b519cb0 src/mem/comm_monitor.cc
--- a/src/mem/comm_monitor.cc Wed Feb 15 09:28:44 2017 -0600
+++ b/src/mem/comm_monitor.cc Wed Feb 15 14:56:54 2017 -0600
@@ -248,8 +248,6 @@
// or even deleted when sendTiming() is called.
const ProbePoints::PacketInfo pkt_info(pkt);
-const bool is_read = pkt->isRead();
-const bool is_write = pkt->isWrite();
const bool expects_response(pkt->needsResponse() &&
!pkt->cacheResponding());
@@ -274,8 +272,8 @@
}
if (successful) {
-DPRINTF(CommMonitor, "Forwarded %s request\n",
-(is_read ? "read" : (is_write ? "write" : "non read/write")));
+DPRINTF(CommMonitor, "Forwarded %s request\n", pkt->isRead() ? "read" :
+pkt->isWrite() ? "write" : "non read/write");
stats.updateReqStats(pkt_info, false, expects_response);
}
return successful;
@@ -291,8 +289,6 @@
// or even deleted when sendTiming() is called.
const ProbePoints::PacketInfo pkt_info(pkt);
-bool is_read = pkt->isRead();
-bool is_write = pkt->isWrite();
Tick latency = 0;
CommMonitorSenderState* received_state =
dynamic_cast<CommMonitorSenderState*>(pkt->senderState);
@@ -325,8 +321,8 @@
if (successful) {
ppPktResp->notify(pkt_info);
-DPRINTF(CommMonitor, "Received %s response\n",
-(is_read ? "Read" : (is_write ? "Write" : "non read/write")));
+DPRINTF(CommMonitor, "Received %s response\n", pkt->isRead() ? "read" :
+pkt->isWrite() ? "write" : "non read/write");
stats.updateRespStats(pkt_info, latency, false);
}
return successful;
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Re: [gem5-dev] Review Request 3802: mem, stats: fix typos in CommMonitor and Stats
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3802/ --- (Updated Feb. 7, 2017, 6:29 p.m.) Review request for Default. Repository: gem5 Description (updated) --- Changeset 11809:e8c2d26050a3 --- mem, stats: fix typos in CommMonitor and Stats Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Reviewed-by: Tony Gutierrez <anthony.gutier...@amd.com> Reviewed-by: Jason Lowe-Power <ja...@lowepower.com> Diffs - src/base/statistics.hh 63325e5b0a9d src/mem/comm_monitor.hh 63325e5b0a9d src/mem/comm_monitor.cc 63325e5b0a9d Diff: http://reviews.gem5.org/r/3802/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3808: mem: fix printing of 1st cache tags line
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3808/#review9410 --- Ship it! Ship It! - Pierre-Yves Péneau On Feb. 7, 2017, 3:25 p.m., Bjoern A. Zeeb wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3808/ > --- > > (Updated Feb. 7, 2017, 3:25 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Rather than having the 1st line on the Log line and every other line on its > own, add a new line to have a common format for all of them. Makes parsing a > lot easier. > > Before: > 1813979170500: system.l2cache: recvTimingReq tags:set: 0 block: 0 > state: f (M) valid: 1 writable: 1 readable: 1 dirty: 1 tag: fff3 > set: 0 block: 1 state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: > 0 tag: f9a3 > > After: > 1813979170500: system.l2cache: recvTimingReq tags: > set: 0 block: 0 state: f (M) valid: 1 writable: 1 readable: 1 dirty: > 1 tag: fff3 > set: 0 block: 1 state: 7 (E) valid: 1 writable: 1 readable: 1 dirty: > 0 tag: f9a3 > > > Diffs > - > > src/mem/cache/cache.cc 63325e5b0a9d > > Diff: http://reviews.gem5.org/r/3808/diff/ > > > Testing > --- > > > Thanks, > > Bjoern A. Zeeb > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3802: mem, stats: fix typos in CommMonitor and Stats
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3802/ --- (Updated Feb. 6, 2017, 2:43 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 11809:e8c2d26050a3 --- mem, stats: fix typos in CommMonitor and Stats Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Diffs (updated) - src/base/statistics.hh 63325e5b0a9d src/mem/comm_monitor.hh 63325e5b0a9d src/mem/comm_monitor.cc 63325e5b0a9d Diff: http://reviews.gem5.org/r/3802/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3801: mem, misc: fix building issue with CommMonitor (unused variables)
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3801/ --- (Updated Feb. 4, 2017, 8:33 p.m.) Review request for Default. Repository: gem5 Description (updated) --- Changeset 11808:e0730e1d7afa --- misc: fix building issue (undefined variables) Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Reviewed-by: Andreas Hansson <andreas.hans...@arm.com> Reviewed-by: Jason Lowe-Power <ja...@lowepower.com> Diffs - src/mem/comm_monitor.cc 63325e5b0a9d Diff: http://reviews.gem5.org/r/3801/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3802: mem, stats: fix typos in CommMonitor and Stats
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3802/ --- (Updated Feb. 4, 2017, 7:41 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 11809:e8c2d26050a3 --- mem, stats: fix typos in CommMonitor and Stats Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Diffs (updated) - src/base/statistics.hh 63325e5b0a9d src/mem/comm_monitor.cc 63325e5b0a9d Diff: http://reviews.gem5.org/r/3802/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 3802: mem, stats: fix typos in CommMonitor and Stats
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3802/ --- Review request for Default. Repository: gem5 Description --- Changeset 11809:e8c2d26050a3 --- mem, stats: fix typos in CommMonitor and Stats Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Diffs - src/mem/comm_monitor.cc e2a6c88eb45d src/base/statistics.hh e2a6c88eb45d Diff: http://reviews.gem5.org/r/3802/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3801: mem, misc: fix building issue with CommMonitor (unused variables)
> On Feb. 3, 2017, 9:58 a.m., Andreas Hansson wrote: > > Thanks for fixing. Could you make it "mem:" and also include CommMonitor in > > the description. I also expect this is due to unused variables in fast > > builds? Not undefined variables. Yes, this is unused variables, thank you for pointing this. - Pierre-Yves --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3801/#review9386 --- On Feb. 3, 2017, 10:04 a.m., Pierre-Yves Péneau wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3801/ > --- > > (Updated Feb. 3, 2017, 10:04 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11808:e0730e1d7afa > ----------- > misc: fix building issue (undefined variables) > > Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> > > > Diffs > - > > src/mem/comm_monitor.cc 63325e5b0a9d > > Diff: http://reviews.gem5.org/r/3801/diff/ > > > Testing > --- > > > Thanks, > > Pierre-Yves Péneau > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3801: mem, misc: fix building issue with CommMonitor (unused variables)
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3801/ --- (Updated Feb. 3, 2017, 10:04 a.m.) Review request for Default. Summary (updated) - mem, misc: fix building issue with CommMonitor (unused variables) Repository: gem5 Description --- Changeset 11808:e0730e1d7afa --- misc: fix building issue (undefined variables) Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Diffs - src/mem/comm_monitor.cc 63325e5b0a9d Diff: http://reviews.gem5.org/r/3801/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3801: misc: fix building issue (undefined variables)
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3801/ --- (Updated Feb. 3, 2017, 10:02 a.m.) Review request for Default. Repository: gem5 Description --- Changeset 11808:e0730e1d7afa --- misc: fix building issue (undefined variables) Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Diffs (updated) - src/mem/comm_monitor.cc 63325e5b0a9d Diff: http://reviews.gem5.org/r/3801/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 3801: misc: fix building issue (undefined variables)
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3801/ --- Review request for Default. Repository: gem5 Description --- Changeset 11808:e0730e1d7afa --- misc: fix building issue (undefined variables) Signed-off-by: Pierre-Yves Péneau <first.l...@lirmm.fr> Diffs - src/mem/comm_monitor.cc 63325e5b0a9d Diff: http://reviews.gem5.org/r/3801/diff/ Testing --- Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3378: scons: make build better on FreeBSD
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3378/#review9357 --- Ship it! Ship It! - Pierre-Yves Péneau On Jan. 31, 2017, 2:44 p.m., Bjoern A. Zeeb wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3378/ > --- > > (Updated Jan. 31, 2017, 2:44 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > scons: make build better on FreeBSD > > Various changes we found needed to build gem5 successfully on > FreeBSD. > > > Diffs > - > > SConstruct e47703369039 > > Diff: http://reviews.gem5.org/r/3378/diff/ > > > Testing > --- > > > Thanks, > > Bjoern A. Zeeb > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3792: misc: Update #!env calls for python to explicit version
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3792/#review9346 --- Ship it! Ship It! - Pierre-Yves Péneau On Jan. 27, 2017, 6:32 p.m., Jason Lowe-Power wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3792/ > --- > > (Updated Jan. 27, 2017, 6:32 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > misc: Update #!env calls for python to explicit version > > In some newer Linux distributions, env python default to Python 3.0. This > patch explicitly uses "python2" instead of just "python" for all scripts > that use #! > > Reported-by: Sanchayan Maity <maitysancha...@gmail.com> > > > Diffs > - > > util/minorview.py cd7f3a1dbf55 > util/o3-pipeview.py cd7f3a1dbf55 > util/oprofile-top.py cd7f3a1dbf55 > util/pbs/job.py cd7f3a1dbf55 > util/pbs/send.py cd7f3a1dbf55 > util/protolib.py cd7f3a1dbf55 > util/qdo cd7f3a1dbf55 > util/regress cd7f3a1dbf55 > util/slicc cd7f3a1dbf55 > util/stats/stats.py cd7f3a1dbf55 > util/streamline/m5stats2streamline.py cd7f3a1dbf55 > util/style.py cd7f3a1dbf55 > util/style/__init__.py cd7f3a1dbf55 > util/style/repo.py cd7f3a1dbf55 > util/style/sort_includes.py cd7f3a1dbf55 > util/style/style.py cd7f3a1dbf55 > util/style/verifiers.py cd7f3a1dbf55 > util/maint/git-patch-to-hg-patch cd7f3a1dbf55 > util/memtest-soak.py cd7f3a1dbf55 > ext/mcpat/regression/regression.py cd7f3a1dbf55 > ext/mcpat/regression/verify_output.py cd7f3a1dbf55 > ext/ply/example/classcalc/calc.py cd7f3a1dbf55 > ext/ply/example/newclasscalc/calc.py cd7f3a1dbf55 > src/unittest/genini.py cd7f3a1dbf55 > tests/testing/__init__.py cd7f3a1dbf55 > tests/testing/helpers.py cd7f3a1dbf55 > tests/testing/results.py cd7f3a1dbf55 > tests/testing/tests.py cd7f3a1dbf55 > tests/testing/units.py cd7f3a1dbf55 > tests/tests.py cd7f3a1dbf55 > util/batch/job.py cd7f3a1dbf55 > util/batch/send.py cd7f3a1dbf55 > util/checkpoint-tester.py cd7f3a1dbf55 > util/compile cd7f3a1dbf55 > util/cpt_upgrader.py cd7f3a1dbf55 > util/decode_inst_dep_trace.py cd7f3a1dbf55 > util/decode_inst_trace.py cd7f3a1dbf55 > util/decode_packet_trace.py cd7f3a1dbf55 > util/dram_lat_mem_rd_plot.py cd7f3a1dbf55 > util/dram_sweep_plot.py cd7f3a1dbf55 > util/encode_inst_dep_trace.py cd7f3a1dbf55 > util/encode_packet_trace.py cd7f3a1dbf55 > util/find_copyrights.py cd7f3a1dbf55 > util/git-pre-commit.py cd7f3a1dbf55 > util/hgstyle.py cd7f3a1dbf55 > > Diff: http://reviews.gem5.org/r/3792/diff/ > > > Testing > --- > > gem5 compiles on arch with this patch and http://reviews.gem5.org/r/3779/. > > Testing done on arch docker image. See > https://hub.docker.com/r/powerjg/arch-dev/. > Run "docker run -v `pwd`:/gem5/ -it powerjg/arch-dev /bin/bash" to > build/run/test gem5. > > > Thanks, > > Jason Lowe-Power > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] [gem5-users] gem5 build failure
On 01/27/2017 02:42 PM, Andreas Sandberg wrote: > On 27/01/17 12:32, Pierre-Yves Péneau wrote: >> On 01/27/2017 01:20 PM, Andreas Sandberg wrote: >>> Hi Pierre, >>> >>> I send out an email to the dev list on the 12th of January (Header order >>> issues) describing a similar issue we have in our CI system. I have an >>> updated version of the style checker that enforces that Python.h is >>> included first and plan to post it after lunch. >> Oh, I didn't see this mail sorry. Problem solved then ! > > Could you have a look at RB3794 [1] and see if that solves your problem? > If it does, we should make sure to commit this change ASAP and update > the style guide. It works. Thank you ! > Cheers, > Andreas > > [1] http://reviews.gem5.org/r/3794/ > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy > the information in any medium. Thank you. > ___ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev -- +-+ | Pierre-Yves Péneau - PhD student | first.last at lirmm.fr | | LIRMM / CNRS - SYSMIC team |+ 33 4 67 41 86 33| | Building 4 Office H2.2 |http://walafc0.org| +-+ ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3794: style: Force Python.h to be included before main header
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3794/#review9332 --- Ship it! Ship It! - Pierre-Yves Péneau On Jan. 27, 2017, 2:39 p.m., Andreas Sandberg wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3794/ > --- > > (Updated Jan. 27, 2017, 2:39 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11803:1dba09aeeefd > --- > style: Force Python.h to be included before main header > > Python's header files set various compiler macros (e.g., > _XOPEN_SOURCE) unconditionally. This triggers preprocessor warnings > that end up being treated as errors. The style guide used to mandate > that Python headers are included before any other header. This > requirement was changed to always include a source file's main header > first, which ended up triggering these errors. > > This change updates the style checker to always include Python.h > before the main header file. > > Change-Id: Id6a4f7fc64a336a8fd26691a0ca682abeb1d1579 > Signed-off-by: Andreas Sandberg <andreas.sandb...@arm.com> > Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com> > > > Diffs > - > > src/python/swig/pyevent.cc be62996c95d1 > src/sim/init.cc be62996c95d1 > src/sim/py_interact.cc be62996c95d1 > util/style/sort_includes.py be62996c95d1 > > Diff: http://reviews.gem5.org/r/3794/diff/ > > > Testing > --- > > > Thanks, > > Andreas Sandberg > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] [gem5-users] gem5 build failure
On 01/27/2017 01:20 PM, Andreas Sandberg wrote: > Hi Pierre, > > I send out an email to the dev list on the 12th of January (Header order > issues) describing a similar issue we have in our CI system. I have an > updated version of the style checker that enforces that Python.h is > included first and plan to post it after lunch. Oh, I didn't see this mail sorry. Problem solved then ! > I would like to avoid including Python.h in header files unless > absolutely necessary. In general, we should try to keep dependencies > within header files as small as possible to avoid wasting time on > recompiling things. I agree. > Cheers, > Andreas > > > On 27/01/17 10:48, Pierre-Yves Péneau wrote: >> I think I have found why this is not working. With the new refactoring >> script, the header corresponding to the source file must be included >> first. But, when Python.h is needed, it also must be included first to >> avoid this error. >> >> So, I think there is two workaround: >> i) the refactoring script should check if Python.h is needed and if so, >> include it first and then include the header file. >> ii) move the Python.h inclusion in the header file. The second one is >> easier as it does not need to change the refactoring script. It also >> sounds better to me. >> >> I tried the second solution and it's working. What do you think ? >> >> On 01/26/2017 06:05 PM, Pierre-Yves Péneau wrote: >>> Hi all, >>> >>> I am trying to build the latest gem5 version and I get the error below. >>> >>>> $ scons /var/tmp/gem5-current/build/X86/gem5.fast >>> [snip] >>> >>>> [ CXX] X86/python/swig/pyevent.cc -> .fo >>>> In file included from /usr/include/python2.7/pyconfig.h:6:0, >>>> from /usr/include/python2.7/Python.h:8, >>>> from /var/tmp/gem5-current/build/X86/sim/init.hh:34, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:35, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >>>> /usr/include/python2.7/pyconfig-64.h:1182:0: error: >>>> "_POSIX_C_SOURCE" redefined [-Werror] >>>> #define _POSIX_C_SOURCE 200112L >>>> ^ >>>> In file included from >>>> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/os_defines.h:39:0, >>>> from >>>> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/c++config.h:2097, >>>> from /usr/include/c++/4.8.2/utility:68, >>>> from /usr/include/c++/4.8.2/algorithm:60, >>>> from >>>> /var/tmp/gem5-current/build/X86/sim/eventq.hh:41, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:34, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >>>> /usr/include/features.h:168:0: note: this is the location of the >>>> previous definition >>>> # define _POSIX_C_SOURCE 200809L >>>> ^ >>>> In file included from /usr/include/python2.7/pyconfig.h:6:0, >>>> from /usr/include/python2.7/Python.h:8, >>>> from /var/tmp/gem5-current/build/X86/sim/init.hh:34, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:35, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >>>> /usr/include/python2.7/pyconfig-64.h:1204:0: error: "_XOPEN_SOURCE" >>>> redefined [-Werror] >>>> #define _XOPEN_SOURCE 600 >>>> ^ >>>> In file included from >>>> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/os_defines.h:39:0, >>>> from >>>> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/c++config.h:2097, >>>> from /usr/include/c++/4.8.2/utility:68, >>>> from /usr/include/c++/4.8.2/algorithm:60, >>>> from >>>> /var/tmp/gem5-current/build/X86/sim/eventq.hh:41, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:34, >>>> from >>>> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >>>> /usr/include/features.h:170:0: note: this is the location of the >>>> previous definition >>>
Re: [gem5-dev] [gem5-users] gem5 build failure
I think I have found why this is not working. With the new refactoring script, the header corresponding to the source file must be included first. But, when Python.h is needed, it also must be included first to avoid this error. So, I think there is two workaround: i) the refactoring script should check if Python.h is needed and if so, include it first and then include the header file. ii) move the Python.h inclusion in the header file. The second one is easier as it does not need to change the refactoring script. It also sounds better to me. I tried the second solution and it's working. What do you think ? On 01/26/2017 06:05 PM, Pierre-Yves Péneau wrote: > Hi all, > > I am trying to build the latest gem5 version and I get the error below. > >> $ scons /var/tmp/gem5-current/build/X86/gem5.fast > > [snip] > >> [ CXX] X86/python/swig/pyevent.cc -> .fo >> In file included from /usr/include/python2.7/pyconfig.h:6:0, >> from /usr/include/python2.7/Python.h:8, >> from /var/tmp/gem5-current/build/X86/sim/init.hh:34, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:35, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >> /usr/include/python2.7/pyconfig-64.h:1182:0: error: "_POSIX_C_SOURCE" >> redefined [-Werror] >> #define _POSIX_C_SOURCE 200112L >> ^ >> In file included from >> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/os_defines.h:39:0, >> from >> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/c++config.h:2097, >> from /usr/include/c++/4.8.2/utility:68, >> from /usr/include/c++/4.8.2/algorithm:60, >> from /var/tmp/gem5-current/build/X86/sim/eventq.hh:41, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:34, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >> /usr/include/features.h:168:0: note: this is the location of the previous >> definition >> # define _POSIX_C_SOURCE 200809L >> ^ >> In file included from /usr/include/python2.7/pyconfig.h:6:0, >> from /usr/include/python2.7/Python.h:8, >> from /var/tmp/gem5-current/build/X86/sim/init.hh:34, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:35, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >> /usr/include/python2.7/pyconfig-64.h:1204:0: error: "_XOPEN_SOURCE" >> redefined [-Werror] >> #define _XOPEN_SOURCE 600 >> ^ >> In file included from >> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/os_defines.h:39:0, >> from >> /usr/include/c++/4.8.2/x86_64-redhat-linux/bits/c++config.h:2097, >> from /usr/include/c++/4.8.2/utility:68, >> from /usr/include/c++/4.8.2/algorithm:60, >> from /var/tmp/gem5-current/build/X86/sim/eventq.hh:41, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.hh:34, >> from >> /var/tmp/gem5-current/build/X86/python/swig/pyevent.cc:31: >> /usr/include/features.h:170:0: note: this is the location of the previous >> definition >> # define _XOPEN_SOURCE 700 >> ^ >> cc1plus: all warnings being treated as errors >> scons: *** [/var/tmp/gem5-current/build/X86/python/swig/pyevent.fo] Error 1 >> scons: building terminated because of errors. > > My last successful build before pulling the changes was in December. I > am using gcc-4.8.5 and python 2.7.5. It seems related to python and > variable redefinition. As far as I know, python 2.7 is supported by > gem5, only python 2.6 has been dropped few months ago. Host is CentOS > 7.2. Any idea of what's going on ? Thanks. > > > > ___ > gem5-users mailing list > gem5-us...@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- +-+ | Pierre-Yves Péneau - PhD student | first.last at lirmm.fr | | LIRMM / CNRS - SYSMIC team |+ 33 4 67 41 86 33| | Building 4 Office H2.2 |http://walafc0.org| +-+ ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3789: syscall_emul: #ifdef new system calls to allow builds on OSX and BSD
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3789/#review9289 --- Ship it! Ship It! - Pierre-Yves Péneau On Jan. 19, 2017, 7:28 p.m., Brandon Potter wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3789/ > --- > > (Updated Jan. 19, 2017, 7:28 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11795:54750ac27cf7 > --- > syscall_emul: #ifdef new system calls to allow builds on OSX and BSD > > > Diffs > - > > src/sim/syscall_emul.cc 97eebddaae84b4c0e555255375f283bbf653862a > src/sim/syscall_emul.hh 97eebddaae84b4c0e555255375f283bbf653862a > > Diff: http://reviews.gem5.org/r/3789/diff/ > > > Testing > --- > > > Thanks, > > Brandon Potter > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3708: commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3708/#review9190 --- Ship it! Ship It! - Pierre-Yves Péneau On Nov. 17, 2016, 9:02 p.m., Rahul Thakur wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3708/ > --- > > (Updated Nov. 17, 2016, 9:02 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11705:f55d4a414fa1 > --- > commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3 > Author: Rahul Thakur <rjtha...@google.com> > Date: Thu Oct 27 17:44:40 2016 -0700 > > mem: Add memory footprint probe > > Change-Id: I0fba8995edd63df4ef49969347be6d2aefceca9f > > > Diffs > - > > COPYING c38fcdaa5fe5 > configs/dram/lat_mem_rd.py c38fcdaa5fe5 > src/mem/probes/MemFootprintProbe.py PRE-CREATION > src/mem/probes/SConscript c38fcdaa5fe5 > src/mem/probes/mem_footprint.hh PRE-CREATION > src/mem/probes/mem_footprint.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/3708/diff/ > > > Testing > --- > > > Thanks, > > Rahul Thakur > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3740: commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3740/#review9148 --- Ship it! Ship It! - Pierre-Yves Péneau On Nov. 21, 2016, 8:03 p.m., Rahul Thakur wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3740/ > --- > > (Updated Nov. 21, 2016, 8:03 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11708:33c0089caa50 > --- > commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60 > Author: Rahul Thakur <rjtha...@google.com> > Date: Thu Oct 27 20:36:16 2016 -0700 > > mem: Refactor CommMonitor stats, add basic atomic mode stats > > Change-Id: I978f1155873b3882e16d9cd74e86400efd9c5e3b > > > Diffs > - > > src/mem/comm_monitor.hh 1d085f66c4ca > src/mem/comm_monitor.cc 1d085f66c4ca > > Diff: http://reviews.gem5.org/r/3740/diff/ > > > Testing > --- > > > Thanks, > > Rahul Thakur > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Base cpu modification
Hi all, I would like to add a new hardware component in gem5. This component will be at the same level than L1 caches. I am planning to modify the base cpu to add a new port and use it to communicate with my component. Eventually, I would like to share my work with the gem5 community. Louisa Bessad (from my lab) had a discussion with Gabor Dozsa from ARM and told me that any modification to the base cpu must be strongly justified to the developers, and so could be very hard to merge in gem5. So, my questions are: - can I do what I want without modifying the base cpu ? - if not, what are the chances that my work will be accepted ? Thank you all. -- +-+ | Pierre-Yves Péneau - PhD student | first.last at lirmm.fr | | LIRMM / CNRS - SYSMIC team |+ 33 4 67 41 86 33| | Building 4 Office H2.2 |http://walafc0.org| +-+ ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3666: arm, config: added support for ex5 model of big.LITTLE
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3666/#review8979 --- Ship it! Ship It! - Pierre-Yves Péneau On Oct. 20, 2016, 6:39 p.m., Anastasiia Butko wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3666/ > --- > > (Updated Oct. 20, 2016, 6:39 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11687:b3946ea8b081 > --- > arm, config: added support for ex5 model of big.LITTLE > > This patch enables using calibrated big and LITTLE > cores, ex5_big and ex5_LITTLE instead of the default > 'arm_detailed' and 'minor' cpus. The ex5 model is based > on the Samsung Exynos 5 Octa (5422) SoC. Operation and > memory hierarchy latencies have been calibrated using the > lmbench micro-benchmark suite. The preliminary validation > results have been published as: > 'Full-System Simulation of big.LITTLE Multicore Architecture > for Performance and Energy Exploration', in International > Symposium on Embedded Multicore/Many-core Systems-on-Chip > (MCSoC'16), Lyon, France (Sep, 2016). > > Reported-by: Anastasiia Butko <abu...@lbl.gov> > > > Diffs > - > > configs/common/CpuConfig.py 4a86763c0b30 > configs/common/ex5_LITTLE.py PRE-CREATION > configs/common/ex5_big.py PRE-CREATION > configs/example/arm/fs_bigLITTLE.py 4a86763c0b30 > > Diff: http://reviews.gem5.org/r/3666/diff/ > > > Testing > --- > > > Thanks, > > Anastasiia Butko > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency
> On Oct. 21, 2016, 3:29 p.m., Pierre-Yves Péneau wrote: > > Hi, > > > > Someone can commit this patch ? I don't have right access on the > > repository, either Sophiane. > > Thank you. > > Jason Lowe-Power wrote: > Sorry we've been so slow on this patch. A couple of questions before I > commit. > > 1. Are all of Andreas H.'s comments resolved? I'd like to see a "Ship It" > from him. > 2. You need to make sure the regressions are passing. I understand that > our regression testing is poor, but I know that the learning_gem5 regression > is failing because of this patch. The file > configs/learning_gem5/part1/caches.py needs to be updated. There are likely > other files that need to be updated as well (configs/examples/arm/devices.py > comes to mind, there may be others). 1. Sophiane answered to Andreas H.' issues but I did not respond (quote: "Please go ahead with the patch as is"). I assume it's ok even without a "Ship It" from him. 2. Regression tests have been done. Failures are due to missing CPU2000 benchmarks. The review will be update soon. - Pierre-Yves --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3502/#review8960 --- On July 28, 2016, 12:31 p.m., Sophiane SENNI wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3502/ > --- > > (Updated July 28, 2016, 12:31 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11536:1a3a96d435ed > --- > mem: Split the hit_latency into tag_latency and data_latency > > If the cache access mode is parallel, i.e. "sequential_access" parameter > is set to "False", tags and data are accessed in parallel. Therefore, > the hit_latency is the maximum latency between tag_latency and > data_latency. On the other hand, if the cache access mode is > sequential, i.e. "sequential_access" parameter is set to "True", > tags and data are accessed sequentially. Therefore, the hit_latency > is the sum of tag_latency plus data_latency. > > > Diffs > - > > configs/common/Caches.py 4aac82f109517217e6bfb3812689280e7a8fa842 > configs/common/O3_ARM_v7a.py 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/Cache.py 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/Tags.py 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/base_set_assoc.hh > 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/fa_lru.cc 4aac82f109517217e6bfb3812689280e7a8fa842 > > Diff: http://reviews.gem5.org/r/3502/diff/ > > > Testing > --- > > Tested using --Debug-flags=Cache > > > Thanks, > > Sophiane SENNI > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3502/#review8960 --- Hi, Someone can commit this patch ? I don't have right access on the repository, either Sophiane. Thank you. - Pierre-Yves Péneau On July 28, 2016, 12:31 p.m., Sophiane SENNI wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3502/ > --- > > (Updated July 28, 2016, 12:31 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11536:1a3a96d435ed > --- > mem: Split the hit_latency into tag_latency and data_latency > > If the cache access mode is parallel, i.e. "sequential_access" parameter > is set to "False", tags and data are accessed in parallel. Therefore, > the hit_latency is the maximum latency between tag_latency and > data_latency. On the other hand, if the cache access mode is > sequential, i.e. "sequential_access" parameter is set to "True", > tags and data are accessed sequentially. Therefore, the hit_latency > is the sum of tag_latency plus data_latency. > > > Diffs > - > > configs/common/Caches.py 4aac82f109517217e6bfb3812689280e7a8fa842 > configs/common/O3_ARM_v7a.py 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/Cache.py 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/Tags.py 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/base_set_assoc.hh > 4aac82f109517217e6bfb3812689280e7a8fa842 > src/mem/cache/tags/fa_lru.cc 4aac82f109517217e6bfb3812689280e7a8fa842 > > Diff: http://reviews.gem5.org/r/3502/diff/ > > > Testing > --- > > Tested using --Debug-flags=Cache > > > Thanks, > > Sophiane SENNI > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3665: arm, config: Enabled MemConfig usage for the example big.LITTLE
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3665/#review --- Ship it! Ship It! - Pierre-Yves Péneau On Oct. 18, 2016, 5:43 a.m., Anastasiia Butko wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3665/ > --- > > (Updated Oct. 18, 2016, 5:43 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11670:e69eb8bb1e2c > --- > arm, config: Enabled MemConfig usage for the example big.LITTLE > > This patch replaces the SimpleMemory with the MemConfig > function. Additional parser arguments are added > (TODO: improve with addCommonOptions & addFSOptions). > > Reported-by: Anastasiia Butko <abu...@lbl.gov> > > > Diffs > - > > configs/example/arm/fs_bigLITTLE.py 220fa4099b9a > > Diff: http://reviews.gem5.org/r/3665/diff/ > > > Testing > --- > > > Thanks, > > Anastasiia Butko > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Stable release
I am glad to see that my email leads to quick response and action :-) Thank you all. On 10/07/2016 04:04 PM, Jason Lowe-Power wrote: > Thanks for getting back to me everyone. I'm going to send out a message to > gem5-users to make sure there are no other objections. If there's nothing > in about a week, we should shut down gem5-stable. > > Who knows how to do this / has the access to do it? I don't. > > Thanks, > Jason > > On Mon, Oct 3, 2016 at 5:59 AM Andreas Sandberg <andreas.sandb...@arm.com> > wrote: > >> +1 for #1 from me as well. >> >> Ideally, I’d like to see #3, but I don’t think we can make that work at >> the moment. >> >> //Andreas >> >> On 03/10/2016, 01:06, "gem5-dev on behalf of Steve Reinhardt" < >> gem5-dev-boun...@gem5.org<mailto:gem5-dev-boun...@gem5.org> on behalf of >> ste...@gmail.com<mailto:ste...@gmail.com>> wrote: >> >> I agree with #1. The existence of gem5-stable is just confusing, since we >> don't have a good process to keep it up-to-date. >> >> Steve >> >> >> On Fri, Sep 30, 2016 at 8:56 AM Beckmann, Brad <brad.beckm...@amd.com >> <mailto:brad.beckm...@amd.com>> >> wrote: >> >> I strongly support 1 as well. >> >> Brad >> >> >> -Original Message- >> From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andreas >> Hansson >> Sent: Friday, September 30, 2016 7:03 AM >> To: gem5 Developer List <gem5-dev@gem5.org<mailto:gem5-dev@gem5.org>> >> Subject: Re: [gem5-dev] Stable release >> >> Hi Jason, >> >> I support 1 for now (based on example the argument you mention). Once we >> have moved to git we can reconsider. >> >> Andreas >> >> On 30/09/2016, 15:00, "gem5-dev on behalf of Jason Lowe-Power" >> <gem5-dev-boun...@gem5.org<mailto:gem5-dev-boun...@gem5.org> on behalf of >> ja...@lowepower.com<mailto:ja...@lowepower.com>> wrote: >> >>> Thanks for bringing this up. It's been a long time since we've >>> discussed gem5-stable on the mailing list. >>> >>> I propose that we come up with a few options on what we, as a >>> community, want to do with gem5-stable, vote on them, and then stick to >> our decision. >>> Below is what I see are the options. If anyone else has other ideas, >>> please chime in! >>> >>> 1. Get rid of gem5-stable. >>> 2. Continue with the previous approach of tagging gem5 every quarter >>> and releasing a gem5-stable branch. >>> 3. Develop a process of milestones and release after each milestone is >>> complete. Between milestone releases, we can backport bugfixes into >>> gem5-stable. >>> >>> My opinions: >>> 1. gem5-stable is no more bug-free than gem5-dev. It's only "stable" in >>> the sense that we never commit to it. *I think this is what we should >>> do for >>> now.* >>> 2. I don't think that the previous gem5-stable approach of tagging gem5 >>> quarterly provides any added benefit. Users can just as easily clone >>> gem5-dev and just not update if they want a "stable" platform. That's >>> all gem5-stable was anyway. >>> 3. I think having milestones and true "releases" would be the best >>> thing we can do. However, I don't think we are currently at a place >>> where we can implement this. If I'm wrong, and someone in the community >>> wants to step up and take this responsibility, I think it would really >>> benefit our users. >>> >>> What do other's think? >>> >>> Cheers, >>> Jason >>> >>> >>> >>> On Fri, Sep 30, 2016 at 4:24 AM Pierre-Yves Péneau < >>> pierre-yves.pen...@lirmm.fr<mailto:pierre-yves.pen...@lirmm.fr>> wrote: >>> >>>> Hi all, >>>> >>>> Since September 2015, gem5 has no stable version. However, a high >>>> activity has been observed this year, and a lot of major features >>>> have been added (big.LITTLE support, power modeling, new GPUs, >>>> ElasticTraces etc..). I am wondering if there is any plan to release >>>> a new stable version in the next weeks/months ? >>>> >>>> Thank you. >>>> >>>> -- >>>> +-+ >>>> | Pierre-Yves Péneau - PhD student | first.last at lirmm.fr | >>>> | LIRMM / CNRS - SYSMIC team |
[gem5-dev] Stable release
Hi all, Since September 2015, gem5 has no stable version. However, a high activity has been observed this year, and a lot of major features have been added (big.LITTLE support, power modeling, new GPUs, ElasticTraces etc..). I am wondering if there is any plan to release a new stable version in the next weeks/months ? Thank you. -- +-+ | Pierre-Yves Péneau - PhD student | first.last at lirmm.fr | | LIRMM / CNRS - SYSMIC team |+ 33 4 67 41 86 33| | Building 4 Office H2.2 |http://walafc0.org| +-+ ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3502/#review8527 --- Ship it! Ship It! - Pierre-Yves Péneau On July 25, 2016, 3:16 p.m., Sophiane SENNI wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3502/ > --- > > (Updated July 25, 2016, 3:16 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11536:1a3a96d435ed > --- > mem: Split the hit_latency into tag_latency and data_latency > > If the cache access mode is parallel, i.e. "sequential_access" parameter > is set to "False", tags and data are accessed in parallel. Therefore, > the hit_latency is the maximum latency between tag_latency and > data_latency. On the other hand, if the cache access mode is > sequential, i.e. "sequential_access" parameter is set to "True", > tags and data are accessed sequentially. Therefore, the hit_latency > is the sum of tag_latency plus data_latency. > > > Diffs > - > > src/mem/cache/tags/fa_lru.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > configs/common/Caches.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/Cache.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/base.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/Tags.py 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/base.hh 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/base.cc 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > src/mem/cache/tags/base_set_assoc.hh > 80e79ae636ca6b021cbf7aa985b5fd56cb5b2708 > > Diff: http://reviews.gem5.org/r/3502/diff/ > > > Testing > --- > > Tested using --Debug-flags=Cache > > > Thanks, > > Sophiane SENNI > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3502: cache: Split the hit latency into tag lookup latency and RAM access latency
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/#review8419
---
I don't like the variable names, I think it's confusing especially in the
Python part which is the user part. "lookup_latency" does not clearly refer to
the tag lookup action , and "ram_latency" is also not very clear. Maybe
something like "tag_latency" and "line_latency" could be better ? I think the
two parts of a cache are well identified in this example.
- Pierre-Yves Péneau
On June 16, 2016, 8:55 p.m., Sophiane SENNI wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> ---
>
> (Updated June 16, 2016, 8:55 p.m.)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> ---
>
> Changeset 11536:1a3a96d435ed
> ---
> cache: Split the hit latency into tag lookup latency and RAM access latency
>
> If the cache access mode is parallel ("sequential_access" parameter set to
> "False"), tags and RAMs are accessed in parallel. Therefore, the hit latency
> is the maximum latency between tag lookup latency and RAM access latency. On
> the other hand, if the cache access mode is sequential ("sequential_access"
> parameter set to "True"), tags and RAM are accessed sequentially. Therefore,
> the hit latency is the sum of tag lookup latency plus RAM access latency.
>
>
> Diffs
> -
>
> src/mem/cache/tags/fa_lru.hh 80e79ae636ca
> src/mem/cache/tags/base.cc 80e79ae636ca
> src/mem/cache/tags/Tags.py 80e79ae636ca
> src/mem/cache/tags/fa_lru.cc 80e79ae636ca
> src/mem/cache/tags/base_set_assoc.hh 80e79ae636ca
> src/mem/cache/tags/base.hh 80e79ae636ca
> configs/common/Caches.py 80e79ae636ca
> src/mem/cache/Cache.py 80e79ae636ca
> src/mem/cache/base.hh 80e79ae636ca
> src/mem/cache/base.cc 80e79ae636ca
>
> Diff: http://reviews.gem5.org/r/3502/diff/
>
>
> Testing
> ---
>
> Tested using --Debug-flags=Cache
>
>
> Thanks,
>
> Sophiane SENNI
>
>
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Re: [gem5-dev] Review Request 3454: misc: Appease clang-3.4.1
> On April 26, 2016, 10:54 p.m., Bjoern A. Zeeb wrote:
> > This was fixed in HEAD after I noticed that we aren't spec compliant; but
> > older versions indeed need the cast.
> >
> > I am currently using at least an #ifdef here:
> >
> > --- a/src/sim/init_signals.cc Tue Apr 05 08:08:12 2016 -0500
> > +++ b/src/sim/init_signals.cc Tue Apr 26 20:51:26 2016 +
> > @@ -66,7 +66,11 @@
> > setupAltStack()
> > {
> > stack_t stack;
> > +#ifdef __FreeBSD__
> > +stack.ss_sp = (char *)fatalSigStack;
> > +#else
> > stack.ss_sp = fatalSigStack;
> > +#endif
> > stack.ss_size = sizeof(fatalSigStack);
> > stack.ss_flags = 0;
> >
> > But for the FreeBSD block we almost also need to check __FreeBSD_version >=
> > 11xx but I haven't done the due diligence yet what the exact version
> > number should be.
>
> Bjoern A. Zeeb wrote:
> https://svnweb.freebsd.org/base?view=revision=294930
>
> PS: this has nothing to do with clang really.
Where was it fixed ? There is no changes in HEAD in init_signals.cc
BTW, I am using HEAD.
- Pierre-Yves
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3454/#review8274
---
On April 26, 2016, 8:02 p.m., Pierre-Yves Péneau wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3454/
> ---
>
> (Updated April 26, 2016, 8:02 p.m.)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> ---
>
> Appease clang-3.4.1
>
>
> Diffs
> -
>
> src/sim/init_signals.cc e41eca4aecbb
>
> Diff: http://reviews.gem5.org/r/3454/diff/
>
>
> Testing
> ---
>
> Fresh install of FreeBSD 10.3-RELEASE (i386), default clang compiler (3.4.1)
>
>
> Thanks,
>
> Pierre-Yves Péneau
>
>
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Re: [gem5-dev] Review Request 3454: misc: Appease clang-3.4.1
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3454/ --- (Updated April 26, 2016, 8:02 p.m.) Review request for Default. Summary (updated) - misc: Appease clang-3.4.1 Repository: gem5 Description (updated) --- Appease clang-3.4.1 Diffs - src/sim/init_signals.cc e41eca4aecbb Diff: http://reviews.gem5.org/r/3454/diff/ Testing --- Fresh install of FreeBSD 10.3-RELEASE (i386), default clang compiler (3.4.1) Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 3454:
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3454/ --- Review request for Default. Repository: gem5 Description --- Diffs (updated) - src/sim/init_signals.cc e41eca4aecbb Diff: http://reviews.gem5.org/r/3454/diff/ Testing --- Fresh install of FreeBSD 10.3-RELEASE (i386), default clang compiler (3.4.1) Thanks, Pierre-Yves Péneau ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] HMC controler breaks FS mode
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Dear all, It seems that the recent commits related to the new HMC interconnect cause a bug. Given a fresh clone of the gem5 repository, and a classic build [1], I cannot launch a full system simulation. I have to get back to 11182:fa8b2a99d4fe to have a working FS simulation. Here the log: gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Nov 4 2015 15:05:02 gem5 started Nov 4 2015 15:05:47 gem5 executing on jaguar.lirmm.fr, pid 56538 command line: ./build/ARM/gem5.opt configs/example/fs.py Traceback (most recent call last): File "", line 1, in File "/tmp/gem5/src/python/m5/main.py", line 389, in main exec filecode in scope File "configs/example/fs.py", line 55, in import Ruby File "/tmp/gem5/configs/ruby/Ruby.py", line 48, in import MemConfig File "/tmp/gem5/configs/common/MemConfig.py", line 42, in import HMC File "/tmp/gem5/configs/common/HMC.py", line 87, in class HMCSystem(SimOject): NameError: name 'SimOject' is not defined Best regards, [1] scons build/ARM/gem5.opt - -- +----------+ | Pierre-Yves Péneau| first.last at lirmm.fr | | PhD student - LIRMM - Sysmic |+ 33 4 67 41 85 85| | Bâtiment 4 Bureau H2.2|http://walafc0.org| +--+ -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQIcBAEBAgAGBQJWOhMhAAoJEPy7VC2L9m/AaIMP+wTmnyIDhsyBqMZLk8Be7OB0 B9HssZCd4qEuMrxcVVNvKuY77qftHkido4O4Sa/bsrCWFQa7proNKhPi1hbqBp48 qfQ2ZFYWJR/ZY10gSEh86x4WwC76GVMKT2QkWwUHS6P7oOU1PcKdoLlOvQjtlX9z Y3MmcGArZWDkNl1ut/4I1MnlIJiAC0On0FNWUBCQqwlg//NvleIpYJuhYXF3ZbOS 8DgV7lo0zbkeLCzuo4fuKLR/xQppxHsXOpI8Ma2g4YAbtcdk3roEpdRhmz6iQN7U tRTvaVwNSsSv1MpTMRLT6q24YlKazaI9vqA7ppwfg55EwYJDn6IiFTbtu6Xcr9rA d7KJEjXR4RXxSF0XAM/sPutMpWC8wfcNWoabnPQ0PYLCrZY3gob6Ua0hZJE5ZmON VJa9ut5EmjGn1Q7t6gIy9jVQHi2hcCuLPT69pzDd6S+3cE7Tciyj/lhLxxihS8sM j7CxYbpNWLOhaxnQEfLJdj50ijJrag4b5aTklnuAdE24JfkRtuTVWINCWnpDebbE 6GravJYbH33GN5Aq4d8m7PpuN2qxElN4poWkgmiOGMUiDyGz3eOv3RKvAcDX3nCP DFZYRAQErHru4U8SjeQW5dpVWuJaDXM/3KvHF7eJ4i1suS3JhYGvvZB6GDlCPuWQ VVeBeAJaBnCiwsXRLufO =drIG -END PGP SIGNATURE- ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
