[m5-dev] Cron [EMAIL PROTECTED] /z/m5/regression/do-regression quick
See /z/m5/regression/regress-2008-09-27-03:00:01 for details. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: add a bit of style
changeset 78b95c17a14c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=78b95c17a14c
description:
add a bit of style
diffstat:
2 files changed, 1 insertion(+), 3 deletions(-)
src/base/fast_alloc.cc |1 -
src/base/fast_alloc.hh |3 +--
diffs (208 lines):
diff -r 4c4b5dfc9944 -r 78b95c17a14c src/base/fast_alloc.cc
--- a/src/base/fast_alloc.ccFri Sep 26 09:37:21 2008 -0700
+++ b/src/base/fast_alloc.ccSat Sep 27 00:15:45 2008 -0700
@@ -34,7 +34,8 @@
* by permission.
*/
-#include assert.h
+#include cassert
+
#include base/fast_alloc.hh
#if !NO_FAST_ALLOC
@@ -51,7 +52,8 @@
unsigned FastAlloc::allocCount[Num_Buckets];
#endif
-void *FastAlloc::moreStructs(int bucket)
+void *
+FastAlloc::moreStructs(int bucket)
{
assert(bucket 0 bucket Num_Buckets);
@@ -71,14 +73,13 @@
return (p + sz);
}
-
#if FAST_ALLOC_DEBUG
-#include typeinfo
+#include iomanip
#include iostream
-#include iomanip
#include map
#include string
+#include typeinfo
using namespace std;
@@ -96,7 +97,6 @@
inUsePrev = prev;
inUseNext = next;
}
-
// constructor: marks as in use, add to in-use list
FastAlloc::FastAlloc()
@@ -131,7 +131,6 @@
inUseNext-inUsePrev = inUsePrev;
}
-
// summarize in-use list
void
FastAlloc::dump_summary()
@@ -148,11 +147,8 @@
cout count type\n
- \n;
for (mapiter = typemap.begin(); mapiter != typemap.end(); ++mapiter)
-{
cout setw(6) mapiter-second mapiter-first endl;
-}
}
-
// show oldest n items on in-use list
void
@@ -160,8 +156,7 @@
{
// sanity check: don't want to crash the debugger if you forget to
// pass in a parameter
-if (n 0 || n numInUse)
-{
+if (n 0 || n numInUse) {
cout FastAlloc::dump_oldest: bad arg n
( numInUse objects in use endl;
return;
@@ -170,11 +165,8 @@
for (FastAlloc *p = inUseHead.inUseNext;
p != inUseHead n 0;
p = p-inUseNext, --n)
-{
cout p typeid(*p).name() endl;
-}
}
-
//
// C interfaces to FastAlloc::dump_summary() and FastAlloc::dump_oldest().
@@ -192,6 +184,6 @@
FastAlloc::dump_oldest(n);
}
-#endif
+#endif // FAST_ALLOC_DEBUG
#endif // NO_FAST_ALLOC
diff -r 4c4b5dfc9944 -r 78b95c17a14c src/base/fast_alloc.hh
--- a/src/base/fast_alloc.hhFri Sep 26 09:37:21 2008 -0700
+++ b/src/base/fast_alloc.hhSat Sep 27 00:15:45 2008 -0700
@@ -34,10 +34,10 @@
* by permission.
*/
-#ifndef __FAST_ALLOC_H__
-#define __FAST_ALLOC_H__
+#ifndef __BASE_FAST_ALLOC_HH__
+#define __BASE_FAST_ALLOC_HH__
-#include stddef.h
+#include cstddef
// Fast structure allocator. Designed for small objects that are
// frequently allocated and deallocated. This code is derived from the
@@ -68,14 +68,15 @@
#if NO_FAST_ALLOC
-class FastAlloc {
+class FastAlloc
+{
};
#else
-class FastAlloc {
+class FastAlloc
+{
public:
-
static void *allocate(size_t);
static void deallocate(void *, size_t);
@@ -84,7 +85,7 @@
#if FAST_ALLOC_DEBUG
FastAlloc();
-FastAlloc(FastAlloc*,FastAlloc*); // for inUseHead, see below
+FastAlloc(FastAlloc *, FastAlloc *); // for inUseHead, see below
virtual ~FastAlloc();
#else
virtual ~FastAlloc() {}
@@ -139,16 +140,14 @@
#endif
};
-
-inline
-int FastAlloc::bucketFor(size_t sz)
+inline int
+FastAlloc::bucketFor(size_t sz)
{
return (sz + Alloc_Quantum - 1) Log2_Alloc_Quantum;
}
-
-inline
-void *FastAlloc::allocate(size_t sz)
+inline void *
+FastAlloc::allocate(size_t sz)
{
int b;
void *p;
@@ -171,14 +170,12 @@
return p;
}
-
-inline
-void FastAlloc::deallocate(void *p, size_t sz)
+inline void
+FastAlloc::deallocate(void *p, size_t sz)
{
int b;
-if (sz Max_Alloc_Size)
-{
+if (sz Max_Alloc_Size) {
::delete [] (char *)p;
return;
}
@@ -191,20 +188,18 @@
#endif
}
-
-inline
-void *FastAlloc::operator new(size_t sz)
+inline void *
+FastAlloc::operator new(size_t sz)
{
return allocate(sz);
}
-
-inline
-void FastAlloc::operator delete(void *p, size_t sz)
+inline void
+FastAlloc::operator delete(void *p, size_t sz)
{
deallocate(p, sz);
}
#endif // NO_FAST_ALLOC
-#endif // __FAST_ALLOC_H__
+#endif // __BASE_FAST_ALLOC_HH__
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[m5-dev] changeset in m5: arch: TheISA shouldn't really ever be used in t...
changeset 8fc3b004b0df in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8fc3b004b0df
description:
arch: TheISA shouldn't really ever be used in the arch directory.
We should always refer to the specific ISA in that arch directory.
This is especially necessary if we're ever going to make it to the
point where we actually have heterogeneous systems.
diffstat:
3 files changed, 2 insertions(+), 3 deletions(-)
src/arch/alpha/ev5.cc |2 +-
src/arch/sparc/regfile.cc |2 +-
src/arch/x86/process.cc |1 -
diffs (truncated from 365 to 300 lines):
diff -r 3440c9ad49b4 -r 8fc3b004b0df src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sat Sep 27 21:03:45 2008 -0700
+++ b/src/arch/alpha/ev5.cc Sat Sep 27 21:03:46 2008 -0700
@@ -383,10 +383,10 @@
#if FULL_SYSTEM
if (val 0x18) {
if (tc-getKernelStats())
-tc-getKernelStats()-mode(TheISA::Kernel::user, tc);
+tc-getKernelStats()-mode(AlphaISA::Kernel::user, tc);
} else {
if (tc-getKernelStats())
-tc-getKernelStats()-mode(TheISA::Kernel::kernel, tc);
+tc-getKernelStats()-mode(AlphaISA::Kernel::kernel, tc);
}
#endif
diff -r 3440c9ad49b4 -r 8fc3b004b0df src/arch/alpha/idle_event.cc
--- a/src/arch/alpha/idle_event.cc Sat Sep 27 21:03:45 2008 -0700
+++ b/src/arch/alpha/idle_event.cc Sat Sep 27 21:03:46 2008 -0700
@@ -33,7 +33,7 @@
#include arch/alpha/kernel_stats.hh
#include cpu/thread_context.hh
-using namespace TheISA;
+using namespace AlphaISA;
void
IdleStartEvent::process(ThreadContext *tc)
diff -r 3440c9ad49b4 -r 8fc3b004b0df src/arch/alpha/interrupts.hh
--- a/src/arch/alpha/interrupts.hh Sat Sep 27 21:03:45 2008 -0700
+++ b/src/arch/alpha/interrupts.hh Sat Sep 27 21:03:46 2008 -0700
@@ -78,7 +78,7 @@
{
DPRINTF(Interrupt, Interrupt %d:%d cleared\n, int_num, index);
-if (int_num 0 || int_num = TheISA::NumInterruptLevels)
+if (int_num 0 || int_num = AlphaISA::NumInterruptLevels)
panic(int_num out of bounds\n);
if (index 0 || index = (int)sizeof(uint64_t) * 8)
diff -r 3440c9ad49b4 -r 8fc3b004b0df src/arch/alpha/linux/threadinfo.hh
--- a/src/arch/alpha/linux/threadinfo.hhSat Sep 27 21:03:45 2008 -0700
+++ b/src/arch/alpha/linux/threadinfo.hhSat Sep 27 21:03:46 2008 -0700
@@ -55,7 +55,7 @@
CopyOut(tc, data, addr, sizeof(T));
-data = TheISA::gtoh(data);
+data = AlphaISA::gtoh(data);
return true;
}
@@ -76,7 +76,7 @@
Addr sp;
if (!addr)
-addr = tc-readMiscRegNoEffect(TheISA::IPR_PALtemp23);
+addr = tc-readMiscRegNoEffect(AlphaISA::IPR_PALtemp23);
FunctionalPort *p = tc-getPhysPort();
p-readBlob(addr, (uint8_t *)sp, sizeof(Addr));
diff -r 3440c9ad49b4 -r 8fc3b004b0df src/arch/alpha/regfile.cc
--- a/src/arch/alpha/regfile.cc Sat Sep 27 21:03:45 2008 -0700
+++ b/src/arch/alpha/regfile.cc Sat Sep 27 21:03:46 2008 -0700
@@ -70,7 +70,7 @@
}
// Then loop through the floating point registers.
-for (int i = 0; i TheISA::NumFloatRegs; ++i) {
+for (int i = 0; i AlphaISA::NumFloatRegs; ++i) {
dest-setFloatRegBits(i, src-readFloatRegBits(i));
}
diff -r 3440c9ad49b4 -r 8fc3b004b0df src/arch/alpha/remote_gdb.cc
--- a/src/arch/alpha/remote_gdb.cc Sat Sep 27 21:03:45 2008 -0700
+++ b/src/arch/alpha/remote_gdb.cc Sat Sep 27 21:03:46 2008 -0700
@@ -140,7 +140,7 @@
#include sim/system.hh
using namespace std;
-using namespace TheISA;
+using namespace AlphaISA;
RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
: BaseRemoteGDB(_system, c, KGDB_NUMREGS)
@@ -161,12 +161,12 @@
#else
Addr last_va;
-va = TheISA::TruncPage(va);
-last_va = TheISA::RoundPage(va + len);
+va = AlphaISA::TruncPage(va);
+last_va = AlphaISA::RoundPage(va + len);
do {
-if (TheISA::IsK0Seg(va)) {
-if (va (TheISA::K0SegBase + pmem-size())) {
+if (AlphaISA::IsK0Seg(va)) {
+if (va (AlphaISA::K0SegBase + pmem-size())) {
DPRINTF(GDBAcc, acc: Mapping is valid K0SEG =
%#x K0SEG + size\n, va);
return true;
@@ -188,12 +188,12 @@
return true;
Addr ptbr = context-readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
-TheISA::PageTableEntry pte =
TheISA::kernel_pte_lookup(context-getPhysPort(), ptbr, va);
+AlphaISA::PageTableEntry pte =
AlphaISA::kernel_pte_lookup(context-getPhysPort(), ptbr, va);
if (!pte.valid()) {
DPRINTF(GDBAcc, acc: %#x pte is invalid\n, va);
return false;
}
-va += TheISA::PageBytes;
+va += AlphaISA::PageBytes;
} while (va last_va);
DPRINTF(GDBAcc, acc: %#x mapping is valid\n, va);
@@
[m5-dev] changeset in m5: alpha: Clean up namespace usage.
changeset d14250d688d2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d14250d688d2
description:
alpha: Clean up namespace usage.
diffstat:
11 files changed, 12 insertions(+), 15 deletions(-)
src/arch/alpha/ev5.hh|1 -
src/arch/alpha/faults.cc |2 +-
src/arch/alpha/faults.hh |2 +-
src/arch/alpha/intregfile.cc |2 +-
src/arch/alpha/isa/main.isa |2 +-
src/arch/alpha/pagetable.hh |2 +-
src/arch/alpha/remote_gdb.cc |4 ++--
src/arch/alpha/stacktrace.hh |1 -
src/arch/alpha/system.cc |1 -
src/arch/alpha/tlb.hh|1 -
src/arch/alpha/vtophys.cc|9 +
diffs (truncated from 1356 to 300 lines):
diff -r 8fc3b004b0df -r d14250d688d2 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sat Sep 27 21:03:46 2008 -0700
+++ b/src/arch/alpha/ev5.cc Sat Sep 27 21:03:47 2008 -0700
@@ -44,7 +44,7 @@
#include sim/debug.hh
#include sim/sim_exit.hh
-using namespace AlphaISA;
+namespace AlphaISA {
#if FULL_SYSTEM
@@ -53,14 +53,14 @@
// Machine dependent functions
//
void
-AlphaISA::initCPU(ThreadContext *tc, int cpuId)
+initCPU(ThreadContext *tc, int cpuId)
{
initIPRs(tc, cpuId);
tc-setIntReg(16, cpuId);
tc-setIntReg(0, cpuId);
-AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
+AlphaFault *reset = new ResetFault;
tc-setPC(tc-readMiscRegNoEffect(IPR_PAL_BASE) + reset-vect());
tc-setNextPC(tc-readPC() + sizeof(MachInst));
@@ -71,7 +71,7 @@
template class CPU
void
-AlphaISA::processInterrupts(CPU *cpu)
+processInterrupts(CPU *cpu)
{
//Check if there are any outstanding interrupts
//Handle the interrupts
@@ -117,7 +117,7 @@
template class CPU
void
-AlphaISA::zeroRegisters(CPU *cpu)
+zeroRegisters(CPU *cpu)
{
// Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the
@@ -126,33 +126,16 @@
cpu-thread-setFloatReg(ZeroReg, 0.0);
}
-Fault
-SimpleThread::hwrei()
+int
+MiscRegFile::getInstAsid()
{
-if (!(readPC() 0x3))
-return new UnimplementedOpcodeFault;
-
-setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
-
-if (!misspeculating()) {
-if (kernelStats)
-kernelStats-hwrei();
-}
-
-// FIXME: XXX check for interrupts? XXX
-return NoFault;
+return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
-AlphaISA::MiscRegFile::getInstAsid()
+MiscRegFile::getDataAsid()
{
-return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-AlphaISA::MiscRegFile::getDataAsid()
-{
-return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
#endif
@@ -162,90 +145,90 @@
//
//
void
-AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
+initIPRs(ThreadContext *tc, int cpuId)
{
for (int i = 0; i NumInternalProcRegs; ++i) {
tc-setMiscRegNoEffect(i, 0);
}
-tc-setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
+tc-setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
tc-setMiscRegNoEffect(IPR_MCSR, 0x6);
tc-setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
-AlphaISA::MiscReg
-AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
+MiscReg
+MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
uint64_t retval = 0;// return value, default 0
switch (idx) {
- case AlphaISA::IPR_PALtemp0:
- case AlphaISA::IPR_PALtemp1:
- case AlphaISA::IPR_PALtemp2:
- case AlphaISA::IPR_PALtemp3:
- case AlphaISA::IPR_PALtemp4:
- case AlphaISA::IPR_PALtemp5:
- case AlphaISA::IPR_PALtemp6:
- case AlphaISA::IPR_PALtemp7:
- case AlphaISA::IPR_PALtemp8:
- case AlphaISA::IPR_PALtemp9:
- case AlphaISA::IPR_PALtemp10:
- case AlphaISA::IPR_PALtemp11:
- case AlphaISA::IPR_PALtemp12:
- case AlphaISA::IPR_PALtemp13:
- case AlphaISA::IPR_PALtemp14:
- case AlphaISA::IPR_PALtemp15:
- case AlphaISA::IPR_PALtemp16:
- case AlphaISA::IPR_PALtemp17:
- case AlphaISA::IPR_PALtemp18:
- case AlphaISA::IPR_PALtemp19:
- case AlphaISA::IPR_PALtemp20:
- case AlphaISA::IPR_PALtemp21:
- case AlphaISA::IPR_PALtemp22:
- case AlphaISA::IPR_PALtemp23:
- case AlphaISA::IPR_PAL_BASE:
+ case IPR_PALtemp0:
+ case IPR_PALtemp1:
+ case IPR_PALtemp2:
+ case IPR_PALtemp3:
+ case IPR_PALtemp4:
+ case IPR_PALtemp5:
+ case IPR_PALtemp6:
+ case IPR_PALtemp7:
+ case IPR_PALtemp8:
+ case IPR_PALtemp9:
+ case IPR_PALtemp10:
+ case IPR_PALtemp11:
+ case IPR_PALtemp12:
+ case IPR_PALtemp13:
+ case IPR_PALtemp14:
+ case IPR_PALtemp15:
+ case IPR_PALtemp16:
+ case IPR_PALtemp17:
+ case IPR_PALtemp18:
+ case IPR_PALtemp19:
+ case IPR_PALtemp20:
+ case IPR_PALtemp21:
+ case IPR_PALtemp22:
+ case IPR_PALtemp23:
+ case IPR_PAL_BASE:
- case AlphaISA::IPR_IVPTBR:
- case AlphaISA::IPR_DC_MODE:
- case
[m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
changeset baeee670d4ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=baeee670d4ce
description:
style: Make a style pass over the whole arch/alpha directory.
diffstat:
46 files changed, 776 insertions(+), 509 deletions(-)
src/arch/alpha/ev5.cc|1
src/arch/alpha/ev5.hh|2
src/arch/alpha/faults.cc |1
src/arch/alpha/faults.hh |5
src/arch/alpha/floatregfile.cc | 10 -
src/arch/alpha/floatregfile.hh | 13 +-
src/arch/alpha/freebsd/system.cc |1
src/arch/alpha/idle_event.cc |2
src/arch/alpha/intregfile.cc | 17 +--
src/arch/alpha/intregfile.hh | 25 +++-
src/arch/alpha/ipr.cc| 97 +-
src/arch/alpha/ipr.hh| 150 +++-
src/arch/alpha/isa_traits.hh | 122 --
src/arch/alpha/linux/linux.cc|2
src/arch/alpha/linux/linux.hh|1
src/arch/alpha/linux/process.cc |1
src/arch/alpha/linux/system.hh |3
src/arch/alpha/locked_mem.hh |1
src/arch/alpha/miscregfile.cc| 77 ++
src/arch/alpha/miscregfile.hh| 49 +++--
src/arch/alpha/mmaped_ipr.hh |1
src/arch/alpha/osfpal.cc |3
src/arch/alpha/osfpal.hh |1
src/arch/alpha/pagetable.cc | 20 +--
src/arch/alpha/pagetable.hh | 84 +++
src/arch/alpha/predecoder.hh | 35 --
src/arch/alpha/process.cc|1
src/arch/alpha/process.hh|6 -
src/arch/alpha/regfile.cc| 35 +++---
src/arch/alpha/regfile.hh| 105 +--
src/arch/alpha/remote_gdb.cc |1
src/arch/alpha/remote_gdb.hh | 13 +-
src/arch/alpha/stacktrace.cc | 202 ++
src/arch/alpha/stacktrace.hh | 59 ---
src/arch/alpha/syscallreturn.hh | 12 --
src/arch/alpha/system.hh |3
src/arch/alpha/tlb.cc|2
src/arch/alpha/tlb.hh|1
src/arch/alpha/tru64/process.cc |1
src/arch/alpha/tru64/process.hh |4
src/arch/alpha/tru64/tru64.hh|4
src/arch/alpha/types.hh | 29 -
src/arch/alpha/utility.cc|3
src/arch/alpha/utility.hh| 71 +++--
src/arch/alpha/vtophys.hh|4
src/kern/tru64/tru64_events.cc |5
diffs (truncated from 5133 to 300 lines):
diff -r d14250d688d2 -r baeee670d4ce src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sat Sep 27 21:03:47 2008 -0700
+++ b/src/arch/alpha/ev5.cc Sat Sep 27 21:03:48 2008 -0700
@@ -459,8 +459,7 @@
// really a control write
ipr[idx] = val;
-tc-getDTBPtr()-flushAddr(val,
-DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
+tc-getDTBPtr()-flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
break;
case IPR_DTB_TAG: {
@@ -529,8 +528,7 @@
// really a control write
ipr[idx] = val;
-tc-getITBPtr()-flushAddr(val,
-ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
+tc-getITBPtr()-flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
break;
default:
@@ -541,18 +539,17 @@
// no error...
}
-
void
copyIprs(ThreadContext *src, ThreadContext *dest)
{
-for (int i = 0; i NumInternalProcRegs; ++i) {
+for (int i = 0; i NumInternalProcRegs; ++i)
dest-setMiscRegNoEffect(i, src-readMiscRegNoEffect(i));
-}
}
} // namespace AlphaISA
#if FULL_SYSTEM
+
using namespace AlphaISA;
Fault
diff -r d14250d688d2 -r baeee670d4ce src/arch/alpha/ev5.hh
--- a/src/arch/alpha/ev5.hh Sat Sep 27 21:03:47 2008 -0700
+++ b/src/arch/alpha/ev5.hh Sat Sep 27 21:03:48 2008 -0700
@@ -65,7 +65,9 @@
const Addr PAddrUncachedBit40 = ULL(0x100);
const Addr PAddrUncachedBit43 = ULL(0x800);
const Addr PAddrUncachedMask = ULL(0x807); // Clear PA42:35
-inline Addr Phys2K0Seg(Addr addr)
+
+inline Addr
+Phys2K0Seg(Addr addr)
{
#if !ALPHA_TLASER
if (addr PAddrUncachedBit43) {
diff -r d14250d688d2 -r baeee670d4ce src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Sat Sep 27 21:03:47 2008 -0700
+++ b/src/arch/alpha/faults.cc Sat Sep 27 21:03:48 2008 -0700
@@ -40,8 +40,7 @@
#include mem/page_table.hh
#endif
-namespace AlphaISA
-{
+namespace AlphaISA {
FaultName MachineCheckFault::_name = mchk;
FaultVect MachineCheckFault::_vect = 0x0401;
@@ -109,7 +108,8 @@
#if FULL_SYSTEM
-void AlphaFault::invoke(ThreadContext * tc)
+void
+AlphaFault::invoke(ThreadContext *tc)
{
FaultBase::invoke(tc);
countStat()++;
@@ -128,29 +128,31 @@
tc-setNextPC(tc-readPC() + sizeof(MachInst));
}
-void ArithmeticFault::invoke(ThreadContext * tc)
+void
+ArithmeticFault::invoke(ThreadContext *tc)
{
FaultBase::invoke(tc);
panic(Arithmetic traps are unimplemented!);
}
-void DtbFault::invoke(ThreadContext * tc)
+void
+DtbFault::invoke(ThreadContext *tc)
{
// Set fault address and flags. Even though
[m5-dev] changeset in m5: alpha: Get rid fo the namespace called EV5.
changeset 3440c9ad49b4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3440c9ad49b4
description:
alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
diffstat:
5 files changed, 3 insertions(+), 5 deletions(-)
src/arch/alpha/ev5.cc |2 ++
src/arch/alpha/ev5.hh |2 --
src/arch/alpha/faults.cc|1 -
src/arch/alpha/tlb.hh |1 -
src/arch/mips/mips_core_specific.cc |2 +-
diffs (255 lines):
diff -r 445da0b17433 -r 3440c9ad49b4 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sat Sep 27 07:25:04 2008 -0700
+++ b/src/arch/alpha/ev5.cc Sat Sep 27 21:03:45 2008 -0700
@@ -44,9 +44,9 @@
#include sim/debug.hh
#include sim/sim_exit.hh
+using namespace AlphaISA;
+
#if FULL_SYSTEM
-
-using namespace EV5;
//
@@ -146,13 +146,13 @@
int
AlphaISA::MiscRegFile::getInstAsid()
{
-return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
AlphaISA::MiscRegFile::getDataAsid()
{
-return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
#endif
@@ -168,7 +168,7 @@
tc-setMiscRegNoEffect(i, 0);
}
-tc-setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
+tc-setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
tc-setMiscRegNoEffect(IPR_MCSR, 0x6);
tc-setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
@@ -477,27 +477,27 @@
ipr[idx] = val;
tc-getDTBPtr()-flushAddr(val,
-EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
case AlphaISA::IPR_DTB_TAG: {
struct AlphaISA::TlbEntry entry;
// FIXME: granularity hints NYI...
- if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
+ if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
panic(PTE GH field != 0);
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- entry.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
- entry.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
+ entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
+ entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
tc-getDTBPtr()-insert(val, entry);
@@ -508,20 +508,20 @@
struct AlphaISA::TlbEntry entry;
// FIXME: granularity hints NYI...
- if (EV5::ITB_PTE_GH(val) != 0)
+ if (AlphaISA::ITB_PTE_GH(val) != 0)
panic(PTE GH field != 0);
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- entry.ppn = EV5::ITB_PTE_PPN(val);
- entry.xre = EV5::ITB_PTE_XRE(val);
+ entry.ppn = AlphaISA::ITB_PTE_PPN(val);
+ entry.xre = AlphaISA::ITB_PTE_XRE(val);
entry.xwe = 0;
- entry.fonr = EV5::ITB_PTE_FONR(val);
- entry.fonw = EV5::ITB_PTE_FONW(val);
- entry.asma = EV5::ITB_PTE_ASMA(val);
- entry.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
+ entry.fonr = AlphaISA::ITB_PTE_FONR(val);
+ entry.fonw = AlphaISA::ITB_PTE_FONW(val);
+ entry.asma = AlphaISA::ITB_PTE_ASMA(val);
+ entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
tc-getITBPtr()-insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
@@ -547,7 +547,7 @@
ipr[idx] = val;
tc-getITBPtr()-flushAddr(val,
-EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
default:
diff -r 445da0b17433 -r 3440c9ad49b4 src/arch/alpha/ev5.hh
--- a/src/arch/alpha/ev5.hh Sat Sep 27 07:25:04 2008 -0700
+++ b/src/arch/alpha/ev5.hh Sat Sep 27 21:03:45 2008 -0700
@@ -36,10 +36,7 @@
#include config/alpha_tlaser.hh
#include
[m5-dev] changeset in m5: gcc: Add extra parens to quell warnings.
changeset 13592d41f290 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=13592d41f290
description:
gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
diffstat:
11 files changed, 9 insertions(+), 17 deletions(-)
src/arch/alpha/pagetable.hh |2 +-
src/arch/alpha/utility.hh |2 +-
src/arch/mips/dsp.cc|2 +-
src/arch/mips/isa/decoder.isa |4 ++--
src/arch/mips/pagetable.hh |2 +-
src/arch/sparc/isa/formats/mem/util.isa |4
src/arch/x86/predecoder.cc |4 ++--
src/base/intmath.hh |2 --
src/base/random_mt.cc |2 +-
src/base/stats/text.cc |1 -
src/dev/terminal.cc |1 -
diffs (truncated from 411 to 300 lines):
diff -r baeee670d4ce -r 13592d41f290 src/arch/alpha/ev5.hh
--- a/src/arch/alpha/ev5.hh Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/alpha/ev5.hh Sat Sep 27 21:03:49 2008 -0700
@@ -80,7 +80,7 @@
inline int DTB_ASN_ASN(uint64_t reg) { return reg 57 AsnMask; }
inline Addr DTB_PTE_PPN(uint64_t reg)
-{ return reg 32 (ULL(1) PAddrImplBits - PageShift) - 1; }
+{ return reg 32 ((ULL(1) (PAddrImplBits - PageShift)) - 1); }
inline int DTB_PTE_XRE(uint64_t reg) { return reg 8 0xf; }
inline int DTB_PTE_XWE(uint64_t reg) { return reg 12 0xf; }
inline int DTB_PTE_FONR(uint64_t reg) { return reg 1 0x1; }
@@ -90,7 +90,7 @@
inline int ITB_ASN_ASN(uint64_t reg) { return reg 4 AsnMask; }
inline Addr ITB_PTE_PPN(uint64_t reg)
-{ return reg 32 (ULL(1) PAddrImplBits - PageShift) - 1; }
+{ return reg 32 ((ULL(1) (PAddrImplBits - PageShift)) - 1); }
inline int ITB_PTE_XRE(uint64_t reg) { return reg 8 0xf; }
inline bool ITB_PTE_FONR(uint64_t reg) { return reg 1 0x1; }
inline bool ITB_PTE_FONW(uint64_t reg) { return reg 2 0x1; }
diff -r baeee670d4ce -r 13592d41f290 src/arch/alpha/pagetable.hh
--- a/src/arch/alpha/pagetable.hh Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/alpha/pagetable.hh Sat Sep 27 21:03:49 2008 -0700
@@ -57,9 +57,9 @@
Addr level3() const
{ return PteAddr(addr PageShift); }
Addr level2() const
-{ return PteAddr(addr NPtePageShift + PageShift); }
+{ return PteAddr(addr (NPtePageShift + PageShift)); }
Addr level1() const
-{ return PteAddr(addr 2 * NPtePageShift + PageShift); }
+{ return PteAddr(addr (2 * NPtePageShift + PageShift)); }
};
struct PageTableEntry
diff -r baeee670d4ce -r 13592d41f290 src/arch/alpha/utility.hh
--- a/src/arch/alpha/utility.hh Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/alpha/utility.hh Sat Sep 27 21:03:49 2008 -0700
@@ -53,14 +53,14 @@
isCallerSaveIntegerRegister(unsigned int reg)
{
panic(register classification not implemented);
-return (reg = 1 reg = 8 || reg = 22 reg = 25 || reg == 27);
+return (reg = 1 reg = 8) || (reg = 22 reg = 25) || reg == 27;
}
inline bool
isCalleeSaveIntegerRegister(unsigned int reg)
{
panic(register classification not implemented);
-return (reg = 9 reg = 15);
+return reg = 9 reg = 15;
}
inline bool
diff -r baeee670d4ce -r 13592d41f290 src/arch/mips/dsp.cc
--- a/src/arch/mips/dsp.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/mips/dsp.cc Sat Sep 27 21:03:49 2008 -0700
@@ -923,10 +923,10 @@
for (int i = 0; i2; i++) {
r_values[i] =
-dspSaturate((int64_t)b_values[i] SIMD_NBITS[SIMD_FMT_QB] - 1,
+dspSaturate((int64_t)b_values[i] (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, ouflag);
r_values[i + 2] =
-dspSaturate((int64_t)a_values[i] SIMD_NBITS[SIMD_FMT_QB] - 1,
+dspSaturate((int64_t)a_values[i] (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, ouflag);
}
diff -r baeee670d4ce -r 13592d41f290 src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/mips/isa/decoder.isa Sat Sep 27 21:03:49 2008 -0700
@@ -416,16 +416,16 @@
Ctrl_Base_DepTag);
break;
case 25:
- data = 0 | fcsr_val
0xFE00 24
- | fcsr_val
0x0080 23;
+ data = (fcsr_val 0xFE00
24)
+
[m5-dev] changeset in m5: gcc: Version 4.3 adds some warnings that we're ...
changeset 7f81bb169068 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7f81bb169068
description:
gcc: Version 4.3 adds some warnings that we're turning off.
We just can't deal with right now.
diffstat:
0 files changed
diffs (11 lines):
diff -r 13592d41f290 -r 7f81bb169068 SConstruct
--- a/SConstructSat Sep 27 21:03:49 2008 -0700
+++ b/SConstructSat Sep 27 21:03:50 2008 -0700
@@ -351,6 +351,7 @@
env.Append(CCFLAGS='-pipe')
env.Append(CCFLAGS='-fno-strict-aliasing')
env.Append(CCFLAGS=Split('-Wall -Wno-sign-compare -Werror -Wundef'))
+env.Append(CXXFLAGS='-Wno-deprecated')
elif env['ICC']:
pass #Fix me... add warning flags once we clean up icc warnings
elif env['SUNCC']:
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Re: [m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
I thought that we had agreed to always use braces for control structures
(for, if, while, etc.) since that makes it easier to add/remove lines
without worrying about adding/removing braces too. I don't see it mentioned
either way on the coding style page, but I know I've developed the habit of
using braces unconditionally based on my recollection of that decision.
I don't really have a strong opinion either way; the #1 thing is that we
should agree and get it down on the wiki page so that these style updates
converge rather than oscillating.
Steve
On Sat, Sep 27, 2008 at 9:04 PM, Nathan Binkert [EMAIL PROTECTED] wrote:
void
copyIprs(ThreadContext *src, ThreadContext *dest)
{
-for (int i = 0; i NumInternalProcRegs; ++i) {
+for (int i = 0; i NumInternalProcRegs; ++i)
dest-setMiscRegNoEffect(i, src-readMiscRegNoEffect(i));
-}
}
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Re: [m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
Also, please make these sorts of large scale formatting changes
judiciously. There's a large collection of patches out there and it can
be non-trivial to keep them applying correctly.
Gabe
Steve Reinhardt wrote:
I thought that we had agreed to always use braces for control
structures (for, if, while, etc.) since that makes it easier to
add/remove lines without worrying about adding/removing braces too. I
don't see it mentioned either way on the coding style page, but I know
I've developed the habit of using braces unconditionally based on my
recollection of that decision.
I don't really have a strong opinion either way; the #1 thing is that
we should agree and get it down on the wiki page so that these style
updates converge rather than oscillating.
Steve
On Sat, Sep 27, 2008 at 9:04 PM, Nathan Binkert [EMAIL PROTECTED]
mailto:[EMAIL PROTECTED] wrote:
void
copyIprs(ThreadContext *src, ThreadContext *dest)
{
-for (int i = 0; i NumInternalProcRegs; ++i) {
+for (int i = 0; i NumInternalProcRegs; ++i)
dest-setMiscRegNoEffect(i, src-readMiscRegNoEffect(i));
-}
}
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___
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Re: [m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
I thought that we had agreed to always use braces for control structures (for, if, while, etc.) since that makes it easier to add/remove lines without worrying about adding/removing braces too. I don't see it mentioned either way on the coding style page, but I know I've developed the habit of using braces unconditionally based on my recollection of that decision. oh, I thought the agreement was that you use braces if there is an else, but if it's just a simple two liner, you don't have to. I don't really have a strong opinion either way; the #1 thing is that we should agree and get it down on the wiki page so that these style updates converge rather than oscillating. Agreed. What do you think about my above statement? If the whole expression fits in two lines, no braces required. More than two requires braces. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
I don't really have a strong opinion either way; the #1 thing is that we should agree and get it down on the wiki page so that these style updates converge rather than oscillating. Agreed. What do you think about my above statement? If the whole expression fits in two lines, no braces required. More than two requires braces. I think that sounds fine. Does no braces required also mean no braces allowed, or is that something left up to the implementers discretion? I think it should be optional rather than forbidden. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
I think that sounds fine. Does no braces required also mean no braces allowed, or is that something left up to the implementers discretion? I think it should be optional rather than forbidden. I'd agree with optional. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] stable
I'm running a full set of regressions and I will commit all of the output so that there will be no differences. Other than that, the only thing left is the problem in the mips register file. Diff #3 that I sent the other day is not actually correct, but it would at least generate an assertion and allow m5 to compile under 4.3. If someone would like to fix it, that would be great. Anything else to do? I personally don't want this to be 2.0, we need to plan a bit ahead for that. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] stable
1.99? Or did we already have one of those? Gabe nathan binkert wrote: I'm running a full set of regressions and I will commit all of the output so that there will be no differences. Other than that, the only thing left is the problem in the mips register file. Diff #3 that I sent the other day is not actually correct, but it would at least generate an assertion and allow m5 to compile under 4.3. If someone would like to fix it, that would be great. Anything else to do? I personally don't want this to be 2.0, we need to plan a bit ahead for that. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
On Sat, Sep 27, 2008 at 9:35 PM, nathan binkert [EMAIL PROTECTED] wrote: I think that sounds fine. Does no braces required also mean no braces allowed, or is that something left up to the implementers discretion? I think it should be optional rather than forbidden. I'd agree with optional. Optional is OK with me, but in that case it's not something that should be fixed in a style update. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: style: Make a style pass over the whole arch/al...
Optional is OK with me, but in that case it's not something that should be fixed in a style update. True, my bad. I was just going really fast. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
