[m5-dev] [PATCH 01 of 41] ruby: get rid of obsolete, unused CustomTopology class
# HG changeset patch
# User Steve Reinhardt steve.reinha...@amd.com
# Date 1263536240 28800
# Node ID 1b05faec653a14e08a7d32657b86a232be31cd77
# Parent 9e14a8c76257df063c65603e7a4001488f5e543f
ruby: get rid of obsolete, unused CustomTopology class.
diff -r 9e14a8c76257 -r 1b05faec653a
src/mem/ruby/network/simple/CustomTopology.cc
--- a/src/mem/ruby/network/simple/CustomTopology.cc Sat Jan 02 07:06:26
2010 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,140 +0,0 @@
-
-#include mem/ruby/network/simple/CustomTopology.hh
-#include mem/protocol/MachineType.hh
-
-static const int INFINITE_LATENCY = 1; // Yes, this is a big hack
-static const int DEFAULT_BW_MULTIPLIER = 1; // Just to be consistent with
above :)
-
-// make a network as described by the networkFile
-void CustomTopology::construct()
-{
-
- Vector Vector SwitchID nodePairs; // node pairs extracted from the
file
- Vectorint latencies; // link latencies for each link extracted
- Vectorint bw_multis; // bw multipliers for each link extracted
- Vectorint weights; // link weights used to enfore e-cube deadlock free
routing
- Vector SwitchID int_network_switches; // internal switches extracted
from the file
- Vectorbool endpointConnectionExist; // used to ensure all endpoints are
connected to the network
-
- endpointConnectionExist.setSize(m_nodes);
-
- // initialize endpoint check vector
- for (int k = 0; k endpointConnectionExist.size(); k++) {
-endpointConnectionExist[k] = false;
- }
-
- stringstream networkFile( m_connections );
-
- string line = ;
-
- while (!networkFile.eof()) {
-
-Vector SwitchID nodes;
-nodes.setSize(2);
-int latency = -1; // null latency
-int weight = -1; // null weight
-int bw_multiplier = DEFAULT_BW_MULTIPLIER; // default multiplier incase
the network file doesn't define it
-int i = 0; // node pair index
-int varsFound = 0; // number of varsFound on the line
-int internalNodes = 0; // used to determine if the link is between 2
internal nodes
-std::getline(networkFile, line, '\n');
-string varStr = string_split(line, ' ');
-
-// parse the current line in the file
-while (varStr != ) {
- string label = string_split(varStr, ':');
-
- // valid node labels
- if (label == ext_node || label == int_node) {
-ASSERT(i 2); // one link between 2 switches per line
-varsFound++;
-bool isNewIntSwitch = true;
-if (label == ext_node) { // input link to node
- MachineType machine = string_to_MachineType(string_split(varStr,
':'));
- string nodeStr = string_split(varStr, ':');
- nodes[i] = MachineType_base_number(machine)
-+ atoi(nodeStr.c_str());
-
- // in nodes should be numbered 0 to m_nodes-1
- ASSERT(nodes[i] = 0 nodes[i] m_nodes);
- isNewIntSwitch = false;
- endpointConnectionExist[nodes[i]] = true;
-}
-if (label == int_node) { // interior node
- nodes[i] = atoi((string_split(varStr, ':')).c_str())+m_nodes*2;
- // in nodes should be numbered = m_nodes*2
- ASSERT(nodes[i] = m_nodes*2);
- for (int k = 0; k int_network_switches.size(); k++) {
-if (int_network_switches[k] == nodes[i]) {
- isNewIntSwitch = false;
-}
- }
- if (isNewIntSwitch) { // if internal switch
-m_number_of_switches++;
-int_network_switches.insertAtBottom(nodes[i]);
- }
- internalNodes++;
-}
-i++;
- } else if (label == link_latency) {
-latency = atoi((string_split(varStr, ':')).c_str());
-varsFound++;
- } else if (label == bw_multiplier) { // not necessary, defaults to
DEFAULT_BW_MULTIPLIER
-bw_multiplier = atoi((string_split(varStr, ':')).c_str());
- } else if (label == link_weight) { // not necessary, defaults to
link_latency
-weight = atoi((string_split(varStr, ':')).c_str());
- } else {
-cerr Error: Unexpected Identifier: label endl;
-exit(1);
- }
- varStr = string_split(line, ' ');
-}
-if (varsFound == 3) { // all three necessary link variables where found so
add the link
- nodePairs.insertAtBottom(nodes);
- latencies.insertAtBottom(latency);
- if (weight != -1) {
-weights.insertAtBottom(weight);
- } else {
-weights.insertAtBottom(latency);
- }
- bw_multis.insertAtBottom(bw_multiplier);
- Vector SwitchID otherDirectionNodes;
- otherDirectionNodes.setSize(2);
- otherDirectionNodes[0] = nodes[1];
- if (internalNodes == 2) { // this is an internal link
-otherDirectionNodes[1] = nodes[0];
- } else {
-otherDirectionNodes[1] = nodes[0]+m_nodes;
- }
- nodePairs.insertAtBottom(otherDirectionNodes);
- latencies.insertAtBottom(latency);
- if (weight != -1) {
-
[m5-dev] [PATCH 05 of 41] ruby: Calculate system total memory capacity in Python
# HG changeset patch
# User Steve Reinhardt steve.reinha...@amd.com
# Date 1263536243 28800
# Node ID 9e35210428f8c5c7fd2bec745d4b4514923add15
# Parent 66e2254601b93184d109026173b22beafed99693
ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.
diff -r 66e2254601b9 -r 9e35210428f8 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
+++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
@@ -127,10 +127,14 @@
network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \
dir_cntrl_nodes))
+mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
+ for dir_cntrl in dir_cntrl_nodes])
+
system.ruby = RubySystem(network = network,
profiler = RubyProfiler(),
tracer = RubyTracer(),
- debug = RubyDebug())
+ debug = RubyDebug(),
+ mem_size_mb = mem_size_mb)
# ---
diff -r 66e2254601b9 -r 9e35210428f8 src/mem/ruby/system/RubySystem.py
--- a/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:23 2010 -0800
@@ -11,6 +11,7 @@
freq_mhz = Param.Int(3000, default frequency for the system);
block_size_bytes = Param.Int(64,
default cache block size; must be a power of two);
+mem_size_mb = Param.Int();
network = Param.RubyNetwork()
debug = Param.RubyDebug(the default debug object)
profiler = Param.RubyProfiler();
diff -r 66e2254601b9 -r 9e35210428f8 src/mem/ruby/system/System.cc
--- a/src/mem/ruby/system/System.cc Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/System.cc Thu Jan 14 22:17:23 2010 -0800
@@ -94,9 +94,14 @@
m_randomization = p-randomization;
m_tech_nm = p-tech_nm;
m_freq_mhz = p-freq_mhz;
+
m_block_size_bytes = p-block_size_bytes;
assert(is_power_of_2(m_block_size_bytes));
m_block_size_bits = log_int(m_block_size_bytes);
+
+m_memory_size_bytes = (uint64_t)p-mem_size_mb * 1024 * 1024;
+m_memory_size_bits = log_int(m_memory_size_bytes);
+
m_network_ptr = p-network;
g_debug_ptr = p-debug;
m_profiler_ptr = p-profiler;
@@ -104,23 +109,12 @@
g_system_ptr = this;
m_mem_vec_ptr = new MemoryVector;
+m_mem_vec_ptr-setSize(m_memory_size_bytes);
}
void RubySystem::init()
{
- // calculate system-wide parameters
- m_memory_size_bytes = 0;
- DirectoryMemory* prev = NULL;
- for (map string, DirectoryMemory*::const_iterator it =
m_directories.begin();
- it != m_directories.end(); it++) {
-if (prev != NULL)
- assert((*it).second-getSize() == prev-getSize()); // must be equal for
proper address mapping
-m_memory_size_bytes += (*it).second-getSize();
-prev = (*it).second;
- }
- m_mem_vec_ptr-setSize(m_memory_size_bytes);
- m_memory_size_bits = log_int(m_memory_size_bytes);
}
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[m5-dev] [PATCH 04 of 41] ruby: Add support for generating topologies in Python
# HG changeset patch
# User Steve Reinhardt steve.reinha...@amd.com
# Date 1263536243 28800
# Node ID 66e2254601b93184d109026173b22beafed99693
# Parent 2d514a17d1f69f9b8302c82550a347be3034dd44
ruby: Add support for generating topologies in Python.
diff -r 2d514a17d1f6 -r 66e2254601b9 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
+++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
@@ -97,24 +97,35 @@
latency = 15
size = 1048576
-class CrossbarTopology(Topology):
-connections=hi
+# It would be nice to lump all the network nodes into a single list,
+# but for consistency with the old scripts I'm segregating them by
+# type. I'm not sure if this is really necessary or not.
+
+# net_nodes = []
+l1_cntrl_nodes = []
+dir_cntrl_nodes = []
- for cpu in cpus:
+for cpu in cpus:
l1_cntrl = L1Cache_Controller()
-cpu_seq = RubySequencer(controller=l1_cntrl,
-icache=L1Cache(controller=l1_cntrl),
-dcache=L1Cache(controller=l1_cntrl))
+cpu_seq = RubySequencer(controller = l1_cntrl,
+icache = L1Cache(controller = l1_cntrl),
+dcache = L1Cache(controller = l1_cntrl))
cpu.controller = l1_cntrl
cpu.sequencer = cpu_seq
cpu.test = cpu_seq.port
cpu_seq.funcmem_port = system.physmem.port
cpu.functional = system.funcmem.port
-dir_cntrl = Directory_Controller(directory=RubyDirectoryMemory(),
- memory_control=RubyMemoryControl())
+dir_cntrl = Directory_Controller(version = i,
+ directory = RubyDirectoryMemory(),
+ memory_control = RubyMemoryControl())
-network = SimpleNetwork(topology=CrossbarTopology())
+# net_nodes += [l1_cntrl, dir_cntrl]
+l1_cntrl_nodes.append(l1_cntrl)
+dir_cntrl_nodes.append(dir_cntrl)
+
+network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \
+dir_cntrl_nodes))
system.ruby = RubySystem(network = network,
profiler = RubyProfiler(),
diff -r 2d514a17d1f6 -r 66e2254601b9 src/mem/ruby/network/Network.py
--- a/src/mem/ruby/network/Network.py Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/network/Network.py Thu Jan 14 22:17:23 2010 -0800
@@ -1,12 +1,40 @@
from m5.params import *
from m5.SimObject import SimObject
+class Link(SimObject):
+type = 'Link'
+latency = Param.Int(1, )
+bw_multiplier = Param.Int()
+weight = Param.Int(1, )
+
+class ExtLink(Link):
+type = 'ExtLink'
+ext_node = Param.RubyController(External node)
+int_node = Param.Int(ID of internal node)
+bw_multiplier = 64
+
+class IntLink(Link):
+type = 'IntLink'
+node_a = Param.Int(ID of internal node on one end)
+node_b = Param.Int(ID of internal node on other end)
+bw_multiplier = 16
+
class Topology(SimObject):
type = 'Topology'
-connections = Param.String()
+ext_links = VectorParam.ExtLink(Links to external nodes)
+int_links = VectorParam.IntLink(Links between internal nodes)
+num_int_nodes = Param.Int(Nunber of internal nodes)
print_config = Param.Bool(False,
display topology config in the stats file)
+def makeCrossbar(nodes):
+ext_links = [ExtLink(ext_node=n, int_node=i)
+ for (i, n) in enumerate(nodes)]
+xbar = len(nodes) # node ID for crossbar switch
+int_links = [IntLink(node_a=i, node_b=xbar) for i in range(len(nodes))]
+return Topology(ext_links=ext_links, int_links=int_links,
+num_int_nodes=len(nodes)+1)
+
class RubyNetwork(SimObject):
type = 'RubyNetwork'
cxx_class = 'Network'
diff -r 2d514a17d1f6 -r 66e2254601b9
src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
--- a/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc Thu Jan
14 22:17:23 2010 -0800
+++ b/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc Thu Jan
14 22:17:23 2010 -0800
@@ -96,7 +96,7 @@
ni-addNode(m_toNetQueues[i], m_fromNetQueues[i]);
m_ni_ptr_vector.insertAtBottom(ni);
}
-m_topology_ptr-createLinks(false); // false because this isn't a
reconfiguration
+m_topology_ptr-createLinks(this, false); // false because this isn't
a reconfiguration
for(int i = 0; i m_router_ptr_vector.size(); i++)
{
m_router_ptr_vector[i]-init();
diff -r 2d514a17d1f6 -r 66e2254601b9
src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
--- a/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.ccThu Jan
14 22:17:23 2010 -0800
+++ b/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.ccThu Jan
14 22:17:23 2010 -0800
@@ -95,7 +95,7 @@
ni-addNode(m_toNetQueues[i], m_fromNetQueues[i]);
[m5-dev] [PATCH 11 of 41] ruby: Added the cache profiler to the new config system
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536244 28800
# Node ID fa362ac18a7a7c2f737fc092f987d94f1beb906a
# Parent a7113be39b6a4f7ec2398fd87518f49445b1e83f
ruby: Added the cache profiler to the new config system
diff -r a7113be39b6a -r fa362ac18a7a configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800
+++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800
@@ -115,10 +115,14 @@
# Eventually this code should go in a python file specific to the
# MOESI_hammer protocol
#
-
-l1i_cache = L1Cache()
-l1d_cache = L1Cache()
-l2_cache = L2Cache()
+l1i_profiler = CacheProfiler(description = (l1i_%s_profiler % i))
+l1i_cache = L1Cache(cache_profiler = l1i_profiler)
+
+l1d_profiler = CacheProfiler(description = (l1d_%s_profiler % i))
+l1d_cache = L1Cache(cache_profiler = l1d_profiler)
+
+l2_profiler = CacheProfiler(description = (l2_%s_profiler % i))
+l2_cache = L2Cache(cache_profiler = l2_profiler)
cpu_seq = RubySequencer(icache = l1i_cache,
dcache = l1d_cache,
diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/profiler/CacheProfiler.cc
--- a/src/mem/ruby/profiler/CacheProfiler.ccThu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/profiler/CacheProfiler.ccThu Jan 14 22:17:24 2010 -0800
@@ -43,10 +43,10 @@
#include mem/ruby/profiler/Profiler.hh
#include mem/gems_common/Vector.hh
-CacheProfiler::CacheProfiler(string description)
- : m_requestSize(-1)
+CacheProfiler::CacheProfiler(const CacheProfilerParams* params)
+ : SimObject(params), m_requestSize(-1)
{
- m_description = description;
+ m_description = params-description;
m_requestTypeVec_ptr = new Vectorint;
m_requestTypeVec_ptr-setSize(int(CacheRequestType_NUM));
@@ -141,3 +141,8 @@
}
}
+CacheProfiler *
+CacheProfilerParams::create()
+{
+return new CacheProfiler(this);
+}
diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/profiler/CacheProfiler.hh
--- a/src/mem/ruby/profiler/CacheProfiler.hhThu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/profiler/CacheProfiler.hhThu Jan 14 22:17:24 2010 -0800
@@ -46,12 +46,15 @@
#include mem/protocol/PrefetchBit.hh
#include mem/protocol/CacheRequestType.hh
+#include params/CacheProfiler.hh
+
template class TYPE class Vector;
-class CacheProfiler {
+class CacheProfiler : public SimObject {
public:
// Constructors
- CacheProfiler(string description);
+ typedef CacheProfilerParams Params;
+ CacheProfiler(const Params *);
// Destructor
~CacheProfiler();
diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/profiler/Profiler.py
--- a/src/mem/ruby/profiler/Profiler.py Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/profiler/Profiler.py Thu Jan 14 22:17:24 2010 -0800
@@ -6,3 +6,8 @@
cxx_class = 'Profiler'
hot_lines = Param.Bool(False, )
all_instructions = Param.Bool(False, )
+
+class CacheProfiler(SimObject):
+type = 'CacheProfiler'
+cxx_class = 'CacheProfiler'
+description = Param.String()
diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/system/Cache.py
--- a/src/mem/ruby/system/Cache.py Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/system/Cache.py Thu Jan 14 22:17:24 2010 -0800
@@ -9,3 +9,4 @@
latency = Param.Int();
assoc = Param.Int();
replacement_policy = Param.String(PSEUDO_LRU, );
+cache_profiler = Param.CacheProfiler();
diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/system/CacheMemory.cc
--- a/src/mem/ruby/system/CacheMemory.ccThu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/system/CacheMemory.ccThu Jan 14 22:17:24 2010 -0800
@@ -58,6 +58,7 @@
m_latency = p-latency;
m_cache_assoc = p-assoc;
m_policy = p-replacement_policy;
+m_profiler_ptr = p-cache_profiler;
}
@@ -363,7 +364,7 @@
void CacheMemory::profileMiss(const CacheMsg msg)
{
m_profiler_ptr-addStatSample(msg.getType(), msg.getAccessMode(),
- msg.getSize(), msg.getPrefetch());
+msg.getSize(), msg.getPrefetch());
}
void CacheMemory::recordCacheContents(CacheRecorder tr) const
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[m5-dev] [PATCH 27 of 41] ruby: small fix to Directory Memory configuration
# HG changeset patch # User Brad Beckmann brad.beckm...@amd.com # Date 1263536246 28800 # Node ID 62c9baf381eb273866b17d83e268c3057298485e # Parent 4bda800b744ff1460dd98c97c5426ebe9170c1e8 ruby: small fix to Directory Memory configuration diff -r 4bda800b744f -r 62c9baf381eb configs/ruby/MOESI_hammer.py --- a/configs/ruby/MOESI_hammer.py Thu Jan 14 22:17:26 2010 -0800 +++ b/configs/ruby/MOESI_hammer.py Thu Jan 14 22:17:26 2010 -0800 @@ -104,7 +104,8 @@ mem_cntrl = RubyMemoryControl(version = i) dir_cntrl = Directory_Controller(version = i, - directory = RubyDirectoryMemory(), + directory = \ + RubyDirectoryMemory(version = i), memBuffer = mem_cntrl) dir_cntrl_nodes.append(dir_cntrl) ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 03 of 41] ruby: Make SLICC-generated objects SimObjects
# HG changeset patch
# User Steve Reinhardt steve.reinha...@amd.com
# Date 1263536243 28800
# Node ID 2d514a17d1f69f9b8302c82550a347be3034dd44
# Parent 9f8c0c3ae627fd5f07913f8d23deef0b9286fdfb
ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
diff -r 9f8c0c3ae627 -r 2d514a17d1f6 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.smThu Jan 14 22:17:22 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-cache.smThu Jan 14 22:17:23 2010 -0800
@@ -34,8 +34,8 @@
*/
machine(L1Cache, AMD Hammer-like protocol)
-: int cache_response_latency,
- int issue_latency
+: int cache_response_latency = 12,
+ int issue_latency = 2
{
// NETWORK BUFFERS
diff -r 9f8c0c3ae627 -r 2d514a17d1f6 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm Thu Jan 14 22:17:22 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-dir.sm Thu Jan 14 22:17:23 2010 -0800
@@ -34,7 +34,7 @@
*/
machine(Directory, AMD Hammer-like protocol)
-: int memory_controller_latency
+: int memory_controller_latency = 12
{
MessageBuffer forwardFromDir, network=To, virtual_network=2,
ordered=false;
diff -r 9f8c0c3ae627 -r 2d514a17d1f6 src/mem/protocol/MOESI_hammer-dma.sm
--- a/src/mem/protocol/MOESI_hammer-dma.sm Thu Jan 14 22:17:22 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-dma.sm Thu Jan 14 22:17:23 2010 -0800
@@ -28,7 +28,7 @@
machine(DMA, DMA Controller)
-: int request_latency
+: int request_latency = 6
{
MessageBuffer responseFromDir, network=From, virtual_network=4,
ordered=true, no_vector=true;
diff -r 9f8c0c3ae627 -r 2d514a17d1f6 src/mem/protocol/SConscript
--- a/src/mem/protocol/SConscript Thu Jan 14 22:17:22 2010 -0800
+++ b/src/mem/protocol/SConscript Thu Jan 14 22:17:23 2010 -0800
@@ -70,6 +70,25 @@
print %s % name
target.extend(sorted(slicc.files()))
+pdir = str(protocol_dir)
+hdir = str(html_dir)
+
+if not isdir(pdir):
+os.mkdir(pdir)
+if not isdir(hdir):
+os.mkdir(hdir)
+
+print SLICC Generator pass 1...
+slicc.findMachines()
+
+print SLICC Generator pass 2...
+slicc.generate()
+
+print SLICC writing C++ files...
+slicc.writeCodeFiles(pdir)
+
+print SLICC writing HTML files...
+slicc.writeHTMLFiles(hdir)
return target, source
def slicc_action(target, source, env):
@@ -108,5 +127,10 @@
nodes = env.SLICC([], [ Value(protocol) ] + sources)
env.Depends(nodes, slicc_depends)
-for f in sorted(s for s in nodes if str(s).endswith('.cc')):
-Source(f)
+for f in nodes:
+s = str(f)
+if s.endswith('.cc'):
+Source(f)
+elif s.endswith('.py'):
+SimObject(f)
+
diff -r 9f8c0c3ae627 -r 2d514a17d1f6
src/mem/ruby/slicc_interface/AbstractController.hh
--- a/src/mem/ruby/slicc_interface/AbstractController.hhThu Jan 14
22:17:22 2010 -0800
+++ b/src/mem/ruby/slicc_interface/AbstractController.hhThu Jan 14
22:17:23 2010 -0800
@@ -16,7 +16,6 @@
public:
typedef RubyControllerParams Params;
AbstractController(const Params *p) : SimObject(p) {}
- virtual void init(Network* net_ptr, const vectorstring argv) = 0;
// returns the number of controllers created of the specific subtype
// virtual int getNumberOfControllers() const = 0;
diff -r 9f8c0c3ae627 -r 2d514a17d1f6 src/mem/slicc/ast/FormalParamAST.py
--- a/src/mem/slicc/ast/FormalParamAST.py Thu Jan 14 22:17:22 2010 -0800
+++ b/src/mem/slicc/ast/FormalParamAST.py Thu Jan 14 22:17:23 2010 -0800
@@ -29,10 +29,11 @@
from slicc.symbols import Var
class FormalParamAST(AST):
-def __init__(self, slicc, type_ast, ident):
+def __init__(self, slicc, type_ast, ident, default = None):
super(FormalParamAST, self).__init__(slicc)
self.type_ast = type_ast
self.ident = ident
+self.default = default
def __repr__(self):
return [FormalParamAST: %s] % self.ident
diff -r 9f8c0c3ae627 -r 2d514a17d1f6 src/mem/slicc/ast/MachineAST.py
--- a/src/mem/slicc/ast/MachineAST.py Thu Jan 14 22:17:22 2010 -0800
+++ b/src/mem/slicc/ast/MachineAST.py Thu Jan 14 22:17:23 2010 -0800
@@ -43,6 +43,7 @@
def files(self, parent=None):
s = set(('%s_Controller.cc' % self.ident,
'%s_Controller.hh' % self.ident,
+ '%s_Controller.py' % self.ident,
'%s_Profiler.cc' % self.ident,
'%s_Profiler.hh' % self.ident,
'%s_Transitions.cc' % self.ident,
diff -r 9f8c0c3ae627 -r 2d514a17d1f6 src/mem/slicc/parser.py
--- a/src/mem/slicc/parser.py Thu Jan 14 22:17:22 2010 -0800
+++ b/src/mem/slicc/parser.py Thu Jan 14 22:17:23 2010 -0800
@@ -115,8 +115,6 @@
def files(self):
f = set([
-'ControllerFactory.cc',
-'ControllerFactory.hh',
'MachineType.cc',
[m5-dev] [PATCH 24 of 41] ruby: added data print to ruby request
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536246 28800
# Node ID 0cafcd0a9c15571a428675f50a6afe33c0277751
# Parent 21f0f940d2cf75299af55e1cf25ad07cfb711df8
ruby: added data print to ruby request
diff -r 21f0f940d2cf -r 0cafcd0a9c15 src/mem/ruby/libruby.cc
--- a/src/mem/ruby/libruby.cc Thu Jan 14 22:17:26 2010 -0800
+++ b/src/mem/ruby/libruby.cc Thu Jan 14 22:17:26 2010 -0800
@@ -68,7 +68,11 @@
ostream operator(std::ostream out, const RubyRequest obj)
{
- out hex 0x obj.paddr flush;
+ out hex 0x obj.paddr data: 0x flush;
+ for (int i = 0; i obj.len; i++) {
+out (int)obj.data[i];
+ }
+ out dec type: RubyRequestType_to_string(obj.type) endl;
return out;
}
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[m5-dev] [PATCH 35 of 41] ruby: Allows boolean defaults for StateMachine parameters
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536247 28800
# Node ID 54967d761bd18605f9fdf1210e8898ae942c7c04
# Parent c75f4c574f887fa9f03f74244508b802ec8ab085
ruby: Allows boolean defaults for StateMachine parameters
diff -r c75f4c574f88 -r 54967d761bd1 src/mem/slicc/parser.py
--- a/src/mem/slicc/parser.py Thu Jan 14 22:17:27 2010 -0800
+++ b/src/mem/slicc/parser.py Thu Jan 14 22:17:27 2010 -0800
@@ -421,10 +421,14 @@
param : type STAR ident
p[0] = ast.FormalParamAST(self, p[1], p[3], None, True)
-def p_param__default(self, p):
+def p_param__default_number(self, p):
param : type ident '=' NUMBER
p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
+def p_param__default_bool(self, p):
+param : type ident '=' LIT_BOOL
+p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
+
# Idents and lists
def p_idents__braced(self, p):
idents : '{' identx '}'
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[m5-dev] [PATCH 30 of 41] ruby: Ruby tester now manages data values dynamically
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536246 28800
# Node ID f5f1581d5b7c5d3443cd0792ec20a8bddfc670d5
# Parent 01bab1b7fc3c1da1d60c386999ba940ed773bab5
ruby: Ruby tester now manages data values dynamically
Instead of relying on static data and ugly internal copying of M5 data into
the ruby_request, the ruby tester now creates and destroys it's data...this
is much cleaner and consistent with other M5 cpu objects.
diff -r 01bab1b7fc3c -r f5f1581d5b7c src/cpu/rubytest/Check.cc
--- a/src/cpu/rubytest/Check.cc Thu Jan 14 22:17:26 2010 -0800
+++ b/src/cpu/rubytest/Check.cc Thu Jan 14 22:17:26 2010 -0800
@@ -81,7 +81,6 @@
Request::Flags flags;
flags.set(Request::PREFETCH);
- uint8_t dummyStackdata = 0;
//
// Prefetches are assumed to be 0 sized
@@ -111,7 +110,6 @@
}
PacketPtr pkt = new Packet(req, cmd, port-idx);
- pkt-dataStatic(dummyStackdata);
//
// push the subblock onto the sender state. The sequencer will update the
@@ -122,6 +120,12 @@
if (port-sendTiming(pkt)) {
DPRINTF(RubyTest, successfully initiated prefetch.\n);
} else {
+//
+// If the packet did not issue, must delete
+//
+delete pkt-senderState;
+delete pkt-req;
+delete pkt;
DPRINTF(RubyTest, prefetch initiation failed because Port was busy.\n);
}
}
@@ -136,7 +140,6 @@
(m_tester_ptr-getCpuPort(random() % m_num_cpu_sequencers));
Request::Flags flags;
- uint8_t writeData = m_value + m_store_count;
//
// Create the particular address for the next byte to be written
@@ -164,7 +167,14 @@
// }
PacketPtr pkt = new Packet(req, cmd, port-idx);
- pkt-dataStatic(writeData);
+ uint8_t* writeData = new uint8_t;
+ *writeData = m_value + m_store_count;
+ pkt-dataDynamic(writeData);
+
+ DPRINTF(RubyTest,
+ data 0x%x check 0x%x\n,
+ *(pkt-getPtruint8_t()),
+ *writeData);
//
// push the subblock onto the sender state. The sequencer will update the
@@ -179,6 +189,13 @@
(TesterStatus_to_string(m_status)).c_str());
m_status = TesterStatus_Action_Pending;
} else {
+//
+// If the packet did not issue, must delete
+// Note: No need to delete the data, the packet destructor will delete it
+//
+delete pkt-senderState;
+delete pkt-req;
+delete pkt;
DPRINTF(RubyTest, failed to initiate action - sequencer not ready\n);
}
@@ -197,7 +214,6 @@
(m_tester_ptr-getCpuPort(random() % m_num_cpu_sequencers));
Request::Flags flags;
- uint8_t dummyStackdata = 0;
//
// Checks are sized depending on the number of bytes written
@@ -216,7 +232,8 @@
}
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port-idx);
- pkt-dataStatic(dummyStackdata);
+ uint8_t* dataArray = new uint8_t[CHECK_SIZE];
+ pkt-dataDynamicArray(dataArray);
//
// push the subblock onto the sender state. The sequencer will update the
@@ -231,6 +248,13 @@
(TesterStatus_to_string(m_status)).c_str());
m_status = TesterStatus_Check_Pending;
} else {
+//
+// If the packet did not issue, must delete
+// Note: No need to delete the data, the packet destructor will delete it
+//
+delete pkt-senderState;
+delete pkt-req;
+delete pkt;
DPRINTF(RubyTest, failed to initiate check - cpu port not ready\n);
}
diff -r 01bab1b7fc3c -r f5f1581d5b7c src/cpu/rubytest/RubyTester.cc
--- a/src/cpu/rubytest/RubyTester.ccThu Jan 14 22:17:26 2010 -0800
+++ b/src/cpu/rubytest/RubyTester.ccThu Jan 14 22:17:26 2010 -0800
@@ -107,19 +107,21 @@
//
RubyTester::SenderState* senderState =
static_castRubyTester::SenderState*(pkt-senderState);
- SubBlock* data = senderState-subBlock;
- assert(data != NULL);
+ SubBlock* subblock = senderState-subBlock;
+ assert(subblock != NULL);
// pop the sender state from the packet
pkt-senderState = senderState-saved;
delete senderState;
- tester-hitCallback(idx, data);
+ tester-hitCallback(idx, subblock);
//
- // Now that the tester has completed, delete the sublock and return
+ // Now that the tester has completed, delete the sublock, packet and return
//
- delete data;
+ delete subblock;
+ delete pkt-req;
+ delete pkt;
return true;
}
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[m5-dev] [PATCH 22 of 41] ruby: fixed MOESI_hammer data writebacks to the directory
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536246 28800
# Node ID 37dbe5d036b3299f6d15ea36a7785badcc766cb6
# Parent 412eb04d0909c94debbe76e07665792e8a0a4a18
ruby: fixed MOESI_hammer data writebacks to the directory
diff -r 412eb04d0909 -r 37dbe5d036b3 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm Thu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-dir.sm Thu Jan 14 22:17:26 2010 -0800
@@ -877,13 +877,13 @@
}
// WB State Transistions
- transition(WB, Writeback_Dirty, WB_E_W) {
+ transition(WB, Writeback_Dirty, WB_O_W) {
l_writeDataToMemory;
l_queueMemoryWBRequest;
j_popIncomingUnblockQueue;
}
- transition(WB, Writeback_Exclusive_Dirty, WB_O_W) {
+ transition(WB, Writeback_Exclusive_Dirty, WB_E_W) {
l_writeDataToMemory;
l_queueMemoryWBRequest;
j_popIncomingUnblockQueue;
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[m5-dev] [PATCH 18 of 41] ruby: fixed Set.cc bug to allow zero sized sets
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID 908ff9da9c54903145f1fe5c97d791d590eb2066
# Parent ede19abf2fa6f359994660129a0a36d3020116f5
ruby: fixed Set.cc bug to allow zero sized sets
This is necessary for example when no dma sequencers are necessary in the
simulated system.
diff -r ede19abf2fa6 -r 908ff9da9c54 src/mem/ruby/common/Set.cc
--- a/src/mem/ruby/common/Set.ccThu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/common/Set.ccThu Jan 14 22:17:25 2010 -0800
@@ -69,8 +69,11 @@
Set::Set(int size)
{
m_p_nArray = NULL;
- assert(size0);
- setSize(size);
+ m_nArrayLen = 0;
+ m_nSize = 0;
+ if(size 0) {
+setSize(size);
+ }
}
Set::~Set() {
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[m5-dev] [PATCH 14 of 41] ruby: Convered ruby tracing support usage of sequencer
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536244 28800
# Node ID ff484152abd5dfad23e6f78205bfa0b8b71e0ade
# Parent af8f083f34c61058e1449d0b65c6da5dc694fe41
ruby: Convered ruby tracing support usage of sequencer
Modified ruby's tracing support to no longer rely on the RubySystem map
to convert a sequencer string name to a sequencer pointer. As a
temporary solution, the code uses the sim_object find function.
Eventually, we should develop a better fix.
diff -r af8f083f34c6 -r ff484152abd5 src/mem/ruby/recorder/CacheRecorder.cc
--- a/src/mem/ruby/recorder/CacheRecorder.ccThu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/recorder/CacheRecorder.ccThu Jan 14 22:17:24 2010 -0800
@@ -48,9 +48,13 @@
delete m_records_ptr;
}
-void CacheRecorder::addRecord(const string sequencer_name, const Address
data_addr, const Address pc_addr, RubyRequestType type, Time time)
+void CacheRecorder::addRecord(Sequencer* sequencer,
+ const Address data_addr,
+ const Address pc_addr,
+ RubyRequestType type,
+ Time time)
{
- m_records_ptr-insert(TraceRecord(sequencer_name, data_addr, pc_addr, type,
time));
+ m_records_ptr-insert(TraceRecord(sequencer, data_addr, pc_addr, type,
time));
}
int CacheRecorder::dumpRecords(string filename)
diff -r af8f083f34c6 -r ff484152abd5 src/mem/ruby/recorder/CacheRecorder.hh
--- a/src/mem/ruby/recorder/CacheRecorder.hhThu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/recorder/CacheRecorder.hhThu Jan 14 22:17:24 2010 -0800
@@ -47,6 +47,7 @@
template class TYPE class PrioHeap;
class Address;
class TraceRecord;
+class Sequencer;
class CacheRecorder {
public:
@@ -57,7 +58,11 @@
~CacheRecorder();
// Public Methods
- void addRecord(const string sequencer_name, const Address data_addr,
const Address pc_addr, RubyRequestType type, Time time);
+ void addRecord(Sequencer* sequencer,
+ const Address data_addr,
+ const Address pc_addr,
+ RubyRequestType type,
+ Time time);
int dumpRecords(string filename);
void print(ostream out) const;
diff -r af8f083f34c6 -r ff484152abd5 src/mem/ruby/recorder/TraceRecord.cc
--- a/src/mem/ruby/recorder/TraceRecord.cc Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/recorder/TraceRecord.cc Thu Jan 14 22:17:24 2010 -0800
@@ -36,10 +36,15 @@
#include mem/ruby/system/Sequencer.hh
#include mem/ruby/system/System.hh
#include mem/protocol/CacheMsg.hh
+#include sim/sim_object.hh
-TraceRecord::TraceRecord(const string sequencer_name, const Address
data_addr, const Address pc_addr, RubyRequestType type, Time time)
+TraceRecord::TraceRecord(Sequencer* _sequencer,
+ const Address data_addr,
+ const Address pc_addr,
+ RubyRequestType type,
+ Time time)
{
- m_sequencer_name = sequencer_name;
+ m_sequencer_ptr = _sequencer;
m_data_address = data_addr;
m_pc_address = pc_addr;
m_time = time;
@@ -63,7 +68,7 @@
TraceRecord TraceRecord::operator=(const TraceRecord obj)
{
- m_sequencer_name = obj.m_sequencer_name;
+ m_sequencer_ptr = obj.m_sequencer_ptr;
m_time = obj.m_time;
m_data_address = obj.m_data_address;
m_pc_address = obj.m_pc_address;
@@ -73,34 +78,38 @@
void TraceRecord::issueRequest() const
{
- // Lookup sequencer pointer from system
- // Note that the chip index also needs to take into account SMT
configurations
- Sequencer* sequencer_ptr = RubySystem::getSequencer(m_sequencer_name);
- assert(sequencer_ptr != NULL);
+ assert(m_sequencer_ptr != NULL);
- RubyRequest request(m_data_address.getAddress(), NULL,
RubySystem::getBlockSizeBytes(), m_pc_address.getAddress(), m_type,
RubyAccessMode_User);
+ RubyRequest request(m_data_address.getAddress(),
+ NULL,
+ RubySystem::getBlockSizeBytes(),
+ m_pc_address.getAddress(),
+ m_type,
+ RubyAccessMode_User);
// Clear out the sequencer
- while (!sequencer_ptr-empty()) {
+ while (!m_sequencer_ptr-empty()) {
g_eventQueue_ptr-triggerEvents(g_eventQueue_ptr-getTime() + 100);
}
- sequencer_ptr-makeRequest(request);
+ m_sequencer_ptr-makeRequest(request);
// Clear out the sequencer
- while (!sequencer_ptr-empty()) {
+ while (!m_sequencer_ptr-empty()) {
g_eventQueue_ptr-triggerEvents(g_eventQueue_ptr-getTime() + 100);
}
}
void TraceRecord::print(ostream out) const
{
- out [TraceRecord: Node, m_sequencer_name , m_data_address
, m_pc_address , m_type , Time: m_time ];
+ out [TraceRecord: Node, m_sequencer_ptr-name() ,
+ m_data_address , m_pc_address ,
+ m_type , Time: m_time ];
}
void TraceRecord::output(ostream out) const
[m5-dev] [PATCH 28 of 41] ruby: fixed the memory total size variable to be 64-bits
# HG changeset patch # User Brad Beckmann brad.beckm...@amd.com # Date 1263536246 28800 # Node ID b2581afcdf3c74326fb4f5732874fc2c9be252e3 # Parent 62c9baf381eb273866b17d83e268c3057298485e ruby: fixed the memory total size variable to be 64-bits diff -r 62c9baf381eb -r b2581afcdf3c src/mem/ruby/system/DirectoryMemory.cc --- a/src/mem/ruby/system/DirectoryMemory.ccThu Jan 14 22:17:26 2010 -0800 +++ b/src/mem/ruby/system/DirectoryMemory.ccThu Jan 14 22:17:26 2010 -0800 @@ -43,7 +43,7 @@ int DirectoryMemory::m_num_directories = 0; int DirectoryMemory::m_num_directories_bits = 0; -int DirectoryMemory::m_total_size_bytes = 0; +uint64 DirectoryMemory::m_total_size_bytes = 0; DirectoryMemory::DirectoryMemory(const Params *p) : SimObject(p) diff -r 62c9baf381eb -r b2581afcdf3c src/mem/ruby/system/DirectoryMemory.hh --- a/src/mem/ruby/system/DirectoryMemory.hhThu Jan 14 22:17:26 2010 -0800 +++ b/src/mem/ruby/system/DirectoryMemory.hhThu Jan 14 22:17:26 2010 -0800 @@ -91,7 +91,7 @@ static int m_num_directories; static int m_num_directories_bits; - static int m_total_size_bytes; + static uint64 m_total_size_bytes; MemoryVector* m_ram; }; ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 07 of 41] ruby: Ruby changes required to use the python config system
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536243 28800
# Node ID 2a756159e6b0844df0d0b198bce8ad654cb58d46
# Parent 207d8bc75eb96dbcb9ee0edd8abaa85ae165c9f4
ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
diff -r 207d8bc75eb9 -r 2a756159e6b0 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
+++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
@@ -102,8 +102,6 @@
# consistent with the NetDest list. Therefore the l1 controller nodes must be
# listed before the directory nodes and directory nodes before dma nodes, etc.
#
-
-# net_nodes = []
l1_cntrl_nodes = []
dir_cntrl_nodes = []
@@ -112,23 +110,43 @@
# controller constructors are called before the network constructor
#
for (i, cpu) in enumerate(cpus):
-l1_cntrl = L1Cache_Controller()
-cpu_seq = RubySequencer(controller = l1_cntrl,
-icache = L1Cache(controller = l1_cntrl),
-dcache = L1Cache(controller = l1_cntrl))
-cpu.controller = l1_cntrl
-cpu.sequencer = cpu_seq
+#
+# First create the Ruby objects associated with this cpu
+# Eventually this code should go in a python file specific to the
+# MOESI_hammer protocol
+#
+
+l1i_cache = L1Cache()
+l1d_cache = L1Cache()
+l2_cache = L2Cache()
+
+cpu_seq = RubySequencer(icache = l1i_cache,
+dcache = l1d_cache,
+funcmem_port = system.physmem.port)
+
+l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ L2cacheMemory = l2_cache)
+
+dir_cntrl = Directory_Controller(version = i,
+ directory = RubyDirectoryMemory(),
+ memBuffer = RubyMemoryControl())
+
+#
+# As noted above: Two independent list are track to maintain the order of
+# nodes/controllers assumed by the ruby network
+#
+l1_cntrl_nodes.append(l1_cntrl)
+dir_cntrl_nodes.append(dir_cntrl)
+
+#
+# Finally tie the memtester ports to the correct system ports
+#
cpu.test = cpu_seq.port
-cpu_seq.funcmem_port = system.physmem.port
cpu.functional = system.funcmem.port
-dir_cntrl = Directory_Controller(version = i,
- directory = RubyDirectoryMemory(),
- memory_control = RubyMemoryControl())
-
-# net_nodes += [l1_cntrl, dir_cntrl]
-l1_cntrl_nodes.append(l1_cntrl)
-dir_cntrl_nodes.append(dir_cntrl)
#
# Important: the topology constructor must be called before the network
diff -r 207d8bc75eb9 -r 2a756159e6b0 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.smThu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-cache.smThu Jan 14 22:17:23 2010 -0800
@@ -34,7 +34,11 @@
*/
machine(L1Cache, AMD Hammer-like protocol)
-: int cache_response_latency = 12,
+: Sequencer * sequencer,
+ CacheMemory * L1IcacheMemory,
+ CacheMemory * L1DcacheMemory,
+ CacheMemory * L2cacheMemory,
+ int cache_response_latency = 12,
int issue_latency = 2
{
@@ -104,7 +108,6 @@
// STRUCTURE DEFINITIONS
MessageBuffer mandatoryQueue, ordered=false;
- Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg[sequencer])';
// CacheEntry
structure(Entry, desc=..., interface=AbstractCacheEntry) {
@@ -122,17 +125,6 @@
bool Sharers,desc=On a GetS, did we find any other sharers in
the system;
}
- external_type(CacheMemory) {
-bool cacheAvail(Address);
-Address cacheProbe(Address);
-void allocate(Address, Entry);
-void deallocate(Address);
-Entry lookup(Address);
-void changePermission(Address, AccessPermission);
-bool isTagPresent(Address);
-void profileMiss(CacheMsg);
- }
-
external_type(TBETable) {
TBE lookup(Address);
void allocate(Address);
@@ -141,17 +133,14 @@
}
TBETable TBEs, template_hack=L1Cache_TBE;
- CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg[icache])';
- CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg[dcache])';
- CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg[l2cache])';
Entry getCacheEntry(Address addr), return_by_ref=yes {
if (L2cacheMemory.isTagPresent(addr)) {
- return
[m5-dev] [PATCH 36 of 41] ruby: MOESI_CMP_token updates to use the new config system
# HG changeset patch # User Brad Beckmann brad.beckm...@amd.com # Date 1263536247 28800 # Node ID 061151fda49a35f2d8ba4a20d2ed159c9ed23493 # Parent 54967d761bd18605f9fdf1210e8898ae942c7c04 ruby: MOESI_CMP_token updates to use the new config system diff -r 54967d761bd1 -r 061151fda49a configs/common/Options.py --- a/configs/common/Options.py Thu Jan 14 22:17:27 2010 -0800 +++ b/configs/common/Options.py Thu Jan 14 22:17:27 2010 -0800 @@ -36,6 +36,7 @@ parser.add_option(--fastmem, action=store_true) parser.add_option(--clock, action=store, type=string, default='1GHz') parser.add_option(--num-dirs, type=int, default=1) +parser.add_option(--num-l2caches, type=int, default=1) # Run duration options parser.add_option(-m, --maxtick, type=int, default=m5.MaxTick, diff -r 54967d761bd1 -r 061151fda49a configs/ruby/MOESI_CMP_token.py --- /dev/null Thu Jan 01 00:00:00 1970 + +++ b/configs/ruby/MOESI_CMP_token.py Thu Jan 14 22:17:27 2010 -0800 @@ -0,0 +1,161 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2009 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Brad Beckmann + +import math +import m5 +from m5.objects import * +from m5.defines import buildEnv +from m5.util import addToPath + +# +# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# +class L1Cache(RubyCache): +latency = 3 + +# +# Note: the L2 Cache latency is not currently used +# +class L2Cache(RubyCache): +latency = 15 + +def create_system(options, phys_mem, piobus, dma_devices): + +if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': +panic(This script requires the MOESI_CMP_token protocol to be built.) + +# +# number of tokens that the owner passes to requests so that shared blocks can +# respond to read requests +# +n_tokens = options.num_cpus + 1 + +cpu_sequencers = [] + +# +# The ruby network creation expects the list of nodes in the system to be +# consistent with the NetDest list. Therefore the l1 controller nodes must be +# listed before the directory nodes and directory nodes before dma nodes, etc. +# +l1_cntrl_nodes = [] +l2_cntrl_nodes = [] +dir_cntrl_nodes = [] +dma_cntrl_nodes = [] + +# +# Must create the individual controllers before the network to ensure the +# controller constructors are called before the network constructor +# + +for i in xrange(options.num_cpus): +# +# First create the Ruby objects associated with this cpu +# +l1i_cache = L1Cache(size = options.l1i_size, +assoc = options.l1i_assoc) +l1d_cache = L1Cache(size = options.l1d_size, +assoc = options.l1d_assoc) + +cpu_seq = RubySequencer(icache = l1i_cache, +dcache = l1d_cache, +physMemPort = phys_mem.port, +physmem = phys_mem) + +if piobus != None: +cpu_seq.pio_port = piobus.port + +l1_cntrl = L1Cache_Controller(version = i, + sequencer = cpu_seq, + L1IcacheMemory = l1i_cache, + L1DcacheMemory = l1d_cache, + l2_select_num_bits = \ +math.log(options.num_l2caches, 2), +
[m5-dev] [PATCH 12 of 41] ruby: Converted MOESI_hammer dma cntrl to new config system
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536244 28800
# Node ID e04160e57f4307f0b1d40524f08f6c1e4b8252ea
# Parent fa362ac18a7a7c2f737fc092f987d94f1beb906a
ruby: Converted MOESI_hammer dma cntrl to new config system
diff -r fa362ac18a7a -r e04160e57f43 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800
+++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800
@@ -104,6 +104,7 @@
#
l1_cntrl_nodes = []
dir_cntrl_nodes = []
+dma_cntrl_nodes = []
#
# Must create the individual controllers before the network to ensure the
@@ -138,12 +139,15 @@
directory = RubyDirectoryMemory(),
memBuffer = RubyMemoryControl())
+dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = DMASequencer())
#
# As noted above: Two independent list are track to maintain the order of
# nodes/controllers assumed by the ruby network
#
l1_cntrl_nodes.append(l1_cntrl)
dir_cntrl_nodes.append(dir_cntrl)
+dma_cntrl_nodes.append(dma_cntrl)
#
# Finally tie the memtester ports to the correct system ports
@@ -157,7 +161,8 @@
# constructor.
#
network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \
-dir_cntrl_nodes))
+dir_cntrl_nodes + \
+dma_cntrl_nodes))
mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
for dir_cntrl in dir_cntrl_nodes])
@@ -166,7 +171,9 @@
network = network,
profiler = RubyProfiler(),
tracer = RubyTracer(),
- debug = RubyDebug(),
+ debug = RubyDebug(filter_string = 'qQin',
+ verbosity_string = 'high',
+ protocol_trace = True),
mem_size_mb = mem_size_mb)
diff -r fa362ac18a7a -r e04160e57f43 src/mem/protocol/MOESI_hammer-dma.sm
--- a/src/mem/protocol/MOESI_hammer-dma.sm Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/protocol/MOESI_hammer-dma.sm Thu Jan 14 22:17:24 2010 -0800
@@ -28,7 +28,8 @@
machine(DMA, DMA Controller)
-: int request_latency = 6
+: DMASequencer * dma_sequencer,
+ int request_latency = 6
{
MessageBuffer responseFromDir, network=From, virtual_network=4,
ordered=true, no_vector=true;
@@ -47,20 +48,14 @@
Ack, desc=DMA write to memory completed;
}
- external_type(DMASequencer) {
-void ackCallback();
-void dataCallback(DataBlock);
- }
-
MessageBuffer mandatoryQueue, ordered=false, no_vector=true;
- DMASequencer dma_sequencer,
factory='RubySystem::getDMASequencer(m_cfg[dma_sequencer])', no_vector=true;
State cur_state, no_vector=true;
State getState(Address addr) {
return cur_state;
}
void setState(Address addr, State state) {
- cur_state := state;
+cur_state := state;
}
out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc=...);
diff -r fa362ac18a7a -r e04160e57f43 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/protocol/RubySlicc_Types.sm Thu Jan 14 22:17:24 2010 -0800
@@ -122,6 +122,11 @@
}
+external_type(DMASequencer) {
+ void ackCallback();
+ void dataCallback(DataBlock);
+}
+
external_type(TimerTable, inport=yes) {
bool isReady();
Address readyAddress();
diff -r fa362ac18a7a -r e04160e57f43 src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc Thu Jan 14 22:17:24 2010 -0800
+++ b/src/mem/ruby/system/DMASequencer.cc Thu Jan 14 22:17:24 2010 -0800
@@ -8,6 +8,10 @@
#include mem/protocol/SequencerRequestType.hh
#include mem/ruby/system/System.hh
+//
+// Fix me: This code needs comments!
+//
+
DMASequencer::DMASequencer(const Params *p)
: RubyPort(p)
{
@@ -15,6 +19,7 @@
void DMASequencer::init()
{
+ RubyPort::init();
m_is_busy = false;
m_data_block_mask = ~ (~0 RubySystem::getBlockSizeBits());
}
@@ -58,11 +63,16 @@
msg.getLineAddress() = line_address(msg.getPhysicalAddress());
msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
int offset = paddr m_data_block_mask;
+
msg.getLen() = (offset + len) = RubySystem::getBlockSizeBytes() ?
len :
RubySystem::getBlockSizeBytes() - offset;
- if (write)
+
+ if (write) {
msg.getDataBlk().setData(data, offset, msg.getLen());
+ }
+
+ assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr-enqueue(msg);
active_request.bytes_issued += msg.getLen();
@@ -82,14 +92,18 @@
SequencerMsg msg;
msg.getPhysicalAddress() = Address(active_request.start_paddr +
[m5-dev] [PATCH 08 of 41] ruby: Added clock to ruby system
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536243 28800
# Node ID 00bb4cb54fa91a68709ce82a878d0b6a724c8950
# Parent 2a756159e6b0844df0d0b198bce8ad654cb58d46
ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
diff -r 2a756159e6b0 -r 00bb4cb54fa9 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
+++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:23 2010 -0800
@@ -158,7 +158,8 @@
mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
for dir_cntrl in dir_cntrl_nodes])
-system.ruby = RubySystem(network = network,
+system.ruby = RubySystem(clock = '1GHz',
+ network = network,
profiler = RubyProfiler(),
tracer = RubyTracer(),
debug = RubyDebug(),
diff -r 2a756159e6b0 -r 00bb4cb54fa9 src/mem/ruby/eventqueue/RubyEventQueue.cc
--- a/src/mem/ruby/eventqueue/RubyEventQueue.cc Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/eventqueue/RubyEventQueue.cc Thu Jan 14 22:17:23 2010 -0800
@@ -40,9 +40,8 @@
// Class public method definitions
-RubyEventQueue theEventQueue;
-
-RubyEventQueue::RubyEventQueue()
+RubyEventQueue::RubyEventQueue(Tick _clock)
+ : m_clock(_clock)
{
m_prio_heap_ptr = NULL;
init();
diff -r 2a756159e6b0 -r 00bb4cb54fa9 src/mem/ruby/eventqueue/RubyEventQueue.hh
--- a/src/mem/ruby/eventqueue/RubyEventQueue.hh Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/eventqueue/RubyEventQueue.hh Thu Jan 14 22:17:23 2010 -0800
@@ -70,14 +70,14 @@
class RubyEventQueue {
public:
// Constructors
- RubyEventQueue();
+ RubyEventQueue(Tick clock);
// Destructor
~RubyEventQueue();
// Public Methods
- Time getTime() const { return m_globalTime; }
+ Time getTime() const { return curTick/m_clock; }
void scheduleEvent(Consumer* consumer, Time timeDelta) {
scheduleEventAbsolute(consumer, timeDelta + m_globalTime); }
void scheduleEventAbsolute(Consumer* consumer, Time timeAbs);
void triggerEvents(Time t); // called to handle all events = time t
@@ -96,6 +96,7 @@
RubyEventQueue operator=(const RubyEventQueue obj);
// Data Members (m_ prefix)
+ Tick m_clock;
PrioHeapRubyEventQueueNode* m_prio_heap_ptr;
Time m_globalTime;
Time m_timeOfLastRecovery;
diff -r 2a756159e6b0 -r 00bb4cb54fa9 src/mem/ruby/system/RubySystem.py
--- a/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:23 2010 -0800
@@ -8,7 +8,7 @@
insert random delays on message enqueue times);
tech_nm = Param.Int(45,
device size used to calculate latency and area information);
-freq_mhz = Param.Int(3000, default frequency for the system);
+clock = Param.Clock('1GHz', )
block_size_bytes = Param.Int(64,
default cache block size; must be a power of two);
mem_size_mb = Param.Int();
diff -r 2a756159e6b0 -r 00bb4cb54fa9 src/mem/ruby/system/System.cc
--- a/src/mem/ruby/system/System.cc Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/System.cc Thu Jan 14 22:17:23 2010 -0800
@@ -60,7 +60,7 @@
int RubySystem::m_random_seed;
bool RubySystem::m_randomization;
int RubySystem::m_tech_nm;
-int RubySystem::m_freq_mhz;
+Tick RubySystem::m_clock;
int RubySystem::m_block_size_bytes;
int RubySystem::m_block_size_bits;
uint64 RubySystem::m_memory_size_bytes;
@@ -93,7 +93,7 @@
srandom(m_random_seed);
m_randomization = p-randomization;
m_tech_nm = p-tech_nm;
-m_freq_mhz = p-freq_mhz;
+m_clock = p-clock;
m_block_size_bytes = p-block_size_bytes;
assert(is_power_of_2(m_block_size_bytes));
@@ -107,6 +107,7 @@
m_profiler_ptr = p-profiler;
m_tracer_ptr = p-tracer;
+g_eventQueue_ptr = new RubyEventQueue(m_clock);
g_system_ptr = this;
m_mem_vec_ptr = new MemoryVector;
m_mem_vec_ptr-setSize(m_memory_size_bytes);
@@ -129,7 +130,7 @@
outrandom_seed: m_random_seed endl;
outrandomization: m_randomization endl;
outtech_nm: m_tech_nm endl;
- outfreq_mhz: m_freq_mhz endl;
+ outcycle_period: m_clock endl;
outblock_size_bytes: m_block_size_bytes endl;
outblock_size_bits: m_block_size_bits endl;
outmemory_size_bytes: m_memory_size_bytes endl;
diff -r 2a756159e6b0 -r 00bb4cb54fa9 src/mem/ruby/system/System.hh
--- a/src/mem/ruby/system/System.hh Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/System.hh Thu Jan 14 22:17:23 2010 -0800
@@ -97,7 +97,6 @@
static int getRandomSeed() { return m_random_seed; }
static int getRandomization() { return m_randomization; }
static int getTechNm() { return m_tech_nm; }
- static int getFreqMhz() { return m_freq_mhz; }
static int getBlockSizeBytes() { return m_block_size_bytes; }
static int getBlockSizeBits() {
[m5-dev] [PATCH 17 of 41] ruby: FS support using the new configuration system
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID ede19abf2fa6f359994660129a0a36d3020116f5
# Parent 78be42cd81cd9aa96c3f8044af8ae7435e7ca5a6
ruby: FS support using the new configuration system
diff -r 78be42cd81cd -r ede19abf2fa6 configs/common/FSConfig.py
--- a/configs/common/FSConfig.pyThu Jan 14 22:17:25 2010 -0800
+++ b/configs/common/FSConfig.pyThu Jan 14 22:17:25 2010 -0800
@@ -79,14 +79,14 @@
return self
-def makeLinuxAlphaRubySystem(mem_mode, rubymem, mdesc = None):
+def makeLinuxAlphaRubySystem(mem_mode, phys_mem, mdesc = None):
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
-self = LinuxAlphaSystem(physmem = rubymem)
+self = LinuxAlphaSystem(physmem = phys_mem)
if not mdesc:
# generic system
mdesc = SysConfig()
@@ -94,7 +94,14 @@
# Create pio bus to connect all device pio ports to rubymem's pio port
self.piobus = Bus(bus_id=0)
-
+
+#
+# Pio functional accesses from devices need direct access to memory
+# RubyPort currently does support functional accesses. Therefore provide
+# the piobus a direct connection to physical memory
+#
+self.piobus.port = phys_mem.port
+
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
@@ -104,13 +111,11 @@
self.tsunami.ide.pio = self.piobus.port
self.tsunami.ethernet.pio = self.piobus.port
-# connect the dma ports directly to ruby dma ports
-self.tsunami.ide.dma = self.physmem.dma_port
-self.tsunami.ethernet.dma = self.physmem.dma_port
+#
+# store the dma devices for later connection to dma ruby ports
+#
+self.dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
-# connect the pio bus to rubymem
-self.physmem.pio_port = self.piobus.port
-
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
diff -r 78be42cd81cd -r ede19abf2fa6 configs/common/Options.py
--- a/configs/common/Options.py Thu Jan 14 22:17:25 2010 -0800
+++ b/configs/common/Options.py Thu Jan 14 22:17:25 2010 -0800
@@ -34,7 +34,9 @@
parser.add_option(--caches, action=store_true)
parser.add_option(--l2cache, action=store_true)
parser.add_option(--fastmem, action=store_true)
-
+parser.add_option(--clock, action=store, type=string, default='1GHz')
+parser.add_option(--num-dirs, type=int, default=1)
+
# Run duration options
parser.add_option(-m, --maxtick, type=int, default=m5.MaxTick,
metavar=T,
diff -r 78be42cd81cd -r ede19abf2fa6 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.pyThu Jan 14 22:17:25 2010 -0800
+++ b/configs/example/ruby_fs.pyThu Jan 14 22:17:25 2010 -0800
@@ -43,10 +43,10 @@
if not buildEnv['FULL_SYSTEM']:
panic(This script requires full-system mode (*_FS).)
-addToPath('../../tests/configs/')
addToPath('../common')
+addToPath('../ruby')
-import ruby_config
+import Ruby
from FSConfig import *
from SysPaths import *
@@ -114,87 +114,25 @@
test_mem_mode = 'timing'
FutureClass = None
-CPUClass.clock = '1GHz'
+CPUClass.clock = options.clock
-#
-# Since we are running in timing mode, set the number of M5 ticks to ruby ticks
-# to the cpu clock frequency
-#
-M5_to_ruby_tick = '1000t'
+physmem = PhysicalMemory()
-np = options.num_cpus
+system = makeLinuxAlphaRubySystem(test_mem_mode, physmem, bm[0])
-# check for max instruction count
-if options.max_inst:
-max_inst = options.max_inst
-else:
-max_inst = 0
-
-# set cache size
-if options.cache_size:
-cache_size = options.cache_size
-else:
-cache_size = 32768 # 32 kB is default
-
-# set cache assoc
-if options.cache_assoc:
-cache_assoc = options.cache_assoc
-else:
-cache_assoc = 8 # 8 is default
-
-# set map levels
-if options.map_levels:
-map_levels = options.map_levels
-else:
-map_levels = 4 # 4 levels is the default
+system.ruby = Ruby.create_system(options,
+ physmem,
+ system.piobus,
+ system.dma_devices)
-if options.protocol == MOESI_hammer:
-ruby_config_file = MOESI_hammer-homogeneous.rb
-elif options.protocol == MOESI_CMP_token:
-ruby_config_file = TwoLevel_SplitL1UnifiedL2.rb
-elif options.protocol == MI_example:
-ruby_config_file = MI_example-homogeneous.rb
-else:
-print Error: unsupported ruby protocol
-sys.exit(1)
+system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
-#
-# Currently, since ruby configuraiton is separate from m5, we need to manually
-# tell ruby that two dma ports are created by
[m5-dev] [PATCH 29 of 41] ruby: Pass pc from the ruby tester
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536246 28800
# Node ID 01bab1b7fc3c1da1d60c386999ba940ed773bab5
# Parent b2581afcdf3c74326fb4f5732874fc2c9be252e3
ruby: Pass pc from the ruby tester
diff -r b2581afcdf3c -r 01bab1b7fc3c src/cpu/rubytest/Check.cc
--- a/src/cpu/rubytest/Check.cc Thu Jan 14 22:17:26 2010 -0800
+++ b/src/cpu/rubytest/Check.cc Thu Jan 14 22:17:26 2010 -0800
@@ -88,7 +88,9 @@
//
Request *req = new Request(m_address.getAddress(),
0,
- flags);
+ flags,
+ curTick,
+ m_pc.getAddress());
Packet::Command cmd;
@@ -146,7 +148,9 @@
//
Request *req = new Request(writeAddr.getAddress(),
1,
- flags);
+ flags,
+ curTick,
+ m_pc.getAddress());
Packet::Command cmd;
@@ -200,7 +204,9 @@
//
Request *req = new Request(m_address.getAddress(),
CHECK_SIZE,
- flags);
+ flags,
+ curTick,
+ m_pc.getAddress());
//
// 50% chance that the request will be an instruction fetch
diff -r b2581afcdf3c -r 01bab1b7fc3c src/mem/request.hh
--- a/src/mem/request.hhThu Jan 14 22:17:26 2010 -0800
+++ b/src/mem/request.hhThu Jan 14 22:17:26 2010 -0800
@@ -194,6 +194,13 @@
setPhys(paddr, size, flags, time);
}
+Request(Addr paddr, int size, Flags flags, Tick time, Addr pc)
+{
+setPhys(paddr, size, flags, time);
+privateFlags.set(VALID_PC);
+_pc = pc;
+}
+
Request(int asid, Addr vaddr, int size, Flags flags, Addr pc,
int cid, ThreadID tid)
{
diff -r b2581afcdf3c -r 01bab1b7fc3c src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Thu Jan 14 22:17:26 2010 -0800
+++ b/src/mem/ruby/system/RubyPort.cc Thu Jan 14 22:17:26 2010 -0800
@@ -177,11 +177,18 @@
// sending them to our assigned ruby port.
//
RubyRequestType type = RubyRequestType_NULL;
+
+//
+// If valid, copy the pc to the ruby request
+//
Addr pc = 0;
+if (pkt-req-hasPC()) {
+pc = pkt-req-getPC();
+}
+
if (pkt-isRead()) {
if (pkt-req-isInstFetch()) {
type = RubyRequestType_IFETCH;
-pc = pkt-req-getPC();
} else {
type = RubyRequestType_LD;
}
___
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[m5-dev] [PATCH 34 of 41] ruby: MI_example updates to use the new config system
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536247 28800
# Node ID c75f4c574f887fa9f03f74244508b802ec8ab085
# Parent 99684e867755307c35e3c61801a49352e2034e31
ruby: MI_example updates to use the new config system
diff -r 99684e867755 -r c75f4c574f88 configs/ruby/MI_example.py
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/configs/ruby/MI_example.pyThu Jan 14 22:17:27 2010 -0800
@@ -0,0 +1,128 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the cache latency is only used by the sequencer on fast path hits
+#
+class Cache(RubyCache):
+latency = 3
+
+def create_system(options, phys_mem, piobus, dma_devices):
+
+if buildEnv['PROTOCOL'] != 'MI_example':
+panic(This script requires the MI_example protocol to be built.)
+
+cpu_sequencers = []
+
+#
+# The ruby network creation expects the list of nodes in the system to be
+# consistent with the NetDest list. Therefore the l1 controller nodes
must be
+# listed before the directory nodes and directory nodes before dma nodes,
etc.
+#
+l1_cntrl_nodes = []
+dir_cntrl_nodes = []
+dma_cntrl_nodes = []
+
+#
+# Must create the individual controllers before the network to ensure the
+# controller constructors are called before the network constructor
+#
+
+for i in xrange(options.num_cpus):
+#
+# First create the Ruby objects associated with this cpu
+# Only one cache exists for this protocol, so by default use the L1D
+# config parameters.
+#
+cache = Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+
+#
+# Only one unified L1 cache exists. Can cache instructions and data.
+#
+cpu_seq = RubySequencer(icache = cache,
+dcache = cache,
+physMemPort = phys_mem.port,
+physmem = phys_mem)
+
+if piobus != None:
+cpu_seq.pio_port = piobus.port
+
+l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ cacheMemory = cache)
+#
+# Add controllers and sequencers to the appropriate lists
+#
+cpu_sequencers.append(cpu_seq)
+l1_cntrl_nodes.append(l1_cntrl)
+
+phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) +
1
+mem_module_size = phys_mem_size / options.num_dirs
+
+for i in xrange(options.num_dirs):
+#
+# Create the Ruby objects associated with the directory controller
+#
+
+mem_cntrl = RubyMemoryControl(version = i)
+
+dir_size = MemorySize('0B')
+dir_size.value = mem_module_size
+
+dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size),
+ memBuffer = mem_cntrl)
+
+dir_cntrl_nodes.append(dir_cntrl)
+
+for i, dma_device in enumerate(dma_devices):
+#
+#
[m5-dev] [PATCH 31 of 41] ruby: Made the RubyTester wakeup frequency configurable
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536247 28800
# Node ID 69b0eb267a9b14f0b02e7114561e4c7de72c2785
# Parent f5f1581d5b7c5d3443cd0792ec20a8bddfc670d5
ruby: Made the RubyTester wakeup frequency configurable
diff -r f5f1581d5b7c -r 69b0eb267a9b configs/example/rubytest.py
--- a/configs/example/rubytest.py Thu Jan 14 22:17:26 2010 -0800
+++ b/configs/example/rubytest.py Thu Jan 14 22:17:27 2010 -0800
@@ -75,7 +75,8 @@
#
# create the tester and system, including ruby
#
-tester = RubyTester(checks_to_complete = options.checks)
+tester = RubyTester(checks_to_complete = options.checks,
+wakeup_frequency = options.wakeup_freq)
system = System(physmem = PhysicalMemory())
diff -r f5f1581d5b7c -r 69b0eb267a9b src/cpu/rubytest/RubyTester.cc
--- a/src/cpu/rubytest/RubyTester.ccThu Jan 14 22:17:26 2010 -0800
+++ b/src/cpu/rubytest/RubyTester.ccThu Jan 14 22:17:27 2010 -0800
@@ -39,7 +39,8 @@
: MemObject(p),
checkStartEvent(this),
m_checks_to_complete(p-checks_to_complete),
-m_deadlock_threshold(p-deadlock_threshold)
+m_deadlock_threshold(p-deadlock_threshold),
+m_wakeup_frequency(p-wakeup_frequency)
{
m_checks_completed = 0;
@@ -167,7 +168,7 @@
checkForDeadlock();
-schedule(checkStartEvent, curTick + 2);
+schedule(checkStartEvent, curTick + m_wakeup_frequency);
} else {
exitSimLoop(Ruby Tester completed);
}
diff -r f5f1581d5b7c -r 69b0eb267a9b src/cpu/rubytest/RubyTester.hh
--- a/src/cpu/rubytest/RubyTester.hhThu Jan 14 22:17:26 2010 -0800
+++ b/src/cpu/rubytest/RubyTester.hhThu Jan 14 22:17:27 2010 -0800
@@ -139,6 +139,7 @@
uint64 m_checks_to_complete;
int m_deadlock_threshold;
int m_num_cpu_sequencers;
+ int m_wakeup_frequency;
};
// Output operator declaration
diff -r f5f1581d5b7c -r 69b0eb267a9b src/cpu/rubytest/RubyTester.py
--- a/src/cpu/rubytest/RubyTester.pyThu Jan 14 22:17:26 2010 -0800
+++ b/src/cpu/rubytest/RubyTester.pyThu Jan 14 22:17:27 2010 -0800
@@ -34,3 +34,4 @@
cpuPort = VectorPort(the cpu ports)
checks_to_complete = Param.Int(100, checks to complete)
deadlock_threshold = Param.Int(5, how often to check for deadlock)
+wakeup_frequency = Param.Int(10, number of cycles between wakeups)
___
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[m5-dev] [PATCH 25 of 41] ruby: Added Cache and MemCntrl profiler calls
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536246 28800
# Node ID 4bacc747d0a2af5b86d133610118264837282987
# Parent 0cafcd0a9c15571a428675f50a6afe33c0277751
ruby: Added Cache and MemCntrl profiler calls
diff -r 0cafcd0a9c15 -r 4bacc747d0a2 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py Thu Jan 14 22:17:26 2010 -0800
+++ b/src/mem/slicc/symbols/StateMachine.py Thu Jan 14 22:17:26 2010 -0800
@@ -236,8 +236,8 @@
void set_atomic(Address addr);
void started_writes();
void clear_atomic();
-void printStats(ostream out) const { s_profiler.dumpStats(out); }
-void clearStats() { s_profiler.clearStats(); }
+void printStats(ostream out) const;
+void clearStats();
private:
''')
@@ -593,6 +593,38 @@
}
}
+void $c_ident::printStats(ostream out) const {
+''')
+#
+# Cache and Memory Controllers have specific profilers associated with
+# them. Print out these stats before dumping state transition stats.
+#
+for param in self.config_parameters:
+if param.type_ast.type.ident == CacheMemory or \
+ param.type_ast.type.ident == MemoryControl:
+assert(param.pointer)
+code('m_${{param.ident}}_ptr-printStats(out);')
+
+code('''
+s_profiler.dumpStats(out);
+}
+
+void $c_ident::clearStats() {
+''')
+#
+# Cache and Memory Controllers have specific profilers associated with
+# them. These stats must be cleared too.
+#
+for param in self.config_parameters:
+if param.type_ast.type.ident == CacheMemory or \
+ param.type_ast.type.ident == MemoryControl:
+assert(param.pointer)
+code('m_${{param.ident}}_ptr-clearStats();')
+
+code('''
+s_profiler.clearStats();
+}
+
// Actions
''')
___
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[m5-dev] [PATCH 41 of 41] ruby: Added a mesh topology
# HG changeset patch # User Brad Beckmann brad.beckm...@amd.com # Date 1263536250 28800 # Node ID 69a46a488db7cd4dbcc6ec681c3dcd2ed549c225 # Parent c5104360b4a1dc8404138adbad93bb9d78b4bae5 ruby: Added a mesh topology diff -r c5104360b4a1 -r 69a46a488db7 configs/common/Options.py --- a/configs/common/Options.py Thu Jan 14 22:17:30 2010 -0800 +++ b/configs/common/Options.py Thu Jan 14 22:17:30 2010 -0800 @@ -37,6 +37,10 @@ parser.add_option(--clock, action=store, type=string, default='1GHz') parser.add_option(--num-dirs, type=int, default=1) parser.add_option(--num-l2caches, type=int, default=1) +parser.add_option(--topology, type=string, default=crossbar, + help='crossbar'|'mesh') +parser.add_option(--mesh-rows, type=int, default=1, + help=the number of rows in the mesh topology) parser.add_option(--garnet-network, type=string, default=none, help='fixed'|'flexible') diff -r c5104360b4a1 -r 69a46a488db7 configs/ruby/Ruby.py --- a/configs/ruby/Ruby.py Thu Jan 14 22:17:30 2010 -0800 +++ b/configs/ruby/Ruby.py Thu Jan 14 22:17:30 2010 -0800 @@ -80,12 +80,22 @@ # Important: the topology constructor must be called before the network # constructor. # +if options.topology == crossbar: +net_topology = makeCrossbar(all_cntrls) +elif options.topology == mesh: +# +# The uniform mesh topology assumes one router per cpu +# +net_topology = makeMesh(all_cntrls, +len(cpu_sequencers), +options.mesh_rows) + if options.garnet_network == fixed: -network = GarnetNetwork_d(topology = makeCrossbar(all_cntrls)) +network = GarnetNetwork_d(topology = net_topology) elif options.garnet_network == flexible: -network = GarnetNetwork(topology = makeCrossbar(all_cntrls)) +network = GarnetNetwork(topology = net_topology) else: -network = SimpleNetwork(topology = makeCrossbar(all_cntrls)) +network = SimpleNetwork(topology = net_topology) # # determine the total memory size of the ruby system and verify it is equal diff -r c5104360b4a1 -r 69a46a488db7 src/mem/ruby/network/Network.py --- a/src/mem/ruby/network/Network.py Thu Jan 14 22:17:30 2010 -0800 +++ b/src/mem/ruby/network/Network.py Thu Jan 14 22:17:30 2010 -0800 @@ -35,6 +35,52 @@ return Topology(ext_links=ext_links, int_links=int_links, num_int_nodes=len(nodes)+1) +def makeMesh(nodes, num_routers, num_rows): +# +# There must be an evenly divisible number of cntrls to routers +# Also, obviously the number or rows must be = the number of routers +# +cntrls_per_router, remainder = divmod(len(nodes), num_routers) +assert(remainder == 0) +assert(num_rows = num_routers) +num_columns = int(num_routers / num_rows) +assert(num_columns * num_rows == num_routers) + +# +# Connect each node to the appropriate router +# +ext_links = [] +for (i, n) in enumerate(nodes): +cntrl_level, router_id = divmod(i, num_routers) +assert(cntrl_level cntrls_per_router) +ext_links.append(ExtLink(ext_node=n, int_node=router_id)) + +# +# Create the mesh links. First row (east-west) links then column +# (north-south) links +# +int_links = [] +for row in xrange(num_rows): +for col in xrange(num_columns): +if (col + 1 num_columns): +east_id = col + (row * num_columns) +west_id = (col + 1) + (row * num_columns) +int_links.append(IntLink(node_a=east_id, + node_b=west_id, + weight=1)) +for col in xrange(num_columns): +for row in xrange(num_rows): +if (row + 1 num_rows): +north_id = col + (row * num_columns) +south_id = col + ((row + 1) * num_columns) +int_links.append(IntLink(node_a=north_id, + node_b=south_id, + weight=2)) + +return Topology(ext_links=ext_links, +int_links=int_links, +num_int_nodes=num_routers) + class RubyNetwork(SimObject): type = 'RubyNetwork' cxx_class = 'Network' ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 21 of 41] ruby: cleaned up ruby profilers
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID 412eb04d0909c94debbe76e07665792e8a0a4a18
# Parent af3701615ac52dc6050d7898b83a2540400eac24
ruby: cleaned up ruby profilers
Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively. Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects. This
simplifies the creation of these profilers.
diff -r af3701615ac5 -r 412eb04d0909 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Thu Jan 14 22:17:25 2010 -0800
+++ b/configs/ruby/MOESI_hammer.py Thu Jan 14 22:17:25 2010 -0800
@@ -74,14 +74,9 @@
#
# First create the Ruby objects associated with this cpu
#
-l1i_profiler = CacheProfiler(description = (l1i_%s_profiler % i))
-l1i_cache = L1Cache(cache_profiler = l1i_profiler)
-
-l1d_profiler = CacheProfiler(description = (l1d_%s_profiler % i))
-l1d_cache = L1Cache(cache_profiler = l1d_profiler)
-
-l2_profiler = CacheProfiler(description = (l2_%s_profiler % i))
-l2_cache = L2Cache(cache_profiler = l2_profiler)
+l1i_cache = L1Cache()
+l1d_cache = L1Cache()
+l2_cache = L2Cache()
cpu_seq = RubySequencer(icache = l1i_cache,
dcache = l1d_cache,
diff -r af3701615ac5 -r 412eb04d0909 configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Thu Jan 14 22:17:25 2010 -0800
+++ b/configs/ruby/Ruby.py Thu Jan 14 22:17:25 2010 -0800
@@ -57,20 +57,7 @@
mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
for dir_cntrl in dir_cntrls])
-#
-# determine the number of memory controllers and other memory controller
-# parameters for the profiler
-#
-mcCount = len(dir_cntrls)
-banksPerRank = dir_cntrls[0].memBuffer.banks_per_rank
-ranksPerDimm = dir_cntrls[0].memBuffer.ranks_per_dimm
-dimmsPerChannel = dir_cntrls[0].memBuffer.dimms_per_channel
-
-ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers),
- mem_cntrl_count = mcCount,
- banks_per_rank = banksPerRank,
- ranks_per_dimm = ranksPerDimm,
- dimms_per_channel = dimmsPerChannel)
+ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers))
ruby = RubySystem(clock = options.clock,
network = network,
diff -r af3701615ac5 -r 412eb04d0909 src/mem/ruby/profiler/CacheProfiler.cc
--- a/src/mem/ruby/profiler/CacheProfiler.ccThu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/profiler/CacheProfiler.ccThu Jan 14 22:17:25 2010 -0800
@@ -43,10 +43,9 @@
#include mem/ruby/profiler/Profiler.hh
#include mem/gems_common/Vector.hh
-CacheProfiler::CacheProfiler(const CacheProfilerParams* params)
- : SimObject(params), m_requestSize(-1)
+CacheProfiler::CacheProfiler(const string description)
{
- m_description = params-description;
+ m_description = description;
m_requestTypeVec_ptr = new Vectorint;
m_requestTypeVec_ptr-setSize(int(CacheRequestType_NUM));
@@ -60,7 +59,7 @@
void CacheProfiler::printStats(ostream out) const
{
- out m_description cache stats: endl;
+ out Cache Stats: m_description endl;
string description =+ m_description;
out description _total_misses: m_misses endl;
@@ -140,9 +139,3 @@
m_hw_prefetches++;
}
}
-
-CacheProfiler *
-CacheProfilerParams::create()
-{
-return new CacheProfiler(this);
-}
diff -r af3701615ac5 -r 412eb04d0909 src/mem/ruby/profiler/CacheProfiler.hh
--- a/src/mem/ruby/profiler/CacheProfiler.hhThu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/profiler/CacheProfiler.hhThu Jan 14 22:17:25 2010 -0800
@@ -46,15 +46,12 @@
#include mem/protocol/PrefetchBit.hh
#include mem/protocol/CacheRequestType.hh
-#include params/CacheProfiler.hh
-
template class TYPE class Vector;
-class CacheProfiler : public SimObject {
+class CacheProfiler {
public:
// Constructors
- typedef CacheProfilerParams Params;
- CacheProfiler(const Params *);
+ CacheProfiler(const string description);
// Destructor
~CacheProfiler();
diff -r af3701615ac5 -r 412eb04d0909 src/mem/ruby/profiler/MemCntrlProfiler.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/src/mem/ruby/profiler/MemCntrlProfiler.cc Thu Jan 14 22:17:25 2010 -0800
@@ -0,0 +1,184 @@
+
+/*
+ * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+
[m5-dev] [PATCH 09 of 41] ruby: Wrapped ruby events into m5 events
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536243 28800
# Node ID bedc07d1355b1d016e93c8a8831274895e5f3741
# Parent 00bb4cb54fa91a68709ce82a878d0b6a724c8950
ruby: Wrapped ruby events into m5 events
Wrapped ruby events using the m5 event object. Removed the prio_heap
from ruby's event queue and instead schedule ruby events on the m5 event
queue.
diff -r 00bb4cb54fa9 -r bedc07d1355b src/mem/ruby/eventqueue/RubyEventQueue.cc
--- a/src/mem/ruby/eventqueue/RubyEventQueue.cc Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/eventqueue/RubyEventQueue.cc Thu Jan 14 22:17:23 2010 -0800
@@ -33,83 +33,35 @@
#include mem/ruby/eventqueue/RubyEventQueue.hh
#include mem/ruby/common/Consumer.hh
-#include mem/ruby/profiler/Profiler.hh
#include mem/ruby/system/System.hh
-#include mem/gems_common/PrioHeap.hh
#include mem/ruby/eventqueue/RubyEventQueueNode.hh
// Class public method definitions
-RubyEventQueue::RubyEventQueue(Tick _clock)
- : m_clock(_clock)
+RubyEventQueue::RubyEventQueue(EventQueue* eventq, Tick _clock)
+ : EventManager(eventq), m_clock(_clock)
{
- m_prio_heap_ptr = NULL;
- init();
- assert(g_eventQueue_ptr == NULL);
- g_eventQueue_ptr = this;
}
RubyEventQueue::~RubyEventQueue()
{
- delete m_prio_heap_ptr;
}
-void RubyEventQueue::init()
-{
- m_globalTime = 1;
- m_timeOfLastRecovery = 1;
- m_prio_heap_ptr = new PrioHeapRubyEventQueueNode;
- m_prio_heap_ptr-init();
-}
-
-bool RubyEventQueue::isEmpty() const
-{
- return (m_prio_heap_ptr-size() == 0);
+void RubyEventQueue::scheduleEvent(Consumer* consumer, Time timeDelta)
+{
+ scheduleEventAbsolute(consumer, timeDelta + getTime());
}
void RubyEventQueue::scheduleEventAbsolute(Consumer* consumer, Time timeAbs)
{
// Check to see if this is a redundant wakeup
- // Time time = timeDelta + m_globalTime;
ASSERT(consumer != NULL);
if (consumer-getLastScheduledWakeup() != timeAbs) {
// This wakeup is not redundant
-RubyEventQueueNode thisNode;
-thisNode.m_consumer_ptr = consumer;
-assert(timeAbs m_globalTime);
-thisNode.m_time = timeAbs;
-m_prio_heap_ptr-insert(thisNode);
-consumer-setLastScheduledWakeup(timeAbs);
- }
-}
-
-void RubyEventQueue::triggerEvents(Time t)
-{
- RubyEventQueueNode thisNode;
-
- while(m_prio_heap_ptr-size() 0 m_prio_heap_ptr-peekMin().m_time = t)
{
-m_globalTime = m_prio_heap_ptr-peekMin().m_time;
-thisNode = m_prio_heap_ptr-extractMin();
-assert(thisNode.m_consumer_ptr != NULL);
-DEBUG_EXPR(EVENTQUEUE_COMP,MedPrio,*(thisNode.m_consumer_ptr));
-DEBUG_EXPR(EVENTQUEUE_COMP,MedPrio,thisNode.m_time);
-thisNode.m_consumer_ptr-triggerWakeup(this);
- }
- m_globalTime = t;
-}
-
-void RubyEventQueue::triggerAllEvents()
-{
- // FIXME - avoid repeated code
- RubyEventQueueNode thisNode;
-
- while(m_prio_heap_ptr-size() 0) {
-m_globalTime = m_prio_heap_ptr-peekMin().m_time;
-thisNode = m_prio_heap_ptr-extractMin();
-assert(thisNode.m_consumer_ptr != NULL);
-DEBUG_EXPR(EVENTQUEUE_COMP,MedPrio,*(thisNode.m_consumer_ptr));
-DEBUG_EXPR(EVENTQUEUE_COMP,MedPrio,thisNode.m_time);
-thisNode.m_consumer_ptr-triggerWakeup(this);
+RubyEventQueueNode *thisNode = new RubyEventQueueNode(consumer);
+assert(timeAbs getTime());
+schedule(thisNode, (timeAbs * m_clock));
+consumer-setLastScheduledWakeup(timeAbs * m_clock);
}
}
@@ -118,5 +70,5 @@
void
RubyEventQueue::print(ostream out) const
{
- out [Event Queue: *m_prio_heap_ptr ];
+ out [Event Queue:];
}
diff -r 00bb4cb54fa9 -r bedc07d1355b src/mem/ruby/eventqueue/RubyEventQueue.hh
--- a/src/mem/ruby/eventqueue/RubyEventQueue.hh Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/eventqueue/RubyEventQueue.hh Thu Jan 14 22:17:23 2010 -0800
@@ -62,15 +62,16 @@
#include config/no_vector_bounds_checks.hh
#include mem/ruby/common/Global.hh
#include mem/gems_common/Vector.hh
+#include sim/eventq.hh
class Consumer;
template class TYPE class PrioHeap;
class RubyEventQueueNode;
-class RubyEventQueue {
+class RubyEventQueue : public EventManager {
public:
// Constructors
- RubyEventQueue(Tick clock);
+ RubyEventQueue(EventQueue* eventq, Tick _clock);
// Destructor
~RubyEventQueue();
@@ -78,28 +79,21 @@
// Public Methods
Time getTime() const { return curTick/m_clock; }
- void scheduleEvent(Consumer* consumer, Time timeDelta) {
scheduleEventAbsolute(consumer, timeDelta + m_globalTime); }
+ void scheduleEvent(Consumer* consumer, Time timeDelta);
void scheduleEventAbsolute(Consumer* consumer, Time timeAbs);
- void triggerEvents(Time t); // called to handle all events = time t
- void triggerAllEvents();
void print(ostream out) const;
- bool isEmpty() const;
- Time getTimeOfLastRecovery() {return m_timeOfLastRecovery;}
- void setTimeOfLastRecovery(Time t) {m_timeOfLastRecovery = t;}
+ void triggerEvents(Time t) { assert(0); }
+ void triggerAllEvents() { assert(0); }
// Private
[m5-dev] [PATCH 10 of 41] ruby: Converted the sequencer deadlock event to m5 eventq
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536244 28800
# Node ID a7113be39b6a4f7ec2398fd87518f49445b1e83f
# Parent bedc07d1355b1d016e93c8a8831274895e5f3741
ruby: Converted the sequencer deadlock event to m5 eventq
diff -r bedc07d1355b -r a7113be39b6a src/mem/ruby/eventqueue/RubyEventQueue.hh
--- a/src/mem/ruby/eventqueue/RubyEventQueue.hh Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/eventqueue/RubyEventQueue.hh Thu Jan 14 22:17:24 2010 -0800
@@ -79,6 +79,7 @@
// Public Methods
Time getTime() const { return curTick/m_clock; }
+ Tick getClock() const { return m_clock; }
void scheduleEvent(Consumer* consumer, Time timeDelta);
void scheduleEventAbsolute(Consumer* consumer, Time timeAbs);
void print(ostream out) const;
diff -r bedc07d1355b -r a7113be39b6a src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/Sequencer.cc Thu Jan 14 22:17:24 2010 -0800
@@ -60,9 +60,8 @@
Sequencer::Sequencer(const Params *p)
-: RubyPort(p)
+: RubyPort(p), deadlockCheckEvent(this)
{
-m_deadlock_check_scheduled = false;
m_outstanding_count = 0;
m_max_outstanding_requests = 0;
@@ -128,9 +127,8 @@
assert(m_outstanding_count == total_outstanding);
if (m_outstanding_count 0) { // If there are still outstanding requests,
keep checking
-g_eventQueue_ptr-scheduleEvent(this, m_deadlock_threshold);
- } else {
-m_deadlock_check_scheduled = false;
+schedule(deadlockCheckEvent,
+ (m_deadlock_threshold * g_eventQueue_ptr-getClock()) + curTick);
}
}
@@ -190,9 +188,8 @@
assert(m_outstanding_count == total_outstanding);
// See if we should schedule a deadlock check
- if (m_deadlock_check_scheduled == false) {
-g_eventQueue_ptr-scheduleEvent(this, m_deadlock_threshold);
-m_deadlock_check_scheduled = true;
+ if (deadlockCheckEvent.scheduled() == false) {
+schedule(deadlockCheckEvent, m_deadlock_threshold);
}
Address line_addr(request-ruby_request.paddr);
diff -r bedc07d1355b -r a7113be39b6a src/mem/ruby/system/Sequencer.hh
--- a/src/mem/ruby/system/Sequencer.hh Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/Sequencer.hh Thu Jan 14 22:17:24 2010 -0800
@@ -124,6 +124,18 @@
bool m_deadlock_check_scheduled;
int m_servicing_atomic;
int m_atomics_counter;
+
+ class SequencerWakeupEvent : public Event
+ {
+ Sequencer *m_sequencer_ptr;
+
+public:
+ SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
+ void process() { m_sequencer_ptr-wakeup(); }
+ const char *description() const { return Sequencer deadlock check; }
+ };
+
+ SequencerWakeupEvent deadlockCheckEvent;
};
// Output operator declaration
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[m5-dev] [PATCH 39 of 41] ruby: MESI_CMP_directory updated to the new config system
# HG changeset patch # User Brad Beckmann brad.beckm...@amd.com # Date 1263536248 28800 # Node ID 8f9794901524089b5b55ceb53f65545224228dfe # Parent 09d89c2eddfe7d505233a4814e1f030917736ca9 ruby: MESI_CMP_directory updated to the new config system diff -r 09d89c2eddfe -r 8f9794901524 configs/ruby/MESI_CMP_directory.py --- /dev/null Thu Jan 01 00:00:00 1970 + +++ b/configs/ruby/MESI_CMP_directory.pyThu Jan 14 22:17:28 2010 -0800 @@ -0,0 +1,152 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2009 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Brad Beckmann + +import math +import m5 +from m5.objects import * +from m5.defines import buildEnv +from m5.util import addToPath + +# +# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# +class L1Cache(RubyCache): +latency = 3 + +# +# Note: the L2 Cache latency is not currently used +# +class L2Cache(RubyCache): +latency = 15 + +def create_system(options, phys_mem, piobus, dma_devices): + +if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': +panic(This script requires the MESI_CMP_directory protocol to be built.) + +cpu_sequencers = [] + +# +# The ruby network creation expects the list of nodes in the system to be +# consistent with the NetDest list. Therefore the l1 controller nodes must be +# listed before the directory nodes and directory nodes before dma nodes, etc. +# +l1_cntrl_nodes = [] +l2_cntrl_nodes = [] +dir_cntrl_nodes = [] +dma_cntrl_nodes = [] + +# +# Must create the individual controllers before the network to ensure the +# controller constructors are called before the network constructor +# + +for i in xrange(options.num_cpus): +# +# First create the Ruby objects associated with this cpu +# +l1i_cache = L1Cache(size = options.l1i_size, +assoc = options.l1i_assoc) +l1d_cache = L1Cache(size = options.l1d_size, +assoc = options.l1d_assoc) + +cpu_seq = RubySequencer(icache = l1i_cache, +dcache = l1d_cache, +physMemPort = phys_mem.port, +physmem = phys_mem) + +if piobus != None: +cpu_seq.pio_port = piobus.port + +l1_cntrl = L1Cache_Controller(version = i, + sequencer = cpu_seq, + L1IcacheMemory = l1i_cache, + L1DcacheMemory = l1d_cache, + l2_select_num_bits = \ +math.log(options.num_l2caches, 2)) +# +# Add controllers and sequencers to the appropriate lists +# +cpu_sequencers.append(cpu_seq) +l1_cntrl_nodes.append(l1_cntrl) + +for i in xrange(options.num_l2caches): +# +# First create the Ruby objects associated with this cpu +# +l2_cache = L2Cache(size = options.l2_size, + assoc = options.l2_assoc) + +l2_cntrl = L2Cache_Controller(version = i, + L2cacheMemory = l2_cache, + N_tokens = n_tokens) + +l2_cntrl_nodes.append(l2_cntrl) + +phys_mem_size = long(phys_mem.range.second) -
[m5-dev] [PATCH 19 of 41] ruby: added ruby stats print
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID 5b8bb9745a6223711954bc629a514419d73cfa81
# Parent 908ff9da9c54903145f1fe5c97d791d590eb2066
ruby: added ruby stats print
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.
diff -r 908ff9da9c54 -r 5b8bb9745a62
src/mem/ruby/network/simple/SimpleNetwork.cc
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc Thu Jan 14 22:17:25
2010 -0800
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc Thu Jan 14 22:17:25
2010 -0800
@@ -225,6 +225,7 @@
for(int i=0; im_switch_ptr_vector.size(); i++) {
m_switch_ptr_vector[i]-printStats(out);
}
+ m_topology_ptr-printStats(out);
}
void SimpleNetwork::clearStats()
@@ -232,6 +233,7 @@
for(int i=0; im_switch_ptr_vector.size(); i++) {
m_switch_ptr_vector[i]-clearStats();
}
+ m_topology_ptr-clearStats();
}
void SimpleNetwork::printConfig(ostream out) const
diff -r 908ff9da9c54 -r 5b8bb9745a62 src/mem/ruby/network/simple/Topology.cc
--- a/src/mem/ruby/network/simple/Topology.cc Thu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/network/simple/Topology.cc Thu Jan 14 22:17:25 2010 -0800
@@ -238,6 +238,20 @@
}
}
+void Topology::printStats(ostream out) const
+{
+for (int cntrl = 0; cntrl m_controller_vector.size(); cntrl++) {
+ m_controller_vector[cntrl]-printStats(out);
+}
+}
+
+void Topology::clearStats()
+{
+for (int cntrl = 0; cntrl m_controller_vector.size(); cntrl++) {
+m_controller_vector[cntrl]-clearStats();
+}
+}
+
void Topology::printConfig(ostream out) const
{
if (m_print_config == false) return;
diff -r 908ff9da9c54 -r 5b8bb9745a62 src/mem/ruby/network/simple/Topology.hh
--- a/src/mem/ruby/network/simple/Topology.hh Thu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/network/simple/Topology.hh Thu Jan 14 22:17:25 2010 -0800
@@ -102,8 +102,8 @@
void initNetworkPtr(Network* net_ptr);
const string getName() { return m_name; }
- void printStats(ostream out) const {}
- void clearStats() {}
+ void printStats(ostream out) const;
+ void clearStats();
void printConfig(ostream out) const;
void print(ostream out) const { out [Topology]; }
diff -r 908ff9da9c54 -r 5b8bb9745a62 src/mem/ruby/system/RubySystem.py
--- a/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:25 2010 -0800
@@ -16,4 +16,5 @@
debug = Param.RubyDebug(the default debug object)
profiler = Param.RubyProfiler();
tracer = Param.RubyTracer();
-
+stats_filename = Param.String(ruby.stats,
+file to which ruby dumps its stats)
diff -r 908ff9da9c54 -r 5b8bb9745a62 src/mem/ruby/system/System.cc
--- a/src/mem/ruby/system/System.cc Thu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/system/System.cc Thu Jan 14 22:17:25 2010 -0800
@@ -56,6 +56,7 @@
//#include mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
//#include mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
#include mem/ruby/system/MemoryControl.hh
+#include base/output.hh
int RubySystem::m_random_seed;
bool RubySystem::m_randomization;
@@ -111,6 +112,12 @@
g_system_ptr = this;
m_mem_vec_ptr = new MemoryVector;
m_mem_vec_ptr-setSize(m_memory_size_bytes);
+
+//
+// Print ruby configuration and stats at exit
+//
+RubyExitCallback* rubyExitCB = new RubyExitCallback(p-stats_filename);
+registerExitCallback(rubyExitCB);
}
@@ -262,9 +269,20 @@
}
#endif
-
RubySystem *
RubySystemParams::create()
{
return new RubySystem(this);
}
+
+/**
+ * virtual process function that is invoked when the callback
+ * queue is executed.
+ */
+void RubyExitCallback::process()
+{
+std::ostream *os = simout.create(stats_filename);
+RubySystem::printConfig(*os);
+*os endl;
+RubySystem::printStats(*os);
+}
diff -r 908ff9da9c54 -r 5b8bb9745a62 src/mem/ruby/system/System.hh
--- a/src/mem/ruby/system/System.hh Thu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/system/System.hh Thu Jan 14 22:17:25 2010 -0800
@@ -48,6 +48,7 @@
#include map
#include sim/sim_object.hh
#include params/RubySystem.hh
+#include base/callback.hh
class Profiler;
class Network;
@@ -203,6 +204,27 @@
return out;
}
+class RubyExitCallback : public Callback
+{
+ private:
+string stats_filename;
+
+ public:
+/**
+ * virtualize the destructor to make sure that the correct one
+ * gets called.
+ */
+
+virtual ~RubyExitCallback() {}
+
+RubyExitCallback(const string _stats_filename)
+{
+ stats_filename = _stats_filename;
+}
+
+virtual void process();
+};
+
#endif //SYSTEM_H
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[m5-dev] [PATCH 37 of 41] ruby: fixed memory fetch bug for persistent requests
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536247 28800
# Node ID 01c7f6873059e7daa8f7fd00e5c39cbf60c2e409
# Parent 061151fda49a35f2d8ba4a20d2ed159c9ed23493
ruby: fixed memory fetch bug for persistent requests
diff -r 061151fda49a -r 01c7f6873059 src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm Thu Jan 14 22:17:27 2010 -0800
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Thu Jan 14 22:17:27 2010 -0800
@@ -61,7 +61,8 @@
// Memory wait states - can block all messages including persistent
requests
O_W, desc=transitioning to Owner, waiting for memory write;
-L_W, desc=transitioning to Locked, waiting for memory read;
+L_O_W, desc=transitioning to Locked, waiting for memory read, could
eventually return to O;
+L_NO_W, desc=transitioning to Locked, waiting for memory read, eventually
return to NO;
DR_L_W, desc=transitioning to Locked underneath a DMA read, waiting for
memory data;
NO_W, desc=transitioning to Not Owner, waiting for memory read;
O_DW_W, desc=transitioning to Owner, waiting for memory before DMA ack;
@@ -571,6 +572,18 @@
}
}
+ action(qp_queueMemoryForPersistent, qp, desc=Queue off-chip fetch
request) {
+enqueue(memQueue_out, MemoryMsg, latency=1) {
+ out_msg.Address := address;
+ out_msg.Type := MemoryRequestType:MEMORY_READ;
+ out_msg.Sender := machineID;
+ out_msg.OriginalRequestorMachId := persistentTable.findSmallest(address);
+ out_msg.MessageSize := MessageSizeType:Request_Control;
+ out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
+ DEBUG_EXPR(out_msg);
+}
+ }
+
action(fd_memoryDma, fd, desc=Queue off-chip fetch request) {
peek(dmaRequestQueue_in, DMARequestMsg) {
enqueue(memQueue_out, MemoryMsg, latency=1) {
@@ -868,8 +881,8 @@
p_popDmaRequestQueue;
}
- transition(O, Lockdown, L_W) {
-qf_queueMemoryFetchRequest;
+ transition(O, Lockdown, L_O_W) {
+qp_queueMemoryForPersistent;
l_popIncomingPersistentQueue;
}
@@ -1059,7 +1072,7 @@
j_popIncomingRequestQueue;
}
- transition({L, DW_L, DR_L, L_W, DR_L_W}, Lockdown) {
+ transition({L, DW_L, DR_L, L_O_W, L_NO_W, DR_L_W}, Lockdown) {
l_popIncomingPersistentQueue;
}
@@ -1089,11 +1102,19 @@
l_popIncomingPersistentQueue;
}
- transition(L_W, Memory_Data, L) {
+ transition({L_NO_W, L_O_W}, Memory_Data, L) {
dd_sendDataWithAllTokensToStarver;
l_popMemQueue;
}
+ transition(L_O_W, {Unlockdown, Own_Lock_or_Unlock}, O_W) {
+l_popIncomingPersistentQueue;
+ }
+
+ transition(L_NO_W, {Unlockdown, Own_Lock_or_Unlock}, NO_W) {
+l_popIncomingPersistentQueue;
+ }
+
transition(DR_L_W, Memory_Data, DR_L) {
dd_sendDataWithAllTokensToStarver;
l_popMemQueue;
@@ -1121,7 +1142,11 @@
ps_tryIssuingPersistentGETSRequest;
}
- transition(O_W, Memory_Ack, O) {
+ //
+ // The O_W + Memory_Data O transistion is confusing, but it can happen if a
+ // presistent request is issued and resolve before memory returns with data
+ //
+ transition(O_W, {Memory_Ack, Memory_Data}, O) {
l_popMemQueue;
}
@@ -1130,19 +1155,23 @@
}
// Blocked states
- transition({NO_W, O_W, L_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR},
{GETX, GETS}) {
+ transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW,
NO_DR}, {GETX, GETS}) {
z_recycleRequest;
}
- transition({NO_W, O_W, L_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW, NO_DR, L,
DW_L, DR_L}, {DMA_READ, DMA_WRITE}) {
+ transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, O_DW_W, O_DR_W, O_DW, NO_DW,
NO_DR, L, DW_L, DR_L}, {DMA_READ, DMA_WRITE}) {
y_recycleDmaRequestQueue;
}
- transition({NO_W, O_W, L_W, DR_L_W, O_DW_W, O_DR_W}, {Data_Owner, Ack_Owner,
Tokens}) {
+ transition({NO_W, O_W, L_O_W, L_NO_W, DR_L_W, O_DW_W, O_DR_W}, {Data_Owner,
Ack_Owner, Tokens}) {
kz_recycleResponse;
}
- transition({NO_W, O_W}, Lockdown, L_W) {
+ transition(NO_W, Lockdown, L_NO_W) {
+l_popIncomingPersistentQueue;
+ }
+
+ transition(O_W, Lockdown, L_O_W) {
l_popIncomingPersistentQueue;
}
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[m5-dev] [PATCH 20 of 41] ruby: Removed RubySystem::getNumberOfSequencers
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID af3701615ac52dc6050d7898b83a2540400eac24
# Parent 5b8bb9745a6223711954bc629a514419d73cfa81
ruby: Removed RubySystem::getNumberOfSequencers
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable
diff -r 5b8bb9745a62 -r af3701615ac5 configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Thu Jan 14 22:17:25 2010 -0800
+++ b/configs/ruby/Ruby.py Thu Jan 14 22:17:25 2010 -0800
@@ -66,7 +66,8 @@
ranksPerDimm = dir_cntrls[0].memBuffer.ranks_per_dimm
dimmsPerChannel = dir_cntrls[0].memBuffer.dimms_per_channel
-ruby_profiler = RubyProfiler(mem_cntrl_count = mcCount,
+ruby_profiler = RubyProfiler(num_of_sequencers = len(cpu_sequencers),
+ mem_cntrl_count = mcCount,
banks_per_rank = banksPerRank,
ranks_per_dimm = ranksPerDimm,
dimms_per_channel = dimmsPerChannel)
diff -r 5b8bb9745a62 -r af3701615ac5 src/mem/ruby/common/Set.cc
--- a/src/mem/ruby/common/Set.ccThu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/common/Set.ccThu Jan 14 22:17:25 2010 -0800
@@ -51,7 +51,8 @@
Set::Set()
{
m_p_nArray = NULL;
- setSize(RubySystem::getNumberOfSequencers());
+ m_nArrayLen = 0;
+ m_nSize = 0;
}
// copy constructor
diff -r 5b8bb9745a62 -r af3701615ac5 src/mem/ruby/profiler/AddressProfiler.cc
--- a/src/mem/ruby/profiler/AddressProfiler.cc Thu Jan 14 22:17:25 2010 -0800
+++ b/src/mem/ruby/profiler/AddressProfiler.cc Thu Jan 14 22:17:25 2010 -0800
@@ -45,15 +45,22 @@
#include mem/ruby/profiler/Profiler.hh
// Helper functions
-static AccessTraceForAddress lookupTraceForAddress(const Address addr,
MapAddress, AccessTraceForAddress* record_map);
-static void printSorted(ostream out, const MapAddress,
AccessTraceForAddress* record_map, string description);
+static AccessTraceForAddress lookupTraceForAddress(const Address addr,
+MapAddress,
+AccessTraceForAddress*
record_map);
-AddressProfiler::AddressProfiler()
+static void printSorted(ostream out,
+int num_of_sequencers,
+const MapAddress, AccessTraceForAddress* record_map,
+string description);
+
+AddressProfiler::AddressProfiler(int num_of_sequencers)
{
m_dataAccessTrace = new MapAddress, AccessTraceForAddress;
m_macroBlockAccessTrace = new MapAddress, AccessTraceForAddress;
m_programCounterAccessTrace = new MapAddress, AccessTraceForAddress;
m_retryProfileMap = new MapAddress, AccessTraceForAddress;
+ m_num_of_sequencers = num_of_sequencers;
clearStats();
}
@@ -88,18 +95,18 @@
out Hot Data Blocks endl;
out --- endl;
out endl;
-printSorted(out, m_dataAccessTrace, block_address);
+printSorted(out, m_num_of_sequencers, m_dataAccessTrace, block_address);
out endl;
out Hot MacroData Blocks endl;
out endl;
out endl;
-printSorted(out, m_macroBlockAccessTrace, macroblock_address);
+printSorted(out, m_num_of_sequencers, m_macroBlockAccessTrace,
macroblock_address);
out Hot Instructions endl;
out endl;
out endl;
-printSorted(out, m_programCounterAccessTrace, pc_address);
+printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace,
pc_address);
}
if (m_all_instructions){
@@ -107,7 +114,7 @@
out All Instructions Profile: endl;
out - endl;
out endl;
-printSorted(out, m_programCounterAccessTrace, pc_address);
+printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace,
pc_address);
out endl;
}
@@ -123,7 +130,7 @@
m_retryProfileHisto.printPercent(out);
out endl;
-printSorted(out, m_retryProfileMap, block_address);
+printSorted(out, m_num_of_sequencers, m_retryProfileMap, block_address);
out endl;
}
@@ -212,7 +219,10 @@
// * Normal Functions **
-static void printSorted(ostream out, const MapAddress,
AccessTraceForAddress* record_map, string description)
+static void printSorted(ostream out,
+int num_of_sequencers,
+const MapAddress, AccessTraceForAddress* record_map,
+string description)
{
const int records_printed = 100;
@@ -241,8 +251,8 @@
// Allows us to track how many lines where touched by n processors
Vectorint64 m_touched_vec;
Vectorint64 m_touched_weighted_vec;
- m_touched_vec.setSize(RubySystem::getNumberOfSequencers()+1);
- m_touched_weighted_vec.setSize(RubySystem::getNumberOfSequencers()+1);
+ m_touched_vec.setSize(num_of_sequencers+1);
+
[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby passed. * build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic passed. See /z/m5/regression/regress-2010-01-15-03:00:01 for details. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
