date:20110319

Re: [m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

2011-03-19 Thread Gabe Black



> On 2011-03-18 18:30:07, Gabe Black wrote:
> > configs/example/se.py, line 83
> > 
> >
> > Splitting on "," would be a little more standard.
> 
> Lisa Hsu wrote:
> True.  I have a moderately good reason for this.  When creating an 
> aggregated checkpoint, the aggregate script makes cpt.b1-b2-b3.X.  So, if 
> you hand your argument over as --bench b1-b2-b3, no finagling is necessary to 
> be able to find the appropriate checkpoint, it just takes the options.bench 
> string and looks for it, exactly the same as a uniprocessor checkpoint 
> restore situation.  Splitting on commas would mean later overwriting the 
> options.bench param to hand over to Simulation.py to find an aggregated 
> checkpoint or doing some other such thing to make things understood.  This 
> just seemed easier, even if it is a little non-traditional.  I'd prefer to 
> keep it this way.

Eh, this seems like optimizing for a coincidence instead of making things work 
like people expect (and other parts of M5 already do). It would also be 
ambiguous if a benchmark had a "-" as part of its name some day.


- Gabe


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/598/#review993
---


On 2011-03-18 16:06:02, Lisa Hsu wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/598/
> ---
> 
> (Updated 2011-03-18 16:06:02)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> se.py: Modify script to make multiprogramming much easier.
> Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 
> and it will
> set up a simulation that instantiates those three workloads.  Only caveat is 
> that now,
> for sanity checking, your -n X must match the number of benches in the list.
> 
> 
> Diffs
> -
> 
>   configs/example/se.py b0ecadb07742 
> 
> Diff: http://reviews.m5sim.org/r/598/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Lisa
> 
>

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[m5-dev] changeset in m5: configs: combine ruby_se.py and se.py to avoid ...

2011-03-19 Thread Lisa Hsu

changeset 89cd8302abd3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=89cd8302abd3
description:
configs: combine ruby_se.py and se.py to avoid all that code duplication

diffstat:

 configs/example/ruby_se.py |  170 -
 configs/example/se.py  |   35 -
 2 files changed, 31 insertions(+), 174 deletions(-)

diffs (249 lines):

diff -r 5cbb0a68dce1 -r 89cd8302abd3 configs/example/ruby_se.py
--- a/configs/example/ruby_se.pySat Mar 19 21:13:02 2011 -0700
+++ /dev/null   Thu Jan 01 00:00:00 1970 +
@@ -1,170 +0,0 @@
-# Copyright (c) 2006-2008 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-
-# Simple test script
-#
-# "m5 test.py"
-
-import os
-import optparse
-import sys
-from os.path import join as joinpath
-
-import m5
-from m5.defines import buildEnv
-from m5.objects import *
-from m5.util import addToPath, panic
-
-if buildEnv['FULL_SYSTEM']:
-panic("This script requires syscall emulation mode (*_SE).")
-
-addToPath('../common')
-addToPath('../ruby')
-
-import Ruby
-
-import Simulation
-from cpu2000 import *
-
-# Get paths we might need.  It's expected this file is in m5/configs/example.
-config_path = os.path.dirname(os.path.abspath(__file__))
-config_root = os.path.dirname(config_path)
-m5_root = os.path.dirname(config_root)
-
-parser = optparse.OptionParser()
-
-# Benchmark options
-parser.add_option("-c", "--cmd",
-default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
-help="The binary to run in syscall emulation mode.")
-parser.add_option("-o", "--options", default="",
-help='The options to pass to the binary, use " " around the entire string')
-parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
-parser.add_option("--output", default="", help="Redirect stdout to a file.")
-parser.add_option("--errout", default="", help="Redirect stderr to a file.")
-
-#
-# Add the ruby specific and protocol specific options
-#
-Ruby.define_options(parser)
-
-execfile(os.path.join(config_root, "common", "Options.py"))
-
-(options, args) = parser.parse_args()
-
-if args:
-print "Error: script doesn't take any positional arguments"
-sys.exit(1)
-
-if options.bench:
-try:
-if buildEnv['TARGET_ISA'] != 'alpha':
-print >>sys.stderr, "Simpoints code only works for Alpha ISA at 
this time"
-sys.exit(1)
-exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
-process = workload.makeLiveProcess()
-except:
-print >>sys.stderr, "Unable to find workload for %s" % options.bench
-sys.exit(1)
-else:
-process = LiveProcess()
-process.executable = options.cmd
-process.cmd = [options.cmd] + options.options.split()
-
-
-if options.input != "":
-process.input = options.input
-if options.output != "":
-process.output = options.output
-if options.errout != "":
-process.errout = options.errout
-
-if options.detailed:
-#check for SMT workload
-workloads = options.cmd.split(';')
-if len(workloads) > 1:
-process = []
-smt_idx = 0
-inputs = []
-outputs = []
-errouts = []
-
-if options.input != "":
-inputs = options.input.split(';')
-if options.output != "":
-outputs = options.output.split(';')
-if options.errout != "":
-errouts = options.errout.split(';')
-
-f

[m5-dev] changeset in m5: enable x86 workloads on se.py

2011-03-19 Thread Lisa Hsu

changeset 5cbb0a68dce1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5cbb0a68dce1
description:
enable x86 workloads on se.py

diffstat:

 configs/example/se.py |  10 +-
 1 files changed, 5 insertions(+), 5 deletions(-)

diffs (22 lines):

diff -r f596091c854d -r 5cbb0a68dce1 configs/example/se.py
--- a/configs/example/se.py Sat Mar 19 21:12:59 2011 -0700
+++ b/configs/example/se.py Sat Mar 19 21:13:02 2011 -0700
@@ -87,13 +87,13 @@
 
 for app in apps:
 try:
-if buildEnv['TARGET_ISA'] != 'alpha':
-print >>sys.stderr, "Simpoints code only works for Alpha ISA 
at this time"
-sys.exit(1)
-exec("workload = %s('alpha', 'tru64', 'ref')" % app)
+if buildEnv['TARGET_ISA'] == 'alpha':
+exec("workload = %s('alpha', 'tru64', 'ref')" % app)
+else:
+exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % 
app)
 multiprocesses.append(workload.makeLiveProcess())
 except:
-print >>sys.stderr, "Unable to find workload for %s" % app
+print >>sys.stderr, "Unable to find workload for %s: %s" % 
(buildEnv['TARGET_ISA'], app)
 sys.exit(1)
 else:
 process = LiveProcess()
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[m5-dev] changeset in m5: util: update aggregator to handle x86 checkpoi...

2011-03-19 Thread Lisa Hsu

changeset c40d598146ec in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c40d598146ec
description:
util:  update aggregator to handle x86 checkpoints.
Also, make update to understand some of the newer serialized variables

diffstat:

 util/checkpoint_aggregator.py |  71 --
 1 files changed, 40 insertions(+), 31 deletions(-)

diffs (119 lines):

diff -r 5955406f7ed0 -r c40d598146ec util/checkpoint_aggregator.py
--- a/util/checkpoint_aggregator.py Sat Mar 19 18:34:59 2011 -0500
+++ b/util/checkpoint_aggregator.py Sat Mar 19 21:12:55 2011 -0700
@@ -1,4 +1,5 @@
 # Copyright (c) 2009 The Regents of The University of Michigan
+# Copyright (c) 2011 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -84,22 +85,30 @@
 merged.set(newsec, "M5_pid", i)
 
 items = config.items(sec)
-for item in items:
-if item[0] == "ppn":
-if config.getint(sec, "tag") != 0:
-merged.set(newsec, item[0], int(item[1]) + 
page_ptr)
-continue
-elif item[0] == "asn":
-tmp = 
re.compile("(.*).Entry(\d+)").search(sec).groups()
-if config.has_option(tmp[0], "nlu"):
-size = config.getint(tmp[0], "nlu")
-if int(tmp[1]) < size:
+if options.alpha:
+for item in items:
+if item[0] == "ppn":
+if config.getint(sec, "tag") != 0:
+merged.set(newsec, item[0], int(item[1]) + 
page_ptr)
+continue
+elif item[0] == "asn":
+tmp = 
re.compile("(.*).Entry(\d+)").search(sec).groups()
+if config.has_option(tmp[0], "nlu"):
+size = config.getint(tmp[0], "nlu")
+if int(tmp[1]) < size:
+merged.set(newsec, item[0], i)
+continue
+else:
 merged.set(newsec, item[0], i)
 continue
-else:
-merged.set(newsec, item[0], i)
+merged.set(newsec, item[0], item[1])
+else:a #x86
+for item in items:
+if item[0] == "paddr":
+merged.set(newsec, item[0], int(item[1]) + 
(page_ptr << 12))
 continue
-merged.set(newsec, item[0], item[1])
+merged.set(newsec, item[0], item[1])
+
 elif sec == "system":
 pass
 elif sec == "Globals":
@@ -117,17 +126,20 @@
 elif item[0] == "numevents":
 merged.optionxform(str("numEvents"))
 
-page_ptr = page_ptr + int(config.get("system", "page_ptr"))
+page_ptr = page_ptr + int(config.get("system", "pagePtr"))
 
 ### memory stuff
 f = open(cpts[i] + "/system.physmem.physmem", "rb")
 gf = gzip.GzipFile(fileobj=f, mode="rb")
-pages = int(config.get("system", "page_ptr"))
+pages = int(config.get("system", "pagePtr"))
 print "pages to be read: ", pages
 
 x = 0
 while x < pages:
-bytesRead = gf.read(1 << 13)
+if options.alpha:
+bytesRead = gf.read(1 << 13)
+else: #x86
+bytesRead = gf.read(1 << 12)
 merged_mem.write(bytesRead)
 x += 1
 
@@ -135,22 +147,15 @@
 f.close()
 
 merged.add_section("system")
-merged.set("system", "page_ptr", page_ptr)
+merged.set("system", "pagePtr", page_ptr)
+merged.set("system", "nextPID", len(args))
+
 print "WARNING: "
-print "Make sure the simulation using this checkpoint has at least "
-if page_ptr > (1<<20):
-print "8G ",
-elif page_ptr > (1<<19):
-print "4G ",
-elif page_ptr > (1<<18):
-print "2G ",
-elif page_ptr > (1<<17):
-print "1G ",
-elif page_ptr > (1<<16):
-print "512KB ",
-else:
-print "this is a small sim, you're probably fine",
-print "of memory."
+print "Make sure the simulation using this checkpoint has at least ",
+if options.alpha:
+print page_ptr, "x 8K of memory"
+else:  # assume x86
+print page_ptr, "x 4K of memory"
 
 merged.add_section("Globals")
 merged.set("Globals", "curTick", max_curtick)
@@ -166,6 +171,10 @@
 
 parser = optparse.OptionParser()
 parser.add_option("--prefix", type="string", de

[m5-dev] changeset in m5: se.py: Modify script to make multiprogramming m...

2011-03-19 Thread Lisa Hsu

changeset f596091c854d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f596091c854d
description:
se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench 
bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads.  Only 
caveat is that now,
for sanity checking, your -n X must match the number of benches in the 
list.

diffstat:

 configs/example/se.py |  28 +++-
 1 files changed, 19 insertions(+), 9 deletions(-)

diffs (51 lines):

diff -r c40d598146ec -r f596091c854d configs/example/se.py
--- a/configs/example/se.py Sat Mar 19 21:12:55 2011 -0700
+++ b/configs/example/se.py Sat Mar 19 21:12:59 2011 -0700
@@ -76,20 +76,30 @@
 print "Error: script doesn't take any positional arguments"
 sys.exit(1)
 
+multiprocesses = []
+apps = []
+
 if options.bench:
-try:
-if buildEnv['TARGET_ISA'] != 'alpha':
-print >>sys.stderr, "Simpoints code only works for Alpha ISA at 
this time"
+apps = options.bench.split("-")
+if len(apps) != options.num_cpus:
+print "number of benchmarks not equal to set num_cpus!"
+sys.exit(1)
+
+for app in apps:
+try:
+if buildEnv['TARGET_ISA'] != 'alpha':
+print >>sys.stderr, "Simpoints code only works for Alpha ISA 
at this time"
+sys.exit(1)
+exec("workload = %s('alpha', 'tru64', 'ref')" % app)
+multiprocesses.append(workload.makeLiveProcess())
+except:
+print >>sys.stderr, "Unable to find workload for %s" % app
 sys.exit(1)
-exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
-process = workload.makeLiveProcess()
-except:
-print >>sys.stderr, "Unable to find workload for %s" % options.bench
-sys.exit(1)
 else:
 process = LiveProcess()
 process.executable = options.cmd
 process.cmd = [options.cmd] + options.options.split()
+multiprocesses.append(process)
 
 
 if options.input != "":
@@ -151,7 +161,7 @@
 CacheConfig.config_cache(options, system)
 
 for i in xrange(np):
-system.cpu[i].workload = process
+system.cpu[i].workload = multiprocesses[i]
 
 if options.fastmem:
 system.cpu[0].physmem_port = system.physmem.port
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[m5-dev] changeset in m5: Ruby: Convert CacheRequestType to RubyRequestType

2011-03-19 Thread Nilay Vaish

changeset 5955406f7ed0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5955406f7ed0
description:
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request 
type.

diffstat:

 src/mem/protocol/MESI_CMP_directory-L1cache.sm  |  12 ++--
 src/mem/protocol/MI_example-cache.sm|  10 +-
 src/mem/protocol/MOESI_CMP_directory-L1cache.sm |  12 ++--
 src/mem/protocol/MOESI_CMP_token-L1cache.sm |  24 
 src/mem/protocol/MOESI_hammer-cache.sm  |  14 ++--
 src/mem/protocol/RubySlicc_Exports.sm   |  28 ++
 src/mem/ruby/profiler/AccessTraceForAddress.cc  |   8 +-
 src/mem/ruby/profiler/AccessTraceForAddress.hh  |   4 +-
 src/mem/ruby/profiler/AddressProfiler.cc|   6 +-
 src/mem/ruby/profiler/AddressProfiler.hh|   2 +-
 src/mem/ruby/profiler/CacheProfiler.cc  |  12 ++--
 src/mem/ruby/profiler/CacheProfiler.hh  |   4 +-
 src/mem/ruby/profiler/Profiler.cc   |   8 +-
 src/mem/ruby/profiler/Profiler.hh   |   4 +-
 src/mem/ruby/recorder/CacheRecorder.hh  |   2 +-
 src/mem/ruby/recorder/Tracer.hh |   2 +-
 src/mem/ruby/slicc_interface/RubyRequest.cc |  63 -
 src/mem/ruby/slicc_interface/RubyRequest.hh |  18 +--
 src/mem/ruby/slicc_interface/RubySlicc_Util.hh  |   2 +-
 src/mem/ruby/system/CacheMemory.cc  |  16 +++---
 src/mem/ruby/system/CacheMemory.hh  |   6 +-
 src/mem/ruby/system/DMASequencer.cc |  10 +---
 src/mem/ruby/system/Sequencer.cc|  16 +++---
 src/mem/ruby/system/Sequencer.hh|   4 +-
 24 files changed, 103 insertions(+), 184 deletions(-)

diffs (truncated from 786 to 300 lines):

diff -r b043c0efa024 -r 5955406f7ed0 
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.smSat Mar 19 18:34:37 
2011 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.smSat Mar 19 18:34:59 
2011 -0500
@@ -183,15 +183,15 @@
 }
   }
 
-  Event mandatory_request_type_to_event(CacheRequestType type) {
-if (type == CacheRequestType:LD) {
+  Event mandatory_request_type_to_event(RubyRequestType type) {
+if (type == RubyRequestType:LD) {
   return Event:Load;
-} else if (type == CacheRequestType:IFETCH) {
+} else if (type == RubyRequestType:IFETCH) {
   return Event:Ifetch;
-} else if ((type == CacheRequestType:ST) || (type == 
CacheRequestType:ATOMIC)) {
+} else if ((type == RubyRequestType:ST) || (type == 
RubyRequestType:ATOMIC)) {
   return Event:Store;
 } else {
-  error("Invalid CacheRequestType");
+  error("Invalid RubyRequestType");
 }
   }
 
@@ -273,7 +273,7 @@
 
 // Check for data access to blocks in I-cache and ifetchs to blocks in 
D-cache
 
-if (in_msg.Type == CacheRequestType:IFETCH) {
+if (in_msg.Type == RubyRequestType:IFETCH) {
   // ** INSTRUCTION ACCESS ***
 
   Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
diff -r b043c0efa024 -r 5955406f7ed0 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm  Sat Mar 19 18:34:37 2011 -0500
+++ b/src/mem/protocol/MI_example-cache.sm  Sat Mar 19 18:34:59 2011 -0500
@@ -84,15 +84,15 @@
   }
 
   // FUNCTIONS
-  Event mandatory_request_type_to_event(CacheRequestType type) {
-   if (type == CacheRequestType:LD) {
+  Event mandatory_request_type_to_event(RubyRequestType type) {
+   if (type == RubyRequestType:LD) {
   return Event:Load;
-} else if (type == CacheRequestType:IFETCH) {
+} else if (type == RubyRequestType:IFETCH) {
   return Event:Ifetch;
-} else if ((type == CacheRequestType:ST) || (type == 
CacheRequestType:ATOMIC)) {
+} else if ((type == RubyRequestType:ST) || (type == 
RubyRequestType:ATOMIC)) {
   return Event:Store;
 } else {
-  error("Invalid CacheRequestType");
+  error("Invalid RubyRequestType");
 }
   }
 
diff -r b043c0efa024 -r 5955406f7ed0 
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm   Sat Mar 19 18:34:37 
2011 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm   Sat Mar 19 18:34:59 
2011 -0500
@@ -194,15 +194,15 @@
 }
   }
 
-  Event mandatory_request_type_to_event(CacheRequestType type) {
-if (type == CacheRequestType:LD) {
+  Event mandatory_request_type_to_event(RubyRequestType type) {
+if (type == RubyRequestType:LD) {
   return Event:Load;
-} else if (type == CacheRequestType:IFETCH) {
+} else if (type == RubyRequestType:IFETCH) {
   return Event:Ifetch;
-} else if ((type == CacheRequestType:ST) || (type == 
CacheRequestType:ATOMIC)) {
+} else if ((type == RubyRequestType:ST) || (type == 
RubyRequestType:ATOMIC)) {

[m5-dev] changeset in m5: Ruby: Convert AccessModeType to RubyAccessMode

2011-03-19 Thread Nilay Vaish

changeset b043c0efa024 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b043c0efa024
description:
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.

diffstat:

 src/cpu/testers/rubytest/Check.cc  |   2 +-
 src/cpu/testers/rubytest/Check.hh  |   4 ++--
 src/mem/protocol/MESI_CMP_directory-msg.sm |   2 +-
 src/mem/protocol/MOESI_CMP_directory-msg.sm|   2 +-
 src/mem/protocol/MOESI_CMP_token-L1cache.sm|   2 +-
 src/mem/protocol/MOESI_CMP_token-dir.sm|   8 
 src/mem/protocol/MOESI_CMP_token-msg.sm|   4 ++--
 src/mem/protocol/RubySlicc_Exports.sm  |  13 +++--
 src/mem/protocol/RubySlicc_Types.sm|   2 +-
 src/mem/ruby/profiler/AccessTraceForAddress.cc |   4 ++--
 src/mem/ruby/profiler/AccessTraceForAddress.hh |   4 ++--
 src/mem/ruby/profiler/AddressProfiler.cc   |   6 +++---
 src/mem/ruby/profiler/AddressProfiler.hh   |   2 +-
 src/mem/ruby/profiler/CacheProfiler.cc |  12 ++--
 src/mem/ruby/profiler/CacheProfiler.hh |  10 +-
 src/mem/ruby/profiler/Profiler.hh  |   2 +-
 src/mem/ruby/slicc_interface/RubyRequest.hh|   8 +---
 src/mem/ruby/system/CacheMemory.cc |   2 +-
 src/mem/ruby/system/CacheMemory.hh |   2 +-
 src/mem/ruby/system/Sequencer.cc   |  10 +-
 src/mem/ruby/system/Sequencer.hh   |   4 ++--
 21 files changed, 50 insertions(+), 55 deletions(-)

diffs (truncated from 471 to 300 lines):

diff -r 19a654839a04 -r b043c0efa024 src/cpu/testers/rubytest/Check.cc
--- a/src/cpu/testers/rubytest/Check.cc Sat Mar 19 14:17:48 2011 -0700
+++ b/src/cpu/testers/rubytest/Check.cc Sat Mar 19 18:34:37 2011 -0500
@@ -44,7 +44,7 @@
 pickInitiatingNode();
 changeAddress(address);
 m_pc = pc;
-m_access_mode = AccessModeType(random() % AccessModeType_NUM);
+m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);
 m_store_count = 0;
 }
 
diff -r 19a654839a04 -r b043c0efa024 src/cpu/testers/rubytest/Check.hh
--- a/src/cpu/testers/rubytest/Check.hh Sat Mar 19 14:17:48 2011 -0700
+++ b/src/cpu/testers/rubytest/Check.hh Sat Mar 19 18:34:37 2011 -0500
@@ -33,7 +33,7 @@
 #include 
 
 #include "cpu/testers/rubytest/RubyTester.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/TesterStatus.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
@@ -73,7 +73,7 @@
 NodeID m_initiatingNode;
 Address m_address;
 Address m_pc;
-AccessModeType m_access_mode;
+RubyAccessMode m_access_mode;
 int m_num_cpu_sequencers;
 RubyTester* m_tester_ptr;
 };
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MESI_CMP_directory-msg.sm
--- a/src/mem/protocol/MESI_CMP_directory-msg.smSat Mar 19 14:17:48 
2011 -0700
+++ b/src/mem/protocol/MESI_CMP_directory-msg.smSat Mar 19 18:34:37 
2011 -0500
@@ -62,7 +62,7 @@
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
   Address Address,  desc="Physical address for this request";
   CoherenceRequestType Type,desc="Type of request (GetS, GetX, PutX, etc)";
-  AccessModeType AccessMode,desc="user/supervisor access type";
+  RubyAccessMode AccessMode,desc="user/supervisor access type";
   MachineID Requestor  ,desc="What component request";
   NetDest Destination,  desc="What components receive the request, 
includes MachineType and num";
   MessageSizeType MessageSize,  desc="size category of the message";
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MOESI_CMP_directory-msg.sm
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm   Sat Mar 19 14:17:48 
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm   Sat Mar 19 18:34:37 
2011 -0500
@@ -84,7 +84,7 @@
   DataBlock DataBlk,   desc="data for the cache line (DMA WRITE 
request)";
   int Acks,desc="How many acks to expect";
   MessageSizeType MessageSize, desc="size category of the message";
-  AccessModeType AccessMode,desc="user/supervisor access type";
+  RubyAccessMode AccessMode,desc="user/supervisor access type";
   PrefetchBit Prefetch, desc="Is this a prefetch request";
 }
 
diff -r 19a654839a04 -r b043c0efa024 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm   Sat Mar 19 14:17:48 
2011 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm   Sat Mar 19 18:34:37 
2011 -0500
@@ -149,7 +149,7 @@
 
 AccessType AccessType,desc="Type of request (used for 
profiling)";
 Time IssueTime,   desc="Time the request was issued";
-AccessModeType AccessMode,desc="user/supervisor access type";
+RubyAccessMode

Re: [m5-dev] Review Request: enable x86 workloads on se.py

2011-03-19 Thread Lisa Hsu



> On 2011-03-18 16:50:14, Ali Saidi wrote:
> > configs/example/se.py, line 92
> > 
> >
> > Why not just change this to exec("workload = %s(buildEnv['TARGET_ISA'], 
> > 'linux', 'ref')" % app) ? I realize that alpha is a special case with 
> > tru64, but everything else is linux.
> >

Good point.  I'll make the change.


- Lisa


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---


On 2011-03-18 16:06:35, Lisa Hsu wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/599/
> ---
> 
> (Updated 2011-03-18 16:06:35)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> enable x86 workloads on se.py
> 
> 
> Diffs
> -
> 
>   configs/example/se.py b0ecadb07742 
> 
> Diff: http://reviews.m5sim.org/r/599/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Lisa
> 
>

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Re: [m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

2011-03-19 Thread Lisa Hsu

> On 2011-03-18 18:30:07, Gabe Black wrote:
> > configs/example/se.py, line 83
> > 
> >
> > Splitting on "," would be a little more standard.

True.  I have a moderately good reason for this.  When creating an aggregated 
checkpoint, the aggregate script makes cpt.b1-b2-b3.X.  So, if you hand 
your argument over as --bench b1-b2-b3, no finagling is necessary to be able to 
find the appropriate checkpoint, it just takes the options.bench string and 
looks for it, exactly the same as a uniprocessor checkpoint restore situation.  
Splitting on commas would mean later overwriting the options.bench param to 
hand over to Simulation.py to find an aggregated checkpoint or doing some other 
such thing to make things understood.  This just seemed easier, even if it is a 
little non-traditional.  I'd prefer to keep it this way.

- Lisa

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---

On 2011-03-18 16:06:02, Lisa Hsu wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/598/
> ---
> 
> (Updated 2011-03-18 16:06:02)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> se.py: Modify script to make multiprogramming much easier.
> Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 
> and it will
> set up a simulation that instantiates those three workloads.  Only caveat is 
> that now,
> for sanity checking, your -n X must match the number of benches in the list.
> 
> 
> Diffs
> -
> 
>   configs/example/se.py b0ecadb07742 
> 
> Diff: http://reviews.m5sim.org/r/598/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Lisa
> 
>

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Re: [m5-dev] Review Request: configs: combine ruby_se.py and se.py to avoid all that code duplication

2011-03-19 Thread Lisa Hsu



> On 2011-03-18 18:17:54, Gabe Black wrote:
> > configs/example/se.py, line 160
> > 
> >
> > I applaud getting rid of the duplication, but isn't it a little 
> > dangerous here to set up a fake TimingSimpleCPU class and to ignore the 
> > se.py options? Maybe you should have a warning if the options don't match 
> > what you're forcing? That would avoid any potential confusion.
> > 
> > Alternatively it might make sense to factor out the common parts of 
> > this script into a bunch of stuff that other people can use in an se.py 
> > like script of their own. That would be nice in the long term, but getting 
> > rid of all that code is still great right now.

Yeah, that's true, though the original ruby_se.py did the same thing.  I'll put 
in a warning if there's a mismatch.


- Lisa


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---


On 2011-03-18 16:06:49, Lisa Hsu wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/600/
> ---
> 
> (Updated 2011-03-18 16:06:49)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> configs: combine ruby_se.py and se.py to avoid all that code duplication
> 
> 
> Diffs
> -
> 
>   configs/example/ruby_se.py b0ecadb07742 
>   configs/example/se.py b0ecadb07742 
> 
> Diff: http://reviews.m5sim.org/r/600/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Lisa
> 
>

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[m5-dev] changeset in m5: Ruby: dma retry fix

2011-03-19 Thread Brad Beckmann

changeset 5f69f1b0039e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5f69f1b0039e
description:
Ruby: dma retry fix

This patch fixes the problem where Ruby would fail to call sendRetry on 
ports
after it nacked the port.  This patch is particularly helpful for 
bursty dma
requests which often include several packets.

diffstat:

 src/mem/ruby/system/DMASequencer.cc |   8 ++--
 src/mem/ruby/system/RubyPort.cc |  24 +---
 2 files changed, 23 insertions(+), 9 deletions(-)

diffs (56 lines):

diff -r ebb373fcb206 -r 5f69f1b0039e src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc   Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/ruby/system/DMASequencer.cc   Sat Mar 19 14:17:48 2011 -0700
@@ -116,9 +116,13 @@
 assert(m_is_busy == true);
 active_request.bytes_completed = active_request.bytes_issued;
 if (active_request.len == active_request.bytes_completed) {
-DPRINTF(RubyDma, "DMA request completed\n"); 
+//
+// Must unset the busy flag before calling back the dma port because
+// the callback may cause a previously nacked request to be reissued
+//
+DPRINTF(RubyDma, "DMA request completed\n");
+m_is_busy = false;
 ruby_hit_callback(active_request.pkt);
-m_is_busy = false;
 return;
 }
 
diff -r ebb373fcb206 -r 5f69f1b0039e src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc   Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/ruby/system/RubyPort.cc   Sat Mar 19 14:17:48 2011 -0700
@@ -305,16 +305,26 @@
 // likely has free resources now.
 //
 if (waitingOnSequencer) {
-for (std::list::iterator i = retryList.begin();
- i != retryList.end(); ++i) {
-(*i)->sendRetry();
-(*i)->onRetryList(false);
-DPRINTF(MemoryAccess,
+//
+// Record the current list of ports to retry on a temporary list before
+// calling sendRetry on those ports.  sendRetry will cause an 
+// immediate retry, which may result in the ports being put back on the
+// list. Therefore we want to clear the retryList before calling
+// sendRetry.
+//
+std::list curRetryList(retryList);
+
+retryList.clear();
+waitingOnSequencer = false;
+
+for (std::list::iterator i = curRetryList.begin();
+ i != curRetryList.end(); ++i) {
+DPRINTF(RubyPort,
 "Sequencer may now be free.  SendRetry to port %s\n",
 (*i)->name());
+(*i)->onRetryList(false);
+(*i)->sendRetry();
 }
-retryList.clear();
-waitingOnSequencer = false;
 }
 }
 
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[m5-dev] changeset in m5: MOESI_hammer: minor fixes to full-bit dir

2011-03-19 Thread Brad Beckmann

changeset 19a654839a04 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19a654839a04
description:
MOESI_hammer: minor fixes to full-bit dir

diffstat:

 src/mem/protocol/MOESI_hammer-dir.sm |  8 +---
 1 files changed, 5 insertions(+), 3 deletions(-)

diffs (39 lines):

diff -r 5f69f1b0039e -r 19a654839a04 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm  Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/protocol/MOESI_hammer-dir.sm  Sat Mar 19 14:17:48 2011 -0700
@@ -186,7 +186,7 @@
   }
 
   PfEntry getProbeFilterEntry(Address addr), return_by_pointer="yes" {
-if(probe_filter_enabled) {
+if (probe_filter_enabled || full_bit_dir_enabled) {
   PfEntry pfEntry := static_cast(PfEntry, "pointer", 
probeFilter.lookup(addr));
   return pfEntry;
 }
@@ -200,8 +200,6 @@
   if (probe_filter_enabled || full_bit_dir_enabled) {
 if (is_valid(pf_entry)) {
   assert(pf_entry.PfState == getDirectoryEntry(addr).DirectoryState);
-} else {
-  assert(getDirectoryEntry(addr).DirectoryState == State:E);
 }
   }
   return getDirectoryEntry(addr).DirectoryState;
@@ -219,6 +217,9 @@
   if (state == State:NX || state == State:NO || state == State:S || state 
== State:O) {
 assert(is_valid(pf_entry));
   }
+  if (state == State:E) {
+assert(is_valid(pf_entry) == false);
+  }
 }
 if (state == State:E || state == State:NX || state == State:NO || state == 
State:S || 
 state == State:O) {
@@ -469,6 +470,7 @@
   peek(requestQueue_in, RequestMsg) {
 set_cache_entry(probeFilter.allocate(address, new PfEntry));
 cache_entry.Owner := in_msg.Requestor;
+cache_entry.Sharers.setSize(machineCount(MachineType:L1Cache));
   }
 }
   }
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[m5-dev] changeset in m5: RubyPort: minor fixes to trace flag and dprintfs

2011-03-19 Thread Brad Beckmann

changeset ebb373fcb206 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ebb373fcb206
description:
RubyPort: minor fixes to trace flag and dprintfs

diffstat:

 src/mem/SConscript  |   4 ++--
 src/mem/ruby/system/RubyPort.cc |  30 +++---
 2 files changed, 17 insertions(+), 17 deletions(-)

diffs (141 lines):

diff -r 0b3252d3b400 -r ebb373fcb206 src/mem/SConscript
--- a/src/mem/SConscriptSat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/SConscriptSat Mar 19 14:17:48 2011 -0700
@@ -66,12 +66,12 @@
 TraceFlag('RubyGenerated')
 TraceFlag('RubyMemory')
 TraceFlag('RubyNetwork')
+TraceFlag('RubyPort')
 TraceFlag('RubyQueue')
-TraceFlag('RubyPort')
 TraceFlag('RubySlicc')
 TraceFlag('RubyStorebuffer')
 TraceFlag('RubyTester')
 
 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
 'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', 
-'RubyMemory', 'RubyDma'])
+'RubyMemory', 'RubyDma', 'RubyPort'])
diff -r 0b3252d3b400 -r ebb373fcb206 src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc   Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/ruby/system/RubyPort.cc   Sat Mar 19 14:17:48 2011 -0700
@@ -103,7 +103,7 @@
RubyPort *_port)
 : SimpleTimingPort(_name, _port)
 {
-DPRINTF(Ruby, "creating port to ruby sequencer to cpu %s\n", _name);
+DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name);
 ruby_port = _port;
 }
 
@@ -111,7 +111,7 @@
  RubyPort *_port, bool _access_phys_mem)
 : SimpleTimingPort(_name, _port)
 {
-DPRINTF(Ruby, "creating port from ruby sequcner to cpu %s\n", _name);
+DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name);
 ruby_port = _port;
 _onRetryList = false;
 access_phys_mem = _access_phys_mem;
@@ -137,7 +137,7 @@
 {
 // In FS mode, ruby memory will receive pio responses from devices
 // and it must forward these responses back to the particular CPU.
-DPRINTF(MemoryAccess,  "Pio response for address %#x\n", pkt->getAddr());
+DPRINTF(RubyPort,  "Pio response for address %#x\n", pkt->getAddr());
 
 assert(pkt->isResponse());
 
@@ -159,7 +159,7 @@
 bool
 RubyPort::M5Port::recvTiming(PacketPtr pkt)
 {
-DPRINTF(MemoryAccess,
+DPRINTF(RubyPort,
 "Timing access caught for address %#x\n", pkt->getAddr());
 
 //dsm: based on SimpleTimingPort::recvTiming(pkt);
@@ -186,7 +186,7 @@
 // pio port.
 if (!isPhysMemAddress(pkt->getAddr())) {
 assert(ruby_port->pio_port != NULL);
-DPRINTF(MemoryAccess,
+DPRINTF(RubyPort,
 "Request for address 0x%#x is assumed to be a pio request\n",
 pkt->getAddr());
 
@@ -205,19 +205,19 @@
 
 if (pkt->isLLSC()) {
 if (pkt->isWrite()) {
-DPRINTF(MemoryAccess, "Issuing SC\n");
+DPRINTF(RubyPort, "Issuing SC\n");
 type = RubyRequestType_Store_Conditional;
 } else {
-DPRINTF(MemoryAccess, "Issuing LL\n");
+DPRINTF(RubyPort, "Issuing LL\n");
 assert(pkt->isRead());
 type = RubyRequestType_Load_Linked;
 }
 } else if (pkt->req->isLocked()) {
 if (pkt->isWrite()) {
-DPRINTF(MemoryAccess, "Issuing Locked RMW Write\n");
+DPRINTF(RubyPort, "Issuing Locked RMW Write\n");
 type = RubyRequestType_Locked_RMW_Write;
 } else {
-DPRINTF(MemoryAccess, "Issuing Locked RMW Read\n");
+DPRINTF(RubyPort, "Issuing Locked RMW Read\n");
 assert(pkt->isRead());
 type = RubyRequestType_Locked_RMW_Read;
 }
@@ -263,7 +263,7 @@
 // Otherwise, we need to delete the senderStatus we just created and return
 // false.
 if (requestStatus == RequestStatus_Issued) {
-DPRINTF(MemoryAccess, "Request %x issued\n", pkt->getAddr());
+DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
 return true;
 }
 
@@ -275,7 +275,7 @@
 ruby_port->addToRetryList(this);
 }
 
-DPRINTF(MemoryAccess,
+DPRINTF(RubyPort,
 "Request for address %#x did not issue because %s\n",
 pkt->getAddr(), RequestStatus_to_string(requestStatus));
 
@@ -351,7 +351,7 @@
 pkt->convertLlToRead();
 }
 }
-DPRINTF(MemoryAccess, "Hit callback needs response %d\n", needsResponse);
+DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
 
 if (accessPhysMem) {
 ruby_port->physMemPort->sendAtomic(pkt);
@@ -361,12 +361,12 @@
 
 // turn packet around to go back to requester if response expected
 if (needsResponse) {
-DPRINTF(MemoryAccess, "Sending packet back over port\n");
+DPRINTF(RubyPort, "Sending packet back over port\n");
 sendTiming(pkt);
 } else {
 delete pkt;
 }
-DPRINTF(MemoryAccess, "Hit

[m5-dev] changeset in m5: ruby: added useful dma progress dprintf

2011-03-19 Thread Brad Beckmann

changeset 0b3252d3b400 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0b3252d3b400
description:
ruby: added useful dma progress dprintf

diffstat:

 src/mem/ruby/system/DMASequencer.cc |  5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diffs (15 lines):

diff -r de9e34de70ff -r 0b3252d3b400 src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc   Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/ruby/system/DMASequencer.cc   Sat Mar 19 14:17:48 2011 -0700
@@ -150,7 +150,10 @@
 assert(m_mandatory_q_ptr != NULL);
 m_mandatory_q_ptr->enqueue(msg);
 active_request.bytes_issued += msg->getLen();
-DPRINTF(RubyDma, "Next DMA segment issued to the DMA cntrl\n");
+DPRINTF(RubyDma, 
+"DMA request bytes issued %d, bytes completed %d, total len %d\n",
+active_request.bytes_issued, active_request.bytes_completed,
+active_request.len);
 }
 
 void
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[m5-dev] changeset in m5: slicc: improved invalid transition message

2011-03-19 Thread Brad Beckmann

changeset de9e34de70ff in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=de9e34de70ff
description:
slicc: improved invalid transition message

diffstat:

 src/mem/slicc/symbols/StateMachine.py |  4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diffs (14 lines):

diff -r 519fba665871 -r de9e34de70ff src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/slicc/symbols/StateMachine.py Sat Mar 19 14:17:48 2011 -0700
@@ -1232,8 +1232,8 @@
 code('''
   default:
 fatal("Invalid transition\\n"
-  "version: %d time: %d addr: %s event: %s state: %s\\n",
-  m_version, g_eventQueue_ptr->getTime(), addr, event, state);
+  "%s time: %d addr: %s event: %s state: %s\\n",
+  name(), g_eventQueue_ptr->getTime(), addr, event, state);
 }
 return TransitionResult_Valid;
 }
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[m5-dev] changeset in m5: MOESI_hammer: fixed dma bug with shared data

2011-03-19 Thread Brad Beckmann

changeset 519fba665871 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=519fba665871
description:
MOESI_hammer: fixed dma bug with shared data

diffstat:

 src/mem/protocol/MOESI_hammer-cache.sm |  35 +
 src/mem/protocol/MOESI_hammer-dir.sm   |   4 +-
 2 files changed, 32 insertions(+), 7 deletions(-)

diffs (90 lines):

diff -r d2cf4b19e8ad -r 519fba665871 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.smSat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/protocol/MOESI_hammer-cache.smSat Mar 19 14:17:48 2011 -0700
@@ -560,7 +560,7 @@
 }
   }
 
-  action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, 
keep a shared copy") {
+  action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, 
remaining the owner") {
 peek(forwardToCache_in, RequestMsg) {
   enqueue(responseNetwork_out, ResponseMsg, 
latency=cache_response_latency) {
 assert(is_valid(cache_entry));
@@ -584,7 +584,7 @@
 }
   }
   
-  action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all 
requestors") {
+  action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all 
requestors, still the owner") {
 peek(forwardToCache_in, RequestMsg) {
   enqueue(responseNetwork_out, ResponseMsg, 
latency=cache_response_latency) {
 assert(is_valid(cache_entry));
@@ -874,12 +874,37 @@
 }
   }
 
-  action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, 
multiple sharers") {
+  action(sq_sendSharedDataFromTBEToCache, "sq", desc="Send shared data from 
TBE to cache, still the owner") {
+peek(forwardToCache_in, RequestMsg) {
+assert(in_msg.Requestor != machineID);
+  enqueue(responseNetwork_out, ResponseMsg, 
latency=cache_response_latency) {
+assert(is_valid(tbe));
+out_msg.Address := address;
+out_msg.Type := CoherenceResponseType:DATA_SHARED;
+out_msg.Sender := machineID;
+out_msg.Destination.add(in_msg.Requestor);
+DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
+out_msg.DataBlk := tbe.DataBlk;
+out_msg.Dirty := tbe.Dirty;
+if (in_msg.DirectedProbe) {
+  out_msg.Acks := machineCount(MachineType:L1Cache);
+} else {
+  out_msg.Acks := 2;
+}
+out_msg.SilentAcks := in_msg.SilentAcks;
+out_msg.MessageSize := MessageSizeType:Response_Data;
+out_msg.InitialRequestTime := in_msg.InitialRequestTime;
+out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
+  }
+}
+  }
+
+  action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, 
multiple sharers, still the owner") {
 peek(forwardToCache_in, RequestMsg) {
   enqueue(responseNetwork_out, ResponseMsg, 
latency=cache_response_latency) {
 assert(is_valid(tbe));
 out_msg.Address := address;
-out_msg.Type := CoherenceResponseType:DATA;
+out_msg.Type := CoherenceResponseType:DATA_SHARED;
 out_msg.Sender := machineID;
 out_msg.Destination := in_msg.MergedRequestors;
 DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
@@ -1599,7 +1624,7 @@
   }
 
   transition({OI, MI}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}, OI) {
-q_sendDataFromTBEToCache;
+sq_sendSharedDataFromTBEToCache;
 l_popForwardQueue;
   }
 
diff -r d2cf4b19e8ad -r 519fba665871 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm  Sat Mar 19 14:17:48 2011 -0700
+++ b/src/mem/protocol/MOESI_hammer-dir.sm  Sat Mar 19 14:17:48 2011 -0700
@@ -1500,14 +1500,14 @@
 
   transition(O_DR_B, Shared_Ack) {
 m_decrementNumberOfMessages;
-so_setOwnerBit;
+r_setSharerBit;
 o_checkForCompletion;
 n_popResponseQueue;
   }
 
   transition(O_DR_B_W, Shared_Ack) {
 m_decrementNumberOfMessages;
-so_setOwnerBit;
+r_setSharerBit;
 n_popResponseQueue;
   }
 
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[m5-dev] changeset in m5: MOESI_CMP_directory: significant dma bug fixes

2011-03-19 Thread Brad Beckmann

changeset d2cf4b19e8ad in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d2cf4b19e8ad
description:
MOESI_CMP_directory: significant dma bug fixes

diffstat:

 src/mem/protocol/MOESI_CMP_directory-L1cache.sm |   67 -
 src/mem/protocol/MOESI_CMP_directory-L2cache.sm |  171 ---
 src/mem/protocol/MOESI_CMP_directory-dir.sm |   27 +++-
 src/mem/protocol/MOESI_CMP_directory-dma.sm |4 +
 src/mem/protocol/MOESI_CMP_directory-msg.sm |1 -
 5 files changed, 233 insertions(+), 37 deletions(-)

diffs (truncated from 637 to 300 lines):

diff -r 9a6a02a235f1 -r d2cf4b19e8ad 
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm   Fri Mar 18 14:12:04 
2011 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm   Sat Mar 19 14:17:48 
2011 -0700
@@ -663,10 +663,27 @@
   }
 
 
+  action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") {
+peek(requestNetwork_in, RequestMsg) {
+  enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
+out_msg.Address := address;
+out_msg.Type := CoherenceResponseType:DMA_ACK;
+out_msg.Sender := machineID;
+out_msg.SenderMachine := MachineType:L1Cache;
+out_msg.Destination.add(mapAddressToRange(address, 
MachineType:L2Cache, 
+l2_select_low_bit, l2_select_num_bits));
+out_msg.Dirty := false;
+out_msg.Acks := 1;
+out_msg.MessageSize := MessageSizeType:Response_Control;
+  }
+}
+  }
+
   action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
 peek(requestNetwork_in, RequestMsg) {
   assert(is_valid(tbe));
-  if (in_msg.RequestorMachine == MachineType:L1Cache) {
+  if (in_msg.RequestorMachine == MachineType:L1Cache || 
+  in_msg.RequestorMachine == MachineType:DMA) {
 enqueue(responseNetwork_out, ResponseMsg, latency=request_latency) {
   out_msg.Address := address;
   out_msg.Type := CoherenceResponseType:DATA;
@@ -895,11 +912,17 @@
 l_popForwardQueue;
   }
 
-  transition(S, {Fwd_GETS, Fwd_DMA}) {
+  transition(S, Fwd_GETS) {
 e_sendData;
 l_popForwardQueue;
   }
 
+  transition(S, Fwd_DMA) {
+e_sendData;
+ub_dmaUnblockL2Cache;
+l_popForwardQueue;
+  }
+
   // Transitions from Owned
   transition({O, OM}, {Load, Ifetch}) {
 h_load_hit;
@@ -924,11 +947,17 @@
 l_popForwardQueue;
   }
 
-  transition(O, {Fwd_GETS, Fwd_DMA}) {
+  transition(O, Fwd_GETS) {
 e_sendData;
 l_popForwardQueue;
   }
 
+  transition(O, Fwd_DMA) {
+e_sendData;
+ub_dmaUnblockL2Cache;
+l_popForwardQueue;
+  }
+
   // Transitions from MM
   transition({MM, MM_W}, {Load, Ifetch}) {
 h_load_hit;
@@ -957,8 +986,8 @@
   }
 
   transition(MM, Fwd_DMA, MM) {
-//ee_sendDataExclusive;
 e_sendData;
+ub_dmaUnblockL2Cache;
 l_popForwardQueue;
   }
 
@@ -995,8 +1024,9 @@
 l_popForwardQueue;
   }
 
-  transition(M, Fwd_DMA, M) {
+  transition(M, Fwd_DMA) {
 e_sendData;
+ub_dmaUnblockL2Cache;
 l_popForwardQueue;
   }
 
@@ -1039,11 +1069,17 @@
 n_popResponseQueue;
   }
 
-  transition(SM, {Fwd_DMA, Fwd_GETS}) {
+  transition(SM, Fwd_GETS) {
 e_sendData;
 l_popForwardQueue;
   }
 
+  transition(SM, Fwd_DMA) {
+e_sendData;
+ub_dmaUnblockL2Cache;
+l_popForwardQueue;
+  }
+
   // Transitions from OM
   transition(OM, Own_GETX) {
 mm_decrementNumberOfMessages;
@@ -1058,11 +1094,17 @@
 l_popForwardQueue;
   }
 
-  transition(OM, {Fwd_DMA, Fwd_GETS}, OM) {
+  transition(OM, Fwd_GETS) {
 e_sendData;
 l_popForwardQueue;
   }
 
+  transition(OM, Fwd_DMA) {
+e_sendData;
+ub_dmaUnblockL2Cache;
+l_popForwardQueue;
+  }
+
   //transition({OM, OMF}, Ack) {
   transition(OM, Ack) {
 m_decrementNumberOfMessages;
@@ -1119,8 +1161,9 @@
 l_popForwardQueue;
   }
 
-  transition(MI, Fwd_DMA, MI) {
+  transition(MI, Fwd_DMA) {
 q_sendDataFromTBEToCache;
+ub_dmaUnblockL2Cache;
 l_popForwardQueue;
   }
 
@@ -1129,11 +1172,17 @@
 l_popForwardQueue;
   }
 
-  transition({SI, OI}, {Fwd_DMA, Fwd_GETS}) {
+  transition({SI, OI}, Fwd_GETS) {
 q_sendDataFromTBEToCache;
 l_popForwardQueue;
   }
 
+  transition({SI, OI}, Fwd_DMA) {
+q_sendDataFromTBEToCache;
+ub_dmaUnblockL2Cache;
+l_popForwardQueue;
+  }
+
   transition(OI, Fwd_GETX, II) {
 q_sendExclusiveDataFromTBEToCache;
 l_popForwardQueue;
diff -r 9a6a02a235f1 -r d2cf4b19e8ad 
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm   Fri Mar 18 14:12:04 
2011 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm   Sat Mar 19 14:17:48 
2011 -0700
@@ -125,6 +125,13 @@
 MII, AccessPermission:Busy, desc="Blocked, doing writeback, was M, got 
Fwd_GETX";
 OLSI, AccessPermission:Busy, desc="Blocked, doing writeback, was OLS";
 ILSI, AccessPermission:Busy, desc="Blo

Re: [m5-dev] Review Request: Ruby: Convert AccessModeType to RubyAccessMode

2011-03-19 Thread Brad Beckmann


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/601/#review996
---

Ship it!


- Brad


On 2011-03-18 21:55:08, Nilay Vaish wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/601/
> ---
> 
> (Updated 2011-03-18 21:55:08)
> 
> 
> Review request for Default.
> 
> 
> Summary
> ---
> 
> Ruby: Convert AccessModeType to RubyAccessMode
> This patch converts AccessModeType to RubyAccessMode so that both the
> protocol dependent and independent code uses the same access mode.
> 
> 
> Diffs
> -
> 
>   src/cpu/testers/rubytest/Check.hh 9a6a02a235f1 
>   src/cpu/testers/rubytest/Check.cc 9a6a02a235f1 
>   src/mem/protocol/MESI_CMP_directory-msg.sm 9a6a02a235f1 
>   src/mem/protocol/MOESI_CMP_directory-msg.sm 9a6a02a235f1 
>   src/mem/protocol/MOESI_CMP_token-L1cache.sm 9a6a02a235f1 
>   src/mem/protocol/MOESI_CMP_token-dir.sm 9a6a02a235f1 
>   src/mem/protocol/MOESI_CMP_token-msg.sm 9a6a02a235f1 
>   src/mem/protocol/RubySlicc_Exports.sm 9a6a02a235f1 
>   src/mem/protocol/RubySlicc_Types.sm 9a6a02a235f1 
>   src/mem/ruby/profiler/AccessTraceForAddress.hh 9a6a02a235f1 
>   src/mem/ruby/profiler/AccessTraceForAddress.cc 9a6a02a235f1 
>   src/mem/ruby/profiler/AddressProfiler.hh 9a6a02a235f1 
>   src/mem/ruby/profiler/AddressProfiler.cc 9a6a02a235f1 
>   src/mem/ruby/profiler/CacheProfiler.hh 9a6a02a235f1 
>   src/mem/ruby/profiler/CacheProfiler.cc 9a6a02a235f1 
>   src/mem/ruby/profiler/Profiler.hh 9a6a02a235f1 
>   src/mem/ruby/slicc_interface/RubyRequest.hh 9a6a02a235f1 
>   src/mem/ruby/system/CacheMemory.hh 9a6a02a235f1 
>   src/mem/ruby/system/CacheMemory.cc 9a6a02a235f1 
>   src/mem/ruby/system/Sequencer.hh 9a6a02a235f1 
>   src/mem/ruby/system/Sequencer.cc 9a6a02a235f1 
> 
> Diff: http://reviews.m5sim.org/r/601/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Nilay
> 
>

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Re: [m5-dev] Review Request: Ruby: Convert CacheRequestType to RubyRequestType

2011-03-19 Thread Brad Beckmann


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/602/#review995
---

Ship it!


- Brad


On 2011-03-18 21:55:58, Nilay Vaish wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/602/
> ---
> 
> (Updated 2011-03-18 21:55:58)
> 
> 
> Review request for Default.
> 
> 
> Summary
> ---
> 
> Ruby: Convert CacheRequestType to RubyRequestType
> This patch converts CacheRequestType to RubyRequestType so that both the
> protocol dependent and independent code makes use of the same request type.
> 
> 
> Diffs
> -
> 
>   src/mem/protocol/MESI_CMP_directory-L1cache.sm 9a6a02a235f1 
>   src/mem/protocol/MI_example-cache.sm 9a6a02a235f1 
>   src/mem/protocol/MOESI_CMP_directory-L1cache.sm 9a6a02a235f1 
>   src/mem/protocol/MOESI_CMP_token-L1cache.sm 9a6a02a235f1 
>   src/mem/protocol/MOESI_hammer-cache.sm 9a6a02a235f1 
>   src/mem/protocol/RubySlicc_Exports.sm 9a6a02a235f1 
>   src/mem/ruby/profiler/AccessTraceForAddress.hh 9a6a02a235f1 
>   src/mem/ruby/profiler/AccessTraceForAddress.cc 9a6a02a235f1 
>   src/mem/ruby/profiler/AddressProfiler.hh 9a6a02a235f1 
>   src/mem/ruby/profiler/AddressProfiler.cc 9a6a02a235f1 
>   src/mem/ruby/profiler/CacheProfiler.hh 9a6a02a235f1 
>   src/mem/ruby/profiler/CacheProfiler.cc 9a6a02a235f1 
>   src/mem/ruby/profiler/Profiler.hh 9a6a02a235f1 
>   src/mem/ruby/profiler/Profiler.cc 9a6a02a235f1 
>   src/mem/ruby/recorder/CacheRecorder.hh 9a6a02a235f1 
>   src/mem/ruby/recorder/Tracer.hh 9a6a02a235f1 
>   src/mem/ruby/slicc_interface/RubyRequest.hh 9a6a02a235f1 
>   src/mem/ruby/slicc_interface/RubyRequest.cc 9a6a02a235f1 
>   src/mem/ruby/slicc_interface/RubySlicc_Util.hh 9a6a02a235f1 
>   src/mem/ruby/system/CacheMemory.hh 9a6a02a235f1 
>   src/mem/ruby/system/CacheMemory.cc 9a6a02a235f1 
>   src/mem/ruby/system/DMASequencer.cc 9a6a02a235f1 
>   src/mem/ruby/system/Sequencer.hh 9a6a02a235f1 
>   src/mem/ruby/system/Sequencer.cc 9a6a02a235f1 
> 
> Diff: http://reviews.m5sim.org/r/602/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Nilay
> 
>

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Re: [m5-dev] Cron /z/m5/regression/do-regression quick

2011-03-19 Thread Nilay

On Sat, March 19, 2011 3:26 am, Cron Daemon wrote:
> scons: *** Found dependency cycle(s):

I am looking at the output of the regression from last night. What do the
following errors mean?

scons: *** Found dependency cycle(s):
  Internal Error: no cycle found for node
build/POWER_SE/params/Directory_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/ALPHA_SE_MESI_CMP_directory/params/DMA_Controller.hh
() in state up_to_date
  Internal Error: no cycle found for node
build/ALPHA_SE/params/L1Cache_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/X86_SE/params/DMA_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/X86_SE/params/Directory_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/POWER_SE/params/L1Cache_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/ALPHA_SE/params/Directory_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/ALPHA_SE/params/DMA_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/ALPHA_SE_MESI_CMP_directory/params/L1Cache_Controller.hh
() in state up_to_date
  Internal Error: no cycle found for node
build/ALPHA_SE_MESI_CMP_directory/params/L2Cache_Controller.hh
() in state up_to_date
  Internal Error: no cycle found for node
build/POWER_SE/params/DMA_Controller.hh () in state up_to_date
  Internal Error: no cycle found for node
build/X86_SE/params/L1Cache_Controller.hh () in state up_to_date

File "/usr/lib/scons/SCons/Taskmaster.py", line 800, in cleanup
Child returned 2
When attemping to execute: scons --ignore-style -k USE_MYSQL=no
EXTRAS=/z/m5/regression/zizzer/encumbered RUBY=True -j 7 -Q
build/ALPHA_SE/tests/fast/quick
build/ALPHA_SE_MOESI_hammer/tests/fast/quick
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick
build/ALPHA_FS/tests/fast/quick build/MIPS_SE/tests/fast/quick
build/POWER_SE/tests/fast/quick build/SPARC_SE/tests/fast/quick
build/X86_SE/tests/fast/quick build/X86_FS/tests/fast/quick
build/ARM_SE/tests/fast/quick build/ARM_FS/tests/fast/quick
Child returned 1
When attemping to execute: util/regress '--scons-opts' '-k USE_MYSQL=no
EXTRAS=/z/m5/regression/zizzer/encumbered RUBY=True -j 7 -Q' 'quick'


--
Nilay

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[m5-dev] Cron /z/m5/regression/do-regression quick

2011-03-19 Thread Cron Daemon

scons: *** Found dependency cycle(s):
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby 
passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby 
passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp 
passed.
* build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 passed.
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby 
passed.
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic 
passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing 
passed.
* 
build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby 
passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 passed.
* build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic passed.
* build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed.
* build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic 
passed.
* build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed.
* 
build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 passed.
* build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed.
* 
build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 passed.
* build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed.
* build/SPARC_SE/tests/fast/quick/00.hello/s

Re: [m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

[m5-dev] changeset in m5: configs: combine ruby_se.py and se.py to avoid ...

[m5-dev] changeset in m5: enable x86 workloads on se.py

[m5-dev] changeset in m5: util: update aggregator to handle x86 checkpoi...

[m5-dev] changeset in m5: se.py: Modify script to make multiprogramming m...

[m5-dev] changeset in m5: Ruby: Convert CacheRequestType to RubyRequestType

[m5-dev] changeset in m5: Ruby: Convert AccessModeType to RubyAccessMode

Re: [m5-dev] Review Request: enable x86 workloads on se.py

Re: [m5-dev] Review Request: se.py: Modify script to make multiprogramming much easier.

Re: [m5-dev] Review Request: configs: combine ruby_se.py and se.py to avoid all that code duplication

[m5-dev] changeset in m5: Ruby: dma retry fix

[m5-dev] changeset in m5: MOESI_hammer: minor fixes to full-bit dir

[m5-dev] changeset in m5: RubyPort: minor fixes to trace flag and dprintfs

[m5-dev] changeset in m5: ruby: added useful dma progress dprintf

[m5-dev] changeset in m5: slicc: improved invalid transition message

[m5-dev] changeset in m5: MOESI_hammer: fixed dma bug with shared data

[m5-dev] changeset in m5: MOESI_CMP_directory: significant dma bug fixes

Re: [m5-dev] Review Request: Ruby: Convert AccessModeType to RubyAccessMode

Re: [m5-dev] Review Request: Ruby: Convert CacheRequestType to RubyRequestType

Re: [m5-dev] Cron /z/m5/regression/do-regression quick

[m5-dev] Cron /z/m5/regression/do-regression quick

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