[gem5-users] Suspecting bubbles in the DRAM controller command bus
Hello Users, I suspect the DRAM controller code is adding unwanted bubbles in the command bus. Consider there are 10 row hit read requests- R0 and R9- in the queue, all targeting Bank0 and a Row miss request- R10 -to Bank1 of same rank and numbered in the arrival order. According to FR-FCFS in open-page policy, the DRAM controller process all row-hit requests to Bank0 and then choose the row-miss request to Bank1. I suspect the problem lies here in the controller code, when it updates the access latency of the row miss request- R10 - to bank1. According to JEDEC timing constraints, the controller can issue Precharge to another bank after a clock cycle(tCK) delay and Activate after tRRD cycles delay(ACT-ACT delay between two banks). This means, by the time DRAM controller process the 10 row hit requests, the Bank1 should be precharged and activated. However, I am not sure if this is taken care of in the below snippet of code. if (bank.openRow == dram_pkt-row) { // nothing to do } else { row_hit = false; // If there is a page open, precharge it. if (bank.openRow != Bank::NO_ROW) { *prechargeBank(bank, std::max(bank.preAllowedAt, curTick()))*; } // next we need to account for the delay in activating the // page Tick act_tick = std::max(bank.actAllowedAt, curTick()); // Record the activation and deal with all the global timing // constraints caused be a new activation (tRRD and tXAW) activateBank(bank, act_tick, dram_pkt-row); // issue the command as early as possible cmd_at = bank.colAllowedAt; } shouldn't this be *prechargeBank(bank, std::max(bank.preAllowedAt, dram_pkt-entrytime)*; I am not sure if my understanding is correct. Please clarify. Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] TraceGen and instruction execution trace
Hello !! Can traceGen module be used to simulate instruction traces? The tests that are available in gem5 rep. use traceGen module to replace CPU and connect traceGen with mem. Is it possible to use traceGen with CPU and feed instructions to CPU from a trace file? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] [gem5 users] a query regarding target_core_clockrate tag in Mcpat xml for ARM FS simulation
Hi All, I am performing ARM FS simulation and want to calculate energy consumption of the program which contains calls to DVFS. I have generated some statistics and with the help of config.ini and stats.txt, I am trying to populate Mcpat xml file to calculate energy. There is a parameter called *param name=target_core_clockrate *under the component System. Also there is a per core parameter called* param name=clock_rate *for each of the simulated core. For per core parameter *clock_rate*, I would set this to that frequency which each of the core is currently running on.(The value will be different for different core). Since each core is running at different frequency, I am not sure what value to put in* target_core_clockrate, *as this tag belongs to system component which necessarily is a global setting. Could you please help me here? Regards Rahul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SystemXBar latency
Hi Yuting, The short answer: for requests, no. The long answer: You may have seen that I just pushed a patch that adds latency in the crossbar on the response path. In essence we just use a queued port to hold on to the packets until they are supposed to be sent. The reason it is challenging to do this on the request side is the assumptions in the gem5 coherency protocol. At the moment, the caches assume that once an Ln cache sends the message successfully, an Ln+1 cache is now owning the packet (and the associated MSHR if any). There is a possibility to be selective about what requests may be delayed in the crossbar, and what requests must pass the crossbar in zero time, but it is not straight forward to make the separation. Instead, what we do at the moment is to annotate a ‘debt’ on the packet, in the form of headerDelay and payloadDelay. Then, we expect a down-stream component to pay for this latency. In worst case we pay for it on the response side (see above), when the packet returns through the crossbar. Thus, the overall latency is growing as expected, we simply do not incur the wait for the request itself. I hope that brings some clarity to the matter. Andreas On 09/07/2015 06:21, gem5-users on behalf of cao2 gem5-users-boun...@gem5.org on behalf of c...@mail.usf.edu wrote: HI there I notice that the tick displayed membus receiving function and sending function are the same, is there any way I can add a latency in between for better tracing result? Regards, Yuting ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Multiple sets of simulation statistics getting populated in stats.txt
Hi Rahul, When you run full-system, the whole point is that the OS is present. This invariably means that there will be background tasks happening besides what ever benchmark you are running. It’s simply something you have to take into account if you want your experiment to be realistic. Andreas From: gem5-users gem5-users-boun...@gem5.orgmailto:gem5-users-boun...@gem5.org on behalf of rahul shrivastava rshrivasta...@gmail.commailto:rshrivasta...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Thursday, 9 July 2015 14:20 To: gem5-users@gem5.orgmailto:gem5-users@gem5.org gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: Re: [gem5-users] Multiple sets of simulation statistics getting populated in stats.txt Hi All, I am keeping the Full system Simulation idle and it keeps on producing stats. As of now there are total 8 stats in stats.txt. This seems to be confusing to me as I dont know that the stats produced in stats.txt belong to my benchmark run or some other stuff running in the background. Could you please shed some light on this? Regards Rahul On Wed, Jul 8, 2015 at 7:53 PM, rahul shrivastava rshrivasta...@gmail.commailto:rshrivasta...@gmail.com wrote: Hi, I am trying to simulate ARM 4 core system in full system simulation mode. Even if I am not performing any task, the statistics are getting populated in stats.txt. Is there some periodic timer set which is causing this issue? Here is the command that I am using M5_PATH=$(pwd)/.. ./build/ARM/gem5.opt --debug-flags=DVFS,EnergyCtrl --debug-file=dfvs_debug.log configs/example/fs.py --cpu-type=AtomicSimpleCPU -n 4 --machine-type=VExpress_EMM --kernel=../linux-linaro-tracking-gem5/vmlinux --dtb-filename=../linux-linaro-tracking-gem5/arch/arm/boot/dts/vexpress-v2p-ca15-tc1-gem5_dvfs_per_core_4cpus.dtb --disk-image=../disks/arm-ubuntu-natty-headless.img --cpu-clock=\['1 GHz','750 MHz','500 MHz'\] Regards Rahul -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users