[gem5-users] Re: How to create two memory object in SE mode

[Taiyu Zhou via gem5-users]

Hi,

What is the address organization between DRAM and PM? If applications want to 
allocate 1G DRAM and 1G PM, is there any hint for the memory allocator function?___
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[gem5-users] Re: 2 level TLB in ARM Full System with Ruby

[Shehab Elsayed via gem5-users]

Hi Ciro,

Thanks for your reply! I don't remember seeing this patch before. I will
check it out.

The reason I specified RUBY is that one solution I found posted used a
cache as a second level TLB and modified the port connections accordingly.
However, that was a cache from the classical system and therefore wouldn't
work with RUBY.

Thanks again!

Best Regards,
Shehab

On Wed, Jul 8, 2020 at 8:30 AM Ciro Santilli  wrote:

> Shehab, sorry for the delay, I had to check a few things about this,
>
> First, are you aware that there is a not-yet-merged patch that implements
> a two level TLB at:
> https://github.com/giactra/gem5/commit/3022ecc8a06a9182b2cf1936941901a785c1b21d
>  ?
>
> It hasn't been merged because we noticed that it broke Linux boot I think.
> But we would like to merge it in the following months.
>
> I'm not sure why Ruby vs classic would matter since the TLB sits behind
> caches anyways? I believe that model will work for either classic or Ruby.
> --
> *From:* Shehab Elsayed via gem5-users 
> *Sent:* Tuesday, June 23, 2020 12:20 AM
> *To:* gem5 users mailing list 
> *Cc:* Shehab Elsayed 
> *Subject:* [gem5-users] 2 level TLB in ARM Full System with Ruby
>
> Hello All,
>
> I was wondering if there is a way to simulate a system with 2 levels of
> TLBs in full system simulation with ruby for ARM?
>
> I have seen other examples that use the classical memory model and use a
> cache as the second level TLB. Is there something similar that can be
> done in Ruby memory system. Can I use a standalone RubyCache as the
> second level TLB?
>
> Thank you very much in advance.
>
> Best Regards,
> Shehab
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[gem5-users] Re: question about cache organization

[Daniel Carvalho via gem5-users]

 Hello Sourjya,

First of all, welcome!

gem5 is very versatile, and there is an infinitude of things you can do with 
it. The first thing you will need to decide is whether you are going to use the 
Classic Cache 
(https://www.gem5.org/documentation/general_docs/memory_system/classic_caches/) 
or the Ruby cache (https://www.gem5.org/documentation/general_docs/ruby/). Each 
has its own advantages and disadvantages. My answer will focus on the Classic 
model. If you'd like to have a tutorial on how to use the Ruby cache, you may 
take a look at the Learning gem5 book 
(https://www.gem5.org/documentation/learning_gem5/introduction/).


There are multiple cache policies you can change right off the bat, including 
Indexing 
(https://www.gem5.org/documentation/general_docs/memory_system/indexing_policies/),
 Replacement 
(https://www.gem5.org/documentation/general_docs/memory_system/replacement_policies/),
 and the cache organization itself (src/mem/cache/tags). Modifying the latter 
will allow you to achieve your goal of changing the data mapping, but you will 
likely need to pair it up with a new indexing policy too. 


Here is an example of a target cache design, and the possible changes needed to 
achieve it: 
https://stackoverflow.com/questions/62784675/are-cache-ways-in-gem5-explicit-or-are-they-implied-derived-from-the-number-of-c/62790543#62790543
 A similar thought process will be applied to most changes targeting the cache 
organization. 


If you prefer to see practical code, you can check the implementation of 
previous tags classes, such as the Sector Cache 
(https://gem5-review.googlesource.com/c/public/gem5/+/9741).


Regards,
Daniel







Em quarta-feira, 8 de julho de 2020 18:30:22 GMT+2, Sourjya Roy via 
gem5-users  escreveu:  
 
  
Hi
 
  
 
I am very new to gem5. I wanted to know if there is tutorial on changing cache 
data mapping or cache organization(eg If I want to change sram with any other 
device technology for a L2 cache) . Also I wanted to know if I can change the 
cache policies and data mapping inside caches.
 
  
 
  
 
Regards,
 
Sourjya
 
Electrical and Computer Engineering
 
Purdue University
 
  
 
  
 
  
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[gem5-users] Re: Running a program on GEM5 for specific number of instructions

[Shougang Yuan via gem5-users]

If you are talking about the SE mode, you can use the se.py. The fast
forward option and max instruction option will be helpful.

On Wed, Jul 8, 2020 at 2:28 PM ABD ALRHMAN ABO ALKHEEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> I want to run a program for 100k instructions but I want to skip the first
> 50k instructions? How can i do this? Any help would be appreciated.
>
> Thanks
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[gem5-users] Running a program on GEM5 for specific number of instructions

[ABD ALRHMAN ABO ALKHEEL via gem5-users]

Hi All,

I want to run a program for 100k instructions but I want to skip the first 50k 
instructions? How can i do this? Any help would be appreciated.

Thanks
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[gem5-users] gem5-20 paper on arXiv

[Jason Lowe-Power via gem5-users]

Hi everyone!

I'm excited to announce that we've published a new gem5 paper! Right now,
it's available on arXiv at this URL: https://arxiv.org/abs/2007.03152

I tried to reach out to everyone who has been involved in gem5 development
since its inception in 2011. However, I'm certain to have missed people.
Plus, I got 100s of emails about this, and I'm sure one fell through the
cracks. If I missed anyone, I'm so sorry!

We will be "releasing" another version of the paper on arXiv in a few
weeks. So, if you spot any errors or if you wish to be included as an
author of the paper and contributed to gem5 between 2011 and gem5 version
20.0, please open an issue on this github repo:
https://github.com/darchr/gem5-20-paper. See the README
 for
authorship information.

If you use gem5-20.0+, we would appreciate it if you would cite this paper.

Cheers,
Jason
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[gem5-users] question about cache organization

[Sourjya Roy via gem5-users]

Hi

I am very new to gem5. I wanted to know if there is tutorial on changing cache 
data mapping or cache organization(eg If I want to change sram with any other 
device technology for a L2 cache) . Also I wanted to know if I can change the 
cache policies and data mapping inside caches.



Regards,

Sourjya

Electrical and Computer Engineering

Purdue University



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[gem5-users] Re: How to track the register values of instructions.

[Jason Lowe-Power via gem5-users]

Hi Yuan,

To be honest, I'm unfamiliar with those functions. I would consult the
source code for more information. Additionally, in gdb, you can just call
any function :).

Cheers,
Jason

On Tue, Jul 7, 2020 at 4:05 PM Shougang Yuan  wrote:

> Hi, Prof.Jason,
>
> Thanks for your detailed reply. I found that in the gem5 website about gdb
> debugging. It mentioned that there are some dump functions that can be
> called from the debugger and the website list some of them. Is there a way
> to know more details about these functions that can dump out the
> instruction queue and the ROB.
>
> Best regards.
> Yuan
>
> On Tue, Jul 7, 2020 at 5:35 PM Jason Lowe-Power 
> wrote:
>
>> Hi Yuan,
>>
>> A couple of suggestions:
>> 1. You can use "--debug-file" to output to a file. Or, you can even use a
>> named pipe with grep to filter out only the instructions you care about.
>> You can also use "--debug-start" to delay debug printing until close to
>> where the problem occurs.
>> 2. You can use GDB to try to debug things. You can use "--debug-break" to
>> have a breakpoint happen at a precise tick. In GDB, you can print out
>> things like the register file values. You should be able to use the thread
>> context and/or the execution context to get the values of registers in GDB.
>> These are the interfaces from the CPU models to the outside world and the
>> ISA implementation, respectively. However, if you're using an out-of-order
>> model, it's not always obvious or easy to figure out what the architectural
>> state of some register is.
>>
>> Cheers,
>> Jason
>>
>> On Tue, Jul 7, 2020 at 2:23 PM Shougang Yuan  wrote:
>>
>>> Hi, Prof.Jason,
>>>
>>> Thanks for your reply. But actually I want to dump out the register
>>> value for some specific instructions because I suspect that the instruction
>>> execution may have some issues in my model. I tried to use Exec and
>>> ExecAll, but the trace is so large and a lot of these traces are not needed
>>> for me. I want to dump out the register values of the instructions I am
>>> interested in. i.e, if I have an add instruction, how can I dump out the
>>> source register value and dst register value of this instruction when it is
>>> executed or when it is in the commit stage. I tried to check the static or
>>> dynamic instruction classes, but seems that these values are not
>>> carried/stored with each instruction? Am I correct? Could you please give
>>> more hints?
>>>
>>> Best regards.
>>> Yuan
>>>
>>> On Thu, Jul 2, 2020 at 11:07 AM Jason Lowe-Power 
>>> wrote:
>>>
 Hi Yuan,

 You might find the Exec and ExecAll debug flags useful.

 Cheers,
 Jason

 On Thu, Jul 2, 2020 at 7:48 AM Shougang Yuan via gem5-users <
 gem5-users@gem5.org> wrote:

> Hi, All,
>
> I am trying to modify the gem5 code and suffer some memory corruption
> bugs. I want to look at more details of each instruction. So is there a 
> way
> to dump out the register value of each instruction.
>
> Best regards.
> Yuan
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[gem5-users] Re: 2 level TLB in ARM Full System with Ruby

[Ciro Santilli via gem5-users]

Shehab, sorry for the delay, I had to check a few things about this,

First, are you aware that there is a not-yet-merged patch that implements a two 
level TLB at: 
https://github.com/giactra/gem5/commit/3022ecc8a06a9182b2cf1936941901a785c1b21d 
?

It hasn't been merged because we noticed that it broke Linux boot I think. But 
we would like to merge it in the following months.

I'm not sure why Ruby vs classic would matter since the TLB sits behind caches 
anyways? I believe that model will work for either classic or Ruby.

From: Shehab Elsayed via gem5-users 
Sent: Tuesday, June 23, 2020 12:20 AM
To: gem5 users mailing list 
Cc: Shehab Elsayed 
Subject: [gem5-users] 2 level TLB in ARM Full System with Ruby

Hello All,

I was wondering if there is a way to simulate a system with 2 levels of TLBs in 
full system simulation with ruby for ARM?

I have seen other examples that use the classical memory model and use a cache 
as the second level TLB. Is there something similar that can be done in Ruby 
memory system. Can I use a standalone RubyCache as the second level TLB?

Thank you very much in advance.

Best Regards,
Shehab
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[gem5-users] Re: How to check ...

[Anuj Falcon via gem5-users]

It's a regular inorder 5 stage pipeline model designed to mimic the
microarchitectural states of actual C-class processor mentioned here.
https://gitlab.com/shaktiproject/cores/c-class


Has fetch, decode(modified), execute, memaccess, writeback connected
through pipe like structures containing FIFOs, with operand forward.

Working on BPU and Fault handling.

Currently tested only with RISCV ISA in baremetal full system simulation.
The model can be found here :
https://gitlab.com/shaktiproject/tools/core-models-gem5

On Fri, 3 Jul, 2020, 4:07 AM Anuj Falcon,  wrote:

> How to know if my CPU model qualifies to be upstreamed with the rest of
> the CPU models in gem 5 ?
>
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[gem5-users] Re: What is miscellaneous register

[Ciro Santilli via gem5-users]

Also, in ARM more specifically, you can see miscregs at
https://github.com/gem5/gem5/blob/cc3e12b504c20b3bc78db52059d3f4f9b02dfbe8/src/arch/arm/miscregs.hh#L56

Most are what the ARM manuals call "System Registers", but a few
others are just convenient ways to implement other ISA features like
e.g. MISCREG_LOCKADDR for LLSC.

On Wed, Jul 8, 2020 at 4:31 AM Gabe Black via gem5-users
 wrote:
>
> A long time ago when gem5 just supported Alpha, there were three types of 
> registers, integers, floats, and everything else. The "everything else" were 
> essentially control registers, or in other words registers which had side 
> effects from accessing them. They were called "Misc" for miscellaneous since 
> they were the left overs if you took away the ints and the floats. There are 
> more types of registers now, but the control registers are still called 
> "Misc".
>
> Gabe
>
> On Tue, Jul 7, 2020 at 2:01 PM Shougang Yuan via gem5-users 
>  wrote:
>>
>> Hi, All,
>>
>> I have one question regarding the miscellaneous register. IN the O3 cpu 
>> model, it mentioned the miscellaneous register(or misc register) a lot of 
>> times. So what's the exact meaning of this register? Can anyone give some 
>> hints?
>>
>> Best regards.
>> Yuan
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