Re: [gem5-users] Reviewboard registration error

[Ali Saidi via gem5-users]

I figured it out!

I think you’ve been going to http://reviews.m5sim.org and I’ve been going to 
http://reviews.gem5.org. It’s the same website, but I think the different name 
is confusing the captcha service we use. If you to the gem5.org site it should 
work and we’ll look at fixing it for the m5sim.org site.

Thanks,
Ali


From: Guru Prasad mailto:gurup...@buffalo.edu>>
Date: Thursday, February 12, 2015 at 8:51 AM
To: Rizwana Begum mailto:rizwana@gmail.com>>, gem5 
users mailing list mailto:gem5-users@gem5.org>>
Cc: Ali Saidi mailto:ali.sa...@arm.com>>
Subject: Re: [gem5-users] Reviewboard registration error

Hi,

I am also facing the same issue.
I'm posting a screenshot of the same - hoping that it helps in some way.

Regards
Guru


On Thu, Feb 12, 2015 at 5:44 AM, Rizwana Begum via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Yes. I had tried different user name. Now, I tried on another web browser,
(Mozilla and Chrome), however, it still results in error.

Its surprising how this is inconsistent. A couple of my colleagues tried here,
and have similar issue. Infact registration page loads with an error displayed
in the bottom already before I fill any details.

Thank you,
-Rizwana



On Thu, Feb 12, 2015 at 2:44 AM, Ali Saidi via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
I don’t see any errors and I’m able to create a new user.

Have you tried a different user name? Different web browser?

Thanks,
Ali


From: Rizwana Begum mailto:rizwana@gmail.com>>
Date: Wednesday, February 11, 2015 at 4:59 PM
To: Ali Saidi mailto:ali.sa...@arm.com>>, gem5 users mailing 
list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] Reviewboard registration error

Hello Ali,

No. It still gives the same error, and redirects to registration page.

Thank you,
-Rizwana

On Wed, Feb 11, 2015 at 4:54 PM, Ali Saidi via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Try now?

Thanks,
Ali


On 2/11/15, 11:36 AM, "Dave Werner via gem5-users" 
mailto:gem5-users@gem5.org>>
wrote:

>Rizwana Begum via gem5-users  gem5.org<http://gem5.org>> 
>writes:
>
>>
>> Hello All,
>> I am trying to register on review board, but end up with error  "An
>internal error occurred: 50EA8B0A168C0.A8CAE85.ED001888".I have been
>trying
>since two days with no luck. Could it be that only the admin can register
>users? I am actually not sure whom I should be contacting regarding
>registration or other issues related to review board.
>>
>> Thank you,
>> -Rizwana
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users  gem5.org<http://gem5.org>
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>Hello,
>
>I am also having the same issue for the past four days. Any word on this
>issue?
>
>Thanks,
>Dave
>___
>gem5-users mailing list
>gem5-users@gem5.org<mailto:gem5-users@gem5.org>
>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium.  Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No:  2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No:  2548782

___
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No: 2548782

___
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


___
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential a

Re: [gem5-users] Reviewboard registration error

[Ali Saidi via gem5-users]

I don’t see any errors and I’m able to create a new user.

Have you tried a different user name? Different web browser?

Thanks,
Ali


From: Rizwana Begum mailto:rizwana@gmail.com>>
Date: Wednesday, February 11, 2015 at 4:59 PM
To: Ali Saidi mailto:ali.sa...@arm.com>>, gem5 users mailing 
list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] Reviewboard registration error

Hello Ali,

No. It still gives the same error, and redirects to registration page.

Thank you,
-Rizwana

On Wed, Feb 11, 2015 at 4:54 PM, Ali Saidi via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Try now?

Thanks,
Ali


On 2/11/15, 11:36 AM, "Dave Werner via gem5-users" 
mailto:gem5-users@gem5.org>>
wrote:

>Rizwana Begum via gem5-users  gem5.org<http://gem5.org>> 
>writes:
>
>>
>> Hello All,
>> I am trying to register on review board, but end up with error  "An
>internal error occurred: 50EA8B0A168C0.A8CAE85.ED001888".I have been
>trying
>since two days with no luck. Could it be that only the admin can register
>users? I am actually not sure whom I should be contacting regarding
>registration or other issues related to review board.
>>
>> Thank you,
>> -Rizwana
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users  gem5.org<http://gem5.org>
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>Hello,
>
>I am also having the same issue for the past four days. Any word on this
>issue?
>
>Thanks,
>Dave
>___
>gem5-users mailing list
>gem5-users@gem5.org<mailto:gem5-users@gem5.org>
>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium.  Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No:  2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No:  2548782

___
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No: 2548782___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Reviewboard registration error

[Ali Saidi via gem5-users]

Try now?

Thanks,
Ali


On 2/11/15, 11:36 AM, "Dave Werner via gem5-users" 
wrote:

>Rizwana Begum via gem5-users  gem5.org> writes:
>
>>
>> Hello All,
>> I am trying to register on review board, but end up with error  "An
>internal error occurred: 50EA8B0A168C0.A8CAE85.ED001888".I have been
>trying
>since two days with no luck. Could it be that only the admin can register
>users? I am actually not sure whom I should be contacting regarding
>registration or other issues related to review board.
>>
>> Thank you,
>> -Rizwana
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users  gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>Hello,
>
>I am also having the same issue for the past four days. Any word on this
>issue?
>
>Thanks,
>Dave
>___
>gem5-users mailing list
>gem5-users@gem5.org
>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium.  Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No:  2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No:  2548782

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Read cache hits and misses after 1000 instructions

[Ali Saidi via gem5-users]

You can dump the stats every 1000 instructions, but it will be quite slow. You 
can modify configs/common/Simulate.py to call m5.stats.dump() and 
m5.stats.reset() on every exit from the simulation loop which you can program 
with cpu.max_insts_any_thread. 

Ali

> On Dec 31, 2014, at 3:37 AM, Kumail Ahmed via gem5-users 
>  wrote:
> 
> Hello,
> 
> Is there any way to read the cache hits/misses every thousand instruction?
> 
> Can you tell me the  files that I can modify to achieve this functionality?
> 
> Thanks,
> Kumail
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] How to enable a device

[Ali Saidi via gem5-users]

The hdlcd should be controlled by the kernel, not by a application as it won’t 
have a mapping for the physical addresses. If you download the latest kernels 
from the website they support the hdlcd.

Ali

On Nov 27, 2014, at 3:05 AM, via gem5-users  wrote:

> Hi,everyone:
> 
> I would like to make the devices in arm architecture work in FS mode like the 
> hdlcd.I found the python code related to the hdlcd in src/dev/arm/RealView.py:
> 
> hdlcd=HDLcd(pio_addr=0x2b00,int_num=117)
> 
> I think the address 0x2b00 is the start address the device responds to, 
> to drive a device,we should  configure its registers,so I wrote the C 
> application hdlcd.c to enable the hdlcd:
> 
> 
> 
> int main()
> 
> { volatile unsigned int *p=(volatile unsigned int*)0x2b000230;(the address of 
> the enable register of hdlcd)
> 
>   *p=0x0001;
> 
>   Return 0;
> 
> 
> }
> 
> 
> 
> 
> Then I compiled the code above and created the script hdlcd.rcS in 
> gem5/configs/boot:
> 
> 
> 
> #!/bin/sh
> 
> #wait for system to calm down
> 
> Sleep 10
> 
> #take a checkpoint in 10ns
> 
> m5 checkpoint 10
> 
> #Reset the stats
> 
> m5 reset stats
> 
> #Run hdlcd
> 
> /hdlcd
> 
> #Exit the simulation
> 
> 
> m5 exit
> 
> 
> 
> Then I run the application in gem5 in FS mode.
> 
> 
> Command line:
> 
> ~/gem5$ sudo mount –o,loop,offset=32256 dist/disks/linux-arm-ael.img /mnt
> 
> ~/gem5$ sudo cp hdlcd /mnt
> 
> ~/gem5$ sudo umount /mnt
> 
> 
> ~/gem5$ export LINUX_IMAGE=dist/disks/linux-arm-ael.img
> 
> 
> ~/gem5$ ./build/ARM/gem5.opt configs/example/fs.py 
> --kernel=vmlinux-3.3-arm-vexpress-emm-pcie --disk=linux-arm-ael.img 
> --mem-size=512MB --machine-type=VExpress_EMM --script=./configs/boot/hdlcd.rcS
> 
> gem5 Simulator System. http://gem5.org
> 
> 
> …
> 
> 
> Info:kernel located at:/dist/binaries/vmlinux-3.3-arm-vexpress-emm-pcie
> 
> Listening for system connection on port 5900
> 
> Listening for system connection on port 3456
> 
> 0:system.cpu.isa:ISA system set to:0xd63b780 0xd63b780
> 
> 
> 0:system.remote_gdb.listener.Listening for remote gdb #0 on port 7000
> 
> Info:Using bootloader at address 0x10
> 
> 
> Info:Using kernel entry physical address at 0x80008000
> 
> 
> REAL SIMULATION
> 
> 
> Info:Entering event queue@0.Starting simulation…
> 
> 
> …
> 
> Writing checkpoint
> 
> Info：Entering event queue @12607424867000.starting simulation…
> 
> 
> Exiting@tick 12608849941000 because m5_exit instruction encountered
> 
> 
> 
> Terminal
> 
> 
> ~/gem5$ ./util/term/m5term 127.0.0.1 3456
> 
> 
> m5 slave terminal:Terminal 0
> 
> 
> …
> 
> 
> Starting Pid 576,tty “:’/etc/rc.d/rc.local’
> 
> 
> Warning:can’t open /etc/matlab:No such file or directory
> 
> Thu Jan 1 00:00:02 UTC 2009
> 
> S:devpts
> 
> Thu Jan 1 00:00:02 UTC 2009
> 
> Segmentation fault
> 
> 
> 
> 
> It showed me a segmentation fault.
> 
> 
> 
> 
> I used gdb to debug it.I set the debug flag “HDLcd”.
> 
> 
> Command line:
> 
> 
> ~/gem5$ gdb --args ./build/ARM/gem5.opt configs/example/fs.py 
> --kernel=vmlinux-3.3-arm-vexpress-emm-pcie --disk=linux-arm-ael.img 
> --mem-size=512MB --machine-type=VExpress_EMM --script=./configs/boot/hdlcd.rcS
> 
> ...
> 
> (gdb)call setDebugFlag(“HDLcd”)
> 
> (gdb) continue
> 
> continuing
> 
> 
> gem5 Simulator System. http://gem5.org
> 
> ...
> 
> Writing checkpoint
> 
> 
> 12607424274000:system.realview.hdlcd:Serializing ARM HDLCD
> 
> Info：Entering event queue @12607424274000.starting simulation…
> 
> 
> Exiting@tick 12608849456000 because m5_exit instruction encountered
> 
> 
> 
> The “Serializing ARM HDLCD” is in HDLcd::serialize(std::ostream &os),it shows 
> the serialize() function is called,but I think if a device is enabled,its 
> read() or write() function should be called.
> 
> So does anyone know how to call the read() or write() function of a device 
> and to make it work.I would appreciate any advice how should I drive a device.
> 
> Thanks
> 
>  
> 
> 
> Ran Luo
> 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Having the Gem5 system without caches

[Ali Saidi via gem5-users]

 

If you haven't specified --caches there aren't any caches in the system.


A configuration file the kernel is reading specifies caches exist for
the kernels purposes, but there aren't any in the system. 

Ali 

On 20.11.2014 15:43, Thom Popovici via gem5-users wrote: 

> Hi!
> 
> I would like to configure the system I am running without any caches, all the 
> request I want to be directed towards the main memory. Does anyone have any 
> scripts or information on how to do that?
> 
> I ran the AtomicSimple case without specifying the --caches, but when I start 
> telnet into the image I get the following:
> Calibrating delay loop (skipped) preset value.. 3999.96 BogoMIPS 
> (lpj=723)
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU1: M5 Simulator Fake M5 x86_64 CPU stepping 01
> 
> Can someone help?
> 
> Thanks
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] how to update m5struct in vmlinux_2.6.27-gcc_4.3.4

[Ali Saidi via gem5-users]

 

You can take that one m5_struct.patch and apply it alone to the kernel
you're trying to use. 

Ali 

On 07.11.2014 03:46, Sanem Arslan via gem5-users wrote: 

> Hi Anthony,
> To apply these patches, should I follow the steps in the following 
> link? http://www.m5sim.org/Compiling_a_Linux_Kernel [1]
> 
> If yes, I couldnt reach the web site since it is broken 
> (http://www.kernel.org/hg/linux-2.6/ [2]). Is there any other way?
> 
> Thanks,
> Sanem.
> 
> Anthony Gutierrez via gem5-users 
> These patches will give an idea, and they're not difficult to port. 
> http://repo.gem5.org/linux-patches/ [3] Anthony Gutierrez 
> http://web.eecs.umich.edu/~atgutier [4] On Thu, Nov 6, 2014 at 3:38 PM, Sanem 
> Arslan via gem5-users < gem5-users@gem5.org> wrote: Hello, I want to update 
> m5struct.c to take additional information from the kernel. I am using kernel, 
> PAL code and disk image for the ALPHA provided by UT Texas 
> (http://www.cs.utexas.edu/~parsec_m5/ [5]). In order to update m5struct, I 
> should reach to files inside vmlinux_2.6.27-gcc_4.3.4 and re-compile it. But 
> I dont know how I can do that. Is there anyone who can guide me on that 
> issue? Thanks in advance. Sanem. 
> ___ gem5-users mailing list 
> gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [6]

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [6]

 

Links:
--
[1] http://www.m5sim.org/Compiling_a_Linux_Kernel
[2] http://www.kernel.org/hg/linux-2.6/
[3] http://repo.gem5.org/linux-patches/
[4] http://web.eecs.umich.edu/~atgutier
[5] http://www.cs.utexas.edu/~parsec_m5/
[6] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Mounting second image FS

[Ali Saidi via gem5-users]

 

Hi George, 

there isn't a way built into the example configuration scripts to
connect more than one disk image, but if you look for how the
--disk-image (disk_image in the python files) is used you can see that
the parameter is ultimately passed from fs.py into FSConfig.py which
adds that disk image to a port on the disk image controller. If your
case you can add another disk as a IDE slave or replace the swapfile
disk image if you dint need it. 

Ali 

On 06.11.2014 20:59, George Michelogiannakis via gem5-users wrote: 

> Hi all, 
> 
> I have the standard setup with the x86 disk image containing parsec. I'm 
> trying to add benchmarks and because that image has no more space, I created 
> new images with the extra benchmarks. Those images don't have the OS, 
> therefore the primary x86 image needs to boot and I need to mount the second 
> image. 
> 
> The only reference in the wiki I could find is that I have to add it to 
> FSConfig.py or provide it as a --disk-image. Does that parameter take two 
> image files? 
> 
> Also, how do I mount it in the rcS file (from the m5 console)? 
> 
> Thank you! 
> George M 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Instcount <=1500 failing for a single core full system simulation

[Ali Saidi via gem5-users]

 

Are you using the latest gem5 code? How long does it take for you to
reach this issue? 

The issue is that these instructions have been created, but they haven't
been deleted. This means that some resource in the pipeline is holding a
reference to the instruction and it's not being deleted, the question is
why and which resource. If you run the debug version of gem5 you'll get
a list of which instructions haven't been deleted and then you can use
those instruction serial numbers to see where they've gone in the
pipeline and how the got "lost." 

Thanks, 

Ali 

On 06.11.2014 20:17, Urmish Ajit Thakker via gem5-users wrote: 

> Hi,
> 
> I was running the full system simulation for the newly released arm 64 
> kernel and image. While running the simulation I encountered the 
> following error -
> 
> gem5.opt: build/ARM/cpu/base_dyn_inst_impl.hh:123: void BaseDynInst< 
>  >::initVars() [with Impl = O3CPUImpl]: 
> Assertion `cpu->instcount <= 1500' failed.
> 
> The number of CPUs I use for simulation is only one (I use the dtb file 
> part of the download package).
> 
> I have seen some related issues on the gem5 mailing list but from what I 
> gathered they seem to be for multicore scenario.
> 
> This is the command that I give to run the simulation -
> 
> build/ARM/gem5.opt configs/example/fs.py --caches --cpu-type=DerivO3CPU 
> --num-cpus=1 --machine-type=VExpress_EMM64 
> --disk-image=/research/uthakker/gem5/arm_october_64/disks/arm_8gb 
> --kernel=vmlinux.aarch64.20140821 
> --dtb-filename=vexpress.aarch64.20140821.dtb 
> --script=/research/uthakker/gem5/gem5/configs/boot/openCV.rcs
> 
> Any pointers as to why is this happening or how should I start debugging 
> this isssue?
> 
> Regards,
> Urmish
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Boot loader issue

[Ali Saidi via gem5-users]

It's also in the full system files tarball on the download page of the website. 

Ali 

Sent from my ARM powered mobile device

> On Nov 2, 2014, at 9:34 AM, Guru Prasad via gem5-users  
> wrote:
> 
> Go to /system/arm and run make
> copy the output to /system/binaries/
> 
> 
>> On Sun, Nov 2, 2014 at 9:33 AM, Anmol Mohanty via gem5-users 
>>  wrote:
>> Hi Gem5 community, I am getting this bootloader issue. This has been raised 
>> before, I have tried all the steps previously suggested and set the correct 
>> paths and environment. Is anyone able to crack this?
>> 
>> I am getting this issue:-
>> ---
>> amohanty@grover:~/gem5$  build/ARM/gem5.opt configs/example/fs.py -b 
>> bbench-ics --kernel=vmlinux_and_config_arm/vmlinux.smp.mouse.arm
>> gem5 Simulator System.  http://gem5.org
>> gem5 is copyrighted software; use the --copyright option for details.
>> 
>> gem5 compiled Sep 17 2014 22:25:55
>> gem5 started Nov  2 2014 07:54:22
>> gem5 executing on grover
>> command line: build/ARM/gem5.opt configs/example/fs.py -b bbench-ics 
>> --kernel=vmlinux_and_config_arm/vmlinux.smp.mouse.arm
>> Global frequency set at 1 ticks per second
>> info: kernel located at: 
>> /home/amohanty/gem5/system/binaries/vmlinux_and_config_arm/vmlinux.smp.mouse.arm
>> fatal: Could not read bootloader: 
>> /home/amohanty/gem5/system/binaries/boot.arm
>>  @ tick 0
>> [ArmSystem:build/ARM/arch/arm/system.cc, line 79]
>> Memory Usage: 481664 KBytes
>> Program aborted at tick 0
>> Aborted (core dumped)
>> ---
>> 
>> Is there even a file like boot.arm. I have tried finding it, but it doesn't 
>> seem to be there
>> 
>> -- 
>> Best Regards,
>> Anmol Mohanty
>> 
>> 
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Problem of ARMv8 in gem5-mirror

[Ali Saidi via gem5-users]

 

The mirror is the current development repository not the stable
repository. There was just a change in the development repository to
switch to using PCI devices for the boot disk. Unfortunately there isn't
really a good way to support both at once, but a new set of kernels is
available on the gem5 download page that support PCI device and coupled
with the config changes in gem5-dev the system will boot. If you want to
use the old kernel for some reason -- you really shouldn't -- you can
replace this line self.realview.ide.disks = [self.cf0] in FSConfig.py
with self.realview.cf_ctrl.disks = [self.cf0]. 

Thanks, 

Ali 

On 28.10.2014 10:27, Erfan Azarkhish via gem5-users wrote: 

> Dear All, 
> 
> I ha 
> ve a problem with booting linux on ARMv8 on gem5-mirror 
> (https://github.com/uart/gem5-mirror [2]): 
> (I need gem5-mirror because of the recent support for XBAR, interleaved 
> addressing, and the new DRAM controller) 
> 
> When I try to boot linux on ARMv8 in the GEM5-STABLE, there is no problem and 
> here is the message I get: 
> [ 2.542771] VFS: Mounted root (ext2 filesystem) on device 8:1. 
> 
> However, when I do the same with GEM5-MIRROR, I get the following message 
> 
> [ 2.542570] VFS: Cannot open root device "sda1" or unknown-block(0,0): error 
> -6 
> [ 2.542571] Please append a correct "root=" boot option; here are the 
> available partitions: 
> [ 2.542572] Kernel panic - not syncing: VFS: Unable to mount root fs on 
> unknown-block(0,0) 
> [ 2.542573] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc2+ #1 
> [ 2.542574] Call trace: 
> [ 2.542575] [] dump_backtrace+0x0/0x12c 
> [ 2.542576] [] show_stack+0x14/0x1c 
> [ 2.542577] [] dump_stack+0x78/0xc4 
> [ 2.542578] [] panic+0xe8/0x208 
> [ 2.542579] [] mount_block_root+0x1d8/0x278 
> [ 2.542580] [] mount_root+0x118/0x134 
> [ 2.542582] [] prepare_namespace+0x140/0x188 
> [ 2.542583] [] kernel_init_freeable+0x1b8/0x1d8 
> [ 2.542584] [] kernel_init+0x10/0xd4 
> 
> Could someone please help me? 
> 
> Thanks a lot 
> Best, -- 
> 
> Erfan Azarkhish
> Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
> DEI - University of Bologna, Italy
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[2] https://github.com/uart/gem5-mirror
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Installing OpenCV on ARM Image and running it on gem5

[Ali Saidi via gem5-users]

 

Do you have enough memory on your x86 machine? It will likely take quite
a bit. 

Thanks, 

Ali 

On 29.10.2014 21:03, Urmish Ajit Thakker via gem5-users wrote: 

> Hi,
> 
> I was wondering if anyone has tried to install opencv on the arm image 
> (armv7) provided in the repository?
> 
> I was able to install all the dependencies for opencv 2.4.5 but when I do a 
> make (after chroot'ing into the image), I get an error
> "virtual memory exhausted: cannot allocate more memory".
> 
> I tried cross compiling, however the cross compiler does not detect the 
> ffmpeg lib. I modify the following variables 
> 
> * LD_LIBRARY_PATH
> * C_INCLUDE_PATH
> * CPLUS_INCLUDE_PATH
> * PKG_CONFIG_PATH
> * PKG_CONFIG_LIBDIR
> * PATH
> * CMAKE_LIBRARY_PATH
> * CMAKE_INCLUDE_PATH
> 
> and point the cmake to the ffmpeg libraries compiled for armv7 architecture. 
> However, it does not detect it and my cmake output is -
> 
> -- Video I/O:
> -- DC1394 1.x: NO
> -- DC1394 2.x: NO
> -- FFMPEG: **NO**
> -- codec: NO
> -- format: NO
> -- util: NO
> -- swscale: NO
> -- gentoo-style: YES
> -- GStreamer: NO
> -- OpenNI: NO
> -- OpenNI PrimeSensor Modules: NO
> -- PvAPI: NO
> -- GigEVisionSDK: NO
> -- UniCap: NO
> -- UniCap ucil: NO
> -- V4L/V4L2: NO/YES
> -- XIMEA: NO
> -- Xine: NO
> My host machine is a 64 bit x86 machine.
> 
> Regards,
> Urmish
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Phys reg 13 to 42 with no access!

[Ali Saidi via gem5-users]

Are you running in SE or FS mode?

For 32-bit ARM code registers 16->32 are various shadow copies of
registers for different interrupt/exception levels.

Ali


On 10/29/14, 10:56 AM, "Negar Miralaei via gem5-users"
 wrote:

>Hi guys,
>
>I'm looking at integer register values/accesses at the Physical Register
>File. Running few applications (from Spec2006), it shows no accesses for
>reg#13 to reg#42 (in some cases the range is from reg#15 to reg#33). I
>was wondering whether anyone knows if these registers are reserved for
>specific conditions or interrupts, which would be used at FS mode.
>I'm using ARM platform, and running in the SE mode.
>
>Thanks,
>Negar
>
>--
>Negar Miralaei
>http://www.cl.cam.ac.uk/~nm537/
>___
>gem5-users mailing list
>gem5-users@gem5.org
>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium.  Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No:  2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No:  2548782

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Fixed repeat-switch bugs

[Ali Saidi via gem5-users]

 

Hi Alberto, 

Yes it would be great if we could have these fixes. Would you mind
posting them to our review board (reviews.gem5.org)? 

With the public/private change below it would probably be best if you
added an accessor methods isLoadStoreBlocked() that was public but left
the variables themselves private. 

Thanks for finding the bugs and fixing them, 

Ali 

On 13.10.2014 17:18, Naranjo Carmona, Alberto Javier via gem5-users
wrote: 

> Hello everybody,
> 
> Part of my research project is to run experiments where I constanly switch 
> from timing to o3 model back and forth (--repeat-switch option). In 
> particular I am using X86 with both MESI and MOESI.
> However, after many switches, I faced some problems while draining the O3 
> model: I either hit the assert(!memReq) assertion in drainSanityCheck() or 
> got stuck in the draining process until I reached the maxtick count and the 
> simulation ended.
> After some debugging I could found the causes of the errors and I was able to 
> switch thousands of times per run. Although it worked fine for my project, it 
> is probable that these changes mess up other parts of the code.
> In this post I want to do two things:
> - Ask if anyone can identify a condition where the modifications I did will 
> result in an error in the simulator
> - Make public the changes so other people can use it
> 
> In particular, the changes I did are:
> /src/cpu/o3/fetch_impl.hh
> @@ -738,7 +738,7 @@
> decoder[tid]->reset();
> 
> // Clear the icache miss if it's outstanding.
> - if (fetchStatus[tid] == IcacheWaitResponse) {
> + if (fetchStatus[tid] == IcacheWaitResponse || fetchStatus[tid] == 
> IcacheWaitRetry) {
> DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.n",
> tid);
> memReq[tid] = NULL;
> 
> /src/cpu/o3/lsq_impl.hh 
> @@ -175,8 +175,10 @@
> }
> 
> if (retryTid != InvalidThreadID) {
> - DPRINTF(Drain, "Not drained, the LSQ has blocked the caches.n");
> - drained = false;
> + if(thread[retryTid].isLoadBlocked || thread[retryTid].isStoreBlocked) {
> + DPRINTF(Drain, "Not drained, the LSQ has blocked the caches.n");
> + drained = false;
> + }
> }
> 
> return drained;
> 
> /src/cpu/o3/lsq_unit.hh
> @@ -466,12 +466,14 @@
> /** The packet that needs to be retried. */
> PacketPtr retryPkt;
> 
> + public: //May be there is a better way than make it public, but I need to 
> know when the store and load are blocked
> /** Whehter or not a store is blocked due to the memory system. */
> bool isStoreBlocked;
> 
> /** Whether or not a load is blocked due to the memory system. */
> bool isLoadBlocked;
> 
> + private:
> /** Has the blocked load been handled. */
> bool loadBlockedHandled;
> 
> /src/mem/ruby/system/RubyMemoryControl.cc
> @@ -675,7 +675,7 @@
> {
> DPRINTF(RubyMemory, "MemoryController drainn");
> if(m_event.scheduled()) {
> - deschedule(m_event);
> + //deschedule(m_event); //Why does it deschedules? If a store request is in 
> flight while draining, it won't be satisfied and the cpu won't drain
> }
> return 0;
> }
> 
> If these changes don't generate any other error somewhere else in the code, 
> do you think I should add it as a patch? If so, what is the process?
> 
> Thank you very much
> -- 
> 
> Alberto Javier Naranjo-Carmona
> M.S. Student Computer Engineering
> Texas A&M University, College Station, TX 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Enabling --dual for ARM on Gem5

[Ali Saidi via gem5-users]

You need to use the ‹machine-type=VExpress_EMM and the Vexpress kernel
from the website.

Thanks,
Ali


On 10/20/14, 6:44 PM, "Ramanan Sivasundaram via gem5-users"
 wrote:

>Has anybody got the --dual args working for ARM on gem5? When I try to run
>build/ARM/gem5.opt configs/example/fs.py
>--disk-image=/home/ram/full_system_images/arm-system-2011-08/disks/arm-ubu
>ntu.img
>--kernel=/home/ram/Desktop/linux-2.6.38.1/vmlinux --mem-size=256MB
>--script=configs/boot/temp.rcS --dual
>
>I get the error output:
>Global frequency set at 1 ticks per second
>Error in unproxying port 'int0' of etherlink
>Traceback (most recent call last):
>  File "", line 1, in 
>  File
>"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/main.py",
>line 388, in main
>  File "configs/example/fs.py", line 245, in 
>Simulation.run(options, root, test_sys, FutureClass)
>  File "/home/ram/gem5/configs/common/Simulation.py", line 415, in run
>m5.instantiate(checkpoint_dir)
>  File
>"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/simulate.py",
>line 87, in instantiate
>  File
>"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/SimObject.py",
>line 926, in unproxyParams
>  File
>"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/params.py",
>line
>1451, in unproxy
>  File
>"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/proxy.py",
>line
>89, in unproxy
>  File
>"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/proxy.py",
>line
>164, in find
>  File
>"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/SimObject.py",
>line 734, in __getattr__
>AttributeError: object 'RealViewPBX' has no attribute 'ethernet'
>  (C++ object is not yet constructed, so wrapped C++ methods are
>unavailable.)
>
>If I run that exact command without the --dual, it works perfectly.
>
>My ultimate goal is to get two instances of gem5 to communicate. Can
>anybody
>help?
>
>Regards
>
>___
>gem5-users mailing list
>gem5-users@gem5.org
>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium.  Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No:  2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No:  2548782

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] [ARM] Interrupt handling

[Ali Saidi via gem5-users]

Yes… however your interrupt solution isn’t necessarily going to solve that 
problem either. You could take an interrupt during a system call or a nested 
interrupt and keeping track of that tends to get pretty ugly. I’d expect the 
amount of time in sys calls the be quite low.

Ali


From: Guru Prasad mailto:gurup...@buffalo.edu>>
Date: Thursday, October 9, 2014 at 1:39 PM
To: Ali Saidi mailto:ali.sa...@arm.com>>, gem5 users mailing 
list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] [ARM] Interrupt handling

Thanks for the answer.
I have thought about this and implemented it earlier.
However, I realized after implementing it that this solution would lead to 
system calls being unaccounted for, right?


On Thu, Oct 9, 2014 at 2:35 PM, Ali Saidi via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
The easiest way to do this is probably to only count instructions when 
InUserMode() is true. You could wrap the stat accounting function in this in 
the o3 commit stage and that would probably solve your problem instead of 
trying to cache all sources of interrupts.
Ali


From: Guru Prasad via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Guru Prasad mailto:gurup...@buffalo.edu>>, gem5 
users mailing list mailto:gem5-users@gem5.org>>
Date: Thursday, October 9, 2014 at 1:08 PM
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: [gem5-users] [ARM] Interrupt handling

Hi,

I am looking to implement some custom instruction accounting.
I tried running some SPEC benchmarks at different frequencies and noticed that 
the number of instructions vary across runs. I believe this is because of timer 
based interrupts and thus would like to eliminate these.

To do this, I've been trying to find out where Gem5 sets the interrupt flags 
and triggers the ISR jump. So far, the O3 model has a 'processInterrupts' 
function that seems to cause the trap.
Is this a reasonable place to stop stat accounting?

Also, I looked into the kernel code to try and figure out how it is resetting 
the IRQ flags. looking at arch/arm/kernel/entry-armv.S, I couldn't find 
precisely where/what is doing this. However, searching kernel code for 
local_irq_enable/local_irq_disable, I see that they seem to be writing to CPSR 
with either orr #128 or bic #128. Is this how interrupts set/reset? If so, is 
src/arch/arm/isa.cc setMiscReg a good place to instrument?



-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No: 2548782

___
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No: 2548782___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] [ARM] Interrupt handling

[Ali Saidi via gem5-users]

The easiest way to do this is probably to only count instructions when 
InUserMode() is true. You could wrap the stat accounting function in this in 
the o3 commit stage and that would probably solve your problem instead of 
trying to cache all sources of interrupts.
Ali


From: Guru Prasad via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Guru Prasad mailto:gurup...@buffalo.edu>>, gem5 
users mailing list mailto:gem5-users@gem5.org>>
Date: Thursday, October 9, 2014 at 1:08 PM
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: [gem5-users] [ARM] Interrupt handling

Hi,

I am looking to implement some custom instruction accounting.
I tried running some SPEC benchmarks at different frequencies and noticed that 
the number of instructions vary across runs. I believe this is because of timer 
based interrupts and thus would like to eliminate these.

To do this, I've been trying to find out where Gem5 sets the interrupt flags 
and triggers the ISR jump. So far, the O3 model has a 'processInterrupts' 
function that seems to cause the trap.
Is this a reasonable place to stop stat accounting?

Also, I looked into the kernel code to try and figure out how it is resetting 
the IRQ flags. looking at arch/arm/kernel/entry-armv.S, I couldn't find 
precisely where/what is doing this. However, searching kernel code for 
local_irq_enable/local_irq_disable, I see that they seem to be writing to CPSR 
with either orr #128 or bic #128. Is this how interrupts set/reset? If so, is 
src/arch/arm/isa.cc setMiscReg a good place to instrument?



-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No: 2548782___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Cannot Compile Gem5 on MacOS Version 10.9.4

[Ali Saidi via gem5-users]

I think you’re running an older version of gem5. WE’ve recently fixed some of 
these issues in the tip of the development repository.

Ali


From: Khaled Mahmoud via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Khaled Mahmoud mailto:khaledi...@yahoo.com>>, 
gem5 users mailing list mailto:gem5-users@gem5.org>>
Date: Thursday, September 25, 2014 at 1:47 AM
To: "gem5-users@gem5.org" 
mailto:gem5-users@gem5.org>>
Subject: [gem5-users] Cannot Compile Gem5 on MacOS Version 10.9.4

Hi,


I am trying to compile gem5 on MacOS version 10.9.4 but I am getting a lot of 
compilation errors.
Most of these error are abut use of undeclared identifier. Can you please help 
:(.
Here is the log of compilation output I see :

In file included from build/ALPHA/base/inet.cc:52:
build/ALPHA/base/inet.hh:325:23: error: base class 'ip_opt' has a flexible 
array member
struct IpOpt : public ip_opt
  ^
build/ALPHA/base/inet.hh:327:35: error: use of undeclared identifier 'opt_type'
uint8_t type() const { return opt_type; }
  ^
build/ALPHA/base/inet.hh:328:55: error: use of undeclared identifier 'opt_type'
uint8_t typeNumber() const { return IP_OPT_NUMBER(opt_type); }
  ^
ext/dnet/ip.h:273:28: note: expanded from macro 'IP_OPT_NUMBER'
#define IP_OPT_NUMBER(o)((o) & 0x1f)
  ^
In file included from build/ALPHA/base/inet.cc:52:
build/ALPHA/base/inet.hh:329:53: error: use of undeclared identifier 'opt_type'
uint8_t typeClass() const { return IP_OPT_CLASS(opt_type); }
^
ext/dnet/ip.h:272:28: note: expanded from macro 'IP_OPT_CLASS'
#define IP_OPT_CLASS(o) ((o) & 0x60)
  ^
In file included from build/ALPHA/base/inet.cc:52:
build/ALPHA/base/inet.hh:330:55: error: use of undeclared identifier 'opt_type'
uint8_t typeCopied() const { return IP_OPT_COPIED(opt_type); }
  ^
ext/dnet/ip.h:271:28: note: expanded from macro 'IP_OPT_COPIED'
#define IP_OPT_COPIED(o)((o) & 0x80)
  ^
In file included from build/ALPHA/base/inet.cc:52:
build/ALPHA/base/inet.hh:331:64: error: use of undeclared identifier 'opt_len'
uint8_t len() const { return IP_OPT_TYPEONLY(type()) ? 1 : opt_len; }
   ^
build/ALPHA/base/inet.hh:337:42: error: use of undeclared identifier 'opt_data'
const uint8_t *data() const { return opt_data.data8; }
 ^
build/ALPHA/base/inet.hh:342:43: error: use of undeclared identifier 'opt_data'
uint16_t satid() const { return ntohs(opt_data.satid); }
  ^
/usr/include/sys/_endian.h:126:39: note: expanded from macro 'ntohs'
#define ntohs(x)__DARWIN_OSSwapInt16(x)
 ^
/usr/include/libkern/_OSByteOrder.h:72:40: note: expanded from macro 
'__DARWIN_OSSwapInt16'
((__uint16_t)(__builtin_constant_p(x) ? __DARWIN_OSSwapConstInt16(x) : 
_OSSwapInt16(x)))
   ^
In file included from build/ALPHA/base/inet.cc:52:
build/ALPHA/base/inet.hh:342:43: error: use of undeclared identifier 'opt_data'
/usr/include/sys/_endian.h:126:39: note: expanded from macro 'ntohs'
#define ntohs(x)__DARWIN_OSSwapInt16(x)
 ^
/usr/include/libkern/_OSByteOrder.h:72:71: note: expanded from macro 
'__DARWIN_OSSwapInt16'
((__uint16_t)(__builtin_constant_p(x) ? __DARWIN_OSSwapConstInt16(x) : 
_OSSwapInt16(x)))
  ^
/usr/include/libkern/_OSByteOrder.h:44:34: note: expanded from macro 
'__DARWIN_OSSwapConstInt16'
((__uint16_t)__uint16_t)(x) & 0xff00) >> 8) | \
 ^
In file included from build/ALPHA/base/inet.cc:52:
build/ALPHA/base/inet.hh:342:43: error: use of undeclared identifier 'opt_data'
/usr/include/sys/_endian.h:126:39: note: expanded from macro 'ntohs'
#define ntohs(x)__DARWIN_OSSwapInt16(x)
 ^
/usr/include/libkern/_OSByteOrder.h:72:71: note: expanded from macro 
'__DARWIN_OSSwapInt16'
((__uint16_t)(__builtin_constant_p(x) ? __DARWIN_OSSwapConstInt16(x) : 
_OSSwapInt16(x)))
  ^
/usr/include/libkern/_OSByteOrder.h:45:32: note: expanded from macro 
'__DARWIN_OSSwapConstInt16'
(((__uint16_t)(x) & 0x00ff) << 8)))
   ^
In file included from build/ALPHA/base/inet.cc:52:
build/ALPHA/base/inet.hh:342:43: error: use of undeclared identifier 'opt_data'
/usr/include/sys/_endian.h:126:39: note: expanded from macro 'ntohs'
#define ntohs(x)__DARWIN_OSSwapInt16(

Re: [gem5-users] Running Assembly code on ARM SE mode

[Ali Saidi via gem5-users]

You can run assembly code, but you’ll need to compile it. Something like the 
following will compile with gcc. It uses both ARM and Thumb code. 

.text
.syntax unified

.globl _start
.arm
_start:
start:
mov r0, #0x1
mov r1, #0
blx loop
.thumb
.align 7
loop:
add r2, r1, #1
subs r0, r0, #1
bne loop
mov r7, #1
svc #0

Ali



On Sep 17, 2014, at 4:49 AM, Vanchinathan Venkataramani via gem5-users 
 wrote:

> Hi all
> 
> Is it possible to write my own assembly code containing around 10-15 
> instructions and run it on gem5 without converting it into a binary with 
> header and footer code?
> 
> Thanks in advance.
> 
> V Vanchinathan
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] ARMv8 Client-Server configuration

[Ali Saidi via gem5-users]

 

Hi Ivan, 

Can you show us more of the output. Does it recognize the PCI devices?
What version of gem5 are you running. The patches required were just
committed last week. 

Ali 

On 15.09.2014 02:08, Ivan Stalev via gem5-users wrote: 

> Hi Ali and Andreas, 
> 
> When I try to boot the client-server system for arm64 with the latest gem5 
> revision (10369) I get a kernel panic: 
> 
> [ 6.660806] VFS: Cannot open root device "sda1" or unknown-block(0,0): error 
> -6 
> [ 6.660807] Please append a correct "root=" boot option; here are the 
> available partitions: 
> [ 6.660809] Kernel panic - not syncing: VFS: Unable to mount root fs on 
> unknown-block(0,0) 
> [ 6.660810] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.16.0-rc6 #2 
> [ 6.660810] Call trace: 
> [ 6.660811] [] dump_backtrace+0x0/0x130 
> [ 6.660813] [] show_stack+0x10/0x1c 
> [ 6.660814] [] dump_stack+0x74/0xb8 
> [ 6.660815] [] panic+0xe0/0x218 
> [ 6.660816] [] mount_block_root+0x1d0/0x270 
> [ 6.660817] [] mount_root+0x110/0x130 
> [ 6.660818] [] prepare_namespace+0x138/0x184 
> [ 6.660819] [] kernel_init_freeable+0x1b8/0x1dc 
> [ 6.660821] [] kernel_init+0x10/0xd4 
> [ 6.660822] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs 
> on unknown-block(0,0) 
> 
> I built the kernel according to Ali's instructions. The command line I use 
> is: 
> 
> ./build/ARM/gem5.fast -d m5out/dual-test configs/example/fs.py 
> --machine-type=VExpress_EMM64 
> --kernel=..path../linux-aarch64-gem5-4003908/vmlinux 
> --dtb-filename=..path../rtsm_ve-aemv8a-5core.dtb --mem-size=4GB 
> --cpu-type=atomic --cpu-clock=2GHz --dual 
> 
> What am I missing? 
> 
> Thanks, 
> 
> Ivan 
> 
> On Thu, Aug 28, 2014 at 2:29 PM, Ali Saidi via gem5-users 
>  wrote:
> 
> You should be able to get a new working kernel with PCIe support for AArch64 
> like the following, however you'll need all the patches that Andreas just 
> mentioned in an email to gem5-dev as committed next week. 
> 
> wget 
> "http://www.linux-arm.org/git?p=linux-aarch64-gem5.git;a=snapshot;h=400390889828685d432d38406cbd9c7afceeaa15;sf=tgz
>  [1]" -O linux-aarch64-gem5.tgz 
> tar zxvf linux-aarch64-gem5.tgz 
> cd linux-aarch64-gem5-4003908 
> make ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- gem5_defconfig 
> make ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- -j4 
> 
> Thanks, 
> Ali 
> 
> From: Ali Saidi via gem5-users 
> Reply-To: Ali Saidi , gem5 users mailing list 
> 
> Date: Saturday, August 23, 2014 at 2:21 PM
> To: Ivan Stalev , gem5 users mailing list 
> 
> 
> Subject: Re: [gem5-users] ARMv8 Client-Server configuration 
> 
> You're not going to have any support for PCIe device with that kernel. We're 
> working on the last bit of debugging and polishing around a kernel that will 
> support it -- I intended to have it out 2 weeks ago, but we're still 
> diligently working and it should be out in the next couple of days. 
> 
> Ali 
> 
> On Aug 20, 2014, at 10:36 AM, Ivan Stalev  wrote: 
> 
> Edit: I was using my own compiled kernel. I am now using the default kernel, 
> vmlinux-3.14-aarch64-vexpress-emm64, and it appears not to crash. I will go 
> ahead and test it out. 
> 
> On Wed, Aug 20, 2014 at 11:19 AM, Ivan Stalev  wrote:
> 
> Hi Andreas, 
> 
> No problem, I figured it wasn't the 80 char README file patch :) 
> 
> I applied the 7 patches you posted this morning, but now when I run in dual 
> mode, gem5 crashes with this: 
> 
> panic: M5 panic instruction called at pc=0xffc8a024. 
> @ tick 58408160 
> [execute:build/ARM/arch/arm/generated/exec-ns.cc.inc, line 241403] 
> 
> The GDB backtrace from gem5.debug suggests that execution is somehow killed 
> from a manually inserted breakpoint. 
> 
> This is also after I had to hardcode the DTB file name for the drivesys in 
> /src/arch/arm/linux/system.cc [2] since it was not picking it up from the 
> command line... 
> 
> warn: Kernel supports device tree, but no DTB file specified 
> fatal: Expected a single ATAG memory entry but got 3 
> @ tick 58402784 
> [initState:build/ARM/arch/arm/linux/system.cc [2], line 202] 
> 
> Can you share how you tested the client-server configuration? 
> 
> Thank you, 
> 
> Ivan 
> 
> On Wed, Aug 20, 2014 at 4:45 AM, Andreas Hansson  
> wrote:
> 
> Hi Ivan, 
> 
> Just following up on this one. I posted the patches yesterday morning, but 
> forgot to "Publish" then. Sorry about the misunderstanding. They are all 
> there now. 
> 
> Andreas 
> 
> From: Andreas Hansson via gem5-users 
> Reply-To: Andreas Hansson , gem5 users mailing list 
> 
> Date: Tuesday, 19 

Re: [gem5-users] ARMv8 Client-Server configuration

[Ali Saidi via gem5-users]

You should be able to get a new working kernel with PCIe support for AArch64 
like the following, however you’ll need all the patches that Andreas just 
mentioned in an email to gem5-dev as committed next week.

wget 
"http://www.linux-arm.org/git?p=linux-aarch64-gem5.git;a=snapshot;h=400390889828685d432d38406cbd9c7afceeaa15;sf=tgz";
 -O linux-aarch64-gem5.tgz
tar zxvf linux-aarch64-gem5.tgz
cd linux-aarch64-gem5-4003908
make ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- gem5_defconfig
make ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- -j4

Thanks,
Ali



From: Ali Saidi via gem5-users mailto:gem5-users@gem5.org>>
Reply-To: Ali Saidi mailto:sa...@umich.edu>>, gem5 users 
mailing list mailto:gem5-users@gem5.org>>
Date: Saturday, August 23, 2014 at 2:21 PM
To: Ivan Stalev mailto:ids...@psu.edu>>, gem5 users mailing 
list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] ARMv8 Client-Server configuration

You’re not going to have any support for PCIe device with that kernel. We’re 
working on the last bit of debugging and polishing around a kernel that will 
support it — I intended to have it out 2 weeks ago, but we’re still diligently 
working and it should be out in the next couple of days.

Ali




On Aug 20, 2014, at 10:36 AM, Ivan Stalev 
mailto:ids...@psu.edu>> wrote:

Edit: I was using my own compiled kernel. I am now using the default kernel, 
vmlinux-3.14-aarch64-vexpress-emm64, and it appears not to crash. I will go 
ahead and test it out.


On Wed, Aug 20, 2014 at 11:19 AM, Ivan Stalev 
mailto:ids...@psu.edu>> wrote:
Hi Andreas,

No problem, I figured it wasn't the 80 char README file patch :)

I applied the 7 patches you posted this morning, but now when I run in dual 
mode, gem5 crashes with this:

panic: M5 panic instruction called at pc=0xffc8a024.
 @ tick 58408160
[execute:build/ARM/arch/arm/generated/exec-ns.cc.inc, line 241403]

The GDB backtrace from gem5.debug suggests that execution is somehow killed 
from a manually inserted breakpoint.

This is also after I had to hardcode the DTB file name for the drivesys in 
/src/arch/arm/linux/system.cc<http://system.cc> since it was not picking it up 
from the command line...

warn: Kernel supports device tree, but no DTB file specified
fatal: Expected a single ATAG memory entry but got 3
 @ tick 58402784
[initState:build/ARM/arch/arm/linux/system.cc<http://system.cc>, line 202]

Can you share how you tested the client-server configuration?

Thank you,

Ivan




On Wed, Aug 20, 2014 at 4:45 AM, Andreas Hansson 
mailto:andreas.hans...@arm.com>> wrote:
Hi Ivan,

Just following up on this one. I posted the patches yesterday morning, but 
forgot to “Publish” then. Sorry about the misunderstanding. They are all there 
now.

Andreas

From: Andreas Hansson via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Andreas Hansson 
mailto:andreas.hans...@arm.com>>, gem5 users mailing 
list mailto:gem5-users@gem5.org>>
Date: Tuesday, 19 August 2014 18:48
To: Ivan Stalev mailto:ids...@psu.edu>>, gem5 users mailing 
list mailto:gem5-users@gem5.org>>, Ali Saidi 
mailto:sa...@umich.edu>>

Subject: Re: [gem5-users] ARMv8 Client-Server configuration

Hi Ivan,

The patches are on the review board as of this morning (UK time).

Comments are welcome as always.

Andreas

From: Ivan Stalev via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Ivan Stalev mailto:ids...@psu.edu>>, gem5 users 
mailing list mailto:gem5-users@gem5.org>>
Date: Tuesday, 19 August 2014 18:44
To: Ali Saidi mailto:sa...@umich.edu>>
Cc: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] ARMv8 Client-Server configuration

Hi Ali,

Have you had the chance to look at the issue or have some suggestions as to 
which source files to look at?

Thanks,

Ivan


On Fri, Aug 8, 2014 at 8:34 PM, Ali Saidi 
mailto:sa...@umich.edu>> wrote:
Hi Ivan,

The kernel that you’re using and the currently gem5 don’t support pci devices 
with arm64. I hope to remedy this within a week.

Thanks,
Ali

On Aug 6, 2014, at 3:42 PM, Ivan Stalev via gem5-users 
mailto:gem5-users@gem5.org>> wrote:

> Hi everyone,
>
> I am trying to run a client-server setup using arm64. I am using the (latest) 
> linaro kernel (3.16) and disk image suggested on the GEM5 downloads page. 
> Simply building the kernel with defconfig (as recommended in the README) does 
> not seem to setup the ethernet drivers. Running "ifconfig -a" only yields the 
> loopback device/interface.
>
> I then opened up the .config (generated by defconfig) using menuconfig and 
> enabled all the settings related to ethernet and re-built the kernel. After 
> booting, "ifconfig -a" results in this:
>
> bond0 Link encap:Ethernet  HWaddr CA:FB:D0:02:D0:7E
>   BROADCAST MASTER MULTICAST  MTU:1500  Metric:1
>

Re: [gem5-users] ARMv8 Client-Server configuration

[Ali Saidi via gem5-users]

You’re not going to have any support for PCIe device with that kernel. We’re 
working on the last bit of debugging and polishing around a kernel that will 
support it — I intended to have it out 2 weeks ago, but we’re still diligently 
working and it should be out in the next couple of days. 

Ali




On Aug 20, 2014, at 10:36 AM, Ivan Stalev  wrote:

> Edit: I was using my own compiled kernel. I am now using the default kernel, 
> vmlinux-3.14-aarch64-vexpress-emm64, and it appears not to crash. I will go 
> ahead and test it out.
> 
> 
> On Wed, Aug 20, 2014 at 11:19 AM, Ivan Stalev  wrote:
> Hi Andreas,
> 
> No problem, I figured it wasn't the 80 char README file patch :)
> 
> I applied the 7 patches you posted this morning, but now when I run in dual 
> mode, gem5 crashes with this:
> 
> panic: M5 panic instruction called at pc=0xffc8a024.
>  @ tick 58408160
> [execute:build/ARM/arch/arm/generated/exec-ns.cc.inc, line 241403]
> 
> The GDB backtrace from gem5.debug suggests that execution is somehow killed 
> from a manually inserted breakpoint.
> 
> This is also after I had to hardcode the DTB file name for the drivesys in 
> /src/arch/arm/linux/system.cc since it was not picking it up from the command 
> line...
> 
> warn: Kernel supports device tree, but no DTB file specified
> fatal: Expected a single ATAG memory entry but got 3
>  @ tick 58402784
> [initState:build/ARM/arch/arm/linux/system.cc, line 202]
> 
> Can you share how you tested the client-server configuration?
> 
> Thank you,
> 
> Ivan
> 
> 
> 
> 
> On Wed, Aug 20, 2014 at 4:45 AM, Andreas Hansson  
> wrote:
> Hi Ivan,
> 
> Just following up on this one. I posted the patches yesterday morning, but 
> forgot to “Publish” then. Sorry about the misunderstanding. They are all 
> there now.
> 
> Andreas
> 
> From: Andreas Hansson via gem5-users 
> Reply-To: Andreas Hansson , gem5 users mailing list 
> 
> Date: Tuesday, 19 August 2014 18:48
> To: Ivan Stalev , gem5 users mailing list 
> , Ali Saidi 
> 
> Subject: Re: [gem5-users] ARMv8 Client-Server configuration
> 
> Hi Ivan,
> 
> The patches are on the review board as of this morning (UK time).
> 
> Comments are welcome as always.
> 
> Andreas
> 
> From: Ivan Stalev via gem5-users 
> Reply-To: Ivan Stalev , gem5 users mailing list 
> 
> Date: Tuesday, 19 August 2014 18:44
> To: Ali Saidi 
> Cc: gem5 users mailing list 
> Subject: Re: [gem5-users] ARMv8 Client-Server configuration
> 
> Hi Ali,
> 
> Have you had the chance to look at the issue or have some suggestions as to 
> which source files to look at?
> 
> Thanks,
> 
> Ivan
> 
> 
> On Fri, Aug 8, 2014 at 8:34 PM, Ali Saidi  wrote:
> Hi Ivan,
> 
> The kernel that you’re using and the currently gem5 don’t support pci devices 
> with arm64. I hope to remedy this within a week.
> 
> Thanks,
> Ali
> 
> On Aug 6, 2014, at 3:42 PM, Ivan Stalev via gem5-users  
> wrote:
> 
> > Hi everyone,
> >
> > I am trying to run a client-server setup using arm64. I am using the 
> > (latest) linaro kernel (3.16) and disk image suggested on the GEM5 
> > downloads page. Simply building the kernel with defconfig (as recommended 
> > in the README) does not seem to setup the ethernet drivers. Running 
> > "ifconfig -a" only yields the loopback device/interface.
> >
> > I then opened up the .config (generated by defconfig) using menuconfig and 
> > enabled all the settings related to ethernet and re-built the kernel. After 
> > booting, "ifconfig -a" results in this:
> >
> > bond0 Link encap:Ethernet  HWaddr CA:FB:D0:02:D0:7E
> >   BROADCAST MASTER MULTICAST  MTU:1500  Metric:1
> >   RX packets:0 errors:0 dropped:0 overruns:0 frame:0
> >   TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
> >   collisions:0 txqueuelen:0
> >   RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
> >
> > dummy0Link encap:Ethernet  HWaddr 02:58:3E:AF:F3:41
> >   BROADCAST NOARP  MTU:1500  Metric:1
> >   RX packets:0 errors:0 dropped:0 overruns:0 frame:0
> >   TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
> >   collisions:0 txqueuelen:0
> >   RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
> >
> > loLink encap:Local Loopback
> >   inet addr:127.0.0.1  Mask:255.0.0.0
> >   UP LOOPBACK RUNNING  MTU:65536  Metric:1
> >   RX packets:8 errors:0 dropped:0 overruns:0 frame:0
> >   TX packets:8 errors:0 dropped:0 overruns:0 carrier:0
> >   collisions:0 txqueuelen:0
> >   RX bytes:784 (784.0 B)  TX bytes:784 (784.0 B)
> >
> > I tried running the sample client-server rcS scripts and tried both dummy0 
> > and bond0, but pings did not go through. From others' posts and sample rcS 
> > scripts, it seems that GEM5 expects eth0.
> >
> > Does anyone know if client-server is supported for arm64 in GEM5, and if 
> > so, how to get them to communicate? I am using the latest GEM5 revision 
> > (10240).
> >
> > Thanks!
> >
> > 

Re: [gem5-users] Full system simulation in AMP mode

[Ali Saidi via gem5-users]

You’d have to add some support to gem5 to segment off a piece of memory for the 
AMP and load some code for it to run. Right now all cores jump into a boot 
loader where they all spin except cpu0 which boots linux. When linux is ready 
to bring up the other cores it sends them an interrupt and they read a 
predefined location to find their starting address. You could modify the boot 
loader to alway jump to a known location and tell linux there is only 1 cpu, 
but you’d still need to segment off a piece of memory.

Ali

On Aug 20, 2014, at 3:09 PM, Namitha Krishna via gem5-users 
 wrote:

> Hi,
> 
> Can anybody tell me how I can use Gem5 for a full system simulation of a 
> dual-core cortex-A9 in Asymmmetric multiprocessing mode when one core is 
> running Linux and the other core is running a bare-metal application. On 
> hardware, the linux core which is the master has to kick the second core with 
> a SEV (Send event) . Should this be done on Gem5 as well? Where can we 
> specify the .elf for the bare metal core if the linux image needs to be 
> passed to --kernel on the command line ? If the number of cores are 
> increased, where should the .elf files for these cores be specified?
> Can somebody please elaborate the steps and the python scripts to be modified 
> please?
> 
> regards,
> Namitha.
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] m5 ops

[Ali Saidi via gem5-users]

 

Did you build the jni with the exact same version of java you're using
to run the program? also, if you run with the jni outside of gem5 I'd
expect to see a fault of some kind. 

Thanks, 

Ali 

On 19.08.2014 11:02, jerry yin via gem5-users wrote: 

> Hi all, 
> 
> I'm following gem5 document step by step to set checkpoint for java program, 
> but get segmentation error. To repeat the error, just follow steps on the 
> website http://www.m5sim.org/M5ops [2] . Does anyone has any idea how to 
> insert java program with roi? 
> 
> Best Wishes, 
> Jer 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[2] http://www.m5sim.org/M5ops
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] ARMv8 Client-Server configuration

[Ali Saidi via gem5-users]

Hi Ivan,

The kernel that you’re using and the currently gem5 don’t support pci devices 
with arm64. I hope to remedy this within a week.

Thanks,
Ali

On Aug 6, 2014, at 3:42 PM, Ivan Stalev via gem5-users  
wrote:

> Hi everyone,
> 
> I am trying to run a client-server setup using arm64. I am using the (latest) 
> linaro kernel (3.16) and disk image suggested on the GEM5 downloads page. 
> Simply building the kernel with defconfig (as recommended in the README) does 
> not seem to setup the ethernet drivers. Running "ifconfig -a" only yields the 
> loopback device/interface. 
> 
> I then opened up the .config (generated by defconfig) using menuconfig and 
> enabled all the settings related to ethernet and re-built the kernel. After 
> booting, "ifconfig -a" results in this:
> 
> bond0 Link encap:Ethernet  HWaddr CA:FB:D0:02:D0:7E
>   BROADCAST MASTER MULTICAST  MTU:1500  Metric:1
>   RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>   TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>   collisions:0 txqueuelen:0
>   RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
> 
> dummy0Link encap:Ethernet  HWaddr 02:58:3E:AF:F3:41
>   BROADCAST NOARP  MTU:1500  Metric:1
>   RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>   TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>   collisions:0 txqueuelen:0
>   RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
> 
> loLink encap:Local Loopback
>   inet addr:127.0.0.1  Mask:255.0.0.0
>   UP LOOPBACK RUNNING  MTU:65536  Metric:1
>   RX packets:8 errors:0 dropped:0 overruns:0 frame:0
>   TX packets:8 errors:0 dropped:0 overruns:0 carrier:0
>   collisions:0 txqueuelen:0
>   RX bytes:784 (784.0 B)  TX bytes:784 (784.0 B)
> 
> I tried running the sample client-server rcS scripts and tried both dummy0 
> and bond0, but pings did not go through. From others' posts and sample rcS 
> scripts, it seems that GEM5 expects eth0. 
> 
> Does anyone know if client-server is supported for arm64 in GEM5, and if so, 
> how to get them to communicate? I am using the latest GEM5 revision (10240). 
> 
> Thanks!
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] DaCapo benchmarks

[Ali Saidi via gem5-users]

 

softfp means that fp arguments are passed in integer registers while
hardfp means that fp registers are used to pass fp arguments. They're
two different ABIs the prior allowing for a single binary to run on
systems with and without an FPU and the latter requiring an FPU because
the registers are used to pass arguments. hardfp will almost certainly
provide higher performance is all cases. You can install the required
libraries on your disk image (and actually all new Ubuntu disk images
default to hardfp and you must install softfp libraries if you desire
them). 

Thanks, 

Ali 

On 31.07.2014 14:51, Paul Rosenfeld via gem5-users wrote: 

> huh, interesting -- never would have imagined that software emulation could 
> ever perform better than a hardware implementation. I guess if you have 
> limited floating point resources on the chip, then offloading some simpler 
> operations into software is a good thing? 
> 
> On Thu, Jul 31, 2014 at 10:45 AM, Anthony Gutierrez via gem5-users 
>  wrote:
> 
> hard/soft FP will have different characteristics respectively whether run on 
> hardware or the simulator. softFP just gives the compiler more flexibility 
> when using the FP unit. softFP does not mean that all FP instructions are 
> done in SW, only that the compiler can choose whether or not to emulate or 
> use the real FP. I'd guess that softFP usually does a better job of 
> optimizing that forcing all FP instructions to be done in hardware, and that 
> hardFP is only used when you have code that needs to be hand optimized. 
> 
> Anthony Gutierrez 
> http://web.eecs.umich.edu/~atgutier [1] 
> 
> On Thu, Jul 31, 2014 at 10:06 AM, Paul Rosenfeld via gem5-users 
>  wrote:
> 
> Just out of curiosity -- from a simulation results standpoint, softFP will 
> have different performance characteristics than hardFP, correct? 
> 
> On Wed, Jul 30, 2014 at 9:17 PM, jerry yin via gem5-users 
>  wrote: 
> 
> Hi Anthony, 
> 
> Thank you! Although I remember having tried both version of jre before, I 
> tried SoftFP again, and it works!
> 
> Best Regards, 
> Jer 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2] 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2]

___
 gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2] 

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2]

 

Links:
--
[1] http://web.eecs.umich.edu/~atgutier
[2] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] ARM compiler flags

[Ali Saidi via gem5-users]

 

I'm not sure what issue you're having, but based on your command line it
looks like you're using quite an old version of gem5 (2.5+ years old).
There are certainly some bugs that have been fixed in the intervening
time. 

Here is my attempt to reproduce your problem on a new version of gem5.
You might try comparing the default flags in this compiler to your own
and see if anything jumps out. 

$ gcc --version 

gcc (Ubuntu/Linaro 4.8.1-10ubuntu9) 4.8.1 

Copyright (C) 2013 Free Software Foundation, Inc. 

This is free software; see the source for copying conditions. There is
NO 

warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. 

$gcc -v 

Using built-in specs. 

COLLECT_GCC=gcc 

COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabihf/4.8/lto-wrapper 

Target: arm-linux-gnueabihf 

Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro
4.8.1-10ubuntu9' --with-bugurl=file:///usr/share/doc/gcc-4.8/README.Bugs
--enable-languages=c,c++,java,go,d,fortran,objc,obj-c++ --prefix=/usr
--program-suffix=-4.8 --enable-shared --enable-linker-build-id
--libexecdir=/usr/lib --without-included-gettext --enable-threads=posix
--with-gxx-include-dir=/usr/include/c++/4.8 --libdir=/usr/lib
--enable-nls --with-sysroot=/ --enable-clocale=gnu
--enable-libstdcxx-debug --enable-libstdcxx-time=yes
--enable-gnu-unique-object --disable-libitm --disable-libquadmath
--enable-plugin --with-system-zlib --disable-browser-plugin
--enable-java-awt=gtk --enable-gtk-cairo
--with-java-home=/usr/lib/jvm/java-1.5.0-gcj-4.8-armhf/jre
--enable-java-home
--with-jvm-root-dir=/usr/lib/jvm/java-1.5.0-gcj-4.8-armhf
--with-jvm-jar-dir=/usr/lib/jvm-exports/java-1.5.0-gcj-4.8-armhf
--with-arch-directory=arm --with-ecj-jar=/usr/share/java/eclipse-ecj.jar
--enable-objc-gc --enable-multiarch --enable-multilib
--disable-sjlj-exceptions --with-arch=armv7-a --with-fpu=vfpv3-d16
--with-float=hard --with-mode=thumb --disable-werror
--enable-checking=release --build=arm-linux-gnueabihf
--host=arm-linux-gnueabihf --target=arm-linux-gnueabihf 

Thread model: posix 

gcc version 4.8.1 (Ubuntu/Linaro 4.8.1-10ubuntu9) 

$ gcc -static -o hello_new tests/test-progs/hello/src/hello.c 

$ ./build/ARM/gem5.opt configs/example/se.py -c hello_new 

gem5 Simulator System. http://gem5.org 

gem5 is copyrighted software; use the --copyright option for details. 

gem5 compiled Jul 24 2014 22:01:48 

gem5 started Jul 25 2014 08:56:23 

gem5 executing on dalmre 

command line: ./build/ARM/gem5.opt configs/example/se.py -c hello_new 

/work/gem5.new/configs/common/CacheConfig.py:48: SyntaxWarning: import *
only allowed at module level 

 def config_cache(options, system): 

Global frequency set at 1 ticks per second 

 0: system.cpu.isa: ISA system set to: 0 0x6de4400 

0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 

 REAL SIMULATION  

info: Entering event queue @ 0. Starting simulation... 

Hello world! 

Exiting @ tick 3221500 because target called exit() 

Thanks, 

Ali 

On 24.07.2014 18:45, via gem5-users wrote: 

> Hi all,
> 
> When I try running my own hello world binary for ARM, compiled 
> natively on the BeagleBone, SE simulation fails as shown below.
> Running the binary from tests/test-progs/hello/bin/arm/linux/hello, 
> however, works just fine.
> 
> Are there any specific options that were used to compile the binary in 
> the repository? Maybe any flags regarding the non-supported 
> instructions for ARM in system call emulation?
> 
> This is the output from gem5:
> 
> ---Simulation begins.
> 0: system.remote_gdb.listener: listening for remote gdb on port 7000
>  REAL SIMULATION 
> info: Entering event queue @ 0. Starting simulation...
> panic: Page table fault when accessing virtual address 0x1c
> @ cycle 698500
> [invoke:build/ARM_SE/sim/faults.cc, line 64]
> Memory Usage: 608316 KBytes
> For more information see: http://www.m5sim.org/panic/4f0b3472 [1]
> Program aborted at cycle 698500
> Aborted
> 
> This is the command line:
> ./build/ARM_SE/m5.debug configs/example/se.py
> 
> I compiled my hello world binary on the BeagleBone Black, running 
> Debian, with gcc-4.4. The binary in test-progs is compiled with 
> gcc-4.3 on an Ubuntu machine. Passing both binaries through the 
> file-command results in this:
> 
> hello world on BeagleBone:
> ELF 32-bit LSB executable, ARM, version 1 (SYSV), statically linked, 
> for GNU/Linux 2.6.26, not stripped
> hello world from repository:
> ELF 32-bit LSB executable, ARM, version 1 (SYSV), statically linked, 
> for GNU/Linux 2.6.16, not stripped
> 
> I run a rather old version of gem5, however I am surprised that the 
> binary in the repository passes simulation, but mine won't. Do you 
> have any pointers that could help me out?
> 
> Thanks,
> Max
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2]

 

Links:
--
[1] http://www

Re: [gem5-users] gem5-users Digest, Vol 96, Issue 17

[Ali Saidi via gem5-users]

 

This shouldn't make a difference. 

On 23.07.2014 14:57, Namitha Krishna via gem5-users wrote: 

> Hello Senni Sophianne, 
> 
> To configure gem5 according to parameters mentioned in O3_ARM_v7a.py file you 
> need to first type on the command line : 
> 
> build/ARM/gem5.opt configs/common/O3_ARM_v7a.py 
> 
> and then once the executable is configured with the parameters in 
> O3_ARM_v7a.py you give the command line options as you mentioned in the mail.

This shouldn't make a difference and I don't think it will do anything.
If you put a print statement in the if arm_detailed block you should see
it get printed when you run with an arm_detailed cpu. That code is
selecting the caches in O3_ARM_v7a. 

Ali 
 ___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Wrong decoding of instructions

[Ali Saidi via gem5-users]

Why don’t you compare the un-modified trace (with —debug-flags=Exec) to the 
modified one?

Ali

On Jul 20, 2014, at 11:06 AM, Vanchinathan Venkataramani via gem5-users 
 wrote:

> I'm trying to execute a binary on ARM gem5 O3CPU model. I made some 
> modification to the code.
> 
> Now, some instructions wrongly get encoded as four micro-ops. I'm not sure 
> how I should go about for debugging this problem.
> 
> Any help is really appreciated.
> 
> Thanks a lot!
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Read error, exit

[Ali Saidi via gem5-users]

We’ll need a better description than that to help. What is printing read error? 
The benchmarks or the simulator?

Ali



On Jul 5, 2014, at 4:56 PM, Qi Jia via gem5-users  wrote:

> Hi all,
> 
> I am trying to add some kind of victim cache in gem5, but when I run the 
> benchmark(e.g. mcf), sometimes it will exit and display "read error, exit". I 
> search the codes but did not find where the panic comes from. Could anyone 
> explain a little on this?
> 
> Any suggestion is appreciated. Thanks in advacne
> 
> -- 
> Qi Jia
> Graduate Student
> Department of Electrical and Computer Engineering
> North Carolina State University, Raleigh
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] [Tracing] General Information regarding trace flags

[Ali Saidi via gem5-users]

src/cpu/exectrace.*

Ali

On Jun 29, 2014, at 10:16 PM, Sudarshan L Sargur via gem5-users 
 wrote:

> Greetings fellow Gem5 users, 
> 
> I'm just starting off with using Gem5 for one of my research projects. 
> 
> I want to use the built in tracing capabilities of Gem5. 
> 
> I used the 'Exec' compound flags and various other simple 'Exec__' flags for 
> this purpose. 
> 
> However, I found that the size of the file is pretty huge(even after 
> zipping). 
> 
> Because of that and since I am only interested in certain sections of the 
> application code, I planned to add a new Trace(Debug) flag.
> 
> This flag needs to only dump traces of branching instructions (with a 
> specific offset) and context switches etc. 
> 
> However, after searching for the usage of DPRINTF("Exec__", I did not find 
> such a usage anywhere. 
> 
> I did read that the way the trace and debug functionalities use the 
> --debug-flag is different. 
> 
> Can somebody give me some guidance as to what could be done and which part of 
> the src/ I need to look at ? 
> 
> And how exactly are the trace flags utilized to dump traces ? 
> 
> Thanks and my apologies if the question seems confusing/ extremely 
> elementary. 
> 
> Sud 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] A problem with running a full ARM system simulation

[Ali Saidi via gem5-users]

It seems to work for me from the latest gem5 repository:


$./build/ARM/gem5.opt configs/example/fs.py --machine-type=VExpress_EMM  
--kernel=/home/ali/gem5/vmlinux-3.3-arm-vexpress-emm-pcie
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Jun 29 2014 16:57:56
gem5 started Jun 29 2014 17:25:04
gem5 executing on zizzer
command line: ./build/ARM/gem5.opt configs/example/fs.py 
--machine-type=VExpress_EMM 
--kernel=/home/ali/gem5/vmlinux-3.3-arm-vexpress-emm-pcie
Global frequency set at 1 ticks per second
info: kernel located at: /home/ali/gem5/vmlinux-3.3-arm-vexpress-emm-pcie
Listening for system connection on port 5900
Listening for system connection on port 3456
  0: system.cpu.isa: ISA system set to: 0x6b52c00 0x6b52c00
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn:   instruction 'mcr icialluis' unimplemented
warn:   instruction 'mcr dccimvac' unimplemented
warn:   instruction 'mcr dccmvau' unimplemented
warn:   instruction 'mcr icimvau' unimplemented
warn:   instruction 'mcr bpiallis' unimplemented
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: Not doing anything for read to miscreg pmcr
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: Not doing anything for write to miscreg pmcr
warn: LCD dual screen mode not supported
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: SCReg: Writing 0x18023d8 to dcc0:site0:pos0:fn1:dev1
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
Exiting @ tick 502846041 because user interrupt received

system.terminal:
Booting Linux on physical CPU 0
Initializing cgroup subsys cpuset
Linux version 3.3.0-rc3gem5+ (gem5@zizzer) (gcc version 4.5.2 (Ubuntu/Linaro 
4.5.2-8ubuntu3) ) #25 SMP Wed Jun 27 21:06:31 EDT 2012
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
Machine: ARM-Versatile Express
SoC: ARM VE Platform
bootconsole [earlycon0] enabled
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 131072
...
Thu Jan  1 00:00:02 UTC 2009
S: devpts
Thu Jan  1 00:00:02 UTC 2009
starting pid 599, tty '': '/sbin/getty -L ttySA0 38400 vt100'

AEL login: 




Ali

On Jun 29, 2014, at 5:12 PM, Besta Maciej  wrote:

> Dear Ali,
> 
> Thanks for the message.
> 
> My command line is:
> 
> build/ARM/gem5.opt configs/example/fs.py 
> --kernel=/home/maciej/iommus/simulations/full-system-images/arm/arm-system-2011-08/binaries/vmlinux-3.3-arm-vexpress-emm-pcie
>  --machine-type=VExpress_EMM 
> --disk-image=/home/maciej/iommus/simulations/full-system-images/arm/arm-system-2011-08/disks/arm-ubuntu-natty-headless.img
> 
> I also tried with the disk image linux-arm-ael.img, the same result. Both 
> images come with the package
> http://www.gem5.org/dist/current/arm/arm-system-2011-08.tar.bz2
> 
> I'm almost sure I'm specifying the correct machine type -- I simply copy & 
> paste from gem5 website:
> http://www.gem5.org/Download
> 
> it says: "VExpress_EMM kernel w/PCI support and config -- Pre-compiled Linux 
> 3.3 VExpress_EMM kernel that includes support for PCIe devices, a patch to 
> add gem5 PCIe support to the revision of the vexpress kernel tree and a 
> config file. This kernel is needed if you want to simulated more than 256MB 
> of RAM or networking. Pass 
> --kernel=/path/to/vmlinux-3.3-arm-vexpress-emm-pcie 
> --machine-type=VExpress_EMM on the command line. You'll still need the file 
> systems below. This kernel supports a maximum of 2047MB (one MB less than 
> 2GB) of memory."
> 
> But actually, I'm not sure about one thing related to this package - it also 
> provides a config file that I paste here (default location):
> arm-system-2011-08/binaries/configs/config-vexpress-emm-w-pcie
> 
> Should I use this path as an additional input for the kernel with some 
> additional command-line option?
> 
> The file m5out/system.terminal is empty after running the simulation.
> 
> My best regards,
> Maciej Besta
> 
> From: Ali Saidi [sa...@umich.edu]
> Sent: Saturday, June 28, 2014 6:35 PM
> To: Besta  Maciej; gem5 users mailing list
> Subject: Re: [gem5-users] A problem with running a full ARM system simulation
> 
> That kernel is a 32-bit ke

Re: [gem5-users] Trying to use more than 2GB or RAM

[Ali Saidi via gem5-users]

Hi,

 

If you want to simulate more RAM on an ARMv8 system you'll need to do something 
like the following:

 

1.  Modify the address map definition in gem5 src/dev/arm/RealView.py. 

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -621,12 +621,16 @@
 self.mmc_fake.clk_domain  = clkdomain
 
 class VExpress_EMM64(VExpress_EMM):
+mem_start_addr = '34GB'
+max_mem_size = '16GB'
+ 
+local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 
pio_addr=0x2A43)
+hdlcd  = HDLcd(pio_addr=0x7FF6, int_num=117)
+ 
 def setupBootLoader(self, mem_bus, cur_sys, loc):
 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
 self.nvmem.port = mem_bus.master
-cur_sys.boot_loader = loc('boot_emm.arm64')
+cur_sys.boot_loader = loc('boot_emm_largemem.arm64')
 cur_sys.atags_addr = 0x800
 cur_sys.load_addr_mask = 0xfff
-cur_sys.load_offset = 0x8000
-
-
+cur_sys.load_offset = 0x88000
2. Modify the bootloader to reflect the new starting offset (-DPHYS_OFFSET).

diff --git a/system/arm/aarch64_bootloader/makefile 
b/system/arm/aarch64_bootloader/makefile
--- a/system/arm/aarch64_bootloader/makefile
+++ b/system/arm/aarch64_bootloader/makefile
@@ -1,4 +1,4 @@
 build:
-   aarch64-linux-gnu-gcc -c  -DPHYS_OFFSET=0x8000 -DCNTFRQ=0x0180 
-DUART_BASE=0x1c09 -DSYSREGS_BASE=0x1c01 -DGIC_DIST_BASE=0x2c001000 
-DGIC_CPU_BASE=0x2c002000 -Dkernel=0x8008 -Dmbox=0x8000fff8 
-Ddtb=0x8100 -o boot_emm.o -march=armv8-a boot.S
-   aarch64-linux-gnu-ld -o boot_emm.arm64 -N -Ttext 0x0010 boot_emm.o 
-non_shared -static
-   rm boot_emm.o
\ No newline at end of file
+   aarch64-linux-gnu-gcc -c  -DPHYS_OFFSET=0x88000 -DCNTFRQ=0x0180 
-DUART_BASE=0x1c09 -DSYSREGS_BASE=0x1c01 -DGIC_DIST_BASE=0x2c001000 
-DGIC_CPU_BASE=0x2c002000 -Dkernel=0x8008 -Dmbox=0x8000fff8 
-Ddtb=0x8100 -o boot_emm.o -march=armv8-a boot.S
+   aarch64-linux-gnu-ld -o boot_emm_largemem.arm64 -N -Ttext 0x0010 
boot_emm.o -non_shared -static
+   rm boot_emm.o

3. Modify the memory definition in the dts file to reflect the new starting 
point.

For example you need to change:



memory@8000 { 

device_type = "memory";

reg = <0x0 0x8000 0x8000>;  
   

};

...

cpu-release-addr = <0x0 0x8000fff8>;  

...

 to

 

cpu-release-addr = <0x8 0x8000fff8>;

...

memory@88000 {

device_type = "memory";

reg = <0x8 0x8000 0x4 0x0>;

};

 

Ali

 

 

On 28.05.2014 18:35, Embedded Systems MadHatter wrote:

> Thank you Ali.
>  
> I forgot to clarify, I'm trying to use it for ARMv8 so far, ARMv7 I expected 
> this limitation, but I'm focusing into the ARMv8 right now.
> 
> 
> On Mon, May 26, 2014 at 1:50 PM, Ali Saidi  wrote:
> For ARMv7 you can only really use 2047MB of RAM with the memory map we have 
> in the simulator. It would be possible to use more with the LPAE extensions 
> we recently implemented, but it would certainly required some work on your 
> part to define a new memory map and modify a dtb file appropriately. For 
> ARMv8 it’s much easier to get more RAM, however it too doesn’t work outside 
> the box. To make this work you need to again modify a DTB file and the armv8 
> boot loader start address to match that address. I’ve got the latter mostly 
> working and will try to get you some instructions in the next week.
> 
> Ali
> 
> 
> 
> On May 21, 2014, at 1:52 PM, Embedded Systems MadHatter via gem5-users 
>  wrote:
> 
> > Hello,
> > I'm trying to launch simulations with ARMv7, ARMv8 and X86, but 
> > unfortunately I cannot use more than 2GB of RAM for the simulation. How can 
> > I set a simulation with more than 2GB of RAM ?
> >
> > My current parameter is: --mem-type=DDR3_1600_x64 --mem-size=2GB
> > ___
> > gem5-users mailing list
> > gem5-users@gem5.org
> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> 
 

 ___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] A problem with running a full ARM system simulation

[Ali Saidi via gem5-users]

That kernel is a 32-bit kernel so you can only use the 32-bit files sytem (not 
the 64-bit one). What command line are you running? What does the 
system.terminal output file show? Are you specifying the correct machine type 
on the command line?

Thanks,
Ali

On Jun 28, 2014, at 2:52 AM, Besta Maciej via gem5-users  
wrote:

> Hello everyone,
> 
> I'm trying to run an ARM full system simulation. I use the pre-compiled Linux 
> 3.3 VExpress_EMM kernel that includes support for PCIe devices, I get it from 
> here:
> 
> http://www.gem5.org/dist/current/arm/vmlinux-emm-pcie-3.3.tar.bz2
> 
> when I try to start the simulation, I get this error:
> 
>  REAL SIMULATION 
> info: Entering event queue @ 0.  Starting simulation...
> warn: Device system.membus.badaddr_responder accessed by write to address 
> 0xfbdf size=4 data=0xfbdf
> gem5.opt: build/ARM/cpu/simple/atomic.cc:426: Fault 
> AtomicSimpleCPU::writeMem(uint8_t*, unsigned int, Addr, unsigned int, 
> uint64_t*): Assertion `!pkt.isError()' failed.
> Program aborted at cycle 8500
> 
> Any idea on what's going on?
> 
> The problem occurs if I use either the newest disk image for the 64 bit ARMv8 
> ISA (from 2014), or the images from 2011; these are the following files:
> 
> http://www.gem5.org/dist/current/arm/arm64-system-02-2014.tgz
> http://www.gem5.org/dist/current/arm/arm-system-2011-08.tar.bz2
> 
> Thanks for any help,
> Maciej
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> 

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] A new branch prediction with gem5

[Ali Saidi via gem5-users]

 

Speaking of, could you address the two comments on the patch so we can
get it committed? 

Thanks, 

Ali 

On 24.06.2014 09:34, Anthony Gutierrez via gem5-users wrote: 

> Sorry. Forgot the link. 
> 
> http://reviews.gem5.org/r/2174/ [1] 
> 
> Anthony Gutierrez 
> http://web.eecs.umich.edu/~atgutier [2] 
> 
> On Tue, Jun 24, 2014 at 10:33 AM, Anthony Gutierrez  
> wrote:
> 
> Hi, 
> 
> Here is an example patch that adds a new branch predictor; in particular it 
> adds the bi-mode branch predictor. It's pretty straight forward. 
> 
> There are some problems with that patch though, which reminds me I need to 
> update it so it can be shipped. 
> 
> Anthony Gutierrez 
> http://web.eecs.umich.edu/~atgutier [2] 
> 
> On Tue, Jun 24, 2014 at 8:32 AM, saber nabavi via gem5-users 
>  wrote: 
> 
> Hi everyone, 
> how can I implement a new branch prediction and integrate it with gem5? 
> 
> tnx. ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [3]

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [3]

 

Links:
--
[1] http://reviews.gem5.org/r/2174/
[2] http://web.eecs.umich.edu/~atgutier
[3] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Fwd: Re: Running benchmark with memory greater than 256MB

[Ali Saidi via gem5-users]

 

You shouldn't need to change the android file-system but the kernel will
need to change as the one on gem5.org doesn't support android. We're
trying to get a git where we can put known working kernels. Hopefully
this will happen within the end of the week but if not it should be done
within two. 

Thanks, 

Ali 

On 10.06.2014 09:26, Vishaal Mohan via gem5-users wrote: 

> -- Forwarded message --
> From: "Vishaal Mohan" 
> Date: Jun 10, 2014 1:36 PM
> Subject: Re: [gem5-users] Running benchmark with memory greater than 256MB
> To: 
> Cc: 
> 
> Thank you Ali. I got the VExpress_EMM platform running. 
> My aim here is to run the Moby mobile benchmark suite on an android image 
> with L1(inst and data caches with size 32kB and associativity 4), L2(512Kb, 
> 16-way assoc) and DRAM(LPDDR2, 1GB). Now, as expected the benchmarks aren't 
> there on the given VEMM kernel. Do I need to build my own android file system 
> and kernel? I am new to gem5 and it would be great if someone can help me 
> with this. 
> Thank you. 
> --Vishaal Mohan 
> 
> On Tue, Jun 3, 2014 at 7:14 PM, Ali Saidi  wrote:
> 
> You'll need to use the VEMM ARM platform instead of the default. If you do 
> that you can then use 2047MB of RAM. 
> 
> Ali 
> 
> On 31.05.2014 01:18, Vishaal Mohan via gem5-users wrote: 
> 
> Hello, 
> I am trying to run bbench on an ARM platform with an Android ICS image. If I 
> try to use memory size greater than 256MB, I got an error saying 'The 
> currently selected ARM platforms doesn't support the amount of DRAM you've 
> selected. Please try another platform.' 
> I tried commenting out the sys.exit(1) function. I then get an error that 
> says: 
> Listening for system connection on port 5910 
> Listening for system connection on port 3457 
> ... 
> fatal: system.membus has two ports with the same range: 
> system.mem_ctrls.port 
> system.bridge.slave 
> 
> And the simulation is aborted. 
> Am I missing something or is there some other way to use memory size more 
> than 256MB? 
> Thanks. 
> Cheers 
> --Vishaal Mohan 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Page fault panic when running m5threads tests in gem5 ARM SE

[Ali Saidi via gem5-users]

If you use gcc 4.2 (or at least libc from back then) it will work. I’m not sure 
why it doesn’t work with a newer libc, but it’s something to do with the exit 
functions and getting the wrong value.

Ali

On Jun 2, 2014, at 12:39 PM, Ali Saidi via gem5-users  
wrote:

> Yea, it looks like something changed, perhaps the definition of some of the 
> structures have changed since the code was written. It looks like it's 
> happening when the thread is about to exit, and the the wrong address is 
> being jumped too. You might try an older version of gcc and see if it works 
> and if you see what has changed.
> 
>  
> Thanks,
> 
> Ali
> 
>  
> On 31.05.2014 04:46, Jack Harvard wrote:
> 
>> I ran m5threads/tests/test___thread and a few others in the tests
>> folder, they all had the same page fault panic (I side), it's an BLX
>> instruction caused the page table panic.
>> Jack Harvard
>> 
>> 
>> On Fri, May 30, 2014 at 6:50 PM, Ali Saidi  wrote:
>>> What test are you running? Ali On 30.05.2014 10:35, Jack Harvard via 
>>> gem5-users wrote: To add, x86 SE runs fine Jack Harvard On Fri, May 30, 
>>> 2014 at 4:21 PM, Jack Harvard  wrote: Did the same 
>>> as this 
>>> http://lacasa.uah.edu/portal/Upload/tutorials/gem5/RunningPrograms-gem5.txt,
>>>  the run now says "panic: Page table fault when accessing virtual address 
>>> 0xf0004", this virtual address looks like an address in library or heap. 
>>> Something is broken, anyone came across the same? Jack Harvard 
>>> ___ gem5-users mailing list 
>>> gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>  
>  
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Running benchmark with memory greater than 256MB

[Ali Saidi via gem5-users]

 

You'll need to use the VEMM ARM platform instead of the default. If you
do that you can then use 2047MB of RAM. 

Ali 

On 31.05.2014 01:18, Vishaal Mohan via gem5-users wrote: 

> Hello, 
> I am trying to run bbench on an ARM platform with an Android ICS image. If I 
> try to use memory size greater than 256MB, I got an error saying 'The 
> currently selected ARM platforms doesn't support the amount of DRAM you've 
> selected. Please try another platform.' 
> I tried commenting out the sys.exit(1) function. I then get an error that 
> says: 
> Listening for system connection on port 5910 
> Listening for system connection on port 3457 
> ... 
> fatal: system.membus has two ports with the same range: 
> system.mem_ctrls.port 
> system.bridge.slave 
> 
> And the simulation is aborted. 
> Am I missing something or is there some other way to use memory size more 
> than 256MB? 
> Thanks. 
> Cheers 
> --Vishaal Mohan 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] GEM5 maximum disk size limit

[Ali Saidi via gem5-users]

 

It should work just fine. See
https://www.mail-archive.com/gem5-users@gem5.org/msg09928.html for an
example for how to create a larger disk image. 

Ali 

On 30.05.2014 06:16, Ahmad Hassan via gem5-users wrote: 

> Hi,
> 
> gem5img.py utility in gem5 only allows creating disk images up to 7.8GB 
> (8455200768). Is it possible to create larger disk image around 200GB for 
> GEM5? Does GEM5 support that?
> 
> If not, then what are the other alternatives to use larger data set (200GB) 
> for a benchmark running in gem5 FS mode.
> 
> Thanks.
> 
> Best Regards, Hassan 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Page fault panic when running m5threads tests in gem5 ARM SE

[Ali Saidi via gem5-users]

 

Yea, it looks like something changed, perhaps the definition of some of
the structures have changed since the code was written. It looks like
it's happening when the thread is about to exit, and the the wrong
address is being jumped too. You might try an older version of gcc and
see if it works and if you see what has changed. 

Thanks, 

Ali 

On 31.05.2014 04:46, Jack Harvard wrote: 

> I ran m5threads/tests/test___thread and a few others in the tests
> folder, they all had the same page fault panic (I side), it's an BLX
> instruction caused the page table panic.
> Jack Harvard
> 
> On Fri, May 30, 2014 at 6:50 PM, Ali Saidi  wrote:
> 
>> What test are you running? Ali On 30.05.2014 10:35, Jack Harvard via 
>> gem5-users wrote: To add, x86 SE runs fine Jack Harvard On Fri, May 30, 2014 
>> at 4:21 PM, Jack Harvard  wrote: Did the same as 
>> this 
>> http://lacasa.uah.edu/portal/Upload/tutorials/gem5/RunningPrograms-gem5.txt 
>> [1], the run now says "panic: Page table fault when accessing virtual 
>> address 0xf0004", this virtual address looks like an address in library or 
>> heap. Something is broken, anyone came across the same? Jack Harvard 
>> ___ gem5-users mailing list 
>> gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2]

 

Links:
--
[1]
http://lacasa.uah.edu/portal/Upload/tutorials/gem5/RunningPrograms-gem5.txt
[2] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Page fault panic when running m5threads tests in gem5 ARM SE

[Ali Saidi via gem5-users]

 

What test are you running? 

Ali 

On 30.05.2014 10:35, Jack Harvard via gem5-users wrote: 

> To add, x86 SE runs fine
> Jack Harvard
> 
> On Fri, May 30, 2014 at 4:21 PM, Jack Harvard  wrote:
> 
>> Did the same as this 
>> http://lacasa.uah.edu/portal/Upload/tutorials/gem5/RunningPrograms-gem5.txt 
>> [1], the run now says "panic: Page table fault when accessing virtual 
>> address 0xf0004", this virtual address looks like an address in library or 
>> heap. Something is broken, anyone came across the same? Jack Harvard
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [2]

 

Links:
--
[1]
http://lacasa.uah.edu/portal/Upload/tutorials/gem5/RunningPrograms-gem5.txt
[2] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Trying to use more than 2GB or RAM

[Ali Saidi via gem5-users]

For ARMv7 you can only really use 2047MB of RAM with the memory map we have in 
the simulator. It would be possible to use more with the LPAE extensions we 
recently implemented, but it would certainly required some work on your part to 
define a new memory map and modify a dtb file appropriately. For ARMv8 it’s 
much easier to get more RAM, however it too doesn’t work outside the box. To 
make this work you need to again modify a DTB file and the armv8 boot loader 
start address to match that address. I’ve got the latter mostly working and 
will try to get you some instructions in the next week.

Ali



On May 21, 2014, at 1:52 PM, Embedded Systems MadHatter via gem5-users 
 wrote:

> Hello,
> I'm trying to launch simulations with ARMv7, ARMv8 and X86, but unfortunately 
> I cannot use more than 2GB of RAM for the simulation. How can I set a 
> simulation with more than 2GB of RAM ?
> 
> My current parameter is: --mem-type=DDR3_1600_x64 --mem-size=2GB
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Splash2 error: cannot execute binary file

[Ali Saidi via gem5-users]

The binary you’re trying to run isn’t likely compiled for the alpha 
architecture, but rather a different one. You much use the same architecture 
and binary format. 

Ali


On May 26, 2014, at 9:29 AM, sahar via gem5-users  wrote:

> I have problem with running splash2 on gem5 simulator . I use this tutorial 
> "https://docs.google.com/document/d/1B7nZSqMLwkwoVNEj_58tMPTk4bKWvoEMbokOAjqeC
> -k/preview"
> but when i run FFT in gem5 by using this code ./build/ALPHA_FS/m5.opt 
> configs/example/fs.py -n 1 -b fft,
> I give this error
> modprobe: FATAL: Could not load /lib/modules/2.6.27.6-dirty/modules.dep: No 
> such file or directory
> modprobe: FATAL: Could not load /lib/modules/2.6.27.6-dirty/modules.dep: No 
> such file or directory
> /tmp/script: line 4: ./FFT: cannot execute binary file
> 
> what should I do? 
> please help me
> thanks
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> 

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Building a 32-bit Linux disk image for hardfloat ABI compiled binaries

[Ali Saidi via gem5-users]

You can run cfdisk (or fdisk) on the image and see what it says. 


$ fdisk my.img 

Command (m for help): p

Disk my.img: 536 MB, 536739840 bytes
16 heads, 63 sectors/track, 1040 cylinders, total 1048320 sectors
Units = sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disk identifier: 0x

  Device Boot  Start End  
Blocks   Id  System
my.img63 1048319  
524128+  83  Linux

Command (m for help): q




Honestly, I haven’t used gem5img is quite some time and just create disk images 
manually. I usually do something like this:
$ truncate disk.img -s 1000M
$ parted disk.img mklabel msdos
$ parted disk.img mkpart primary 1MB 1047MB #Note this starts at 1MB rather 
than the usual 32kb (sector 63) above. This is sector 2048
$ losetup -o 1048576 /dev/loop1 disk.img
$ mkfs.ext3 /dev/loop1
$ mount /dev/loop1 /mnt

$ umount /mnt
$ losetup -d /dev/loop1


Ali

On May 17, 2014, at 5:48 AM, Kiyeon Lee via gem5-users  
wrote:

> Hi, Ali.
> Thanks for your quick response.
> How can I check and set the partition type to Linux (83)?
> 
> Are there something else I need to do besides running the gem5img.py script?
> 
> Thanks.
> 
> --Kiyeon
> Seems like maybe the partition time isn't set to Linux (83)?
> 
>  
> Ali
> 
>  
> On 16.05.2014 10:37, Kiyeon Lee via gem5-users wrote:
> 
>> Hi.
>>  
>> I need a 32-bit Linux disk image for hardfloat ABI compiled ARM binaries.
>> The pre-built disk images provided by the gem5 website 
>> (http://www.gem5.org/dist/current/arm/arm-system-2011-08.tar.bz2) only 
>> support softfloat ARM binaries.
>>  
>> I followed the instructions written in the following webpage: 
>> http://gem5.org/Ubuntu_Disk_Image_for_ARM_Full_System
>> I am using Ubuntu Core 12.04 
>> (http://cdimage.ubuntu.com/ubuntu-core/releases/12.04/release/ubuntu-core-12.04.4-core-armhf.tar.gz)
>>  to build a gem5 compatible disk image.
>>  
>> However, I get the following error message during system bootup.
>>  
>> "mount: unknown filesystem type 'none'
>> I tried ext2 and ext3 file systems when I created a blank disk image using 
>> gem5img.py. Both ext2 and ext3 are giving me the same error message as above.
>> 
>> Does anyone have any idea what I may have been missing? 
>> 
>> Thanks!
>> 
>> -- Kiyeon
>> 
>>  
>> 
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>  
>  
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Building a 32-bit Linux disk image for hardfloat ABI compiled binaries

[Ali Saidi via gem5-users]

 

Seems like maybe the partition time isn't set to Linux (83)? 

Ali 

On 16.05.2014 10:37, Kiyeon Lee via gem5-users wrote: 

> Hi. 
> 
> I need a 32-bit Linux disk image for hardfloat ABI compiled ARM binaries. 
> The pre-built disk images provided by the gem5 website 
> (http://www.gem5.org/dist/current/arm/arm-system-2011-08.tar.bz2 [2]) only 
> support softfloat ARM binaries. 
> 
> I followed the instructions written in the following webpage: 
> http://gem5.org/Ubuntu_Disk_Image_for_ARM_Full_System [3] 
> I am using Ubuntu Core 12.04 
> (http://cdimage.ubuntu.com/ubuntu-core/releases/12.04/release/ubuntu-core-12.04.4-core-armhf.tar.gz
>  [4]) to build a gem5 compatible disk image. 
> 
> However, I get the following error message during system bootup. 
> 
> "mount: unknown filesystem type 'none' 
> 
> I tried ext2 and ext3 file systems when I created a blank disk image using 
> gem5img.py. Both ext2 and ext3 are giving me the same error message as above. 
> 
> Does anyone have any idea what I may have been missing? 
> 
> Thanks! 
> 
> -- Kiyeon 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[2] http://www.gem5.org/dist/current/arm/arm-system-2011-08.tar.bz2
[3] http://gem5.org/Ubuntu_Disk_Image_for_ARM_Full_System
[4]
http://cdimage.ubuntu.com/ubuntu-core/releases/12.04/release/ubuntu-core-12.04.4-core-armhf.tar.gz___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Page table fault when accessing virtual address 0x98

[Ali Saidi via gem5-users]

 

--debug-flags=Exec --debug-start= 

Ali 

On 08.05.2014 02:13, jiakunli2010 via gem5-users wrote: 

> Thanks for the reply. But I don't know how to get to the trace around the 
> warning lines. (only the terminated tick printed) How to find the tick at 
> which warning appears? 
> 
> jiakunli2010，jiakunli2...@gmail.com 
> 2014/5/8 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] error after add a cache replacement

[Ali Saidi via gem5-users]

 

Perhaps there is some bad data in the srcMasterId? The master Ids are
allocated at the beginning of simulation and the error you're seeing is
that a master ID was either allocated after this or is junk. Each master
id uniquely identifies every device in the system that can generate a
packet. 

Ali 

On 05.05.2014 21:02, 陈越佳 via gem5-users wrote: 

> Hi. I have solve the problem above. But I have another problem. I want to 
> change the lrc.cc. If the A pkt is a read operation, the block in the cache 
> shouldn't be replaced. And if the B pkt is a write operation, the block in 
> teh cache should be replaced. I modified the insertBolock in lrc.ccas follow: 
> if(pkt->isWrite()){ 
> 
> ***code not changed 
> 
> } 
> 
> means if the pkt is write, execute the insertBlock. But when I run the 
> benchmark,there is another error"gem5.opt: 
> build/ALPHA/mem/cache/tags/wf.cc:195: void WF::invalidate(WF::BlkType*): 
> Assertion `blk->srcMasterId < cache->system->maxMasters()' failed." 
> Anyone can help me? 
> Thanks 
> Yuejia 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Prefetcher Simulation halted

[Ali Saidi via gem5-users]

 

There have been a couple of bugs with the prefetcher. Are you using the
latest version of gem5? This patch may help:
http://reviews.gem5.org/r/2242/ 

Ali 

On 07.05.2014 02:08, Prasanth Nunna via gem5-users wrote: 

> Dear gem5-users,
> 
> I have designed a new prefetcher and I have run it on gem5 ALPHA ISA for 
> blackscholes. I am dynamically updating prefetch degree and printing it 
> whenever its updated. 
> 
> I am trying to create checkpoints for blacksholes using the following command:
> ./build/ALPHA/gem5.opt ./configs/example/fs.py --cpu-type=detailed --caches 
> --l2cache --l2_size=512kB --script=./m5parsec/blackscholes_4c_simsmall.rcS 
> --kernel=vmlinux --disk-image=linux-latest.img 
> --take-checkpoints=100,50 
> --checkpoint-dir=/home/prasanth/gem5/m5out/checkpoints/blackscholes_simsmall/
> 
> I can see the output printed in the terminal until the real simulation 
> started but after that there are no entries in the terminal. Also the 
> terminal on port 3456 halted after printing the following:
> 
> prasanth@prasanth-VPCCB15FG:~$ telnet localhost 3456
> Trying 127.0.0.1...
> Connected to localhost.
> Escape character is '^]'.
>  m5 slave terminal: Terminal 0 
> M5 console: m5AlphaAccess @ 0xFD02
> Got Configuration 623
> memsize 2000 pages 1 
> First free page after ROM 0xFC018000
> HWRPB 0xFC018000 l1pt 0xFC04 l2pt 0xFC042000 
> l3pt_rpb 0xFC044000 l3pt_kernel 0xFC048000 l2reserv 
> 0xFC046000
> kstart = 0xFC31, kend = 0xFC899860, kentry = 
> 0xFC31, numCPUs = 0x1
> CPU Clock at 2000 MHz IntrClockFrequency=1024 
> Booting with 1 processor(s) 
> KSP: 0x20043FE8 PTBR 0x20
> Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
> Memory cluster 0 [0 - 392]
> Memory cluster 1 [392 - 65144]
> Initalizing mdt_bitmap addr 0xFC038000 mem_pages 1 
> ConsoleDispatch at virt 1658 phys 18658 val FC0100A8
> unix_boot_mem ends at FC076000 
> k_argc = 0 
> jumping to kernel at 0xFC31, (PCBB 0xFC018180 pfn 1101)
> CallbackFixup 0 18000, t7=FC814000
> Linux version 2.6.27.6-dirty (joel@capillary) (gcc version 4.3.4 
> (crosstool-NG-1.5.2) ) #1 SMP Sat Mar 6 19:10:44 CST 2010
> Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
> Major Options: SMP LEGACY_START VERBOSE_MCHECK 
> Command line: root=/dev/hda1 console=ttyS0
> memcluster 0, usage 1, start 0, end 392
> memcluster 1, usage 0, start 392, end 65536
> freeing pages 1103:65536
> reserving pages 1103:1104
> SMP: 1 CPUs probed -- cpu_present_map = 1
> Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65088
> Kernel command line: root=/dev/hda1 console=ttyS0
> PID hash table entries: 2048 (order: 11, 16384 bytes)
> Using epoch = 1900
> Console: colour dummy device 80x25
> console [ttyS0] enabled
> Dentry cache hash table entries: 65536 (order: 6, 524288 bytes)
> Inode-cache hash table entries: 32768 (order: 5, 262144 bytes)
> Memory: 509920k/524288k available (3757k kernel code, 10632k reserved, 261k 
> data, 208k init)
> Mount-cache hash table entries: 512
> SMP mode deactivated.
> Brought up 1 CPUs
> SMP: Total of 1 processors activated (4002.20 BogoMIPS).
> net_namespace: 552 bytes
> NET: Registered protocol family 16
> 
> It has been at the same point for a whole day. Someone please help me with 
> this.
> 
> Regards, N Prasanth. 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Page table fault when accessing virtual address 0x98

[Ali Saidi via gem5-users]

 

The page fault you're seeing below is what you would see on a normal
system as a segmentation fault. You're likely referencing a null pointer
plus some offset. You need to look at a trace of the instructions and
memory system, see how that address is generated and assuming it's the
problem I mentioned, why a previous write disappeared or got lost in
your cache modifications. 

Thanks, 

Ali 

On 07.05.2014 09:27, jiakunli2010 via gem5-users wrote: 

> Hello All! 
> 
> I am running SPEC2006 (4 workloads on 4-core) using gem5 classic memory, 
> timing cpu model. The error message are pasted below. 
> 
> However, when I applied one workload to the same 4-core system, I got no 
> errors for any of the four workloads. The system could also run some other 
> mixes of SPEC2006 workloads and the "Hello world!" example. I searched the 
> debug file but did not find any clues. 
> 
> I made considerable modification to the source code of cache system, I 
> suppose it was bugs there. 
> 
> Does anyone have any idea about where the errors may come from or any 
> suggestion on the debugging method? 
> 
>  
> 
> info: Increaseing stack size by one page. 
> 
> info: Increaseing stack size by one page. 
> 
> Warning line 7126: Column "C918" for row "R10193" ignored 
> 
> Warning line 7189: Column "C932" for row "1." ignored 
> 
> Warning line 7834: Column "C1084" for row "8" ignored 
> 
> info: Increaseing stack size by one page. 
> 
> Warning line 8824: Column "C1306" for row "1." ignored 
> 
> Warning line 8827: Column "C1306" for row "0" ignored 
> 
> Syntax error in line 8829 
> 
> panic: Page table fault when accessing virtual address 0x98 
> 
> @ cycle 32812561593 
> 
> [invoke: build/ARM/sim/faults.cc, line 70] 
> 
> Memory Usage: 2884000 KBytes 
> 
>  
> 
> jiakunli2010，jiakunli2...@gmail.com 
> 
> 2014/5/7 
> 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Problem trying to execute a 12 core ARMv8

[Ali Saidi via gem5-users]

 

You can modify the current gic model to support more cores (and the
associated linux driver). Similarly, it's simply a question of changing
the memory map in the dtb file if you'd like more than 2GB of ram. 

Ali 

On 05.05.2014 11:46, Embedded Systems MadHatter via gem5-users wrote: 

> Thanks, 
> 
> Indeed it only supports 8 cores max. 
> Also it only supports max of 2GB memory. 
> 
> On Wed, Apr 30, 2014 at 11:35 AM, Embedded Systems MadHatter 
>  wrote:
> 
> Thanks Neal, 
> 
> I'll take that into account and change everything to 8 cores max and see if 
> it will work, for now. 
> 
> On Tue, Apr 29, 2014 at 10:07 PM, Neal Haas  wrote:
> 
> The GIC in the gem5 source cannot support more than 8 CPUs. You would need 
> GICv3 which has not yet been implemented. At least, that's what I think. 
> 
> On Tue, Apr 29, 2014 at 1:34 PM, Embedded Systems MadHatter 
>  wrote: 
> 
> Hello, 
> 
> I'm trying to run a 12 cores ARM simulation, following are my parameters, I 
> had a segmentation fault at a Linux initially, but I changed the kernel in 
> drivers/irqchip/irq-gic.c 
> and change the parameter 
> 
> #define NR_GIC_CPU_IF 8 
> 
> to 
> 
> #define NR_GIC_CPU_IF 32 
> 
> because I was having a BUG assertion due to its limitation (I believe, so 
> that is why I made the change). 
> 
> After recompiling and regenerating DTS, added additional CPUs as recommended 
> in the documentation. 
> 
> Please someone could point the cause of the error and provide insights on how 
> to directions to fix it. 
> 
> error: 
> 
> command line: ./build/ARM/gem5.fast configs/mine/fs.py 
> --disk-image=/opt/arm/gem5/armv8_system/disks/linaro-minimal-armv8.img 
> --kernel=/opt/arm/gem5/armv8_system/binaries/vmlinux-mine-aarch64-vexpress-emm64
>  
> --dtb-filename=/opt/vlsi/arm/gem5/armv8_system/binaries/rtsm_ve-aemv8a-mine.dtb
>  --machine-type=VExpress_EMM64 --caches --l2cache --l1d_size=32kB 
> --l1i_size=32kB --l2_size=256kB --l3_size=20MB --l1d_assoc=4 --l1i_assoc=4 
> --l2_assoc=8 --l3_assoc=16 --cacheline_size=64 -n 12 --sys-clock=2.0GHz 
> --cpu-clock=2.0GHz --mem-type=DDR3_1600_x64 
> Global frequency set at 1 ticks per second 
> info: kernel located at: 
> /opt/arm/gem5/armv8_system/binaries/vmlinux-mine-aarch64-vexpress-emm64 
> warn: Highest ARM exception-level set to AArch32 but bootloader is for 
> AArch64. Assuming you wanted these to match. 
> Listening for system connection on port 5901 
> Listening for system connection on port 3456 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7000 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7001 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7002 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7003 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7004 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7005 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7006 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7007 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7008 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7009 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7010 
> 0: system.remote_gdb.listener: listening for remote gdb on port 7011 
> info: Using bootloader at address 0x10 
> info: Using kernel entry physical address at 0x80080040 
> info: Loading DTB file: 
> /opt/arm/gem5/armv8_system/binaries/rtsm_ve-aemv8a-mine.dtb at address 
> 0x8800 
>  REAL SIMULATION  
> info: Entering event queue @ 0. Starting simulation... 
> warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 
> panic: event not found! 
> @ tick 56582624 
> [remove:build/ARM/sim/eventq.cc, line 195] 
> Memory Usage: 56582624 KBytes 
> Program aborted at cycle 82604385 
> Aborted (core dumped) 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1] 
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1]

 

Links:
--
[1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users