Re: Explination of S0C4 reason code 4 and related data areas
In m3obqemtv0@garlic.com, on 04/26/2012 at 10:48 AM, Anne Lynn Wheeler l...@garlic.com said: page transfers/io is done with channel programs which have real addresses. On most machines in the family, but DOS/VSE running with ECPS:VSE used virtual addresses in channel programs. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Wed, 25 Apr 2012 19:19:32 -0400 Shmuel Metz (Seymour J.) shmuel+ibm-m...@patriot.net wrote: :In 2aadp75utk3rndje61uiscu5ocln0lt...@4ax.com, on 04/24/2012 : at 04:23 PM, Binyamin Dissen bdis...@dissensoftware.com said: :If the invalid page can be paged-in, in what way is it invalid? :The page-invalid bit is one, per PoOps. Its invalid because its invalid. Got it. Thanks. -- Binyamin Dissen bdis...@dissensoftware.com http://www.dissensoftware.com Director, Dissen Software, Bar Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
In d5php7p6gadkvajvc7aqj71l5ur517p...@4ax.com, on 04/26/2012 at 09:01 AM, Binyamin Dissen bdis...@dissensoftware.com said: Its invalid because its invalid. Got it. Thanks. This is a case where I prefer the Burroughs notation; they called the equivalent flag the presence bit, which is more neutral. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
shmuel+ibm-m...@patriot.net (Shmuel Metz , Seymour J.) writes: This is a case where I prefer the Burroughs notation; they called the equivalent flag the presence bit, which is more neutral. page transfers/io is done with channel programs which have real addresses. virtual memory has segment and page tables that map specific virtual memory pages to real pages. when a virtual page is selected for replacement, the corresponding page table entry invalid bit is set, the contents of the real page is written out, the replacing virtual page is read into the real page location, and then the corresponding page table entry invalid bit (for the replacing virtual page) is trned off. this is copy of presentation on cp/40 given at 1982 SEAS meeting http://www.garlic.com/~lynn/cp40seas1982.txt where they modified standard 360/40 to support virtual memory. In the 360/40, there were 64 4kbyte real pages. The added hardware gave each 4k real page had an virtual address space identifier (somewhat analogous to storage keys) plus a virtual page number. Running a virtual machine involved loading a virtual address space identifier into control register. In virtual address mode ... all real pages would be interrogated for matching virtual address space identifier plus matching virtual page number. cp/40 morphed into cp/67 when standard 360/67 with virtual memory hardware becamse available ... which looked much more like 370 virtual memory segment and page tables ... that continue through the various generations. I've claimed that the 801/risc effort was at least partially in reaction to the enormous complexity of the (failed) future system effort (which was going to completely replace 360/370 ... but imploded before even being announced) ... some past posts http://www.garlic.com/~lynn/submain.html#futuresys ... where 801/risc was going to the opposite extreme (to FS) by eliminating a lot of hardware complexity and simplifying the hardware. One of the things in 801/risc were inverted pagetables ... which are effectively much more like the 360/40 virtual memory implementation. 801/risc romp chip instead of having a virtual address space identifier had a 12bit virtual segment identifier (aka STE associative ... rather than the 360/370 STO associative). romp had 32bit virtual addressing with 16 256mbyte segments. When going to run something ... the segment identifiers were loaded into the 16 segment registers. Running in virtual address space made would peal off the virtual address space number and index the corresponding segment register, pull out the segment identifier ... and then use the virtual segment identifier plust segment virtual page number to look for the associated real page number. In 801/ROMP, rather than turning off the invalid bit ... to indicate virtual page is available ... the corresponding segment-id plus segment-virtual-page-number is loaded (for corresponding real page). misc. past posts mentioning 801, risc, romp, rios, power, power/pc, etc http://www.garlic.com/~lynn/subtopic.html#801 -- virtualization experience starting Jan1968, online at home since Mar1970 -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Tue, 24 Apr 2012 17:03:24 -0700, Edward Jaffe edja...@phoenixsoftware.com wrote: . . . I once saw an 0C5 in an MVS guest running under VM. Turned out to be a bug in VM. The last time I saw an 0C5 was on a LURA instruction, but I am sufficiently ancient that I can recall the time when they were almost as common as 0C4s. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
SV: Explination of S0C4 reason code 4 and related data areas
-Ursprungligt meddelande- Från: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] För Andy Wood Skickat: den 25 april 2012 09:15 Till: IBM-MAIN@bama.ua.edu Ämne: Re: Explination of S0C4 reason code 4 and related data areas On Tue, 24 Apr 2012 17:03:24 -0700, Edward Jaffe edja...@phoenixsoftware.com wrote: . . . I once saw an 0C5 in an MVS guest running under VM. Turned out to be a bug in VM. The last time I saw an 0C5 was on a LURA instruction, but I am sufficiently ancient that I can recall the time when they were almost as common as 0C4s. Lura is a Swedish word for deceive. :) Regards, Thomas Berg __ Thomas Berg Specialist AM/DQS SWEDBANK AB (publ) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
In CAArMM9Rgbww-g1LRnqXkKL44H=s9e9vsg-0b+a+o-os0rkj...@mail.gmail.com, on 04/24/2012 at 02:57 PM, Tony Harminc t...@harminc.net said: However exceptions that occur because of low storage or page protection are certainly protection exceptions, Indeed, as are access-list violations. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
In 2aadp75utk3rndje61uiscu5ocln0lt...@4ax.com, on 04/24/2012 at 04:23 PM, Binyamin Dissen bdis...@dissensoftware.com said: If the invalid page can be paged-in, in what way is it invalid? The page-invalid bit is one, per PoOps. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
In 77142d37c0c3c34da0d7b1da7d7ca3495...@nwt-s-mbx1.rocketsoftware.com, on 04/24/2012 at 03:02 PM, Bill Fairchild bfairch...@rocketsoftware.com said: There is another very common way for a massive number of S0C4s to be generated and instantly resolved, which I have often seen in System traces, and that is when one GETMAINs a large area of new storage and then zeroes it all out with a MVCL instruction. Those aren't S0C4's at all, just program interrupts with IC '11'x or '91'x.. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
In oiddp7t76842onvoct9tjcfvj2qkhh0...@4ax.com, on 04/24/2012 at 05:21 PM, Binyamin Dissen bdis...@dissensoftware.com said: But I would suggest that most references to invalid pages do not cause an 0C4. Nor did I suggest that most would. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
In 002101cd1f3b$43f7b090$cbe711b0$@net, on 04/20/2012 at 05:19 PM, Micheal Butz michealb...@optonline.net said: A S0C4 reason code 4 means the storage key and the PSW key don't match Only if you're still running OS/360; otherwise 0C4 is seriously overloaded. Does it matter what the PSW key at the time of the STORAGE OBTAIN was How would the processor know? Of what significance does is the key the TCB (TCBPKF) From the perspective of the processor, none. All that is significant[1] to the processor is the opcode, the PSW key, the storage key, the translation tables, the control registers and the storage address. [1] For indicating a Program interrupt[1] that z/OS will reflect as an ABEND s0C4. [2] Not necessarily IC 4. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
In caarmm9t_+dh5ijesv1rj9fjr3ct5t0axsoazzkqnqiuxczq...@mail.gmail.com, on 04/20/2012 at 06:54 PM, Tony Harminc t...@harminc.net said: There are other possible reasons for an 0C4-04 abend, but 0C4-04 is always a protection exception of some sort. I wouldn't call invalid page and invalid segment protection exceptions. In fact, invalid page normally causes a pagein rather than an ABEND S0C4. -- Shmuel (Seymour J.) Metz, SysProg and JOAT ISO position; see http://patriot.net/~shmuel/resume/brief.html We don't care. We don't have to care, we're Congress. (S877: The Shut up and Eat Your spam act of 2003) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Mon, 23 Apr 2012 16:58:12 -0400 Shmuel Metz (Seymour J.) shmuel+ibm-m...@patriot.net wrote: :In 002101cd1f3b$43f7b090$cbe711b0$@net, on 04/20/2012 : at 05:19 PM, Micheal Butz michealb...@optonline.net said: :A S0C4 reason code 4 means the storage key and the PSW key don't :match :Only if you're still running OS/360; otherwise 0C4 is seriously :overloaded. While 0C4 is overloaded, 0C4-4 is quite specific. -- Binyamin Dissen bdis...@dissensoftware.com http://www.dissensoftware.com Director, Dissen Software, Bar Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Mon, 23 Apr 2012 17:01:11 -0400 Shmuel Metz (Seymour J.) shmuel+ibm-m...@patriot.net wrote: :In :caarmm9t_+dh5ijesv1rj9fjr3ct5t0axsoazzkqnqiuxczq...@mail.gmail.com, :on 04/20/2012 : at 06:54 PM, Tony Harminc t...@harminc.net said: :There are other possible reasons for an 0C4-04 abend, but 0C4-04 is :always a protection exception of some sort. :I wouldn't call invalid page and invalid segment protection :exceptions. In fact, invalid page normally causes a pagein rather than :an ABEND S0C4. If the invalid page can be paged-in, in what way is it invalid? -- Binyamin Dissen bdis...@dissensoftware.com http://www.dissensoftware.com Director, Dissen Software, Bar Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
It is invalid in the sense described in the Principles of Operation paragraph about the Page-Invalid Bit (I) found in the discussion of the Page-Table Entry: the page-table entry cannot be used for translation. The fact that the operating system can resolve the invalidity by performing a page-in and then turning off the Page-Invalid Bit is not relevant to the invalidity of the page at the time of the S0C4 interrupt. DAT is unaware of operating system functions that may or may not occur long after the interrupt is generated. If the operating system cannot page-in the invalid page, then the invalidity changes from possibly temporary to seriously permanent. Bill Fairchild Programmer Rocket Software 408 Chamberlain Park Lane * Franklin, TN 37069-2526 * USA t: +1.617.614.4503 * e: bfairch...@rocketsoftware.com * w: www.rocketsoftware.com -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Binyamin Dissen Sent: Tuesday, April 24, 2012 8:24 AM To: IBM-MAIN@bama.ua.edu Subject: Re: Explination of S0C4 reason code 4 and related data areas If the invalid page can be paged-in, in what way is it invalid? -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Tue, 24 Apr 2012 16:23:50 +0300, Binyamin Dissen wrote: If the invalid page can be paged-in, in what way is it invalid? Bit 53 of a page table entry is the Page-invalid bit. If it is set in the page table entry that is used to reference a location in storage, a Page-translation exception, PIC 11 (commonly known as a page fault) is recognized. Similarly, bit 58 of the segment table entry is the Segment-invalid bit. If it is set in the segment table that is used to reference the page table needed to reference a location in storage, a Segment-translation exception (PIC 10) is recognized. There are similar invalid bits in bit 58 of each of the three levels of region tables. It is more common for these exceptions to be resolved and the instruction retried than it is for the access to result in a S0C4 abend. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Tue, 24 Apr 2012 09:15:05 -0500 Tom Marchant m42tom-ibmm...@yahoo.com wrote: :On Tue, 24 Apr 2012 16:23:50 +0300, Binyamin Dissen wrote: :If the invalid page can be paged-in, in what way is it invalid? :Bit 53 of a page table entry is the Page-invalid bit. If it is set in :the page table entry that is used to reference a location in :storage, a Page-translation exception, PIC 11 (commonly known :as a page fault) is recognized. :Similarly, bit 58 of the segment table entry is the Segment-invalid :bit. If it is set in the segment table that is used to reference the :page table needed to reference a location in storage, a :Segment-translation exception (PIC 10) is recognized. :There are similar invalid bits in bit 58 of each of the three levels :of region tables. :It is more common for these exceptions to be resolved and the :instruction retried than it is for the access to result in a S0C4 abend. As I specified page in, it is clear that the hardware received an exception. But I would suggest that most references to invalid pages do not cause an 0C4. -- Binyamin Dissen bdis...@dissensoftware.com http://www.dissensoftware.com Director, Dissen Software, Bar Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Tue, 24 Apr 2012 17:21:24 +0300, Binyamin Dissen bdis...@dissensoftware.com wrote: On Tue, 24 Apr 2012 09:15:05 -0500 Tom Marchant m42tom-ibmm...@yahoo.com wrote: :It is more common for these exceptions to be resolved and the :instruction retried than it is for the access to result in a S0C4 abend. As I specified page in, it is clear that the hardware received an exception. I'm not sure what you mean by that. _All_ S0C4 abends are the result of the processor recognizing an exception. But I would suggest that most references to invalid pages do not cause an 0C4. Yes. That's what I wrote. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
There is another very common way for a massive number of S0C4s to be generated and instantly resolved, which I have often seen in System traces, and that is when one GETMAINs a large area of new storage and then zeroes it all out with a MVCL instruction. A S0C4 interrupt occurs when the MVCL instruction, which runs interruptibly, touches the first byte of each successively higher virtual page in the large area. Then z/OS finds an available page frame, uses it to back the virtual page just referenced, updates the page table appropriately, and redispatches the same MVCL, which is then able to zero out the same 4K that produced a S0C4, updates its register with the next address to move to, which finally becomes the first byte of the next higher 4K virtual page, then another S0C4 occurs, etc. etc. until the whole GETMAINed area contains X'00'. Bill Fairchild Programmer Rocket Software 408 Chamberlain Park Lane * Franklin, TN 37069-2526 * USA t: +1.617.614.4503 * e: bfairch...@rocketsoftware.com * w: www.rocketsoftware.com -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Tom Marchant Sent: Tuesday, April 24, 2012 9:40 AM To: IBM-MAIN@bama.ua.edu Subject: Re: Explination of S0C4 reason code 4 and related data areas On Tue, 24 Apr 2012 17:21:24 +0300, Binyamin Dissen bdis...@dissensoftware.com wrote: On Tue, 24 Apr 2012 09:15:05 -0500 Tom Marchant m42tom-ibmm...@yahoo.com wrote: :It is more common for these exceptions to be resolved and the :instruction retried than it is for the access to result in a S0C4 abend. As I specified page in, it is clear that the hardware received an exception. I'm not sure what you mean by that. _All_ S0C4 abends are the result of the processor recognizing an exception. But I would suggest that most references to invalid pages do not cause an 0C4. Yes. That's what I wrote. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
They are not - 0C4's - they are pic-10/11/3E/etc. S0C4 is when the supervisor says that it cannot resolve the fault. On Tue, 24 Apr 2012 15:02:10 + Bill Fairchild bfairch...@rocketsoftware.com wrote: :There is another very common way for a massive number of S0C4s to be generated and instantly resolved, which I have often seen in System traces, and that is when one GETMAINs a large area of new storage and then zeroes it all out with a MVCL instruction. A S0C4 interrupt occurs when the MVCL instruction, which runs interruptibly, touches the first byte of each successively higher virtual page in the large area. Then z/OS finds an available page frame, uses it to back the virtual page just referenced, updates the page table appropriately, and redispatches the same MVCL, which is then able to zero out the same 4K that produced a S0C4, updates its register with the next address to move to, which finally becomes the first byte of the next higher 4K virtual page, then another S0C4 occurs, etc. etc. until the whole GETMAINed area contains X'00'. : :Bill Fairchild :Programmer :Rocket Software :408 Chamberlain Park Lane * Franklin, TN 37069-2526 * USA :t: +1.617.614.4503 * e: bfairch...@rocketsoftware.com * w: www.rocketsoftware.com : : :-Original Message- :From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Tom Marchant :Sent: Tuesday, April 24, 2012 9:40 AM :To: IBM-MAIN@bama.ua.edu :Subject: Re: Explination of S0C4 reason code 4 and related data areas : :On Tue, 24 Apr 2012 17:21:24 +0300, Binyamin Dissen bdis...@dissensoftware.com wrote: : :On Tue, 24 Apr 2012 09:15:05 -0500 Tom Marchant :m42tom-ibmm...@yahoo.com :wrote: : ::It is more common for these exceptions to be resolved and the ::instruction retried than it is for the access to result in a S0C4 abend. : :As I specified page in, it is clear that the hardware received an exception. : :I'm not sure what you mean by that. _All_ S0C4 abends are the result of the processor recognizing an exception. : :But I would suggest that most references to invalid pages do not :cause an 0C4. : :Yes. That's what I wrote. : :-- :For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN : :-- :For IBM-MAIN subscribe / signoff / archive access instructions, :send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN -- Binyamin Dissen bdis...@dissensoftware.com http://www.dissensoftware.com Director, Dissen Software, Bar Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
You are right. I meant to say there is another very common way for a massive number of program interrupt code 11 interrupts (invalid page) to be generated... They are potential S0C4 ABENDs which are resolved felicitously. Bill Fairchild Programmer Rocket Software 408 Chamberlain Park Lane * Franklin, TN 37069-2526 * USA t: +1.617.614.4503 * e: bfairch...@rocketsoftware.com * w: www.rocketsoftware.com -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Binyamin Dissen Sent: Tuesday, April 24, 2012 10:24 AM To: IBM-MAIN@bama.ua.edu Subject: Re: Explination of S0C4 reason code 4 and related data areas They are not - 0C4's - they are pic-10/11/3E/etc. S0C4 is when the supervisor says that it cannot resolve the fault. On Tue, 24 Apr 2012 15:02:10 + Bill Fairchild bfairch...@rocketsoftware.com wrote: :There is another very common way for a massive number of S0C4s to be generated and instantly resolved, which I have often seen in System traces, and that is when one GETMAINs a large area of new storage and then zeroes it all out with a MVCL instruction. A S0C4 interrupt occurs when the MVCL instruction, which runs interruptibly, touches the first byte of each successively higher virtual page in the large area. Then z/OS finds an available page frame, uses it to back the virtual page just referenced, updates the page table appropriately, and redispatches the same MVCL, which is then able to zero out the same 4K that produced a S0C4, updates its register with the next address to move to, which finally becomes the first byte of the next higher 4K virtual page, then another S0C4 occurs, etc. etc. until the whole GETMAINed area contains X'00'. : :Bill Fairchild :Programmer :Rocket Software :408 Chamberlain Park Lane * Franklin, TN 37069-2526 * USA :t: +1.617.614.4503 * e: bfairch...@rocketsoftware.com * w: www.rocketsoftware.com : : :-Original Message- :From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Tom Marchant :Sent: Tuesday, April 24, 2012 9:40 AM :To: IBM-MAIN@bama.ua.edu :Subject: Re: Explination of S0C4 reason code 4 and related data areas : :On Tue, 24 Apr 2012 17:21:24 +0300, Binyamin Dissen bdis...@dissensoftware.com wrote: : :On Tue, 24 Apr 2012 09:15:05 -0500 Tom Marchant :m42tom-ibmm...@yahoo.com :wrote: : ::It is more common for these exceptions to be resolved and the ::instruction retried than it is for the access to result in a S0C4 abend. : :As I specified page in, it is clear that the hardware received an exception. : :I'm not sure what you mean by that. _All_ S0C4 abends are the result of the processor recognizing an exception. : :But I would suggest that most references to invalid pages do not :cause an 0C4. : :Yes. That's what I wrote. : :-- :For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN : :-- :For IBM-MAIN subscribe / signoff / archive access instructions, :send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN -- Binyamin Dissen bdis...@dissensoftware.com http://www.dissensoftware.com Director, Dissen Software, Bar Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On 23 April 2012 17:01, Shmuel Metz (Seymour J.) shmuel+ibm-m...@patriot.net wrote: on 04/20/2012 at 06:54 PM, Tony Harminc t...@harminc.net said: There are other possible reasons for an 0C4-04 abend, but 0C4-04 is always a protection exception of some sort. I wouldn't call invalid page and invalid segment protection exceptions. In fact, invalid page normally causes a pagein rather than an ABEND S0C4. Neither would I, nor did I. However exceptions that occur because of low storage or page protection are certainly protection exceptions, and typically lead to an Abend S0C4-04. An unresolved page or segment translation exception eventually turns into a S0C4-11 or 10. Almost certainly, though, these are not the problem with the OP's program. Tony H. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On 4/24/2012 8:23 AM, Binyamin Dissen wrote: They are not - 0C4's - they are pic-10/11/3E/etc. I once saw an 0C5 in an MVS guest running under VM. Turned out to be a bug in VM. -- Edward E Jaffe Phoenix Software International, Inc 831 Parkview Drive North El Segundo, CA 90245 310-338-0400 x318 edja...@phoenixsoftware.com http://www.phoenixsoftware.com/ -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On Fri, 20 Apr 2012 17:19:25 -0400 Micheal Butz michealb...@optonline.net wrote: :Was wondering If someone could clear up some things for me :A S0C4 reason code 4 means the storage key and the PSW key don't match :typically trying to access storage key 0 when the PSW key is key 8 Usually update, but on occasion fetch. :Two questions arise from this :. Does it matter what the PSW key at the time of the STORAGE OBTAIN :was e.g. :1. Obtaining storage from subpool 0 where the storage key is 8 and PSW :key at the time for what ever reason was in KEY 0. What does Obtaining storage from subpool 0 where the storage key is 8 mean? TCB key? : Would I have to set the PSW Key to 0 if I were trying to access that :storage later on say while running in some other task because when I did the :STORAGE OBTAIN the PSW KEY 8 - 11 was 0 SP=0 when Supervisor/key=0 is special in that it is converted to subpool 252 which is in key 0. :2. The same situation would be then true if access CSA storage subpool :241 with Key=8 ( Iknow a no no) but the PSW KEY was 0. Later on when trying :to access/modify the storage would I have to set PSW key 8 - 11 have to be 0 :. Of what significance does is the key the TCB (TCBPKF) since it :seems only PSW KEY 8 - 11 and the key the page of the storage is seems to be :relevant Look at the Selecting the Right Subpool for Your Virtual Storage Request section in MVS Programming: Authorized Assembler Services Guide -- Binyamin Dissen bdis...@dissensoftware.com http://www.dissensoftware.com Director, Dissen Software, Bar Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Explination of S0C4 reason code 4 and related data areas
Hi, Was wondering If someone could clear up some things for me A S0C4 reason code 4 means the storage key and the PSW key don't match typically trying to access storage key 0 when the PSW key is key 8 Two questions arise from this . Does it matter what the PSW key at the time of the STORAGE OBTAIN was e.g. 1. Obtaining storage from subpool 0 where the storage key is 8 and PSW key at the time for what ever reason was in KEY 0. Would I have to set the PSW Key to 0 if I were trying to access that storage later on say while running in some other task because when I did the STORAGE OBTAIN the PSW KEY 8 - 11 was 0 2. The same situation would be then true if access CSA storage subpool 241 with Key=8 ( Iknow a no no) but the PSW KEY was 0. Later on when trying to access/modify the storage would I have to set PSW key 8 - 11 have to be 0 . Of what significance does is the key the TCB (TCBPKF) since it seems only PSW KEY 8 - 11 and the key the page of the storage is seems to be relevant Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
The storage keys exceptions are determined during the process of executing the specific instruction. The value of PSW key at any time prior to the specific instruction being executed is not relevant. On Fri, Apr 20, 2012 at 2:19 PM, Micheal Butz michealb...@optonline.netwrote: Hi, Was wondering If someone could clear up some things for me A S0C4 reason code 4 means the storage key and the PSW key don't match typically trying to access storage key 0 when the PSW key is key 8 Two questions arise from this . Does it matter what the PSW key at the time of the STORAGE OBTAIN was e.g. 1. Obtaining storage from subpool 0 where the storage key is 8 and PSW key at the time for what ever reason was in KEY 0. Would I have to set the PSW Key to 0 if I were trying to access that storage later on say while running in some other task because when I did the STORAGE OBTAIN the PSW KEY 8 - 11 was 0 2. The same situation would be then true if access CSA storage subpool 241 with Key=8 ( Iknow a no no) but the PSW KEY was 0. Later on when trying to access/modify the storage would I have to set PSW key 8 - 11 have to be 0 . Of what significance does is the key the TCB (TCBPKF) since it seems only PSW KEY 8 - 11 and the key the page of the storage is seems to be relevant Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
Re: Explination of S0C4 reason code 4 and related data areas
On 20 April 2012 17:19, Micheal Butz michealb...@optonline.net wrote: A S0C4 reason code 4 means the storage key and the PSW key don't match There are other possible reasons for an 0C4-04 abend, but 0C4-04 is always a protection exception of some sort. typically trying to access storage key 0 when the PSW key is key 8 Yes, typically. Does it matter what the PSW key at the time of the STORAGE OBTAIN was e.g. 1. Obtaining storage from subpool 0 where the storage key is 8 and PSW key at the time for what ever reason was in KEY 0. Would I have to set the PSW Key to 0 if I were trying to access that storage later on say while running in some other task because when I did the STORAGE OBTAIN the PSW KEY 8 - 11 was 0 Are you trying to ask if the PSW key at the time of STORAGE OBTAIN or GETMAIN determines the key of the storage that is obtained? If so, the answer is it depends. Both the form of the macro you use to obtain storage, and the subpool you obtain it from can affect the key of that storage. You need to read carefully both the description of the keywords on the macro you are using, and that of the subpool you are specifying. Some subpool requests return storage with a key of the caller's PSW key; others do not. There are further subtleties. The summary of subpools in section 1.8.3 of the MVS Diagnosis Reference is very helpful, but is not entirely a substitute for reading the macro descriptions carefully. 2. The same situation would be then true if access CSA storage subpool 241 with Key=8 ( Iknow a no no) but the PSW KEY was 0. Later on when trying to access/modify the storage would I have to set PSW key 8 - 11 have to be 0 An instruction executed when the PSW key is 0 will not encounter an exception because of key-controlled storage protection, but it can still fail if page protection or low storage protection is in effect. . Of what significance does is the key the TCB (TCBPKF) since it seems only PSW KEY 8 - 11 and the key the page of the storage is seems to be relevant Significance to what? To the key of the storage that you obtain? Or to other things? Certainly TCBPKF has no direct effect on what happens during the execution of a machine instruction. Tony H. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
