Re: [PATCH] iio: adc: exynos: drop unneeded variable assignment
On Sat, Apr 10, 2021 at 10:18 PM Krzysztof Kozlowski wrote: > > The initialization of 'ret' variable in probe function is shortly after > overwritten. This initialization is simply not used. > > Addresses-Coverity: Unused value > Signed-off-by: Krzysztof Kozlowski > --- Thanks Krzysztof, Reviewed-by: Alim Akhtar > drivers/iio/adc/exynos_adc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c > index 784c10deeb1a..2d8e36408f0e 100644 > --- a/drivers/iio/adc/exynos_adc.c > +++ b/drivers/iio/adc/exynos_adc.c > @@ -794,7 +794,7 @@ static int exynos_adc_probe(struct platform_device *pdev) > struct s3c2410_ts_mach_info *pdata = dev_get_platdata(>dev); > struct iio_dev *indio_dev = NULL; > bool has_ts = false; > - int ret = -ENODEV; > + int ret; > int irq; > > indio_dev = devm_iio_device_alloc(>dev, sizeof(struct > exynos_adc)); > -- > 2.25.1 > -- Regards, Alim
RE: [PATCH -next] scsi: ufs: fix all Kconfig help text indentation
Hello Randy, > -Original Message- > From: Randy Dunlap > Sent: 07 January 2021 02:26 > To: linux-kernel@vger.kernel.org > Cc: Randy Dunlap ; Alim Akhtar > ; Avri Altman ; linux- > s...@vger.kernel.org; James E.J. Bottomley ; Martin K. > Petersen > Subject: [PATCH -next] scsi: ufs: fix all Kconfig help text indentation > > Use consistent and expected indentation for all Kconfig text. > > Signed-off-by: Randy Dunlap > Cc: Alim Akhtar > Cc: Avri Altman > Cc: linux-s...@vger.kernel.org > Cc: "James E.J. Bottomley" > Cc: "Martin K. Petersen" > --- Reviewed-by: Alim Akhtar
RE: [PATCH 0/2] two UFS changes
Hi Bean, > -Original Message- > From: Bean Huo > Sent: 08 December 2020 00:32 > To: alim.akh...@samsung.com; avri.alt...@wdc.com; > asuto...@codeaurora.org; j...@linux.ibm.com; > martin.peter...@oracle.com; stanley@mediatek.com; > bean...@micron.com; bvanass...@acm.org; tomas.wink...@intel.com; > c...@codeaurora.org > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: [PATCH 0/2] two UFS changes > > From: Bean Huo > > > > Bean Huo (2): > scsi: ufs: Remove an unused macro definition POWER_DESC_MAX_SIZE > scsi: ufs: Fix wrong print message in dev_err() > > drivers/scsi/ufs/ufs.h| 1 - > drivers/scsi/ufs/ufshcd.c | 2 +- > 2 files changed, 1 insertion(+), 2 deletions(-) > Thanks! Acked-by: Alim Akhtar > -- > 2.17.1
RE: [PATCH 11/19] scsi: ufs: ufshcd: Fix some function doc-rot
Hi > -Original Message- > From: Lee Jones > Sent: 02 November 2020 17:27 > To: martin.peter...@oracle.com > Cc: linux-kernel@vger.kernel.org; Lee Jones ; Alim > Akhtar ; Avri Altman ; > Santosh Yaraganavi ; Vinayak Holikatti > > Subject: [PATCH 11/19] scsi: ufs: ufshcd: Fix some function doc-rot > > Fixes the following W=1 kernel build warning(s): > > drivers/scsi/ufs/ufshcd.c:6603: warning: Function parameter or member > 'hba' not described in 'ufshcd_try_to_abort_task' > drivers/scsi/ufs/ufshcd.c:6603: warning: Function parameter or member 'tag' > not described in 'ufshcd_try_to_abort_task' > drivers/scsi/ufs/ufshcd.c:6603: warning: Excess function parameter 'cmd' > description in 'ufshcd_try_to_abort_task' > > Cc: Alim Akhtar > Cc: Avri Altman > Cc: Santosh Yaraganavi > Cc: Vinayak Holikatti > Signed-off-by: Lee Jones > --- Thanks! Acked-by: Alim Akhtar
RE: [PATCH v2] scsi: ufs-exynos: use devm_platform_ioremap_resource_byname()
Hi Bean, > -Original Message- > From: Bean Huo > Sent: 16 September 2020 14:10 > To: alim.akh...@samsung.com; avri.alt...@wdc.com; > asuto...@codeaurora.org; j...@linux.ibm.com; > martin.peter...@oracle.com; stanley@mediatek.com; > bean...@micron.com; bvanass...@acm.org; tomas.wink...@intel.com; > c...@codeaurora.org > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: [PATCH v2] scsi: ufs-exynos: use > devm_platform_ioremap_resource_byname() > > From: Bean Huo > > Use devm_platform_ioremap_resource_byname() to simplify the code. > > Signed-off-by: Bean Huo > --- Thanks! Acked-by: Alim Akhtar > > v1-v2: change the patch commit subject >
RE: linux-next: Tree for Jul 20 (scsi/ufs/exynos)
Hi Randy and Martin, > -Original Message- > From: Martin K. Petersen > Sent: 10 September 2020 07:58 > To: Randy Dunlap > Cc: Alim Akhtar ; 'Stephen Rothwell' > ; 'Linux Next Mailing List' n...@vger.kernel.org>; 'Linux Kernel Mailing List' ker...@vger.kernel.org>; 'linux-scsi' ; 'Santosh > Yaraganavi' ; 'Vinayak Holikatti' > ; 'Seungwon Jeon' > Subject: Re: linux-next: Tree for Jul 20 (scsi/ufs/exynos) > > > Randy, > > > I am still seeing this in linux-next of 20200909. > > Was there a patch posted that I missed and is not applied anywhere yet? > > This patch became a victim of dropping the Exynos changes in 5.9. I have > added it back in. > Sorry about not following on this after 5.9-rc1 was out. As Martin pointed this was posted https://www.spinics.net/lists/linux-scsi/msg144970.html I just send V2 of the same with Randy's Acked-by Please take a look. > -- > Martin K. PetersenOracle Linux Engineering
[PATCH v2] scsi: ufs: Fix 'unmet direct dependencies' config warning
With !CONFIG_OF and SCSI_UFS_EXYNOS selected, the below warning is given: WARNING: unmet direct dependencies detected for PHY_SAMSUNG_UFS Depends on [n]: OF [=n] && (ARCH_EXYNOS || COMPILE_TEST [=y]) Selected by [y]: - SCSI_UFS_EXYNOS [=y] && SCSI_LOWLEVEL [=y] && SCSI [=y] && SCSI_UFSHCD_PLATFORM [=y] && (ARCH_EXYNOS || COMPILE_TEST [=y]) Fix it by removing PHY_SAMSUNG_UFS dependency. Reported-by: Randy Dunlap Signed-off-by: Alim Akhtar Acked-by: Randy Dunlap --- * Changes since v1 - rebased on 5.10-scsi-queue - Added Randy's Acked-by drivers/scsi/ufs/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index f6394999b98c..dcdb4eb1f90b 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -165,7 +165,6 @@ config SCSI_UFS_BSG config SCSI_UFS_EXYNOS tristate "EXYNOS specific hooks to UFS controller platform driver" depends on SCSI_UFSHCD_PLATFORM && (ARCH_EXYNOS || COMPILE_TEST) - select PHY_SAMSUNG_UFS help This selects the EXYNOS specific additions to UFSHCD platform driver. UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with base-commit: 32417d7844ab0bc154c39128d9ac026f4f8a7907 -- 2.17.1
RE: [RESEND PATCH v10 04/10] scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk
Hi Eric,
> -Original Message-
> From: Eric Biggers
> Sent: 12 August 2020 05:59
> To: Alim Akhtar
> Cc: r...@kernel.org; devicet...@vger.kernel.org;
linux-s...@vger.kernel.org;
> k...@kernel.org; avri.alt...@wdc.com; martin.peter...@oracle.com;
> kwmad@samsung.com; stanley@mediatek.com;
> c...@codeaurora.org; linux-samsung-...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; kis...@ti.com
> Subject: Re: [RESEND PATCH v10 04/10] scsi: ufs: introduce
> UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk
>
> Hi Alim,
>
> On Sat, Jun 13, 2020 at 08:17:00AM +0530, Alim Akhtar wrote:
> > Some UFS host controllers like Exynos uses granularities of PRDT
> > length and offset as bytes, whereas others uses actual segment count.
> >
> > Reviewed-by: Avri Altman
> > Signed-off-by: Kiwoong Kim
> > Signed-off-by: Alim Akhtar
> > ---
> > drivers/scsi/ufs/ufshcd.c | 30 +++---
> > drivers/scsi/ufs/ufshcd.h | 6 ++
> > 2 files changed, 29 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
> > index ee30ed6cc805..ba093d0d0942 100644
> > --- a/drivers/scsi/ufs/ufshcd.c
> > +++ b/drivers/scsi/ufs/ufshcd.c
> > @@ -2151,8 +2151,14 @@ static int ufshcd_map_sg(struct ufs_hba *hba,
> struct ufshcd_lrb *lrbp)
> > return sg_segments;
> >
> > if (sg_segments) {
> > - lrbp->utr_descriptor_ptr->prd_table_length =
> > - cpu_to_le16((u16)sg_segments);
> > +
> > + if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
> > + lrbp->utr_descriptor_ptr->prd_table_length =
> > + cpu_to_le16((sg_segments *
> > + sizeof(struct ufshcd_sg_entry)));
> > + else
> > + lrbp->utr_descriptor_ptr->prd_table_length =
> > + cpu_to_le16((u16) (sg_segments));
> >
> > prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
> >
> > @@ -3500,11 +3506,21 @@ static void
> ufshcd_host_memory_configure(struct ufs_hba *hba)
> >
> cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
> >
> > /* Response upiu and prdt offset should be in double words
*/
> > - utrdlp[i].response_upiu_offset =
> > - cpu_to_le16(response_offset >> 2);
> > - utrdlp[i].prd_table_offset = cpu_to_le16(prdt_offset >> 2);
> > - utrdlp[i].response_upiu_length =
> > - cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
> > + if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
> > + utrdlp[i].response_upiu_offset =
> > + cpu_to_le16(response_offset);
> > + utrdlp[i].prd_table_offset =
> > + cpu_to_le16(prdt_offset);
> > + utrdlp[i].response_upiu_length =
> > + cpu_to_le16(ALIGNED_UPIU_SIZE);
> > + } else {
> > + utrdlp[i].response_upiu_offset =
> > + cpu_to_le16(response_offset >> 2);
> > + utrdlp[i].prd_table_offset =
> > + cpu_to_le16(prdt_offset >> 2);
> > + utrdlp[i].response_upiu_length =
> > + cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
> > + }
> >
> > ufshcd_init_lrb(hba, >lrb[i], i);
> > }
>
> Isn't this patch missing an update to ufshcd_print_trs()? It uses
> ->prd_table_length as the number of segments, not the number of bytes.
>
prd_table_length will be populated before it reaches ufshcd_print_trs()
based on UFSHCD_QUIRK_PRDT_BYTE_GRAN.
> - Eric
RE: [RFT PATCH v5] serial: samsung: Removes the IRQ not found warning
Hi Tamseel,
> -Original Message-
> From: Tamseel Shams
> Sent: 10 August 2020 08:30
> To: kg...@kernel.org; k...@kernel.org; gre...@linuxfoundation.org;
> jsl...@suse.com
> Cc: linux-arm-ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org;
> linux-ser...@vger.kernel.org; linux-kernel@vger.kernel.org;
> alim.akh...@samsung.com; Tamseel Shams
> Subject: [RFT PATCH v5] serial: samsung: Removes the IRQ not found warning
>
> In few older Samsung SoCs like s3c2410, s3c2412 and s3c2440, UART IP is having
> 2 interrupt lines.
> However, in other SoCs like s3c6400, s5pv210, exynos5433, and exynos4210
> UART is having only 1 interrupt line. Due to this, "platform_get_irq(platdev,
> 1)"
> call in the driver gives the following false-positive error:
> "IRQ index 1 not found" on newer SoC's.
>
> This patch adds the condition to check for Tx interrupt only for the those
> SoC's
> which have 2 interrupt lines.
>
> Signed-off-by: Tamseel Shams
> ---
Tested on exynos7 platform, don’t see " IRQ index 1 not found" with this patch
applied
Fill free to added
Tested-by: Alim Akhtar
Reviewed-by: Alim Akhtar
> Commit message is changed.
>
> Added RFT, for older platform.
>
> Addressed Krzysztof's review comments [1] [1] ->
> https://lkml.org/lkml/2020/7/21/150
>
> drivers/tty/serial/samsung_tty.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/tty/serial/samsung_tty.c
> b/drivers/tty/serial/samsung_tty.c
> index 6ef614d8648c..b923683e6a25 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -1911,9 +1911,11 @@ static int s3c24xx_serial_init_port(struct
> s3c24xx_uart_port *ourport,
> ourport->tx_irq = ret + 1;
> }
>
> - ret = platform_get_irq(platdev, 1);
> - if (ret > 0)
> - ourport->tx_irq = ret;
> + if (!s3c24xx_serial_has_interrupt_mask(port)) {
> + ret = platform_get_irq(platdev, 1);
> + if (ret > 0)
> + ourport->tx_irq = ret;
> + }
> /*
>* DMA is currently supported only on DT platforms, if DMA properties
>* are specified.
> --
> 2.17.1
RE: [PATCH v8 0/4] scsi: ufs: Add Host Performance Booster Support
> -Original Message- > From: Avri Altman > Sent: 06 August 2020 19:27 > To: Bean Huo ; daejun7.p...@samsung.com; > j...@linux.ibm.com; martin.peter...@oracle.com; asuto...@codeaurora.org; > bean...@micron.com; stanley@mediatek.com; c...@codeaurora.org; > bvanass...@acm.org; tomas.wink...@intel.com; ALIM AKHTAR > > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org; Sang-yoon Oh > ; Sung-Jun Park > ; yongmyung lee > ; Jinyoung CHOI ; > Adel Choi ; BoRam Shin > > Subject: RE: [PATCH v8 0/4] scsi: ufs: Add Host Performance Booster Support > > > > > > On Thu, 2020-08-06 at 10:12 +, Avri Altman wrote: > > > > > > > > > > > > > we didn't see you Acked-by in the pathwork, would you like to add > > > > them? > > > > Just for reminding us that you have agreed to mainline this series > > > > patchset. > > > > > > I acked it - > > > https://protect2.fireeye.com/url?k=039c5a1c-5e48e674-039dd153-0cc47a > > > 3356b2- > 66867eb5b9700b6a=1=https%3A%2F%2Fwww.spinics.net%2Flists% > > > 2Flinux-scsi%2Fmsg144660.html > > > And asked Martin to move forward - > > > https://protect2.fireeye.com/url?k=94dceb38-c9085750-94dd6077-0cc47a > > > 3356b2- > 19ab1f41f48ff179=1=https%3A%2F%2Fwww.spinics.net%2Flists% > > > 2Flinux-scsi%2Fmsg144738.html Which he did, and got some sparse > > > errors: > > > https://protect2.fireeye.com/url?k=a40e2dd1-f9da91b9-a40fa69e-0cc47a > > > 3356b2- > 81fae05297aebb0e=1=https%3A%2F%2Fwww.spinics.net%2Flists% > > > 2Flinux-scsi%2Fmsg144977.html > > > Which I asked Daejun to fix - > > > https://protect2.fireeye.com/url?k=6badf100-36794d68-6bac7a4f-0cc47a > > > 3356b2- > f84580e236611583=1=https%3A%2F%2Fwww.spinics.net%2Flists% > > > 2Flinux-scsi%2Fmsg144987.html > > > > > > For the next chain of events I guess you can follow by yourself. > > > > > > Thanks, > > > Avri > > > > Avri > > Sorry for making you confusing. yes, I knew that, and following. > > I mean Acked-by tag in the patchset, then we see your acked in the > > patchwork, and let others know that you acked it, rather than going > > backtrack history email. > > > > Hi Daejun > > I think you can add Avri's Acked-by tag in your patchset, just for > > quickly moving forward and reminding. > Ahhh - One moment please - > While rebasing the v8 on my platform, I noticed some substantial changes since > v6. > e.g. the hpb lun ref counting isn't there anymore, as well as some more stuff. > While those changes might be only for the best, I think any tested-by tag > should > be re-assign. > > Anyway, as for myself, I am not planning to put any more time in this, until > there > is a clear decision where this series is going to. > > Martin - Are you considering to merge the HPB feature eventually to mainline > kernel? > V8 has removed the "UFS feature layer" which was the main topic of discussion. What else we thing is blocking this to be in mainline? Bart / Martin, any thought? > Thanks, > Avri > > > > thanks, > > Bean
RE: mmotm 2020-07-27-18-18 uploaded (drivers/scsi/ufs/: SCSI_UFS_EXYNOS)
Hi Randy, > -Original Message- > From: Randy Dunlap > Sent: 28 July 2020 08:53 > To: Andrew Morton ; broo...@kernel.org; linux- > fsde...@vger.kernel.org; linux-kernel@vger.kernel.org; linux...@kvack.org; > linux-n...@vger.kernel.org; mho...@suse.cz; mm-comm...@vger.kernel.org; > s...@canb.auug.org.au; linux-scsi ; Alim Akhtar > ; Seungwon Jeon > Subject: Re: mmotm 2020-07-27-18-18 uploaded (drivers/scsi/ufs/: > SCSI_UFS_EXYNOS) > > On 7/27/20 6:19 PM, Andrew Morton wrote: > > The mm-of-the-moment snapshot 2020-07-27-18-18 has been uploaded to > > > >http://www.ozlabs.org/~akpm/mmotm/ > > > > mmotm-readme.txt says > > > > README for mm-of-the-moment: > > > > http://www.ozlabs.org/~akpm/mmotm/ > > > > This is a snapshot of my -mm patch queue. Uploaded at random > > hopefully more than once a week. > > > > You will need quilt to apply these patches to the latest Linus release > > (5.x or 5.x-rcY). The series file is in broken-out.tar.gz and is > > duplicated in http://ozlabs.org/~akpm/mmotm/series > > > > on i386: > > when CONFIG_OF is not set/enabled: > > WARNING: unmet direct dependencies detected for PHY_SAMSUNG_UFS > Depends on [n]: OF [=n] && (ARCH_EXYNOS || COMPILE_TEST [=y]) > Selected by [m]: > - SCSI_UFS_EXYNOS [=m] && SCSI_LOWLEVEL [=y] && SCSI [=y] && > SCSI_UFSHCD_PLATFORM [=m] && (ARCH_EXYNOS || COMPILE_TEST [=y]) > Have already posted a fix for this [1] [1] https://www.spinics.net/lists/linux-scsi/msg144970.html > > Full randconfig file is attached. > Thanks for config file, I can reproduce it and confirm that [1] above fixes this Warning. > > -- > ~Randy > Reported-by: Randy Dunlap
RE: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support
Hi Martin > -Original Message- > From: Avri Altman > Sent: 19 July 2020 12:05 > To: Alim Akhtar ; daejun7.p...@samsung.com; > j...@linux.ibm.com; martin.peter...@oracle.com; asuto...@codeaurora.org; > bean...@micron.com; stanley@mediatek.com; c...@codeaurora.org; > bvanass...@acm.org; tomas.wink...@intel.com > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org; 'Sang-yoon Oh' > ; 'Sung-Jun Park' > ; 'yongmyung lee' > ; 'Jinyoung CHOI' young.c...@samsung.com>; 'Adel Choi' ; 'BoRam > Shin' > Subject: RE: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support > > Martin - Can we move forward with this one? > > Thanks, > Avri > > > > > > > v5 -> v6 > > > > Change base commit to b53293fa662e28ae0cdd40828dc641c09f133405 > > > > > > > If no further comments, can this series have your Reviewed-by or > > > Acked-by tag, so that this can be taken for 5.9? > > > Thanks! > > Hey, yes. So sorry for this delay, I was away for few days. > > Yes - This series looks good to me. > > This series needs your attention. Thanks, > > Thanks, > > Avri > > > > > > > > > v4 -> v5 > > > > Delete unused macro define. > > >
RE: linux-next: Tree for Jul 20 (scsi/ufs/exynos)
Hi Randy, > -Original Message- > From: Randy Dunlap > Sent: 20 July 2020 22:11 > To: Stephen Rothwell ; Linux Next Mailing List n...@vger.kernel.org> > Cc: Linux Kernel Mailing List ; linux-scsi > s...@vger.kernel.org>; Santosh Yaraganavi ; > Vinayak Holikatti ; Alim Akhtar > ; Seungwon Jeon > Subject: Re: linux-next: Tree for Jul 20 (scsi/ufs/exynos) > > On 7/20/20 2:42 AM, Stephen Rothwell wrote: > > Hi all, > > > > Changes since 20200717: > > > > on x86_64: > > WARNING: unmet direct dependencies detected for PHY_SAMSUNG_UFS > Depends on [n]: OF [=n] && (ARCH_EXYNOS || COMPILE_TEST [=y]) > Selected by [y]: > - SCSI_UFS_EXYNOS [=y] && SCSI_LOWLEVEL [=y] && SCSI [=y] && > SCSI_UFSHCD_PLATFORM [=y] && (ARCH_EXYNOS || COMPILE_TEST [=y]) > Thanks, will post a patch shortly. > > There are no build errors since provides stubs for functions when > CONFIG_OF is not enabled. > > But new warnings are not OK. > > thanks. > -- > ~Randy > Reported-by: Randy Dunlap
RE: [PATCH][next] phy: samsung-ufs: fix check on failed devm_clk_get call for rx1_symbol_clk
Hello Colin,
> -Original Message-
> From: Colin King
> Sent: 20 July 2020 22:00
> To: Kishon Vijay Abraham I ; Vinod Koul ;
> Seungwon Jeon ; Kiwoong Kim
> ; Alim Akhtar
> Cc: kernel-janit...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH][next] phy: samsung-ufs: fix check on failed devm_clk_get call
> for rx1_symbol_clk
>
> From: Colin Ian King
>
> The check to see if the call to devm_clk_get on rx1_symbol_clk is checking the
> wrong variable, this looks like a copy-paste error. Fix this to check
> phy->rx1_symbol instead of phy->rx0_symbol.
>
This fix is already posted by Gustavo [1]
[1] https://lkml.org/lkml/2020/7/20/617
Thanks!
> Addresses-Coverity: ("Copy-paste error")
> Fixes: bca21e930451 ("phy: samsung-ufs: add UFS PHY driver for samsung SoC")
> Signed-off-by: Colin Ian King
> ---
> drivers/phy/samsung/phy-samsung-ufs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c
> b/drivers/phy/samsung/phy-samsung-ufs.c
> index 43ef77d1d96c..9832599a0283 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -147,7 +147,7 @@ static int samsung_ufs_phy_symbol_clk_init(struct
> samsung_ufs_phy *phy)
> }
>
> phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> - if (IS_ERR(phy->rx0_symbol_clk)) {
> + if (IS_ERR(phy->rx1_symbol_clk)) {
> dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> return PTR_ERR(phy->rx1_symbol_clk);
> }
> --
> 2.27.0
RE: [PATCH v2][next] phy: samsung-ufs: Fix IS_ERR argument
Hi Gustavo,
> -Original Message-
> From: Gustavo A. R. Silva
> Sent: 20 July 2020 18:57
> To: Kishon Vijay Abraham I ; Vinod Koul ;
> Seungwon Jeon ; Alim Akhtar
> ; Kiwoong Kim
> Cc: linux-kernel@vger.kernel.org; Gustavo A. R. Silva
> Subject: [PATCH v2][next] phy: samsung-ufs: Fix IS_ERR argument
>
> Fix IS_ERR argument in samsung_ufs_phy_symbol_clk_init(). The proper
> argument to be passed to IS_ERR() is phy->rx1_symbol_clk.
>
> This bug was detected with the help of Coccinelle.
>
> Fixes: bca21e930451 ("phy: samsung-ufs: add UFS PHY driver for samsung
SoC")
> Signed-off-by: Gustavo A. R. Silva
> ---
Reviewed-by: Alim Akhtar
> Changes in v2:
> - Update subject line and changelog text.
>
> drivers/phy/samsung/phy-samsung-ufs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c
> b/drivers/phy/samsung/phy-samsung-ufs.c
> index 43ef77d1d96c..9832599a0283 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -147,7 +147,7 @@ static int samsung_ufs_phy_symbol_clk_init(struct
> samsung_ufs_phy *phy)
> }
>
> phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> - if (IS_ERR(phy->rx0_symbol_clk)) {
> + if (IS_ERR(phy->rx1_symbol_clk)) {
> dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> return PTR_ERR(phy->rx1_symbol_clk);
> }
> --
> 2.27.0
RE: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support
Hi Avi, > -Original Message- > From: Avi Shchislowski > Sent: 16 July 2020 15:31 > To: Bart Van Assche ; daejun7.p...@samsung.com; Avri > Altman ; j...@linux.ibm.com; > martin.peter...@oracle.com; asuto...@codeaurora.org; > bean...@micron.com; stanley@mediatek.com; c...@codeaurora.org; > tomas.wink...@intel.com; ALIM AKHTAR > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org; Sang-yoon Oh > ; Sung-Jun Park > ; yongmyung lee > ; Jinyoung CHOI ; > Adel Choi ; BoRam Shin > > Subject: RE: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support > > > > > -Original Message- > > From: Bart Van Assche > > Sent: Thursday, July 16, 2020 4:42 AM > > To: Avi Shchislowski ; > > daejun7.p...@samsung.com; Avri Altman ; > > j...@linux.ibm.com; martin.peter...@oracle.com; > > asuto...@codeaurora.org; bean...@micron.com; > stanley@mediatek.com; > > c...@codeaurora.org; tomas.wink...@intel.com; ALIM AKHTAR > > > > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org; > > Sang-yoon Oh ; Sung-Jun Park > > ; yongmyung lee > > ; Jinyoung CHOI young.c...@samsung.com>; > > Adel Choi ; BoRam Shin > > > Subject: Re: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster > > Support > > > > CAUTION: This email originated from outside of Western Digital. Do not > > click on links or open attachments unless you recognize the sender and > > know that the content is safe. > > > > > > On 2020-07-15 11:34, Avi Shchislowski wrote: > > > My name is Avi Shchislowski, I am managing the WDC's Linux Host R > > > team > > in which Avri is a member of. > > > As the review process of HPB is progressing very constructively, we > > > are getting > > more and more requests from OEMs, Inquiring about HPB in general, and > > host control mode in particular. > > > > > > Their main concern is that HPB will make it to 5.9 merge window, but > > > the host > > control mode patches will not. > > > Thus, because of recent Google's GKI, the next Android LTS might not > > > include > > HPB with host control mode. > > > > > > Aside of those requests, initial host control mode testing are > > > showing > > promising prospective with respect of performance gain. > > > > > > What would be, in your opinion, the best policy that host control > > > mode is > > included in next Android LTS? > > > > Hi Avi, > > > > Are you perhaps referring to the HPB patch series that has already been > posted? > > Although I'm not sure of this, I think that the SCSI maintainer > > expects more > > Reviewed-by: and Tested-by: tags. Has anyone from WDC already taken > > the time to review and/or test this patch series? > > > > Thanks, > > > > Bart. > > Yes, I am referring to the current proposal which I am replying to: > [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support This proposal > does not contains host mode, hence our customers concern. > What would be, in your opinion, the best policy that host control mode is > included in next Android LTS assuming it will be based on kernel v5.9 ? > This series has nothing to do with Host mode control, this series is targeted for device mode control. General consensus here is to land this series as it is (unless someone has more review comments) and lets add/enhance whatever need to be done for adding Host mode controls as well as other HPB2.0 related changes. > Thanks, > Avi
[PATCH v13 1/2] dt-bindings: phy: Document Samsung UFS PHY bindings
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index ..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+properties:
+ "#phy-cells":
+const: 0
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+maxItems: 1
+
+ reg-names:
+items:
+ - const: phy-pma
+
+ clocks:
+items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+ufs_phy: ufs-phy@15571800 {
+compatible = "samsung,exynos7-ufs-phy";
+reg = <0x15571800 0x240>;
+reg-names = "phy-pma";
+samsung,pmu-syscon = <_system_controller>;
+#phy-cells = <0>;
+clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+};
+...
base-commit: 0ff35966d171ec99b118df666c1687cc86ba8d7e
--
2.17.1
[PATCH v13 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
[Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
Reported-by: kernel test robot
Reviewed-by: Kiwoong Kim
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Tested-by: Paweł Chmiel
---
- Changes V12 -> V13
* Addressed more review comments from Vinod [1]
[1] https://lkml.org/lkml/2020/7/13/99
- Changes V11 -> V12
* Fixed kernel test robot warnings
- Changes V10 -> V11
* Addressed review comments from Vinod
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 81 ++
drivers/phy/samsung/phy-samsung-ufs.c | 366 ++
drivers/phy/samsung/phy-samsung-ufs.h | 139 ++
5 files changed, 596 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 19f2e3119343..e20d2fcc9fe7 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index ..518923141958
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MOD
RE: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
Hi Vinod,
> -Original Message-
> From: Vinod Koul
> Sent: 13 July 2020 11:48
> To: Alim Akhtar
> Cc: robh...@kernel.org; k...@kernel.org; kwmad@samsung.com;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; linux-samsung-...@vger.kernel.org; kis...@ti.com
> Subject: Re: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for
samsung
> SoC
>
> On 03-07-20, 22:41, Alim Akhtar wrote:
>
> > +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> > + END_UFS_PHY_CFG
> > +};
>
> This is dummy, why not add a check to make config optional?
>
Currently this is dummy, however this might be used for the similar platform
which do some phy tunning post init.
Will just remove this for now for this platform, will add this check in
driver.
> > +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy
> > +*phy) {
> > + int ret = 0;
>
> superfluous init, am sure I flagged it before as well
>
Yes, you did, but 0-DAY CI kernel test gave warning [1], so I kept this as
it is.
[1] https://lkml.org/lkml/2020/7/3/81
> > +
> > + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> > + if (IS_ERR(phy->tx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n",
> __func__, ret);
> > + goto out;
> > + }
> > +
> > + ret = clk_prepare_enable(phy->rx0_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n",
> __func__, ret);
> > + clk_disable_unprepare(phy->tx0_symbol_clk);
> > + goto out;
> > + }
> > +
> > + ret = clk_prepare_enable(phy->rx1_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n",
> __func__, ret);
> > + clk_disable_unprepare(phy->tx0_symbol_clk);
> > + clk_disable_unprepare(phy->rx0_symbol_clk);
>
> maybe it will look better if we add common rollback and jump to proper
labels
>
Sure, will change in next version.
> > +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy) {
> > + int ret;
> > +
> > + phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
> > + if (IS_ERR(phy->ref_clk))
> > + dev_err(phy->dev, "failed to get ref_clk clock\n");
> > +
> > + ret = clk_prepare_enable(phy->ref_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
__func__,
> ret);
> > + return ret;
> > + }
> > +
> > + dev_info(phy->dev, "UFS MPHY ref_clk_rate = %ld\n",
> > +clk_get_rate(phy->ref_clk));
>
> debug pls
>
Sure, will change
> > +static int samsung_ufs_phy_init(struct phy *phy) {
> > + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
>
> ss_phy perhaps?
>
Sure, will change
> > + int ret;
> > +
> > + _phy->lane_cnt = phy->attrs.bus_width;
> > + _phy->ufs_phy_state = CFG_PRE_INIT;
> > +
> > + if (_phy->drvdata->has_symbol_clk) {
> > + ret = samsung_ufs_phy_symbol_clk_init(_phy);
> > + if (ret)
> > + dev_err(_phy->dev, "failed to set ufs phy symbol
> clocks\n");
> > + }
> > +
> > + ret = samsung_ufs_phy_clks_init(_phy);
> > + if (ret)
> > + dev_err(_phy->dev, "failed to set ufs phy clocks\n");
> > +
> > + samsung_ufs_phy_calibrate(phy);
> > +
> > + return 0;
>
> not return samsung_ufs_phy_calibrate() ?
> --
Will add an error path.
> ~Vinod
RE: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support
Hi Avri, > -Original Message- > From: Daejun Park > Sent: 13 July 2020 16:04 > To: avri.alt...@wdc.com; j...@linux.ibm.com; martin.peter...@oracle.com; > asuto...@codeaurora.org; bean...@micron.com; > stanley@mediatek.com; c...@codeaurora.org; bvanass...@acm.org; > tomas.wink...@intel.com; ALIM AKHTAR ; Daejun > Park > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org; Sang-yoon Oh > ; Sung-Jun Park > ; yongmyung lee > ; Jinyoung CHOI ; > Adel Choi ; BoRam Shin > > Subject: [PATCH v6 0/5] scsi: ufs: Add Host Performance Booster Support > > Changelog: > > v5 -> v6 > Change base commit to b53293fa662e28ae0cdd40828dc641c09f133405 > If no further comments, can this series have your Reviewed-by or Acked-by tag, so that this can be taken for 5.9? Thanks! > v4 -> v5 > Delete unused macro define.
Re: [RESEND PATCH v10] dt-bindings: ufs: Add bindings for Samsung ufs host
Hi Rob
Can you please take this via your tree?
On Thu, Jun 25, 2020 at 6:20 AM Alim Akhtar wrote:
>
> This patch adds DT bindings for Samsung ufs hci
>
> Reviewed-by: Rob Herring
> Signed-off-by: Alim Akhtar
> ---
>
> Hi Rob
> This is just a rebase on your's dt/next
>
> This patch was part of [1]
> [1] https://lkml.org/lkml/2020/5/27/1697
>
> .../bindings/ufs/samsung,exynos-ufs.yaml | 89 +++
> 1 file changed, 89 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
>
> diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> new file mode 100644
> index ..38193975c9f1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> @@ -0,0 +1,89 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SoC series UFS host controller Device Tree Bindings
> +
> +maintainers:
> + - Alim Akhtar
> +
> +description: |
> + Each Samsung UFS host controller instance should have its own node.
> + This binding define Samsung specific binding other then what is used
> + in the common ufshcd bindings
> + [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
> +
> +properties:
> +
> + compatible:
> +enum:
> + - samsung,exynos7-ufs
> +
> + reg:
> +items:
> + - description: HCI register
> + - description: vendor specific register
> + - description: unipro register
> + - description: UFS protector register
> +
> + reg-names:
> +items:
> + - const: hci
> + - const: vs_hci
> + - const: unipro
> + - const: ufsp
> +
> + clocks:
> +items:
> + - description: ufs link core clock
> + - description: unipro main clock
> +
> + clock-names:
> +items:
> + - const: core_clk
> + - const: sclk_unipro_main
> +
> + interrupts:
> +maxItems: 1
> +
> + phys:
> +maxItems: 1
> +
> + phy-names:
> +const: ufs-phy
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - phys
> + - phy-names
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +#include
> +
> +ufs: ufs@1557 {
> + compatible = "samsung,exynos7-ufs";
> + reg = <0x1557 0x100>,
> + <0x15570100 0x100>,
> + <0x15571000 0x200>,
> + <0x15572000 0x300>;
> + reg-names = "hci", "vs_hci", "unipro", "ufsp";
> + interrupts = ;
> + clocks = <_fsys1 ACLK_UFS20_LINK>,
> +<_fsys1 SCLK_UFSUNIPRO20_USER>;
> + clock-names = "core_clk", "sclk_unipro_main";
> + pinctrl-names = "default";
> + pinctrl-0 = <_rst_n _refclk_out>;
> + phys = <_phy>;
> + phy-names = "ufs-phy";
> +};
> +...
>
> base-commit: b3a9e3b9622ae10064826dccb4f7a52bd88c7407
> prerequisite-patch-id: e0425bbe8f2aff3882b728a0caf0218b6b3e9b6e
> prerequisite-patch-id: c8c8502c512f9d6fdaf7d30e54dde3e68c3d855b
> prerequisite-patch-id: 8505df2fd70632150b50543cadc6fd7dd42d191c
> prerequisite-patch-id: 1a9701ab83425940c8aacb76737edb57ab815e47
> prerequisite-patch-id: 7881e0b87f1f04f657d9e6d450fb5231ad6ffa1a
> prerequisite-patch-id: 01dbc0e550e3fcad6e525e7e3183f9f0312e8496
> prerequisite-patch-id: ad801812fff960abab3f27d2c7383be9fd9aa439
> prerequisite-patch-id: 65474c9540e6dc749d30223897de1f486d6b3843
> prerequisite-patch-id: 64b58cd4c5ecfacf28fc20c31a6617092a1e1931
> prerequisite-patch-id: 9bcdd2995fd3f6361f8d5e89c56645058ac9ff96
> --
> 2.17.1
>
--
Regards,
Alim
Re: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
Hi Vinod
Gentle Reminder !!
On Fri, Jul 3, 2020 at 11:02 PM Alim Akhtar wrote:
>
> This patch introduces Samsung UFS PHY driver. This driver
> supports to deal with phy calibration and power control
> according to UFS host driver's behavior.
>
> [Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
> Reported-by: kernel test robot
> Reviewed-by: Kiwoong Kim
> Signed-off-by: Seungwon Jeon
> Signed-off-by: Alim Akhtar
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Tested-by: Paweł Chmiel
> ---
> - Changes V11 -> V12
> * Fixed kernel test robot warnings
>
> - Changes V10 -> V11
> * Addressed review comments from Vinod
>
> drivers/phy/samsung/Kconfig | 9 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++
> drivers/phy/samsung/phy-samsung-ufs.c | 359 ++
> drivers/phy/samsung/phy-samsung-ufs.h | 139 ++
> 5 files changed, 594 insertions(+)
> create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
> create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
>
> diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> index 19f2e3119343..e20d2fcc9fe7 100644
> --- a/drivers/phy/samsung/Kconfig
> +++ b/drivers/phy/samsung/Kconfig
> @@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
> Enable PCIe PHY support for Exynos SoC series.
> This driver provides PHY interface for Exynos PCIe controller.
>
> +config PHY_SAMSUNG_UFS
> + tristate "SAMSUNG SoC series UFS PHY driver"
> + depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enable this to support the Samsung UFS PHY driver for
> + Samsung SoCs. This driver provides the interface for UFS
> + host controller to do PHY related programming.
> +
> config PHY_SAMSUNG_USB2
> tristate "Samsung USB 2.0 PHY driver"
> depends on HAS_IOMEM
> diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
> index db9b1aa0de6e..3959100fe8a2 100644
> --- a/drivers/phy/samsung/Makefile
> +++ b/drivers/phy/samsung/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
> +obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
> obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
> phy-exynos-usb2-y += phy-samsung-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
> b/drivers/phy/samsung/phy-exynos7-ufs.h
> new file mode 100644
> index ..c4aab792d30e
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.h
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UFS PHY driver data for Samsung EXYNOS7 SoC
> + *
> + * Copyright (C) 2020 Samsung Electronics Co., Ltd.
> + */
> +#ifndef _PHY_EXYNOS7_UFS_H_
> +#define _PHY_EXYNOS7_UFS_H_
> +
> +#include "phy-samsung-ufs.h"
> +
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
> +
> +/* Calibration for phy initialization */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
> + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
> + PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
> + PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
> + END_UFS_PHY_CFG
> +};
> +
> +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> + END_UFS_PHY_CFG
> +};
> +
> +/* Calibration for HS mode series A/B */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
> + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
> + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
&g
RE: [PATCH v3] ARM: dts: exynos: Remove DMA controller bus node name to fix dtschema warnings
Hi Krzysztof
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: 05 July 2020 23:48
> To: Rob Herring ; Kukjin Kim ;
> Krzysztof Kozlowski ; devicet...@vger.kernel.org;
linux-arm-
> ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: Bartlomiej Zolnierkiewicz ; Sylwester
Nawrocki
> ; Alim Akhtar ; Chanwoo
> Choi ; Pankaj Dubey
>
> Subject: [PATCH v3] ARM: dts: exynos: Remove DMA controller bus node name
> to fix dtschema warnings
>
> There is no need to keep DMA controller nodes under AMBA bus node.
> Remove the "amba" node to fix dtschema warnings like:
>
> amba: $nodename:0: 'amba' does not match '^(bus|soc|axi|ahb|apb)(@[0-
> 9a-f]+)?$'
>
> Signed-off-by: Krzysztof Kozlowski
>
Reviewed-by: Alim Akhtar
> ---
>
> Changes since v2:
> 1. Keep the alphabetical order in exynos4210-universal_c210.dts, as
suggested
> by Marek
>
> Changes since v1:
> 1. Remove the bus, as suggested by Marek
> ---
> arch/arm/boot/dts/exynos3250.dtsi | 47 +++
> arch/arm/boot/dts/exynos4.dtsi| 70 +-
> .../boot/dts/exynos4210-universal_c210.dts| 28 ++--
> arch/arm/boot/dts/exynos5250.dtsi | 92 ++---
> arch/arm/boot/dts/exynos5410.dtsi | 46 +++
> arch/arm/boot/dts/exynos5420.dtsi | 130 --
> 6 files changed, 187 insertions(+), 226 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
> b/arch/arm/boot/dts/exynos3250.dtsi
> index 044e5da64a76..d3fb45a56527 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -418,33 +418,26 @@
> status = "disabled";
> };
>
> - amba {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> - pdma0: pdma@1268 {
> - compatible = "arm,pl330", "arm,primecell";
> - reg = <0x1268 0x1000>;
> - interrupts = IRQ_TYPE_LEVEL_HIGH>;
> - clocks = < CLK_PDMA0>;
> - clock-names = "apb_pclk";
> - #dma-cells = <1>;
> - #dma-channels = <8>;
> - #dma-requests = <32>;
> - };
> -
> - pdma1: pdma@1269 {
> - compatible = "arm,pl330", "arm,primecell";
> - reg = <0x1269 0x1000>;
> - interrupts = IRQ_TYPE_LEVEL_HIGH>;
> - clocks = < CLK_PDMA1>;
> - clock-names = "apb_pclk";
> - #dma-cells = <1>;
> - #dma-channels = <8>;
> - #dma-requests = <32>;
> - };
> + pdma0: pdma@1268 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x1268 0x1000>;
> + interrupts = ;
> + clocks = < CLK_PDMA0>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + };
> +
> + pdma1: pdma@1269 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x1269 0x1000>;
> + interrupts = ;
> + clocks = < CLK_PDMA1>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> };
>
> adc: adc@126c {
> diff --git a/arch/arm/boot/dts/exynos4.dtsi
b/arch/arm/boot/dts/exynos4.dtsi
> index d2779a790ce3..a1e54449f33f 100644
> --- a/arch/arm/boot/dts/exynos4.dtsi
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -669,45 +669,37 @@
> status = "disabled";
> };
>
> - amba: amba {
> - #address-cells = <1>;
> -
RE: [PATCH v1 2/2] arm64: dts: exynos: keep LDO12 always-on
Hi Krzysztof,
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: 05 July 2020 23:53
> To: Alim Akhtar
> Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> samsung-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> robh...@kernel.org
> Subject: Re: [PATCH v1 2/2] arm64: dts: exynos: keep LDO12 always-on
>
> On Sun, Jul 05, 2020 at 12:39:18PM +0530, Alim Akhtar wrote:
> > LDO12 on exynos7 supply power to VDDQ_UFS20_RESET, in case this
> > regulator is OFF, UFS host controller can not send command to UFS
> > device. To keep this supply ON, set regulator-always-on property for
> > this ldo.
>
> Why UFS does not take any supplies? This looks like a workaround for the case
> of not implementing any consumer.
>
This particular supply is not part of UFS HCI spec and binding documentation,
as per binding only one supply for host controller and three others for UFS
device are needed. My best guess is, VDDQ_UFS20_RESET supply to reset logic
block inside HCI, which might be specific to this controller version (I did not
find any such supply in the latest host controller though).
> Best regards,
> Krzysztof
>
>
> >
> > Signed-off-by: Alim Akhtar
> > ---
> > arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> > b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> > index bb86950032d3..92fecc539c6c 100644
> > --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> > +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> > @@ -194,6 +194,7 @@
> > regulator-min-microvolt = <100>;
> > regulator-max-microvolt = <130>;
> > regulator-enable-ramp-delay = <125>;
> > + regulator-always-on;
> > };
> >
> > ldo13_reg: LDO13 {
> > --
> > 2.17.1
> >
RE: [PATCH] scsi: ufs: change upiu_flags to be u8
Hi Bean
> -Original Message-
> From: Bean Huo
> Sent: 06 July 2020 18:10
> To: alim.akh...@samsung.com; avri.alt...@wdc.com;
> asuto...@codeaurora.org; j...@linux.ibm.com; martin.peter...@oracle.com;
> stanley@mediatek.com; bean...@micron.com; bvanass...@acm.org;
> tomas.wink...@intel.com; c...@codeaurora.org
> Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH] scsi: ufs: change upiu_flags to be u8
>
> From: Bean Huo
>
> According to the UFS Spec, the Flags in the UPIU is one-byte length, not
> 4 bytes. change it to be u8.
>
> Signed-off-by: Bean Huo
> ---
Reviewed-by: Alim Akhtar
Booted and tested on exynos7 board, tested basic read/write, so
Tested-by: Alim Akhtar
Thanks,
> drivers/scsi/ufs/ufshcd.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index
> 96d830bb900f..d7fd5891e81f 100644
> --- a/drivers/scsi/ufs/ufshcd.c
> +++ b/drivers/scsi/ufs/ufshcd.c
> @@ -2240,7 +2240,7 @@ static void ufshcd_disable_intr(struct ufs_hba *hba,
> u32 intrs)
> * @cmd_dir: requests data direction
> */
> static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
> - u32 *upiu_flags, enum dma_data_direction cmd_dir)
> + u8 *upiu_flags, enum dma_data_direction cmd_dir)
> {
> struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
> u32 data_direction;
> @@ -2286,7 +2286,7 @@ static void ufshcd_prepare_req_desc_hdr(struct
> ufshcd_lrb *lrbp,
> * @upiu_flags: flags
> */
> static
> -void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32
> upiu_flags)
> +void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8
> +upiu_flags)
> {
> struct scsi_cmnd *cmd = lrbp->cmd;
> struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; @@ -2319,7
> +2319,7 @@ void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp,
> u32 upiu_flags)
> * @upiu_flags: flags
> */
> static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
> - struct ufshcd_lrb *lrbp, u32 upiu_flags)
> + struct ufshcd_lrb *lrbp, u8 upiu_flags)
> {
> struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
> struct ufs_query *query = >dev_cmd.query; @@ -2376,7 +2376,7
> @@ static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
> static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
> struct ufshcd_lrb *lrbp)
> {
> - u32 upiu_flags;
> + u8 upiu_flags;
> int ret = 0;
>
> if ((hba->ufs_version == UFSHCI_VERSION_10) || @@ -2404,7 +2404,7
> @@ static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
> */
> static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb
*lrbp) {
> - u32 upiu_flags;
> + u8 upiu_flags;
> int ret = 0;
>
> if ((hba->ufs_version == UFSHCI_VERSION_10) || @@ -6124,7 +6124,7
> @@ static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
> int tag;
> struct completion wait;
> unsigned long flags;
> - u32 upiu_flags;
> + u8 upiu_flags;
>
> down_read(>clk_scaling_lock);
>
> --
> 2.17.1
[PATCH v1 2/2] arm64: dts: exynos: keep LDO12 always-on
LDO12 on exynos7 supply power to VDDQ_UFS20_RESET,
in case this regulator is OFF, UFS host controller
can not send command to UFS device. To keep this supply
ON, set regulator-always-on property for this ldo.
Signed-off-by: Alim Akhtar
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index bb86950032d3..92fecc539c6c 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -194,6 +194,7 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <130>;
regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
};
ldo13_reg: LDO13 {
--
2.17.1
[PATCH v1 1/2] arm64: dts: exynos: Fix silent hang after boot
Once regulators are disabled after kernel boot, on espresso
board silent hang observed because of LDO7 being disabled.
LDO7 actually provide power to CPU cores and non-cpu blocks
circuitries.
Keep this regulator always-on to fix this hang.
Fixes: 9589f7721e16 ("arm64: dts: Add S2MPS15 PMIC node on exynos7-espresso")
Signed-off-by: Alim Akhtar
---
-
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 790f12ca8981..bb86950032d3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -157,6 +157,7 @@
regulator-min-microvolt = <70>;
regulator-max-microvolt = <115>;
regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
};
ldo8_reg: LDO8 {
base-commit: 9e50b94b3eb0d859a2586b5a40d7fd6e5afd9210
--
2.17.1
[PATCH 1/2] arm64: dts: exynos: Fix silent hang after boot
Once regulators are disabled after kernel boot, on espresso
board silent hang observed because of LDO7 being disabled.
LDO7 actually provide power to CPU cores and non-cpu blocks
circuitries.
Keep this regulator always-on to fix this hang.
Fixes: 9589f7721e16 ("arm64: dts: Add S2MPS15 PMIC node on exynos7-espresso")
Signed-off-by: Alim Akhtar
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 790f12ca8981..bb86950032d3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -157,6 +157,7 @@
regulator-min-microvolt = <70>;
regulator-max-microvolt = <115>;
regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
};
ldo8_reg: LDO8 {
base-commit: 9e50b94b3eb0d859a2586b5a40d7fd6e5afd9210
--
2.17.1
[PATCH 2/2] arm64: dts: exynos: keep LDO12 always-on
LDO12 on exynos7 supply power to VDDQ_UFS20_RESET,
in case this regulator is OFF, UFS host controller
can not send command to UFS device. To keep this supply
ON, set regulator-always-on property for this ldo.
Signed-off-by: Alim Akhtar
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index bb86950032d3..92fecc539c6c 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -194,6 +194,7 @@
regulator-min-microvolt = <100>;
regulator-max-microvolt = <130>;
regulator-enable-ramp-delay = <125>;
+ regulator-always-on;
};
ldo13_reg: LDO13 {
--
2.17.1
RE: [PATCH] arm64: dts: exynos: Add minimal bootargs
Hi Krzysztof,
> > > @@ -24,6 +24,7 @@
> > >
> > > chosen {
> > > stdout-path = _2;
> > > + bootargs = "earlycon=exynos4210,0x14c3
> > > console=ttySAC0,115200n8";
>
> Hi,
>
> The console is already chosen by stdout-path and earlycon would use it as
> well,
> so no need for the address. It should be just "earlycon" if you want to
> enable it
> unconditionally.
>
Indeed only "earlycon" will do here. Thanks for point this out.
> Also, why did you use different serial for console?
>
Once UART driver gets probed then console changes to ttySAC0. In case I am
using stdout-path only,
after bootconsole is disabled, kernel logs re-start printing from beginning
(which might be expected behaviour?)
[0.012416] printk: console [tty0] enabled
[0.016491] printk: bootconsole [exynos4210] disabled
[0.00] Booting Linux on physical CPU 0x00 [0x410fd032]
[0.00] Linux version 5.8.0-rc3-next-20200703-8-g4af626444f4a-dirty
(alim@alim) (aarch64-linux-gnu-gcc (Linaro GCC 7.4-2019.02) 7.4.1 20181213 [l0
[0.00] Machine model: Samsung Exynos7 Espresso board based on Exynos7
> However the question is, are you sure you want earlycon on every, including
> successful boot? On most of the boards we do not enable by default. If
> developer needs, he can choose it for example via U-Boot "setenv opts
> earlycon".
>
Using U-Boot is not the case always, any bootload can be used to boot the
Linux, currently I am Coreboot.
And 'earlycon' is not setup by default.
As Espresson board is development board, IMO it is ok to keep it enable all the
time, this helps in quickly knowing what going on incase boot fails early.
Let me know if it is ok to keep " console=ttySAC0,115200n8" or shell I just
re-spin with only 'earlycon'? or any other suggestion?
Thanks!
> However it's a development kit so it could be enabled on default...
>
> Best regards,
> Krzysztof
>
> > > };
> > >
> > > memory@4000 {
> > >
> > > base-commit: 9e50b94b3eb0d859a2586b5a40d7fd6e5afd9210
> > > --
> > > 2.17.1
> >
> >
RE: [PATCH] arm64: dts: exynos: Add minimal bootargs
Adding Krzysztof's correct email address.
Sorry about noise.
> -Original Message-
> From: Alim Akhtar
> Sent: 03 July 2020 23:56
> To: r...@kernel.org
> Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> samsung-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> robh...@kernel.org; Alim Akhtar
> Subject: [PATCH] arm64: dts: exynos: Add minimal bootargs
>
> Add minimal bootargs to enable earlycon and console.
> This really useful in case kernel has crashed early in boot process.
>
> Signed-off-by: Alim Akhtar
> ---
> arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> index 790f12ca8981..d7b42d5a3b2d 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
> @@ -24,6 +24,7 @@
>
> chosen {
> stdout-path = _2;
> + bootargs = "earlycon=exynos4210,0x14c3
> console=ttySAC0,115200n8";
> };
>
> memory@4000 {
>
> base-commit: 9e50b94b3eb0d859a2586b5a40d7fd6e5afd9210
> --
> 2.17.1
[PATCH] arm64: dts: exynos: Add minimal bootargs
Add minimal bootargs to enable earlycon and console.
This really useful in case kernel has crashed early in
boot process.
Signed-off-by: Alim Akhtar
---
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 790f12ca8981..d7b42d5a3b2d 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -24,6 +24,7 @@
chosen {
stdout-path = _2;
+ bootargs = "earlycon=exynos4210,0x14c3
console=ttySAC0,115200n8";
};
memory@4000 {
base-commit: 9e50b94b3eb0d859a2586b5a40d7fd6e5afd9210
--
2.17.1
[PATCH v12 1/2] dt-bindings: phy: Document Samsung UFS PHY bindings
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index ..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+properties:
+ "#phy-cells":
+const: 0
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+maxItems: 1
+
+ reg-names:
+items:
+ - const: phy-pma
+
+ clocks:
+items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+ufs_phy: ufs-phy@15571800 {
+compatible = "samsung,exynos7-ufs-phy";
+reg = <0x15571800 0x240>;
+reg-names = "phy-pma";
+samsung,pmu-syscon = <_system_controller>;
+#phy-cells = <0>;
+clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+};
+...
base-commit: aab2003999e78bbf2058dae1e661c44ede1d9766
--
2.17.1
[PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
[Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
Reported-by: kernel test robot
Reviewed-by: Kiwoong Kim
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Tested-by: Paweł Chmiel
---
- Changes V11 -> V12
* Fixed kernel test robot warnings
- Changes V10 -> V11
* Addressed review comments from Vinod
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++
drivers/phy/samsung/phy-samsung-ufs.c | 359 ++
drivers/phy/samsung/phy-samsung-ufs.h | 139 ++
5 files changed, 594 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 19f2e3119343..e20d2fcc9fe7 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index ..c4aab792d30e
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ P
RE: [PATCH v2 4/8] arm64: dts: exynos: Remove DMA controller bus node name to fix dtschema warnings
Hi Krzysztof > -Original Message- > From: Krzysztof Kozlowski > Sent: 02 July 2020 21:22 > To: Thierry Reding ; Uwe Kleine-König koe...@pengutronix.de>; Lee Jones ; Rob Herring > ; Kukjin Kim ; Krzysztof Kozlowski > ; linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- > samsung-...@vger.kernel.org > Cc: Marek Szyprowski ; Bartlomiej Zolnierkiewicz > ; Sylwester Nawrocki ; > Alim Akhtar ; Chanwoo Choi > ; Pankaj Dubey > Subject: [PATCH v2 4/8] arm64: dts: exynos: Remove DMA controller bus node > name to fix dtschema warnings > > There is no need to keep DMA controller nodes under AMBA bus node. > Remove the "amba" node to fix dtschema warnings like: > > amba: $nodename:0: 'amba' does not match '^(bus|soc|axi|ahb|apb)(@[0- > 9a-f]+)?$' > > Signed-off-by: Krzysztof Kozlowski > Reviewed-by: Alim Akhtar > --- > > Changes since v1: > 1. Remove the bus, as suggested by Marek > --- > arch/arm64/boot/dts/exynos/exynos5433.dtsi | 47 +- > arch/arm64/boot/dts/exynos/exynos7.dtsi| 47 +- > 2 files changed, 40 insertions(+), 54 deletions(-)
RE: [PATCH v2 3/8] arm64: dts: exynos: Remove generic arm,armv8-pmuv3 compatible
HI Krzysztof
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: 02 July 2020 21:22
> To: Thierry Reding ; Uwe Kleine-König koe...@pengutronix.de>; Lee Jones ; Rob Herring
> ; Kukjin Kim ; Krzysztof Kozlowski
> ; linux-...@vger.kernel.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> samsung-...@vger.kernel.org
> Cc: Marek Szyprowski ; Bartlomiej Zolnierkiewicz
> ; Sylwester Nawrocki ;
> Alim Akhtar ; Chanwoo Choi
> ; Pankaj Dubey
> Subject: [PATCH v2 3/8] arm64: dts: exynos: Remove generic arm,armv8-pmuv3
> compatible
>
> The ARM PMU node is described enough with first compatible so remove the
> arm,armv8-pmuv3 to fix dtschema warnings like:
>
> arm-pmu: compatible: Additional items are not allowed ('arm,armv8-pmuv3'
> was unexpected)
> arm-pmu: compatible: ['arm,cortex-a57-pmu', 'arm,armv8-pmuv3'] is too long
>
> Signed-off-by: Krzysztof Kozlowski
>
Reviewed-by: Alim Akhtar
> ---
>
> Changes since v1:
> 1. None
>
> Not tested although no effect expected.
> ---
Booted on exynos7 board and see arm PMU still gets registered
Tested-by: Alim Akhtar
RE: [PATCH v2 2/8] arm64: dts: exynos: Describe PWM interrupts on Exynos7
Hi Krzysztof,
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: 02 July 2020 21:22
> To: Thierry Reding ; Uwe Kleine-König koe...@pengutronix.de>; Lee Jones ; Rob Herring
> ; Kukjin Kim ; Krzysztof Kozlowski
> ; linux-...@vger.kernel.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> samsung-...@vger.kernel.org
> Cc: Marek Szyprowski ; Bartlomiej Zolnierkiewicz
> ; Sylwester Nawrocki ;
> Alim Akhtar ; Chanwoo Choi
> ; Pankaj Dubey
> Subject: [PATCH v2 2/8] arm64: dts: exynos: Describe PWM interrupts on
> Exynos7
>
> Add interrupts property to PWM node on Exynos7 to describe the hardware
> fully. No functional change as the interrupts are not used by drivers.
>
> Signed-off-by: Krzysztof Kozlowski
>
Reviewed-by: Alim Akhtar
> ---
>
> Changes since v1:
> 1. Correct the interrupts, change message.
>
> Not tested
> ---
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index f590891efe25..709742b98c9c 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -581,6 +581,11 @@
> pwm: pwm@136c {
> compatible = "samsung,exynos4210-pwm";
> reg = <0x136c 0x100>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ;
> samsung,pwm-outputs = <0>, <1>, <2>, <3>;
> #pwm-cells = <3>;
> clocks = <_peric0 PCLK_PWM>;
> --
> 2.17.1
[PATCH v11 1/2] dt-bindings: phy: Document Samsung UFS PHY bindings
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index ..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+properties:
+ "#phy-cells":
+const: 0
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+maxItems: 1
+
+ reg-names:
+items:
+ - const: phy-pma
+
+ clocks:
+items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+ufs_phy: ufs-phy@15571800 {
+compatible = "samsung,exynos7-ufs-phy";
+reg = <0x15571800 0x240>;
+reg-names = "phy-pma";
+samsung,pmu-syscon = <_system_controller>;
+#phy-cells = <0>;
+clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+};
+...
base-commit: aab2003999e78bbf2058dae1e661c44ede1d9766
--
2.17.1
[PATCH v11 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
[Robot: -Wmissing-prototypes]
Reported-by: kernel test robot
Reviewed-by: Kiwoong Kim
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Tested-by: Paweł Chmiel
---
Change log V10 -> V11
* Addressed review comments from Vinod.
* minor clean up
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 86 +++
drivers/phy/samsung/phy-samsung-ufs.c | 357 ++
drivers/phy/samsung/phy-samsung-ufs.h | 139 ++
5 files changed, 592 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 19f2e3119343..e20d2fcc9fe7 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index ..c4aab792d30e
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_
RE: [RESEND PATCH v10 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
Hi Vinod
> -Original Message-
> From: Vinod Koul
> Sent: 01 July 2020 12:23
> To: Alim Akhtar
> Cc: robh...@kernel.org; k...@kernel.org; kwmad@samsung.com;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; linux-samsung-...@vger.kernel.org; kis...@ti.com
> Subject: Re: [RESEND PATCH v10 2/2] phy: samsung-ufs: add UFS PHY driver
for
> samsung SoC
>
> Hi Alim,
>
> On 25-06-20, 05:26, Alim Akhtar wrote:
>
> > +int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
>
> static ?
>
Sure, already got warning email from Kobot. Will fix this.
> > +{
> > + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> > + const unsigned int timeout_us = 10;
> > + const unsigned int sleep_us = 10;
> > + u32 val;
> > + int err;
> > +
> > + err = readl_poll_timeout(
> > + ufs_phy->reg_pma +
> PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
> > + val, (val & PHY_PLL_LOCK_BIT), sleep_us,
timeout_us);
> > + if (err) {
> > + dev_err(ufs_phy->dev,
> > + "failed to get phy pll lock acquisition %d\n", err);
> > + goto out;
> > + }
> > +
> > + err = readl_poll_timeout(
> > + ufs_phy->reg_pma +
> PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
> > + val, (val & PHY_CDR_LOCK_BIT), sleep_us,
timeout_us);
> > + if (err) {
> > + dev_err(ufs_phy->dev,
> > + "failed to get phy cdr lock acquisition %d\n", err);
> > + goto out;
>
> this one can be dropped
>
Sure, will update.
> > + }
> > +
> > +out:
> > + return err;
> > +}
> > +
> > +int samsung_ufs_phy_calibrate(struct phy *phy)
>
> static?
>
Will fix
> > +{
> > + struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> > + struct samsung_ufs_phy_cfg **cfgs = ufs_phy->cfg;
> > + const struct samsung_ufs_phy_cfg *cfg;
> > + int i;
> > + int err = 0;
>
> err before i would make it look better
>
sure
> > +
> > + if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
> > +ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
> > + dev_err(ufs_phy->dev, "invalid phy config index %d\n",
> > + ufs_phy-
> >ufs_phy_state);
>
> single line now?
>
Yes,
> > + return -EINVAL;
> > + }
> > +
> > + if (ufs_phy->is_pre_init)
> > + ufs_phy->is_pre_init = false;
>
> that sounds bit strange, you clear it if set? Can you explain what is
going on
> here, and add comments
>
Hmm, yes right, this is not needed, let me change this and will add a
comment.
The idea here is, before exiting phy calibration in one state, change the
state to next state,
So that when next time calibrate() is called, it will do the phy settings
for the next stage.
> > +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy
> > +*phy) {
> > + int ret = 0;
>
> superfluous init
>
ok
> > +
> > + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> > + if (IS_ERR(phy->tx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> > + goto out;
> > + }
> > +
> > + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n",
> > + __func__, ret);
> > + goto out;
> > + }
> > + ret = clk_prepare_enable(phy->rx0_symbol_clk);
> > + if (ret) {
> > + dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n",
> > + __func__, ret);
>
> so we keep tx0_symbol_clk enabled when bailing out?
>
Will add a clk_disable_unprepare()
> > +
RE: [RFC PATCH v3 0/5] scsi: ufs: Add Host Performance Booster Support
> -Original Message- > From: Avri Altman > Sent: 30 June 2020 12:09 > To: daejun7.p...@samsung.com; Bean Huo ; > j...@linux.ibm.com; martin.peter...@oracle.com; asuto...@codeaurora.org; > stanley@mediatek.com; c...@codeaurora.org; bvanass...@acm.org; > tomas.wink...@intel.com; ALIM AKHTAR > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org; Sang-yoon Oh > ; Sung-Jun Park > ; yongmyung lee > ; Jinyoung CHOI ; > Adel Choi ; BoRam Shin > > Subject: RE: [RFC PATCH v3 0/5] scsi: ufs: Add Host Performance Booster > Support > > Hi, > > > > > Hi Bean, > > > On Mon, 2020-06-29 at 15:15 +0900, Daejun Park wrote: > > > > > Seems you intentionally ignored to give you comments on my > > > > > suggestion. > > > > > let me provide the reason. > > > > > > > > Sorry! I replied to your comment ( > > > > https://protect2.fireeye.com/url?k=be575021-e3854728-be56db6e- > > 0cc47a31cdf8- > > > 6c7d0e1e42762b92=1=https%3A%2F%2Flkml.org%2Flkml%2F2020%2F6% > > 2F15%2F1492), > > > > but you didn't reply on that. I thought you agreed because you > > > > didn't send any more comments. > > > > > > > > > > > > > Before submitting your next version patch, please check your L2P > > > > > mapping HPB reqeust submission logical algorithem. I have did > > > > > > > > We are also reviewing the code that you submitted before. > > > > It seems to be a performance improvement as it sends a map request > > > > directly. > > > > > > > > > performance comparison testing on 4KB, there are about 13% > > > > > performance drop. Also the hit count is lower. I don't know if > > > > > this is related to > > > > > > > > It is interesting that there is actually a performance improvement. > > > > Could you share the test environment, please? However, I think > > > > stability is important to HPB driver. We have tested our method > > > > with the real products and the HPB 1.0 driver is based on that. > > > > > > I just run fio benchmark tool with --rw=randread, --bs=4kb, -- > > > size=8G/10G/64G/100G. and see what performance diff with the direct > > > submission approach. > > > > Thanks! > > > > > > After this patch, your approach can be done as an incremental patch? > > > > I would > > > > like to test the patch that you submitted and verify it. > > > > > > > > > your current work queue scheduling, since you didn't add the > > > > > timer for each HPB request. > > > > > > > > > > Taking into consideration of the HPB 2.0, can we submit the HPB > > > write request to the SCSI layer? if not, it will be a direct submission > > > way. > > > why not directly use direct way? or maybe you have a more advisable > > > approach to work around this. would you please share with us. > > > appreciate. > > > > I am considering a direct submission way for the next version. > > We will implement the write buffer command of HPB 2.0, after patching > > HPB 1.0. > > > > As for the direct submission of HPB releated command including HPB > > write buffer, I think we'd better discuss the right approach in depth > > before moving on to the next step. > I vote to stay with the current implementation because: > 1) Bean is probably right about 2.0, but it's out of scope for now - > there is a long way to go before we'll need to worry about it > 2) For now, we should focus on the functional flows. > Performance issues, should such issues indeed exists, can be dealt with > later. > And, > 3) The current code base is running in production for more than 3 years now. > I am not so eager to dump a robust, well debugged code unless it > absolutely > necessary. > Avri and Bean, I think this is good approach to take, and let us add incremental patches to add future specification enhancements. > Thanks, > Avri >
RE: [PATCH 1/4] arm64: dts: exynos: Add PWM interrupts on Exynos7
Hi Krzysztof,
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: 30 June 2020 02:15
> To: Rob Herring ; Kukjin Kim ;
> Krzysztof Kozlowski ; devicet...@vger.kernel.org;
linux-arm-
> ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: Marek Szyprowski ; Bartlomiej Zolnierkiewicz
> ; Sylwester Nawrocki ;
> Alim Akhtar ; Chanwoo Choi
> ; Pankaj Dubey
> Subject: [PATCH 1/4] arm64: dts: exynos: Add PWM interrupts on Exynos7
>
> Add required interrupts to PWM node on Exynos7. This fixes DT schema
> warning:
>
> pwm@136c: 'interrupts' is a required property
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Not tested
> ---
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index f590891efe25..523547b3d539 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -581,6 +581,11 @@
> pwm: pwm@136c {
> compatible = "samsung,exynos4210-pwm";
> reg = <0x136c 0x100>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ;
PWM IRQs are from 449 ~ 453 for PWM[0] ~ PWM[4] on this SoC.
444 ~ 447 are for HSI2C and 448 is for ADC.
Please see the exynos7.dtsi
Also drivers/pwm/pwm-samsung.c does not uses interrupt at all, still we need
interrupts property to be added here?
> samsung,pwm-outputs = <0>, <1>, <2>, <3>;
> #pwm-cells = <3>;
> clocks = <_peric0 PCLK_PWM>;
> --
> 2.17.1
RE: [PATCH] scsi: ufs: ufs-exynos: Remove an unnecessary NULL check
Hi Dan, > -Original Message- > From: Dan Carpenter > On Sat, Jun 27, 2020 at 10:51:44PM +0530, Alim Akhtar wrote: > > Hi Dan > > > > > -Original Message- > > > The "head" pointer can't be NULL because it points to an address in the > > middle > > > of a ufs_hba struct. Looking at this code, probably someone would wonder > > if > > > the intent was to check whether "hba" is NULL, but "hba" > > > isn't NULL and the check can just be removed. > > > > > > Signed-off-by: Dan Carpenter > > > --- > > Please add Fixes: tag > > With that > > Acked-by: Alim Akhtar > > It's not a bug fix it's just a cleanup. > Acked-by: Alim Akhtar Thanks! > regards, > dan carpenter
RE: [PATCH] scsi: ufs: ufs-exynos: Remove an unnecessary NULL check
Hi Dan
> -Original Message-
> The "head" pointer can't be NULL because it points to an address in the
middle
> of a ufs_hba struct. Looking at this code, probably someone would wonder
if
> the intent was to check whether "hba" is NULL, but "hba"
> isn't NULL and the check can just be removed.
>
> Signed-off-by: Dan Carpenter
> ---
Please add Fixes: tag
With that
Acked-by: Alim Akhtar
Thanks!
> drivers/scsi/ufs/ufs-exynos.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index
> 16544b3dad47..802f7de626e8 100644
> --- a/drivers/scsi/ufs/ufs-exynos.c
> +++ b/drivers/scsi/ufs/ufs-exynos.c
> @@ -264,7 +264,7 @@ static int exynos_ufs_get_clk_info(struct exynos_ufs
> *ufs)
> u8 div = 0;
> int ret = 0;
>
> - if (!head || list_empty(head))
> + if (list_empty(head))
> goto out;
>
> list_for_each_entry(clki, head, list) {
> --
> 2.27.0
[PATCH -next] scsi: ufs: ufs-exynos: Fix build warning
While building for x86_64 allmodconfig, below warning reported
WARNING: modpost: missing MODULE_LICENSE() in drivers/scsi/ufs/ufs-exynos.o
Add the missing license/author/description tags.
Fixes: 55f4b1f73631 ("scsi: ufs: ufs-exynos: Add UFS host support for Exynos
SoCs")
Reported-by: Stephen Rothwell
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufs-exynos.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 16544b3dad47..b0796066a449 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -1290,3 +1290,8 @@ static struct platform_driver exynos_ufs_pltform = {
},
};
module_platform_driver(exynos_ufs_pltform);
+
+MODULE_AUTHOR("Alim Akhtar ");
+MODULE_AUTHOR("Seungwon Jeon ");
+MODULE_DESCRIPTION("Exynos UFS HCI Driver");
+MODULE_LICENSE("GPL v2");
base-commit: 3f9437c6234d95d96967f1b438a4fb71b6be254d
--
2.17.1
RE: linux-next: build warning after merge of the scsi tree
Hi Stephen
> -Original Message-
> From: Stephen Rothwell
> Sent: 25 June 2020 09:11
> To: James Bottomley
> Cc: Linux Next Mailing List ; Linux Kernel
Mailing
> List ; Alim Akhtar
;
> Martin K. Petersen ; Seungwon Jeon
>
> Subject: linux-next: build warning after merge of the scsi tree
>
> Hi all,
>
> After merging the scsi tree, today's linux-next build (x86_64
> allmodconfig) produced this warning:
>
> WARNING: modpost: missing MODULE_LICENSE() in drivers/scsi/ufs/ufs-
> exynos.o
>
Sorry about that, will send a fix patch soon.
> Introduced by commit
>
> 55f4b1f73631 ("scsi: ufs: ufs-exynos: Add UFS host support for Exynos
SoCs")
>
> (not sure why I missed this earlier, sorry)
>
> --
> Cheers,
> Stephen Rothwell
[RESEND PATCH v10] dt-bindings: ufs: Add bindings for Samsung ufs host
This patch adds DT bindings for Samsung ufs hci
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
---
Hi Rob
This is just a rebase on your's dt/next
This patch was part of [1]
[1] https://lkml.org/lkml/2020/5/27/1697
.../bindings/ufs/samsung,exynos-ufs.yaml | 89 +++
1 file changed, 89 insertions(+)
create mode 100644
Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
new file mode 100644
index ..38193975c9f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS host controller Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+description: |
+ Each Samsung UFS host controller instance should have its own node.
+ This binding define Samsung specific binding other then what is used
+ in the common ufshcd bindings
+ [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+
+properties:
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs
+
+ reg:
+items:
+ - description: HCI register
+ - description: vendor specific register
+ - description: unipro register
+ - description: UFS protector register
+
+ reg-names:
+items:
+ - const: hci
+ - const: vs_hci
+ - const: unipro
+ - const: ufsp
+
+ clocks:
+items:
+ - description: ufs link core clock
+ - description: unipro main clock
+
+ clock-names:
+items:
+ - const: core_clk
+ - const: sclk_unipro_main
+
+ interrupts:
+maxItems: 1
+
+ phys:
+maxItems: 1
+
+ phy-names:
+const: ufs-phy
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - phys
+ - phy-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+ufs: ufs@1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = ;
+ clocks = <_fsys1 ACLK_UFS20_LINK>,
+<_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rst_n _refclk_out>;
+ phys = <_phy>;
+ phy-names = "ufs-phy";
+};
+...
base-commit: b3a9e3b9622ae10064826dccb4f7a52bd88c7407
prerequisite-patch-id: e0425bbe8f2aff3882b728a0caf0218b6b3e9b6e
prerequisite-patch-id: c8c8502c512f9d6fdaf7d30e54dde3e68c3d855b
prerequisite-patch-id: 8505df2fd70632150b50543cadc6fd7dd42d191c
prerequisite-patch-id: 1a9701ab83425940c8aacb76737edb57ab815e47
prerequisite-patch-id: 7881e0b87f1f04f657d9e6d450fb5231ad6ffa1a
prerequisite-patch-id: 01dbc0e550e3fcad6e525e7e3183f9f0312e8496
prerequisite-patch-id: ad801812fff960abab3f27d2c7383be9fd9aa439
prerequisite-patch-id: 65474c9540e6dc749d30223897de1f486d6b3843
prerequisite-patch-id: 64b58cd4c5ecfacf28fc20c31a6617092a1e1931
prerequisite-patch-id: 9bcdd2995fd3f6361f8d5e89c56645058ac9ff96
--
2.17.1
RE: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
Hi Vinod, > -Original Message- > From: Vinod Koul > Sent: 24 June 2020 23:00 > To: Alim Akhtar > Cc: 'Kishon Vijay Abraham I' ; r...@kernel.org; > k...@kernel.org; linux-samsung-...@vger.kernel.org; avri.alt...@wdc.com; > stanley@mediatek.com; linux-s...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; c...@codeaurora.org; devicet...@vger.kernel.org; > kwmad@samsung.com; linux-kernel@vger.kernel.org; 'Martin K. Petersen' > > Subject: Re: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI > > Hi Alim, > > On 24-06-20, 22:27, Alim Akhtar wrote: > > > > > Sure, will re-send this series. > > > > > > But patches have not been sent right, pls send and me/Kishon will > > > review > > > > > Thanks for your kind attention on this series. As per [0] comment from > > Kishon, patch 7/10 [1] and probably 6/10 [2] should have been Applied > > after > > 5.8-rc1 was tagged. > > And that is something I am trying atm, but I dont have patches in my mailbox, so > would you be kind enough to resend me these patches after rebasing to phy- > next, also do add acks/reviews collected in previous posts. > > I dont think I have seen resend, or maybe I wasnt cced > Just noticed you were not CCed. I have sent those two patches. https://patchwork.kernel.org/patch/11624571/ https://patchwork.kernel.org/patch/11624569/ PTAL, Thanks, > > -- > ~Vinod
[RESEND PATCH v10 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Reviewed-by: Kiwoong Kim
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
Cc: Vinod Koul
Tested-by: Paweł Chmiel
---
This is just a rebase on phy-next tree.
This patch was part of a series [1] which adds ufs
host controller driver.
[1] https://lkml.org/lkml/2020/5/27/1697
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++
drivers/phy/samsung/phy-samsung-ufs.c | 380 ++
drivers/phy/samsung/phy-samsung-ufs.h | 143 ++
5 files changed, 619 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 9e483d1fdaf2..fc1e3c17f842 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index ..c4aab792d30e
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG
[RESEND PATCH v10 1/2] dt-bindings: phy: Document Samsung UFS PHY bindings
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
This is just a rebase on phy-next, was part of series [1]
which adds ufs host contoller driver.
[1] https://lkml.org/lkml/2020/5/27/1697
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index ..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+properties:
+ "#phy-cells":
+const: 0
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+maxItems: 1
+
+ reg-names:
+items:
+ - const: phy-pma
+
+ clocks:
+items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+ufs_phy: ufs-phy@15571800 {
+compatible = "samsung,exynos7-ufs-phy";
+reg = <0x15571800 0x240>;
+reg-names = "phy-pma";
+samsung,pmu-syscon = <_system_controller>;
+#phy-cells = <0>;
+clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+};
+...
--
2.17.1
RE: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
Hi Vinod > -Original Message- > From: Vinod Koul > Sent: 24 June 2020 15:51 > To: Alim Akhtar > Cc: 'Kishon Vijay Abraham I' ; r...@kernel.org; > k...@kernel.org; linux-samsung-...@vger.kernel.org; avri.alt...@wdc.com; > stanley@mediatek.com; linux-s...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; c...@codeaurora.org; devicet...@vger.kernel.org; > kwmad@samsung.com; linux-kernel@vger.kernel.org; 'Martin K. Petersen' > > Subject: Re: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI > > On 20-06-20, 07:29, Alim Akhtar wrote: > > Hi Kishon, > > > > > -Original Message- > > > From: Alim Akhtar > > > Sent: 11 June 2020 20:49 > > > To: 'Kishon Vijay Abraham I' ; 'Martin K. Petersen' > > > > >> > > > > >> Applied [1,2,3,4,5,9] to 5.9/scsi-queue. The series won't show > > > > >> up in my > > > > > public > > > > >> tree until shortly after -rc1 is released. > > > > >> > > > > > Thanks Martin, > > > > > Hi Rob and Kishon/Vinod > > > > > Can you please pickup dt-bindings and PHY driver respectively? > > > > > > > > You might have CC'ed me only for the PHY patch. I don't have the > > > > dt-bindings in my inbox. Care to re-send what's missing again? > > > > This will be merged after -rc1 is tagged. > > > > > > > > -rc1 is out, I do not see phy driver patch in your tree[1] yet, let me know if I am > looking into right tree. > > [1] -> git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git > > Right tree > > > > Thanks! > > > > > Sure, will re-send this series. > > But patches have not been sent right, pls send and me/Kishon will review > Thanks for your kind attention on this series. As per [0] comment from Kishon, patch 7/10 [1] and probably 6/10 [2] should have been Applied after 5.8-rc1 was tagged. I have already send and re-send V10 of this series. Kishon has already reviewed and provided comments and I have addressed them as well. These patches already have and Reviewed-by, Tested-by tags. Let me know if something more needs to be done from my side. [0] https://lkml.org/lkml/2020/6/7/410 [1] https://lkml.org/lkml/2020/5/27/1705 [2] https://lkml.org/lkml/2020/5/27/1701 Thanks! > Thanks > -- > ~Vinod
RE: [PATCH] serial: samsung: fix spelling mistake
Hi Tamseel, > -Original Message- > From: Tamseel Shams > Sent: 17 June 2020 16:29 > To: kg...@kernel.org; k...@kernel.org; gre...@linuxfoundation.org; > jsl...@suse.com > Cc: linux-arm-ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org; > linux-ser...@vger.kernel.org; linux-kernel@vger.kernel.org; > alim.akh...@samsung.com; Tamseel Shams > Subject: [PATCH] serial: samsung: fix spelling mistake > > There is a spelling mistake in a comment. Fix it. > > Signed-off-by: Tamseel Shams > --- Reviewed-by: Alim Akhtar > drivers/tty/serial/samsung_tty.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/samsung_tty.c > b/drivers/tty/serial/samsung_tty.c > index 6ef614d8648c..050a47fecdef 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -6,7 +6,7 @@ > * http://armlinux.simtec.co.uk/ > */ > > -/* Hote on 2410 error handling > +/* Note on 2410 error handling > * > * The s3c2410 manual has a love/hate affair with the contents of the > * UERSTAT register in the UART blocks, and keeps marking some of the > -- > 2.17.1
[PATCH -next] scsi: ufs: allow exynos ufs driver to build as module
Allow Exynos UFS driver to build as a module.
This patch fix the below build issue reported by
kernel build robot.
drivers/scsi/ufs/ufs-exynos.o: in function `exynos_ufs_probe':
drivers/scsi/ufs/ufs-exynos.c:1231: undefined reference to `ufshcd_pltfrm_init'
drivers/scsi/ufs/ufs-exynos.o: in function `exynos_ufs_pre_pwr_mode':
drivers/scsi/ufs/ufs-exynos.c:635: undefined reference to
`ufshcd_get_pwr_dev_param'
drivers/scsi/ufs/ufs-exynos.o:undefined reference to `ufshcd_pltfrm_shutdown'
drivers/scsi/ufs/ufs-exynos.o:undefined reference to `ufshcd_pltfrm_suspend'
drivers/scsi/ufs/ufs-exynos.o:undefined reference to `ufshcd_pltfrm_resume'
drivers/scsi/ufs/ufs-exynos.o:undefined reference to
`ufshcd_pltfrm_runtime_suspend'
drivers/scsi/ufs/ufs-exynos.o:undefined reference to
`ufshcd_pltfrm_runtime_resume'
drivers/scsi/ufs/ufs-exynos.o:undefined reference to
`ufshcd_pltfrm_runtime_idle'
Fixes: 55f4b1f73631 ("scsi: ufs: ufs-exynos: Add UFS host support for Exynos
SoCs")
Reported-by: kernel test robot
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 8cd90262784d..3188a50dfb51 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -162,7 +162,7 @@ config SCSI_UFS_BSG
If unsure, say N.
config SCSI_UFS_EXYNOS
- bool "EXYNOS specific hooks to UFS controller platform driver"
+ tristate "EXYNOS specific hooks to UFS controller platform driver"
depends on SCSI_UFSHCD_PLATFORM && (ARCH_EXYNOS || COMPILE_TEST)
select PHY_SAMSUNG_UFS
help
base-commit: ce2cc8efd7a40cbd17841add878cb691d0ce0bba
prerequisite-patch-id: c12207f678b32e29496ec7e324425c8f49422a2c
prerequisite-patch-id: 8263330366e8c180c0ab9f76fbd4dbbcf0bee427
prerequisite-patch-id: 7456972c04fc1a76c922196aecd98e9ed17cc6eb
--
2.17.1
RE: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
Hi Kishon, > -Original Message- > From: Alim Akhtar > Sent: 11 June 2020 20:49 > To: 'Kishon Vijay Abraham I' ; 'Martin K. Petersen' > > >> > > >> Applied [1,2,3,4,5,9] to 5.9/scsi-queue. The series won't show up > > >> in my > > > public > > >> tree until shortly after -rc1 is released. > > >> > > > Thanks Martin, > > > Hi Rob and Kishon/Vinod > > > Can you please pickup dt-bindings and PHY driver respectively? > > > > You might have CC'ed me only for the PHY patch. I don't have the > > dt-bindings in my inbox. Care to re-send what's missing again? This > > will be merged after -rc1 is tagged. > > -rc1 is out, I do not see phy driver patch in your tree[1] yet, let me know if I am looking into right tree. [1] -> git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git Thanks! > Sure, will re-send this series. > > > Thanks > > Kishon
Re: [RFC PATCH v2 2/5] scsi: ufs: Add UFS-feature layer
Hi Bean, On Wed, Jun 17, 2020 at 3:12 PM Bean Huo wrote: > > > > HPB1.0 isn't part of ufs3.1, but published only later. > > > Allowing earlier versions will required to quirk the descriptor > > > sizes. > > > I see Bean's point here, but I vote for adding it in a single > > > quirk, when the time comes. > > > > > > > I second Avri here, older devices need a quirk to handle, let do that > > as a separate patch. > > > Thanks, > > > Avri > > > > > > what is useful point of adding a quirk for this? > > From the customer side piont, they just get our FW image, and then do > FFU. If adding a quirk here, that means they also need to change UFS > driver. Also, you expand the qurik structure. > > > from cambridge dictionary: > Qurik: > an unusual habit or part of someone's personality, or something > that > is strange and unexpected. > > HPB feature is unexpected?? > > > please tell me the useful point of adding a Quirk. > The point is not about adding a quirk per say, it's about doing that as a separate patch so that we know which device/ features are added and why it is added. Please understand there is no denial about your proposal or thought. Thanks!! > Bean > > > -- Regards, Alim
Re: [PATCH][next] scsi: ufs: ufs-exynos: fix spelling mistake "pa_granularty" -> "pa_granularity"
On Wed, Jun 17, 2020 at 2:19 PM Colin King wrote:
>
> From: Colin Ian King
>
> There is a spelling mistake in a dev_warn message. Fix it.
>
> Signed-off-by: Colin Ian King
> ---
Thanks Colin,
Reviewed-by: Alim Akhtar
> drivers/scsi/ufs/ufs-exynos.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
> index 440f2af83d9c..0a9e99084f2a 100644
> --- a/drivers/scsi/ufs/ufs-exynos.c
> +++ b/drivers/scsi/ufs/ufs-exynos.c
> @@ -883,7 +883,7 @@ static int exynos_ufs_post_link(struct ufs_hba *hba)
> if (attr->pa_granularity < 1 || attr->pa_granularity > 6) {
> /* Valid range for granularity: 1 ~ 6 */
> dev_warn(hba->dev,
> - "%s: pa_granularty %d is invalid, assuming
> backwards compatibility\n",
> + "%s: pa_granularity %d is invalid, assuming
> backwards compatibility\n",
> __func__,
> attr->pa_granularity);
> attr->pa_granularity = 6;
> --
> 2.27.0.rc0
>
--
Regards,
Alim
Re: [RFC PATCH v2 2/5] scsi: ufs: Add UFS-feature layer
On Wed, Jun 17, 2020 at 12:27 PM Avri Altman wrote:
>
> >
> > Hi, Bean
> > >
> > > On Mon, 2020-06-15 at 16:23 +0900, Daejun Park wrote:
> > > > +void ufsf_scan_features(struct ufs_hba *hba)
> > > > +{
> > > > + int ret;
> > > > +
> > > > + init_waitqueue_head(>ufsf.sdev_wait);
> > > > + atomic_set(>ufsf.slave_conf_cnt, 0);
> > > > +
> > > > + if (hba->dev_info.wspecversion >= HPB_SUPPORTED_VERSION &&
> > > > + (hba->dev_info.b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT))
> > >
> > > How about removing this check "(hba->dev_info.wspecversion >=
> > > HPB_SUPPORTED_VERSION" since ufs with lower version than v3.1 can add
> > > HPB feature by FFU,
> > > if (hba->dev_info.b_ufs_feature_sup _FEATURE_SUPPORT_HPB_BIT) is
> > > enough.
> > OK, changing it seems no problem. But I want to know what other people
> > think
> > about this version checking code.
> HPB1.0 isn't part of ufs3.1, but published only later.
> Allowing earlier versions will required to quirk the descriptor sizes.
> I see Bean's point here, but I vote for adding it in a single quirk, when the
> time comes.
>
I second Avri here, older devices need a quirk to handle, let do that
as a separate patch.
> Thanks,
> Avri
--
Regards,
Alim
RE: [RESEND PATCH v10 10/10] arm64: dts: Add node for ufs exynos7
> On Sat, Jun 13, 2020 at 08:17:06AM +0530, Alim Akhtar wrote: > > Adding dt node foe UFS and UFS-PHY for exynos7 SoC. > > > > Signed-off-by: Alim Akhtar > > Tested-by: Paweł Chmiel > > --- > > .../boot/dts/exynos/exynos7-espresso.dts | 4 ++ > > arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 ++- > > 2 files changed, 45 insertions(+), 2 deletions(-) > > > > This is already applied and in the linux-next. Don't resend applied patches. > Sorry Krzysztof, did not realized that this was already landed in Linux-next, your point taken. > Best regards, > Krzysztof
[RESEND PATCH v10 04/10] scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk
Some UFS host controllers like Exynos uses granularities of PRDT length and
offset as bytes, whereas others uses actual segment count.
Reviewed-by: Avri Altman
Signed-off-by: Kiwoong Kim
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 30 +++---
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ee30ed6cc805..ba093d0d0942 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2151,8 +2151,14 @@ static int ufshcd_map_sg(struct ufs_hba *hba, struct
ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16)sg_segments);
+
+ if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -3500,11 +3506,21 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
- cpu_to_le16(response_offset >> 2);
- utrdlp[i].prd_table_offset = cpu_to_le16(prdt_offset >> 2);
- utrdlp[i].response_upiu_length =
- cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset >> 2);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset >> 2);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
ufshcd_init_lrb(hba, >lrb[i], i);
}
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index f8d08cb9caf7..a9b9ace9fc72 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -535,6 +535,12 @@ enum ufshcd_quirks {
* enabled via HCE register.
*/
UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
+
+ /*
+* This quirk needs to be enabled if the host controller regards
+* resolution of the values of PRDTO and PRDTL in UTRD as byte.
+*/
+ UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
};
enum ufshcd_caps {
--
2.17.1
[RESEND PATCH v10 02/10] scsi: ufs: add quirk to disallow reset of interrupt aggregation
Some host controllers support interrupt aggregation but don't allow
resetting counter and timer in software.
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 3 ++-
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 3655b88fc862..0e9704da58bd 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -4884,7 +4884,8 @@ static irqreturn_t ufshcd_transfer_req_compl(struct
ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 071f0edf3f64..53096642f9a8 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -523,6 +523,12 @@ enum ufshcd_quirks {
* Clear handling for transfer/task request list is just opposite.
*/
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR= 1 << 6,
+
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
};
enum ufshcd_caps {
--
2.17.1
[RESEND PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
This patch-set introduces UFS (Universal Flash Storage) host controller support for Samsung family SoC. Mostly, it consists of UFS PHY and host specific driver. - Changes since v9 * fixed the review comments by Rob on ufs dt bindings * Addeded Rob's reviwed-by tag on 08/10 patch - Changes since v8 * fixed make dt_binding_check error as pointed by Rob * Addressed review comments from Randy Dunlap - Changes since v7: * fixed review comments from Rob and Kishon * Addeded reviwed-by tags * rebased on top of v5.7-rc4 - Changes since v6: * Addressed review comments from Avri and Christoph * Added Reviewed-by tags of Avri and Can on various patches - Changes since v5: * re-introduce various quicks which was removed because of no driver * consumer of those quirks, initial 4 patches does the same. * Added Reviewed-by tags * rebased on top of v5.7-rc1 * included Kiwoong's patch in this series, which this driver needs - Changes since v4: * Addressed review comments from Avir and Rob * Minor improvment on the ufs phy and ufshc drivers * Added Tested-by from Pawel * Change UFS binding to DT schema format - Changes since v3: * Addressed Kishon's and Avir's review comments * fixed make dt_binding_check error as pointed by Rob - Changes since v2: * fixed build warning by kbuild test robot * Added Reported-by tags - Changes since v1: * fixed make dt_binding_check error as pointed by Rob * Addressed Krzysztof's review comments * Added Reviewed-by tags Note: This series is based on Linux-5.7-rc4 (commit: 0e698dfa2822) Alim Akhtar (9): scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk to disallow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk dt-bindings: phy: Document Samsung UFS PHY bindings phy: samsung-ufs: add UFS PHY driver for samsung SoC dt-bindings: ufs: Add bindings for Samsung ufs host scsi: ufs-exynos: add UFS host support for Exynos SoCs arm64: dts: Add node for ufs exynos7 Kiwoong Kim (1): scsi: ufs: add quirk to fix abnormal ocs fatal error .../bindings/phy/samsung,ufs-phy.yaml | 75 + .../bindings/ufs/samsung,exynos-ufs.yaml | 89 ++ .../boot/dts/exynos/exynos7-espresso.dts |4 + arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 +- drivers/phy/samsung/Kconfig |9 + drivers/phy/samsung/Makefile |1 + drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++ drivers/phy/samsung/phy-samsung-ufs.c | 380 + drivers/phy/samsung/phy-samsung-ufs.h | 143 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos.c | 1292 + drivers/scsi/ufs/ufs-exynos.h | 287 drivers/scsi/ufs/ufshcd.c | 126 +- drivers/scsi/ufs/ufshcd.h | 29 + drivers/scsi/ufs/unipro.h | 33 + 16 files changed, 2596 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml create mode 100644 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h base-commit: 0e698dfa282211e414076f9dc7e83c1c288314fd -- 2.17.1
[RESEND PATCH v10 07/10] phy: samsung-ufs: add UFS PHY driver for samsung SoC
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Reviewed-by: Kiwoong Kim
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
Tested-by: Paweł Chmiel
---
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++
drivers/phy/samsung/phy-samsung-ufs.c | 380 ++
drivers/phy/samsung/phy-samsung-ufs.h | 143 ++
5 files changed, 619 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 9e483d1fdaf2..fc1e3c17f842 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index ..c4aab792d30e
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A)
[RESEND PATCH v10 03/10] scsi: ufs: add quirk to enable host controller without hce
Some host controllers don't support host controller enable via HCE.
Reviewed-by: Can Guo
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 76 +--
drivers/scsi/ufs/ufshcd.h | 6
2 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 0e9704da58bd..ee30ed6cc805 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3534,6 +3534,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, _cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, _cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -4251,7 +4297,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba,
bool can_sleep)
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -4260,7 +4306,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba,
bool can_sleep)
*
* Returns 0 on success, non-zero value on failure
*/
-int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -4308,6 +4354,32 @@ int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+
+int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 53096642f9a8..f8d08cb9caf7 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -529,6 +529,12 @@ enum ufshcd_quirks {
* that the interrupt aggregation timer and counter are reset by s/w.
*/
UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
+
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
};
enum ufshcd_caps {
--
2.17.1
[RESEND PATCH v10 09/10] scsi: ufs-exynos: add UFS host support for Exynos SoCs
This patch introduces Exynos UFS host controller driver, which mainly handles vendor-specific operations including link startup, power mode change and hibernation/unhibernation. Reported-by: kbuild test robot Reported-by: Julia Lawall [robot: drivers/scsi/ufs/ufs-exynos.c:931:8-10: WARNING: possible condition with no effect (if == else) ] Reviewed-by: Kiwoong Kim Reviewed-by: Avri Altman Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar Tested-by: Paweł Chmiel --- drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos.c | 1292 + drivers/scsi/ufs/ufs-exynos.h | 287 drivers/scsi/ufs/unipro.h | 33 + 5 files changed, 1625 insertions(+) create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index e2005aeddc2d..7da886d3c323 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -160,3 +160,15 @@ config SCSI_UFS_BSG Select this if you need a bsg device node for your UFS controller. If unsure, say N. + +config SCSI_UFS_EXYNOS + bool "EXYNOS specific hooks to UFS controller platform driver" + depends on SCSI_UFSHCD_PLATFORM && (ARCH_EXYNOS || COMPILE_TEST) + select PHY_SAMSUNG_UFS + help + This selects the EXYNOS specific additions to UFSHCD platform driver. + UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with + UFS-PHY driver. + + Select this if you have UFS host controller on EXYNOS chipset. + If unsure, say N. diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile index 94c6c5d7334b..f0c5b95ec9cc 100644 --- a/drivers/scsi/ufs/Makefile +++ b/drivers/scsi/ufs/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210. obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_CDNS_PLATFORM) += cdns-pltfrm.o obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o +obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o ufshcd-core-y += ufshcd.o ufs-sysfs.o ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c new file mode 100644 index ..440f2af83d9c --- /dev/null +++ b/drivers/scsi/ufs/ufs-exynos.c @@ -0,0 +1,1292 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UFS Host Controller driver for Exynos specific extensions + * + * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. + * Author: Seungwon Jeon + * Author: Alim Akhtar + * + */ + +#include +#include +#include +#include +#include +#include + +#include "ufshcd.h" +#include "ufshcd-pltfrm.h" +#include "ufshci.h" +#include "unipro.h" + +#include "ufs-exynos.h" + +/* + * Exynos's Vendor specific registers for UFSHCI + */ +#define HCI_TXPRDT_ENTRY_SIZE 0x00 +#define PRDT_PREFECT_ENBIT(31) +#define PRDT_SET_SIZE(x) ((x) & 0x1F) +#define HCI_RXPRDT_ENTRY_SIZE 0x04 +#define HCI_1US_TO_CNT_VAL 0x0C +#define CNT_VAL_1US_MASK 0x3FF +#define HCI_UTRL_NEXUS_TYPE0x40 +#define HCI_UTMRL_NEXUS_TYPE 0x44 +#define HCI_SW_RST 0x50 +#define UFS_LINK_SW_RSTBIT(0) +#define UFS_UNIPRO_SW_RST BIT(1) +#define UFS_SW_RST_MASK(UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST) +#define HCI_DATA_REORDER 0x60 +#define HCI_UNIPRO_APB_CLK_CTRL0x68 +#define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) +#define HCI_AXIDMA_RWDATA_BURST_LEN0x6C +#define HCI_GPIO_OUT 0x70 +#define HCI_ERR_EN_PA_LAYER0x78 +#define HCI_ERR_EN_DL_LAYER0x7C +#define HCI_ERR_EN_N_LAYER 0x80 +#define HCI_ERR_EN_T_LAYER 0x84 +#define HCI_ERR_EN_DME_LAYER 0x88 +#define HCI_CLKSTOP_CTRL 0xB0 +#define REFCLK_STOPBIT(2) +#define UNIPRO_MCLK_STOP BIT(1) +#define UNIPRO_PCLK_STOP BIT(0) +#define CLK_STOP_MASK (REFCLK_STOP |\ +UNIPRO_MCLK_STOP |\ +UNIPRO_PCLK_STOP) +#define HCI_MISC 0xB4 +#define REFCLK_CTRL_EN BIT(7) +#define UNIPRO_PCLK_CTRL_ENBIT(6) +#define UNIPRO_MCLK_CTRL_ENBIT(5) +#define HCI_CORECLK_CTRL_ENBIT(4) +#define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ +UNIPRO_PCLK_CTRL_EN |\ +UNIPRO_MCLK_CTRL_EN) +/* Device fatal error */ +#define DFES_ERR_ENBIT(31) +#define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ +UIC_DATA_LINK_LAYER_ERROR_PA_INIT) +#define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPOR
[RESEND PATCH v10 05/10] scsi: ufs: add quirk to fix abnormal ocs fatal error
From: Kiwoong Kim
Some controller like Exynos determines if FATAL ERROR (0x7)
in OCS field in UTRD occurs for values other than GOOD (0x0)
in STATUS field in response upiu as well as errors that a
host controller can't cover.
This patch is to prevent from reporting command results in
those cases.
Signed-off-by: Kiwoong Kim
Signed-off-by: Alim Akhtar
Reviewed-by: Avri Altman
---
drivers/scsi/ufs/ufshcd.c | 6 ++
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ba093d0d0942..33ebffa8257d 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -4794,6 +4794,12 @@ ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct
ufshcd_lrb *lrbp)
/* overall command status of utrd */
ocs = ufshcd_get_tr_ocs(lrbp);
+ if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
+ if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
+ MASK_RSP_UPIU_RESULT)
+ ocs = OCS_SUCCESS;
+ }
+
switch (ocs) {
case OCS_SUCCESS:
result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index a9b9ace9fc72..e1d09c2c4302 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -541,6 +541,12 @@ enum ufshcd_quirks {
* resolution of the values of PRDTO and PRDTL in UTRD as byte.
*/
UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
+
+ /*
+* This quirk needs to be enabled if the host controller reports
+* OCS FATAL ERROR with device error through sense data
+*/
+ UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
};
enum ufshcd_caps {
--
2.17.1
[RESEND PATCH v10 10/10] arm64: dts: Add node for ufs exynos7
Adding dt node foe UFS and UFS-PHY for exynos7 SoC.
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../boot/dts/exynos/exynos7-espresso.dts | 4 ++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 ++-
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 7af288fa9475..790f12ca8981 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -406,6 +406,10 @@
};
};
+ {
+ status = "okay";
+};
+
_phy {
vbus-supply = <_vbus_reg>;
vbus-boost-supply = <_boost_5v>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 5558045637ac..300ad7326ea8 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -220,9 +220,14 @@
#clock-cells = <1>;
clocks = <_pll>, <_top1 DOUT_ACLK_FSYS1_200>,
<_top1 DOUT_SCLK_MMC0>,
-<_top1 DOUT_SCLK_MMC1>;
+<_top1 DOUT_SCLK_MMC1>,
+<_top1 DOUT_SCLK_UFSUNIPRO20>,
+<_top1 DOUT_SCLK_PHY_FSYS1>,
+<_top1 DOUT_SCLK_PHY_FSYS1_26M>;
clock-names = "fin_pll", "dout_aclk_fsys1_200",
- "dout_sclk_mmc0", "dout_sclk_mmc1";
+ "dout_sclk_mmc0", "dout_sclk_mmc1",
+ "dout_sclk_ufsunipro20",
"dout_sclk_phy_fsys1",
+ "dout_sclk_phy_fsys1_26m";
};
serial_0: serial@1363 {
@@ -601,6 +606,40 @@
};
};
+ ufs: ufs@1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>, /* 0: HCI standard */
+ <0x15570100 0x100>, /* 1: Vendor specificed */
+ <0x15571000 0x200>, /* 2: UNIPRO */
+ <0x15572000 0x300>; /* 3: UFS protector */
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = ;
+ clocks = <_fsys1 ACLK_UFS20_LINK>,
+ <_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ freq-table-hz = <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_rst_n _refclk_out>;
+ phys = <_phy>;
+ phy-names = "ufs-phy";
+ status = "disabled";
+ };
+
+ ufs_phy: ufs-phy@15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <_system_controller>;
+ #phy-cells = <0>;
+ clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+<_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+<_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+<_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+ clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk",
+ "tx0_symbol_clk";
+ };
+
usbdrd_phy: phy@1550 {
compatible = "samsung,exynos7-usbdrd-phy";
reg = <0x1550 0x100>;
--
2.17.1
[RESEND PATCH v10 08/10] dt-bindings: ufs: Add bindings for Samsung ufs host
This patch adds DT bindings for Samsung ufs hci
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
---
.../bindings/ufs/samsung,exynos-ufs.yaml | 89 +++
1 file changed, 89 insertions(+)
create mode 100644
Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
new file mode 100644
index ..38193975c9f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS host controller Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+description: |
+ Each Samsung UFS host controller instance should have its own node.
+ This binding define Samsung specific binding other then what is used
+ in the common ufshcd bindings
+ [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+
+properties:
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs
+
+ reg:
+items:
+ - description: HCI register
+ - description: vendor specific register
+ - description: unipro register
+ - description: UFS protector register
+
+ reg-names:
+items:
+ - const: hci
+ - const: vs_hci
+ - const: unipro
+ - const: ufsp
+
+ clocks:
+items:
+ - description: ufs link core clock
+ - description: unipro main clock
+
+ clock-names:
+items:
+ - const: core_clk
+ - const: sclk_unipro_main
+
+ interrupts:
+maxItems: 1
+
+ phys:
+maxItems: 1
+
+ phy-names:
+const: ufs-phy
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - phys
+ - phy-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+ufs: ufs@1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = ;
+ clocks = <_fsys1 ACLK_UFS20_LINK>,
+<_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rst_n _refclk_out>;
+ phys = <_phy>;
+ phy-names = "ufs-phy";
+};
+...
--
2.17.1
[RESEND PATCH v10 06/10] dt-bindings: phy: Document Samsung UFS PHY bindings
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index ..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+properties:
+ "#phy-cells":
+const: 0
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+maxItems: 1
+
+ reg-names:
+items:
+ - const: phy-pma
+
+ clocks:
+items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+ufs_phy: ufs-phy@15571800 {
+compatible = "samsung,exynos7-ufs-phy";
+reg = <0x15571800 0x240>;
+reg-names = "phy-pma";
+samsung,pmu-syscon = <_system_controller>;
+#phy-cells = <0>;
+clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+};
+...
--
2.17.1
[RESEND PATCH v10 01/10] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
In the right behavior, setting the bit to '0' indicates clear and '1'
indicates no change. If host controller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Reviewed-by: Can Guo
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 11 +--
drivers/scsi/ufs/ufshcd.h | 5 +
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 698e8d20b4ba..3655b88fc862 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -645,7 +645,11 @@ static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb
*lrbp)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
}
/**
@@ -655,7 +659,10 @@ static inline void ufshcd_utrl_clear(struct ufs_hba *hba,
u32 pos)
*/
static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6ffc08ad85f6..071f0edf3f64 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -518,6 +518,11 @@ enum ufshcd_quirks {
* ops (get_ufs_hci_version) to get the correct version.
*/
UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
+
+ /*
+* Clear handling for transfer/task request list is just opposite.
+*/
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR= 1 << 6,
};
enum ufshcd_caps {
--
2.17.1
RE: [PATCH v1 1/2] scsi: ufs: Remove unused field in struct uic_command
Hi Stanley
> -Original Message-
> From: Stanley Chu
> Sent: 12 June 2020 20:40
> To: linux-s...@vger.kernel.org; martin.peter...@oracle.com;
> avri.alt...@wdc.com; alim.akh...@samsung.com; j...@linux.ibm.com;
> asuto...@codeaurora.org
> Cc: bean...@micron.com; c...@codeaurora.org; matthias@gmail.com;
> bvanass...@acm.org; linux-media...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> kuohong.w...@mediatek.com; peter.w...@mediatek.com; chun-
> hung...@mediatek.com; andy.t...@mediatek.com;
> chaotian.j...@mediatek.com; cc.c...@mediatek.com; Stanley Chu
>
> Subject: [PATCH v1 1/2] scsi: ufs: Remove unused field in struct
uic_command
>
> Remove unused field "cmd_active" in struct ufs_command.
>
> Signed-off-by: Stanley Chu
> ---
Reviewed-by: Alim Akhtar
> drivers/scsi/ufs/ufshcd.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index
> bf97d616e597..814e44871ff0 100644
> --- a/drivers/scsi/ufs/ufshcd.h
> +++ b/drivers/scsi/ufs/ufshcd.h
> @@ -88,7 +88,6 @@ enum dev_cmd_type {
> * @argument1: UIC command argument 1
> * @argument2: UIC command argument 2
> * @argument3: UIC command argument 3
> - * @cmd_active: Indicate if UIC command is outstanding
> * @result: UIC command result
> * @done: UIC command completion
> */
> @@ -97,7 +96,6 @@ struct uic_command {
> u32 argument1;
> u32 argument2;
> u32 argument3;
> - int cmd_active;
> int result;
> struct completion done;
> };
> --
> 2.18.0
RE: [PATCH v2 0/2] scsi: ufs: Fix and cleanup device quirks
Hi Stanley, > -Original Message- > From: Stanley Chu > Sent: 12 June 2020 06:56 > To: linux-s...@vger.kernel.org; martin.peter...@oracle.com; > avri.alt...@wdc.com; alim.akh...@samsung.com; j...@linux.ibm.com; > asuto...@codeaurora.org > Cc: bean...@micron.com; c...@codeaurora.org; matthias@gmail.com; > bvanass...@acm.org; linux-media...@lists.infradead.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > kuohong.w...@mediatek.com; peter.w...@mediatek.com; chun- > hung...@mediatek.com; andy.t...@mediatek.com; > chaotian.j...@mediatek.com; cc.c...@mediatek.com; Stanley Chu > > Subject: [PATCH v2 0/2] scsi: ufs: Fix and cleanup device quirks > > Hi, > this series provides some device quirk fixes and cleanups. > > v1 -> v2: > - Sort device quirks in alphabetical order (Alim Akhtar) > > Stanley Chu (2): > scsi: ufs: Add DELAY_BEFORE_LPM quirk for Micron devices > scsi: ufs: Cleanup device vendor name and device quirk table > > drivers/scsi/ufs/ufs_quirks.h | 3 ++- > drivers/scsi/ufs/ufshcd.c | 15 +++ > 2 files changed, 9 insertions(+), 9 deletions(-) > For this series Reviewed-by: Alim Akhtar Thanks! > -- > 2.18.0
RE: [PATCH v3 2/2] scsi: ufs: remove wrapper function ufshcd_setup_clocks()
Hi Bean,
> -Original Message-
> From: Winkler, Tomas
> Sent: 07 June 2020 04:58
> To: Bean Huo ; alim.akh...@samsung.com;
> avri.alt...@wdc.com; asuto...@codeaurora.org; j...@linux.ibm.com;
> martin.peter...@oracle.com; stanley@mediatek.com;
> bean...@micron.com; bvanass...@acm.org; c...@codeaurora.org;
> ebigg...@kernel.org
> Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v3 2/2] scsi: ufs: remove wrapper function
> ufshcd_setup_clocks()
>
>
> >
> > From: Bean Huo
> >
> > The static function ufshcd_setup_clocks() is just a wrapper around
> > __ufshcd_setup_clocks(), remove it. Rename original function wrapped
> > __ufshcd_setup_clocks() to new ufshcd_setup_clocks().
>
> Not sure about this change, we have only one call with skip_ref_clock set
to
> true, the original code actually make sense from readability stand point.
>
I do agree with Tomas, it easy to read and understand the original code.
Thanks
> >
> > Signed-off-by: Bean Huo
> > ---
> > drivers/scsi/ufs/ufshcd.c | 32
> > 1 file changed, 12 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
> > index ec4f55211648..531d0b7878db 100644
> > --- a/drivers/scsi/ufs/ufshcd.c
> > +++ b/drivers/scsi/ufs/ufshcd.c
> > @@ -215,9 +215,7 @@ static int ufshcd_eh_host_reset_handler(struct
> > scsi_cmnd *cmd); static int ufshcd_clear_tm_cmd(struct ufs_hba *hba,
> > int tag); static void ufshcd_hba_exit(struct ufs_hba *hba); static
> > int ufshcd_probe_hba(struct ufs_hba *hba, bool async); -static int
> > __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
> > -bool skip_ref_clk);
> > -static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
> > +static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on, bool
> > +skip_ref_clk);
> > static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); static
> > inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
> > static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); @@
> > -1497,7 +1495,7 @@ static void ufshcd_ungate_work(struct work_struct
> *work)
> > }
> >
> > spin_unlock_irqrestore(hba->host->host_lock, flags);
> > - ufshcd_setup_clocks(hba, true);
> > + ufshcd_setup_clocks(hba, true, false);
> >
> > ufshcd_enable_irq(hba);
> >
> > @@ -1655,10 +1653,10 @@ static void ufshcd_gate_work(struct
> > work_struct
> > *work)
> > ufshcd_disable_irq(hba);
> >
> > if (!ufshcd_is_link_active(hba))
> > - ufshcd_setup_clocks(hba, false);
> > + ufshcd_setup_clocks(hba, false, false);
> > else
> > /* If link is active, device ref_clk can't be switched off
*/
> > - __ufshcd_setup_clocks(hba, false, true);
> > + ufshcd_setup_clocks(hba, false, true);
> >
> > /*
> > * In case you are here to cancel this work the gating state @@ -
> > 7683,8 +7681,7 @@ static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
> > return 0;
> > }
> >
> > -static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
> > - bool skip_ref_clk)
> > +static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on, bool
> > +skip_ref_clk)
> > {
> > int ret = 0;
> > struct ufs_clk_info *clki;
> > @@ -7747,11 +7744,6 @@ static int __ufshcd_setup_clocks(struct ufs_hba
> > *hba, bool on,
> > return ret;
> > }
> >
> > -static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) -{
> > - return __ufshcd_setup_clocks(hba, on, false);
> > -}
> > -
> > static int ufshcd_init_clocks(struct ufs_hba *hba) {
> > int ret = 0;
> > @@ -7858,7 +7850,7 @@ static int ufshcd_hba_init(struct ufs_hba *hba)
> > if (err)
> > goto out_disable_hba_vreg;
> >
> > - err = ufshcd_setup_clocks(hba, true);
> > + err = ufshcd_setup_clocks(hba, true, false);
> > if (err)
> > goto out_disable_hba_vreg;
> >
> > @@ -7880,7 +7872,7 @@ static int ufshcd_hba_init(struct ufs_hba *hba)
> > out_disable_vreg:
> > ufshcd_setup_vreg(hba, false);
> > out_disable_clks:
> > - ufshcd_setup_clocks(hba, false);
> > + ufshcd_setup_clocks(hba, false, false);
> > out_disable_hba_vreg:
> > ufshcd_setup_hba_vreg(hba, false);
> > out:
> > @@ -7896,7 +7888,7 @@ static void ufshcd_hba_exit(struct ufs_hba *hba)
> > if (ufshcd_is_clkscaling_supported(hba))
> > if (hba->devfreq)
> > ufshcd_suspend_clkscaling(hba);
> > - ufshcd_setup_clocks(hba, false);
> > + ufshcd_setup_clocks(hba, false, false);
> > ufshcd_setup_hba_vreg(hba, false);
> > hba->is_powered = false;
> > ufs_put_device_desc(hba);
> > @@ -8259,10 +8251,10 @@ static int ufshcd_suspend(struct ufs_hba *hba,
> > enum ufs_pm_op pm_op)
> > ufshcd_disable_irq(hba);
> >
> > if (!ufshcd_is_link_active(hba))
> > - ufshcd_setup_clocks(hba,
RE: [PATCH v3 1/2] scsi: ufs: Add SPDX GPL-2.0 to replace GPL v2 boilerplate
Hi Bean > -Original Message- > From: Bean Huo > Sent: 06 June 2020 01:35 > To: alim.akh...@samsung.com; avri.alt...@wdc.com; > asuto...@codeaurora.org; j...@linux.ibm.com; martin.peter...@oracle.com; > stanley@mediatek.com; bean...@micron.com; bvanass...@acm.org; > tomas.wink...@intel.com; c...@codeaurora.org; ebigg...@kernel.org > Cc: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: [PATCH v3 1/2] scsi: ufs: Add SPDX GPL-2.0 to replace GPL v2 boilerplate > > From: Bean Huo > > Add SPDX GPL-2.0 to UFS driver files that specified the GPL version 2 license, > remove the full boilerplate text. > > Signed-off-by: Bean Huo > --- > drivers/scsi/ufs/ufs.h | 27 +-- > drivers/scsi/ufs/ufshcd-pci.c| 25 + > drivers/scsi/ufs/ufshcd-pltfrm.c | 27 +-- > drivers/scsi/ufs/ufshcd.c| 30 +- > drivers/scsi/ufs/ufshcd.h| 27 +-- > drivers/scsi/ufs/ufshci.h| 27 +-- > 6 files changed, 6 insertions(+), 157 deletions(-) > Reviewed-by: Alim Akhtar > -- > 2.17.1
RE: [PATCH v1 2/2] scsi: ufs: Cleanup device vendor and quirk definition
Hi Stanley
> -Original Message-
> From: Stanley Chu
> Sent: 10 June 2020 11:07
> To: linux-s...@vger.kernel.org; martin.peter...@oracle.com;
> avri.alt...@wdc.com; alim.akh...@samsung.com; j...@linux.ibm.com;
> asuto...@codeaurora.org
> Cc: bean...@micron.com; c...@codeaurora.org; matthias@gmail.com;
> bvanass...@acm.org; linux-media...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> kuohong.w...@mediatek.com; peter.w...@mediatek.com; chun-
> hung...@mediatek.com; andy.t...@mediatek.com;
> chaotian.j...@mediatek.com; cc.c...@mediatek.com; Stanley Chu
>
> Subject: [PATCH v1 2/2] scsi: ufs: Cleanup device vendor and quirk
definition
>
> Cleanup below items,
> - Arrange vendor name in alphabetical order
> - Squash device quirks as compact as possible in device quirk table
> to enhance performance of the lookup.
>
> Signed-off-by: Stanley Chu
> ---
> drivers/scsi/ufs/ufs_quirks.h | 2 +-
> drivers/scsi/ufs/ufshcd.c | 6 ++
> 2 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufs_quirks.h b/drivers/scsi/ufs/ufs_quirks.h
index
> e80d5f26a442..2a0041493e30 100644
> --- a/drivers/scsi/ufs/ufs_quirks.h
> +++ b/drivers/scsi/ufs/ufs_quirks.h
> @@ -13,9 +13,9 @@
> #define UFS_ANY_MODEL "ANY_MODEL"
>
> #define UFS_VENDOR_MICRON 0x12C
> -#define UFS_VENDOR_TOSHIBA 0x198
> #define UFS_VENDOR_SAMSUNG 0x1CE
> #define UFS_VENDOR_SKHYNIX 0x1AD
> +#define UFS_VENDOR_TOSHIBA 0x198
> #define UFS_VENDOR_WDC 0x145
>
> /**
> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index
> dea4fddf9332..7c93cb446f51 100644
> --- a/drivers/scsi/ufs/ufshcd.c
> +++ b/drivers/scsi/ufs/ufshcd.c
> @@ -219,10 +219,8 @@ static struct ufs_dev_fix ufs_fixups[] = {
> UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
> UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
> UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
> - UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
> - UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
> - UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
> - UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
> + UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
> + UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS |
> UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
> UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
> UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
> --
While at this, may be arrange the table in alphabetical order.
> 2.18.0
RE: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
Hi Kishon > -Original Message- > From: Kishon Vijay Abraham I > Sent: 08 June 2020 08:23 > To: Alim Akhtar ; 'Martin K. Petersen' > ; r...@kernel.org > Cc: k...@kernel.org; linux-samsung-...@vger.kernel.org; > avri.alt...@wdc.com; stanley@mediatek.com; linux-s...@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; c...@codeaurora.org; > devicet...@vger.kernel.org; kwmad@samsung.com; linux- > ker...@vger.kernel.org; 'Vinod Koul' > Subject: Re: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI > > Hi Alim, > > On 6/8/2020 8:15 AM, Alim Akhtar wrote: > > > > > >> -Original Message- > >> From: Martin K. Petersen > >> Sent: 03 June 2020 08:02 > >> To: r...@kernel.org; Alim Akhtar > >> Cc: Martin K . Petersen ; > >> k...@kernel.org; > > linux- > >> samsung-...@vger.kernel.org; avri.alt...@wdc.com; > >> stanley@mediatek.com; linux-s...@vger.kernel.org; linux-arm- > >> ker...@lists.infradead.org; c...@codeaurora.org; > > devicet...@vger.kernel.org; > >> kwmad@samsung.com; linux-kernel@vger.kernel.org > >> Subject: Re: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI > >> > >> On Thu, 28 May 2020 06:46:48 +0530, Alim Akhtar wrote: > >> > >>> This patch-set introduces UFS (Universal Flash Storage) host > >>> controller support for Samsung family SoC. Mostly, it consists of > >>> UFS PHY and host specific driver. > >>> [...] > >> > >> Applied [1,2,3,4,5,9] to 5.9/scsi-queue. The series won't show up in > >> my > > public > >> tree until shortly after -rc1 is released. > >> > > Thanks Martin, > > Hi Rob and Kishon/Vinod > > Can you please pickup dt-bindings and PHY driver respectively? > > You might have CC'ed me only for the PHY patch. I don't have the dt-bindings > in > my inbox. Care to re-send what's missing again? This will be merged after > -rc1 is > tagged. > Sure, will re-send this series. > Thanks > Kishon > > > > >> Thanks! > >> > >> -- > >> Martin K. Petersen Oracle Linux Engineering > >
Re: [EXT] [PATCH v2 1/5] scsi: ufs: Allow UFS 3.0 as a valid version
Hi Jose On Thu, Apr 30, 2020 at 1:44 PM Jose Abreu wrote: > > From: Bean Huo (beanhuo) > Date: Apr/29/2020, 13:59:08 (UTC+00:00) > > > Probably. I think we can leave them or change the dev_err to a dev_warn. > > > This way we have logs in case someone is using a non-supported version. > > > > > > What do you think ? > > > > > Hi, Jose > > Seems after your patch, all of current released UFS control versions will > > be supported except the > > version suffix is non-zero. Right? > > I think we cover all versions with this patch. > Are you still on this? > --- > Thanks, > Jose Miguel Abreu -- Regards, Alim
Re: [PATCH] scsi: ufs: Bump supported UFS HCI version to 3.0
HI Manivannan
On Thu, Jun 4, 2020 at 12:08 PM Manivannan Sadhasivam
wrote:
>
> UFS HCI 3.0 versions are being used in Qcom SM8250 based boards. Hence,
> adding it to the list of supported versions.
>
> I don't have the exact information of the additional registers supported
> in version 3.0. Hence the change just adds 0x300 to the list of supported
> versions to remove the below warning:
>
> "ufshcd-qcom 1d84000.ufshc: invalid UFS version 0x300"
>
> Signed-off-by: Manivannan Sadhasivam
> ---
> drivers/scsi/ufs/ufshci.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/scsi/ufs/ufshci.h b/drivers/scsi/ufs/ufshci.h
> index c2961d37cc1c..f2ee81669b00 100644
> --- a/drivers/scsi/ufs/ufshci.h
> +++ b/drivers/scsi/ufs/ufshci.h
> @@ -104,6 +104,7 @@ enum {
> UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
> UFSHCI_VERSION_20 = 0x0200, /* 2.0 */
> UFSHCI_VERSION_21 = 0x0210, /* 2.1 */
> + UFSHCI_VERSION_30 = 0x0300, /* 3.0 */
See the current discussion on this https://lkml.org/lkml/2020/4/27/192
> };
>
> /*
> --
> 2.17.1
>
--
Regards,
Alim
RE: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
> -Original Message- > From: Martin K. Petersen > Sent: 03 June 2020 08:02 > To: r...@kernel.org; Alim Akhtar > Cc: Martin K . Petersen ; k...@kernel.org; linux- > samsung-...@vger.kernel.org; avri.alt...@wdc.com; > stanley@mediatek.com; linux-s...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; c...@codeaurora.org; devicet...@vger.kernel.org; > kwmad@samsung.com; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI > > On Thu, 28 May 2020 06:46:48 +0530, Alim Akhtar wrote: > > > This patch-set introduces UFS (Universal Flash Storage) host > > controller support for Samsung family SoC. Mostly, it consists of UFS > > PHY and host specific driver. > > [...] > > Applied [1,2,3,4,5,9] to 5.9/scsi-queue. The series won't show up in my public > tree until shortly after -rc1 is released. > Thanks Martin, Hi Rob and Kishon/Vinod Can you please pickup dt-bindings and PHY driver respectively? > Thanks! > > -- > Martin K. PetersenOracle Linux Engineering
RE: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
> -Original Message- > From: Alim Akhtar > Sent: 28 May 2020 06:47 > To: r...@kernel.org > Cc: devicet...@vger.kernel.org; linux-s...@vger.kernel.org; k...@kernel.org; > avri.alt...@wdc.com; martin.peter...@oracle.com; > kwmad@samsung.com; stanley@mediatek.com; > c...@codeaurora.org; linux-samsung-...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Alim Akhtar > > Subject: [PATCH v10 00/10] exynos-ufs: Add support for UFS HCI > > This patch-set introduces UFS (Universal Flash Storage) host controller > support > for Samsung family SoC. Mostly, it consists of UFS PHY and host specific > driver. > . . . > Alim Akhtar (9): > scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr > scsi: ufs: add quirk to disallow reset of interrupt aggregation > scsi: ufs: add quirk to enable host controller without hce > scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk > dt-bindings: phy: Document Samsung UFS PHY bindings > phy: samsung-ufs: add UFS PHY driver for samsung SoC > dt-bindings: ufs: Add bindings for Samsung ufs host > scsi: ufs-exynos: add UFS host support for Exynos SoCs > arm64: dts: Add node for ufs exynos7 > > Kiwoong Kim (1): > scsi: ufs: add quirk to fix abnormal ocs fatal error > > .../bindings/phy/samsung,ufs-phy.yaml | 75 + > .../bindings/ufs/samsung,exynos-ufs.yaml | 89 ++ > .../boot/dts/exynos/exynos7-espresso.dts |4 + > arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 +- > drivers/phy/samsung/Kconfig |9 + > drivers/phy/samsung/Makefile |1 + > drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++ > drivers/phy/samsung/phy-samsung-ufs.c | 380 + > drivers/phy/samsung/phy-samsung-ufs.h | 143 ++ > drivers/scsi/ufs/Kconfig | 12 + > drivers/scsi/ufs/Makefile |1 + > drivers/scsi/ufs/ufs-exynos.c | 1292 + > drivers/scsi/ufs/ufs-exynos.h | 287 > drivers/scsi/ufs/ufshcd.c | 126 +- > drivers/scsi/ufs/ufshcd.h | 29 + > drivers/scsi/ufs/unipro.h | 33 + > 16 files changed, 2596 insertions(+), 14 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs- > phy.yaml > create mode 100644 Documentation/devicetree/bindings/ufs/samsung,exynos- > ufs.yaml > create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h > create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c > create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h > create mode 100644 drivers/scsi/ufs/ufs-exynos.c > create mode 100644 drivers/scsi/ufs/ufs-exynos.h > Hi Martin and Kishon, Can you please take the patches into your respective trees? Thanks, > > base-commit: 0e698dfa282211e414076f9dc7e83c1c288314fd > -- > 2.17.1
RE: [PATCH v10 10/10] arm64: dts: Add node for ufs exynos7
> -Original Message- > From: Krzysztof Kozlowski > Sent: 29 May 2020 13:36 > To: Alim Akhtar > Cc: r...@kernel.org; devicet...@vger.kernel.org; linux-s...@vger.kernel.org; > avri.alt...@wdc.com; martin.peter...@oracle.com; > kwmad@samsung.com; stanley@mediatek.com; > c...@codeaurora.org; linux-samsung-...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v10 10/10] arm64: dts: Add node for ufs exynos7 > > On Thu, May 28, 2020 at 06:46:58AM +0530, Alim Akhtar wrote: > > Adding dt node foe UFS and UFS-PHY for exynos7 SoC. > > > > Signed-off-by: Alim Akhtar > > Tested-by: Paweł Chmiel > > --- > > .../boot/dts/exynos/exynos7-espresso.dts | 4 ++ > > arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 ++- > > Thanks, applied to next/dt-late. It might miss this merge window and in such > case I will keep it for v5.9 cycle. Thanks Krzysztof. > > Best regards, > Krzysztof
[PATCH v10 08/10] dt-bindings: ufs: Add bindings for Samsung ufs host
This patch adds DT bindings for Samsung ufs hci
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
---
.../bindings/ufs/samsung,exynos-ufs.yaml | 89 +++
1 file changed, 89 insertions(+)
create mode 100644
Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
new file mode 100644
index ..38193975c9f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS host controller Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+description: |
+ Each Samsung UFS host controller instance should have its own node.
+ This binding define Samsung specific binding other then what is used
+ in the common ufshcd bindings
+ [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+
+properties:
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs
+
+ reg:
+items:
+ - description: HCI register
+ - description: vendor specific register
+ - description: unipro register
+ - description: UFS protector register
+
+ reg-names:
+items:
+ - const: hci
+ - const: vs_hci
+ - const: unipro
+ - const: ufsp
+
+ clocks:
+items:
+ - description: ufs link core clock
+ - description: unipro main clock
+
+ clock-names:
+items:
+ - const: core_clk
+ - const: sclk_unipro_main
+
+ interrupts:
+maxItems: 1
+
+ phys:
+maxItems: 1
+
+ phy-names:
+const: ufs-phy
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - phys
+ - phy-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+ufs: ufs@1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = ;
+ clocks = <_fsys1 ACLK_UFS20_LINK>,
+<_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rst_n _refclk_out>;
+ phys = <_phy>;
+ phy-names = "ufs-phy";
+};
+...
--
2.17.1
[PATCH v10 04/10] scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk
Some UFS host controllers like Exynos uses granularities of PRDT length and
offset as bytes, whereas others uses actual segment count.
Reviewed-by: Avri Altman
Signed-off-by: Kiwoong Kim
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 30 +++---
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ee30ed6cc805..ba093d0d0942 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2151,8 +2151,14 @@ static int ufshcd_map_sg(struct ufs_hba *hba, struct
ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16)sg_segments);
+
+ if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -3500,11 +3506,21 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
- cpu_to_le16(response_offset >> 2);
- utrdlp[i].prd_table_offset = cpu_to_le16(prdt_offset >> 2);
- utrdlp[i].response_upiu_length =
- cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset >> 2);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset >> 2);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
ufshcd_init_lrb(hba, >lrb[i], i);
}
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index f8d08cb9caf7..a9b9ace9fc72 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -535,6 +535,12 @@ enum ufshcd_quirks {
* enabled via HCE register.
*/
UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
+
+ /*
+* This quirk needs to be enabled if the host controller regards
+* resolution of the values of PRDTO and PRDTL in UTRD as byte.
+*/
+ UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v10 03/10] scsi: ufs: add quirk to enable host controller without hce
Some host controllers don't support host controller enable via HCE.
Reviewed-by: Can Guo
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 76 +--
drivers/scsi/ufs/ufshcd.h | 6
2 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 0e9704da58bd..ee30ed6cc805 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3534,6 +3534,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, _cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, _cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -4251,7 +4297,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba,
bool can_sleep)
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -4260,7 +4306,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba,
bool can_sleep)
*
* Returns 0 on success, non-zero value on failure
*/
-int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -4308,6 +4354,32 @@ int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+
+int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 53096642f9a8..f8d08cb9caf7 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -529,6 +529,12 @@ enum ufshcd_quirks {
* that the interrupt aggregation timer and counter are reset by s/w.
*/
UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
+
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v10 01/10] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
In the right behavior, setting the bit to '0' indicates clear and '1'
indicates no change. If host controller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Reviewed-by: Can Guo
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 11 +--
drivers/scsi/ufs/ufshcd.h | 5 +
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 698e8d20b4ba..3655b88fc862 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -645,7 +645,11 @@ static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb
*lrbp)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
}
/**
@@ -655,7 +659,10 @@ static inline void ufshcd_utrl_clear(struct ufs_hba *hba,
u32 pos)
*/
static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6ffc08ad85f6..071f0edf3f64 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -518,6 +518,11 @@ enum ufshcd_quirks {
* ops (get_ufs_hci_version) to get the correct version.
*/
UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
+
+ /*
+* Clear handling for transfer/task request list is just opposite.
+*/
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR= 1 << 6,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v10 00/10] exynos-ufs: Add support for UFS HCI
This patch-set introduces UFS (Universal Flash Storage) host controller support for Samsung family SoC. Mostly, it consists of UFS PHY and host specific driver. - Changes since v9 * fixed the review comments by Rob on ufs dt bindings * Addeded Rob's reviwed-by tag on 08/10 patch - Changes since v8 * fixed make dt_binding_check error as pointed by Rob * Addressed review comments from Randy Dunlap - Changes since v7: * fixed review comments from Rob and Kishon * Addeded reviwed-by tags * rebased on top of v5.7-rc4 - Changes since v6: * Addressed review comments from Avri and Christoph * Added Reviewed-by tags of Avri and Can on various patches - Changes since v5: * re-introduce various quicks which was removed because of no driver * consumer of those quirks, initial 4 patches does the same. * Added Reviewed-by tags * rebased on top of v5.7-rc1 * included Kiwoong's patch in this series, which this driver needs - Changes since v4: * Addressed review comments from Avir and Rob * Minor improvment on the ufs phy and ufshc drivers * Added Tested-by from Pawel * Change UFS binding to DT schema format - Changes since v3: * Addressed Kishon's and Avir's review comments * fixed make dt_binding_check error as pointed by Rob - Changes since v2: * fixed build warning by kbuild test robot * Added Reported-by tags - Changes since v1: * fixed make dt_binding_check error as pointed by Rob * Addressed Krzysztof's review comments * Added Reviewed-by tags Note: This series is based on Linux-5.7-rc4 (commit: 0e698dfa2822) Alim Akhtar (9): scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk to disallow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk dt-bindings: phy: Document Samsung UFS PHY bindings phy: samsung-ufs: add UFS PHY driver for samsung SoC dt-bindings: ufs: Add bindings for Samsung ufs host scsi: ufs-exynos: add UFS host support for Exynos SoCs arm64: dts: Add node for ufs exynos7 Kiwoong Kim (1): scsi: ufs: add quirk to fix abnormal ocs fatal error .../bindings/phy/samsung,ufs-phy.yaml | 75 + .../bindings/ufs/samsung,exynos-ufs.yaml | 89 ++ .../boot/dts/exynos/exynos7-espresso.dts |4 + arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 +- drivers/phy/samsung/Kconfig |9 + drivers/phy/samsung/Makefile |1 + drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++ drivers/phy/samsung/phy-samsung-ufs.c | 380 + drivers/phy/samsung/phy-samsung-ufs.h | 143 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos.c | 1292 + drivers/scsi/ufs/ufs-exynos.h | 287 drivers/scsi/ufs/ufshcd.c | 126 +- drivers/scsi/ufs/ufshcd.h | 29 + drivers/scsi/ufs/unipro.h | 33 + 16 files changed, 2596 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml create mode 100644 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h base-commit: 0e698dfa282211e414076f9dc7e83c1c288314fd -- 2.17.1
[PATCH v10 09/10] scsi: ufs-exynos: add UFS host support for Exynos SoCs
This patch introduces Exynos UFS host controller driver, which mainly handles vendor-specific operations including link startup, power mode change and hibernation/unhibernation. Reported-by: kbuild test robot Reported-by: Julia Lawall [robot: drivers/scsi/ufs/ufs-exynos.c:931:8-10: WARNING: possible condition with no effect (if == else) ] Reviewed-by: Kiwoong Kim Reviewed-by: Avri Altman Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar Tested-by: Paweł Chmiel --- drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos.c | 1292 + drivers/scsi/ufs/ufs-exynos.h | 287 drivers/scsi/ufs/unipro.h | 33 + 5 files changed, 1625 insertions(+) create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index e2005aeddc2d..7da886d3c323 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -160,3 +160,15 @@ config SCSI_UFS_BSG Select this if you need a bsg device node for your UFS controller. If unsure, say N. + +config SCSI_UFS_EXYNOS + bool "EXYNOS specific hooks to UFS controller platform driver" + depends on SCSI_UFSHCD_PLATFORM && (ARCH_EXYNOS || COMPILE_TEST) + select PHY_SAMSUNG_UFS + help + This selects the EXYNOS specific additions to UFSHCD platform driver. + UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with + UFS-PHY driver. + + Select this if you have UFS host controller on EXYNOS chipset. + If unsure, say N. diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile index 94c6c5d7334b..f0c5b95ec9cc 100644 --- a/drivers/scsi/ufs/Makefile +++ b/drivers/scsi/ufs/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210. obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o obj-$(CONFIG_SCSI_UFS_CDNS_PLATFORM) += cdns-pltfrm.o obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o +obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o ufshcd-core-y += ufshcd.o ufs-sysfs.o ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c new file mode 100644 index ..440f2af83d9c --- /dev/null +++ b/drivers/scsi/ufs/ufs-exynos.c @@ -0,0 +1,1292 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UFS Host Controller driver for Exynos specific extensions + * + * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. + * Author: Seungwon Jeon + * Author: Alim Akhtar + * + */ + +#include +#include +#include +#include +#include +#include + +#include "ufshcd.h" +#include "ufshcd-pltfrm.h" +#include "ufshci.h" +#include "unipro.h" + +#include "ufs-exynos.h" + +/* + * Exynos's Vendor specific registers for UFSHCI + */ +#define HCI_TXPRDT_ENTRY_SIZE 0x00 +#define PRDT_PREFECT_ENBIT(31) +#define PRDT_SET_SIZE(x) ((x) & 0x1F) +#define HCI_RXPRDT_ENTRY_SIZE 0x04 +#define HCI_1US_TO_CNT_VAL 0x0C +#define CNT_VAL_1US_MASK 0x3FF +#define HCI_UTRL_NEXUS_TYPE0x40 +#define HCI_UTMRL_NEXUS_TYPE 0x44 +#define HCI_SW_RST 0x50 +#define UFS_LINK_SW_RSTBIT(0) +#define UFS_UNIPRO_SW_RST BIT(1) +#define UFS_SW_RST_MASK(UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST) +#define HCI_DATA_REORDER 0x60 +#define HCI_UNIPRO_APB_CLK_CTRL0x68 +#define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) +#define HCI_AXIDMA_RWDATA_BURST_LEN0x6C +#define HCI_GPIO_OUT 0x70 +#define HCI_ERR_EN_PA_LAYER0x78 +#define HCI_ERR_EN_DL_LAYER0x7C +#define HCI_ERR_EN_N_LAYER 0x80 +#define HCI_ERR_EN_T_LAYER 0x84 +#define HCI_ERR_EN_DME_LAYER 0x88 +#define HCI_CLKSTOP_CTRL 0xB0 +#define REFCLK_STOPBIT(2) +#define UNIPRO_MCLK_STOP BIT(1) +#define UNIPRO_PCLK_STOP BIT(0) +#define CLK_STOP_MASK (REFCLK_STOP |\ +UNIPRO_MCLK_STOP |\ +UNIPRO_PCLK_STOP) +#define HCI_MISC 0xB4 +#define REFCLK_CTRL_EN BIT(7) +#define UNIPRO_PCLK_CTRL_ENBIT(6) +#define UNIPRO_MCLK_CTRL_ENBIT(5) +#define HCI_CORECLK_CTRL_ENBIT(4) +#define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ +UNIPRO_PCLK_CTRL_EN |\ +UNIPRO_MCLK_CTRL_EN) +/* Device fatal error */ +#define DFES_ERR_ENBIT(31) +#define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ +UIC_DATA_LINK_LAYER_ERROR_PA_INIT) +#define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPOR
[PATCH v10 10/10] arm64: dts: Add node for ufs exynos7
Adding dt node foe UFS and UFS-PHY for exynos7 SoC.
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../boot/dts/exynos/exynos7-espresso.dts | 4 ++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 ++-
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 7af288fa9475..790f12ca8981 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -406,6 +406,10 @@
};
};
+ {
+ status = "okay";
+};
+
_phy {
vbus-supply = <_vbus_reg>;
vbus-boost-supply = <_boost_5v>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 5558045637ac..300ad7326ea8 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -220,9 +220,14 @@
#clock-cells = <1>;
clocks = <_pll>, <_top1 DOUT_ACLK_FSYS1_200>,
<_top1 DOUT_SCLK_MMC0>,
-<_top1 DOUT_SCLK_MMC1>;
+<_top1 DOUT_SCLK_MMC1>,
+<_top1 DOUT_SCLK_UFSUNIPRO20>,
+<_top1 DOUT_SCLK_PHY_FSYS1>,
+<_top1 DOUT_SCLK_PHY_FSYS1_26M>;
clock-names = "fin_pll", "dout_aclk_fsys1_200",
- "dout_sclk_mmc0", "dout_sclk_mmc1";
+ "dout_sclk_mmc0", "dout_sclk_mmc1",
+ "dout_sclk_ufsunipro20",
"dout_sclk_phy_fsys1",
+ "dout_sclk_phy_fsys1_26m";
};
serial_0: serial@1363 {
@@ -601,6 +606,40 @@
};
};
+ ufs: ufs@1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>, /* 0: HCI standard */
+ <0x15570100 0x100>, /* 1: Vendor specificed */
+ <0x15571000 0x200>, /* 2: UNIPRO */
+ <0x15572000 0x300>; /* 3: UFS protector */
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = ;
+ clocks = <_fsys1 ACLK_UFS20_LINK>,
+ <_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ freq-table-hz = <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_rst_n _refclk_out>;
+ phys = <_phy>;
+ phy-names = "ufs-phy";
+ status = "disabled";
+ };
+
+ ufs_phy: ufs-phy@15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <_system_controller>;
+ #phy-cells = <0>;
+ clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+<_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+<_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+<_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+ clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk",
+ "tx0_symbol_clk";
+ };
+
usbdrd_phy: phy@1550 {
compatible = "samsung,exynos7-usbdrd-phy";
reg = <0x1550 0x100>;
--
2.17.1
[PATCH v10 07/10] phy: samsung-ufs: add UFS PHY driver for samsung SoC
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Reviewed-by: Kiwoong Kim
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
Cc: Kishon Vijay Abraham I
Tested-by: Paweł Chmiel
---
drivers/phy/samsung/Kconfig | 9 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++
drivers/phy/samsung/phy-samsung-ufs.c | 380 ++
drivers/phy/samsung/phy-samsung-ufs.h | 143 ++
5 files changed, 619 insertions(+)
create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 9e483d1fdaf2..fc1e3c17f842 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
Enable PCIe PHY support for Exynos SoC series.
This driver provides PHY interface for Exynos PCIe controller.
+config PHY_SAMSUNG_UFS
+ tristate "SAMSUNG SoC series UFS PHY driver"
+ depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h
b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index ..c4aab792d30e
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A)
[PATCH v10 06/10] dt-bindings: phy: Document Samsung UFS PHY bindings
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index ..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+properties:
+ "#phy-cells":
+const: 0
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+maxItems: 1
+
+ reg-names:
+items:
+ - const: phy-pma
+
+ clocks:
+items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+ufs_phy: ufs-phy@15571800 {
+compatible = "samsung,exynos7-ufs-phy";
+reg = <0x15571800 0x240>;
+reg-names = "phy-pma";
+samsung,pmu-syscon = <_system_controller>;
+#phy-cells = <0>;
+clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+};
+...
--
2.17.1
[PATCH v10 02/10] scsi: ufs: add quirk to disallow reset of interrupt aggregation
Some host controllers support interrupt aggregation but don't allow
resetting counter and timer in software.
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 3 ++-
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 3655b88fc862..0e9704da58bd 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -4884,7 +4884,8 @@ static irqreturn_t ufshcd_transfer_req_compl(struct
ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 071f0edf3f64..53096642f9a8 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -523,6 +523,12 @@ enum ufshcd_quirks {
* Clear handling for transfer/task request list is just opposite.
*/
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR= 1 << 6,
+
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v10 05/10] scsi: ufs: add quirk to fix abnormal ocs fatal error
From: Kiwoong Kim
Some controller like Exynos determines if FATAL ERROR (0x7)
in OCS field in UTRD occurs for values other than GOOD (0x0)
in STATUS field in response upiu as well as errors that a
host controller can't cover.
This patch is to prevent from reporting command results in
those cases.
Signed-off-by: Kiwoong Kim
Signed-off-by: Alim Akhtar
Reviewed-by: Avri Altman
---
drivers/scsi/ufs/ufshcd.c | 6 ++
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ba093d0d0942..33ebffa8257d 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -4794,6 +4794,12 @@ ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct
ufshcd_lrb *lrbp)
/* overall command status of utrd */
ocs = ufshcd_get_tr_ocs(lrbp);
+ if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
+ if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
+ MASK_RSP_UPIU_RESULT)
+ ocs = OCS_SUCCESS;
+ }
+
switch (ocs) {
case OCS_SUCCESS:
result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index a9b9ace9fc72..e1d09c2c4302 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -541,6 +541,12 @@ enum ufshcd_quirks {
* resolution of the values of PRDTO and PRDTL in UTRD as byte.
*/
UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
+
+ /*
+* This quirk needs to be enabled if the host controller reports
+* OCS FATAL ERROR with device error through sense data
+*/
+ UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
};
enum ufshcd_caps {
--
2.17.1
RE: [PATCH v9 08/10] dt-bindings: ufs: Add DT binding documentation for ufs
Hi Rob,
> -Original Message-
> From: Rob Herring
> Sent: 26 May 2020 23:39
> To: Alim Akhtar
> Cc: devicet...@vger.kernel.org; linux-s...@vger.kernel.org;
k...@kernel.org;
> avri.alt...@wdc.com; martin.peter...@oracle.com;
> kwmad@samsung.com; stanley@mediatek.com;
> c...@codeaurora.org; linux-samsung-...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v9 08/10] dt-bindings: ufs: Add DT binding
documentation
> for ufs
>
> On Thu, May 14, 2020 at 06:09:12AM +0530, Alim Akhtar wrote:
> > This patch adds DT binding for samsung ufs hci
>
> Subject should indicate this is for Samsung in some way.
>
Sure will update the Subject as suggested by you.
> >
> > Signed-off-by: Alim Akhtar
> > ---
> > .../bindings/ufs/samsung,exynos-ufs.yaml | 91 +++
> > 1 file changed, 91 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> > b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> > new file mode 100644
> > index ..eaa64cc32d52
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> > @@ -0,0 +1,91 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
> > +---
> > +$id:
> > +https://protect2.fireeye.com/url?k=9995443c-c4461d82-9994cf73-0cc47a3
> > +1ba82-
> 2c9d6322e4bc35a5=1=http%3A%2F%2Fdevicetree.org%2Fschemas%2F
> > +ufs%2Fsamsung%2Cexynos-ufs.yaml%23
> > +$schema:
> > +https://protect2.fireeye.com/url?k=70bd56cd-2d6e0f73-70bcdd82-0cc47a3
> > +1ba82-7865215595a4146c=1=http%3A%2F%2Fdevicetree.org%2Fmeta-
> schem
> > +as%2Fcore.yaml%23
> > +
> > +title: Samsung SoC series UFS host controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Alim Akhtar
> > +
> > +description: |
> > + Each Samsung UFS host controller instance should have its own node.
> > + This binding define Samsung specific binding other then what is
> > +used
> > + in the common ufshcd bindings
> > + [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
> > +
> > +properties:
> > +
> > + compatible:
> > +enum:
> > + - samsung,exynos7-ufs
> > +
> > + reg:
> > +items:
> > + - description: HCI register
> > + - description: vendor specific register
> > + - description: unipro register
> > + - description: UFS protector register
> > +
> > + reg-names:
> > +items:
> > + - const: hci
> > + - const: vs_hci
> > + - const: unipro
> > + - const: ufsp
> > +
> > + clocks:
> > +maxItems: 2
>
> maxItems is redundant.
>
Will drop it.
> > +items:
> > + - description: ufs link core clock
> > + - description: unipro main clock
> > +
> > + clock-names:
> > +maxItems: 2
>
> Here too.
Will drop it.
>
> > +items:
> > + - const: core_clk
> > + - const: sclk_unipro_main
> > +
> > + interrupts:
> > +maxItems: 1
> > +
> > + phys:
> > +maxItems: 1
> > +
> > + phy-names:
> > +maxItems: 1
>
> What's the name? (Though a name is kind of pointless when there is only
> 1.)
Not sure are you suggesting to drop the phy-names completely? Or just keep
"phy-names:" only.
I looked into how other bindings has handle it, I will change this as
phy-names:
const: ufs-phy
Hope you are ok with this.
>
> With those fixed,
>
> Reviewed-by: Rob Herring
>
With adding "phy-names" entry, I will adds your Reviewed-by tag, will post
the updated changes soon.
Thank you!!
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - phys
> > + - phy-names
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +#include
> > +#include
> > +
> > +ufs: ufs@1557 {
> > + compatible = "samsung,exynos7-ufs";
> > + reg = <0x1557 0x100>,
> > + <0x15570100 0x100>,
> > + <0x15571000 0x200>,
> > + <0x15572000 0x300>;
> > + reg-names = "hci", "vs_hci", "unipro", "ufsp";
> > + interrupts = ;
> > + clocks = <_fsys1 ACLK_UFS20_LINK>,
> > +<_fsys1 SCLK_UFSUNIPRO20_USER>;
> > + clock-names = "core_clk", "sclk_unipro_main";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_rst_n _refclk_out>;
> > + phys = <_phy>;
> > + phy-names = "ufs-phy";
> > +};
> > +...
> > --
> > 2.17.1
> >
RE: [PATCH v9 10/10] arm64: dts: Add node for ufs exynos7
> -Original Message- > From: Krzysztof Kozlowski > Sent: 19 May 2020 12:47 > To: Alim Akhtar > Cc: r...@kernel.org; devicet...@vger.kernel.org; linux-s...@vger.kernel.org; > avri.alt...@wdc.com; martin.peter...@oracle.com; > kwmad@samsung.com; stanley@mediatek.com; > c...@codeaurora.org; linux-samsung-...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v9 10/10] arm64: dts: Add node for ufs exynos7 > > On Thu, May 14, 2020 at 06:09:14AM +0530, Alim Akhtar wrote: > > Adding dt node foe UFS and UFS-PHY for exynos7 SoC. > > > > Signed-off-by: Alim Akhtar > > Tested-by: Paweł Chmiel > > --- > > .../boot/dts/exynos/exynos7-espresso.dts | 4 ++ > > arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 ++- > > 2 files changed, 45 insertions(+), 2 deletions(-) > > I will pick it up after all bindings get Rob's ack (or are picked up as > well). The > second bindings patch are still pending on that. > Thank Krzysztof, Yes, one binding still awaiting Rob's ack, I have addressed his comment in this v9 series. Hoping he will find some time to review the same. > Best regards, > Krzysztof
[PATCH v9 06/10] dt-bindings: phy: Document Samsung UFS PHY bindings
This patch documents Samsung UFS PHY device tree bindings
Reviewed-by: Rob Herring
Signed-off-by: Alim Akhtar
Tested-by: Paweł Chmiel
---
.../bindings/phy/samsung,ufs-phy.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index ..636cc501b54f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+properties:
+ "#phy-cells":
+const: 0
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+maxItems: 1
+
+ reg-names:
+items:
+ - const: phy-pma
+
+ clocks:
+items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol ( tx0 symbol clock)
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ samsung,pmu-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle for PMU system controller interface, used to
+ control pmu registers bits for ufs m-phy
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+ufs_phy: ufs-phy@15571800 {
+compatible = "samsung,exynos7-ufs-phy";
+reg = <0x15571800 0x240>;
+reg-names = "phy-pma";
+samsung,pmu-syscon = <_system_controller>;
+#phy-cells = <0>;
+clocks = <_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
+ <_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
+ <_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
+clock-names = "ref_clk", "rx1_symbol_clk",
+ "rx0_symbol_clk", "tx0_symbol_clk";
+
+};
+...
--
2.17.1
[PATCH v9 03/10] scsi: ufs: add quirk to enable host controller without hce
Some host controllers don't support host controller enable via HCE.
Reviewed-by: Can Guo
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 76 +--
drivers/scsi/ufs/ufshcd.h | 6
2 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 0e9704da58bd..ee30ed6cc805 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3534,6 +3534,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, _cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, _cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -4251,7 +4297,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba,
bool can_sleep)
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -4260,7 +4306,7 @@ static inline void ufshcd_hba_stop(struct ufs_hba *hba,
bool can_sleep)
*
* Returns 0 on success, non-zero value on failure
*/
-int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -4308,6 +4354,32 @@ int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+
+int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with
non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 53096642f9a8..f8d08cb9caf7 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -529,6 +529,12 @@ enum ufshcd_quirks {
* that the interrupt aggregation timer and counter are reset by s/w.
*/
UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
+
+ /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+ UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v9 02/10] scsi: ufs: add quirk to disallow reset of interrupt aggregation
Some host controllers support interrupt aggregation but don't allow
resetting counter and timer in software.
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 3 ++-
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 3655b88fc862..0e9704da58bd 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -4884,7 +4884,8 @@ static irqreturn_t ufshcd_transfer_req_compl(struct
ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 071f0edf3f64..53096642f9a8 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -523,6 +523,12 @@ enum ufshcd_quirks {
* Clear handling for transfer/task request list is just opposite.
*/
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR= 1 << 6,
+
+ /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v9 04/10] scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk
Some UFS host controllers like Exynos uses granularities of PRDT length and
offset as bytes, whereas others uses actual segment count.
Reviewed-by: Avri Altman
Signed-off-by: Kiwoong Kim
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 30 +++---
drivers/scsi/ufs/ufshcd.h | 6 ++
2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ee30ed6cc805..ba093d0d0942 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2151,8 +2151,14 @@ static int ufshcd_map_sg(struct ufs_hba *hba, struct
ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16)sg_segments);
+
+ if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -3500,11 +3506,21 @@ static void ufshcd_host_memory_configure(struct ufs_hba
*hba)
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
- cpu_to_le16(response_offset >> 2);
- utrdlp[i].prd_table_offset = cpu_to_le16(prdt_offset >> 2);
- utrdlp[i].response_upiu_length =
- cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset >> 2);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset >> 2);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
ufshcd_init_lrb(hba, >lrb[i], i);
}
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index f8d08cb9caf7..a9b9ace9fc72 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -535,6 +535,12 @@ enum ufshcd_quirks {
* enabled via HCE register.
*/
UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
+
+ /*
+* This quirk needs to be enabled if the host controller regards
+* resolution of the values of PRDTO and PRDTL in UTRD as byte.
+*/
+ UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v9 01/10] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
In the right behavior, setting the bit to '0' indicates clear and '1'
indicates no change. If host controller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Reviewed-by: Can Guo
Reviewed-by: Avri Altman
Signed-off-by: Seungwon Jeon
Signed-off-by: Alim Akhtar
---
drivers/scsi/ufs/ufshcd.c | 11 +--
drivers/scsi/ufs/ufshcd.h | 5 +
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 698e8d20b4ba..3655b88fc862 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -645,7 +645,11 @@ static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb
*lrbp)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
}
/**
@@ -655,7 +659,10 @@ static inline void ufshcd_utrl_clear(struct ufs_hba *hba,
u32 pos)
*/
static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6ffc08ad85f6..071f0edf3f64 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -518,6 +518,11 @@ enum ufshcd_quirks {
* ops (get_ufs_hci_version) to get the correct version.
*/
UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
+
+ /*
+* Clear handling for transfer/task request list is just opposite.
+*/
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR= 1 << 6,
};
enum ufshcd_caps {
--
2.17.1
[PATCH v9 08/10] dt-bindings: ufs: Add DT binding documentation for ufs
This patch adds DT binding for samsung ufs hci
Signed-off-by: Alim Akhtar
---
.../bindings/ufs/samsung,exynos-ufs.yaml | 91 +++
1 file changed, 91 insertions(+)
create mode 100644
Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
new file mode 100644
index ..eaa64cc32d52
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS host controller Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar
+
+description: |
+ Each Samsung UFS host controller instance should have its own node.
+ This binding define Samsung specific binding other then what is used
+ in the common ufshcd bindings
+ [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+
+properties:
+
+ compatible:
+enum:
+ - samsung,exynos7-ufs
+
+ reg:
+items:
+ - description: HCI register
+ - description: vendor specific register
+ - description: unipro register
+ - description: UFS protector register
+
+ reg-names:
+items:
+ - const: hci
+ - const: vs_hci
+ - const: unipro
+ - const: ufsp
+
+ clocks:
+maxItems: 2
+items:
+ - description: ufs link core clock
+ - description: unipro main clock
+
+ clock-names:
+maxItems: 2
+items:
+ - const: core_clk
+ - const: sclk_unipro_main
+
+ interrupts:
+maxItems: 1
+
+ phys:
+maxItems: 1
+
+ phy-names:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - phys
+ - phy-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+ufs: ufs@1557 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = ;
+ clocks = <_fsys1 ACLK_UFS20_LINK>,
+<_fsys1 SCLK_UFSUNIPRO20_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ pinctrl-names = "default";
+ pinctrl-0 = <_rst_n _refclk_out>;
+ phys = <_phy>;
+ phy-names = "ufs-phy";
+};
+...
--
2.17.1
[PATCH v9 00/10] exynos-ufs: Add support for UFS HCI
This patch-set introduces UFS (Universal Flash Storage) host controller support for Samsung family SoC. Mostly, it consists of UFS PHY and host specific driver. - Changes since v8 * fixed make dt_binding_check error as pointed by Rob * Addressed review comments from Randy Dunlap - Changes since v7: * fixed review comments from Rob and Kishon * Addeded reviwed-by tags * rebased on top of v5.7-rc4 - Changes since v6: * Addressed review comments from Avri and Christoph * Added Reviewed-by tags of Avri and Can on various patches - Changes since v5: * re-introduce various quicks which was removed because of no driver * consumer of those quirks, initial 4 patches does the same. * Added Reviewed-by tags * rebased on top of v5.7-rc1 * included Kiwoong's patch in this series, which this driver needs - Changes since v4: * Addressed review comments from Avir and Rob * Minor improvment on the ufs phy and ufshc drivers * Added Tested-by from Pawel * Change UFS binding to DT schema format - Changes since v3: * Addressed Kishon's and Avir's review comments * fixed make dt_binding_check error as pointed by Rob - Changes since v2: * fixed build warning by kbuild test robot * Added Reported-by tags - Changes since v1: * fixed make dt_binding_check error as pointed by Rob * Addressed Krzysztof's review comments * Added Reviewed-by tags Note: This series is based on Linux-5.7-rc4 (commit: 0e698dfa2822) Alim Akhtar (9): scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr scsi: ufs: add quirk to disallow reset of interrupt aggregation scsi: ufs: add quirk to enable host controller without hce scsi: ufs: introduce UFSHCD_QUIRK_PRDT_BYTE_GRAN quirk dt-bindings: phy: Document Samsung UFS PHY bindings phy: samsung-ufs: add UFS PHY driver for samsung SoC dt-bindings: ufs: Add DT binding documentation for ufs scsi: ufs-exynos: add UFS host support for Exynos SoCs arm64: dts: Add node for ufs exynos7 Kiwoong Kim (1): scsi: ufs: add quirk to fix abnormal ocs fatal error .../bindings/phy/samsung,ufs-phy.yaml | 75 + .../bindings/ufs/samsung,exynos-ufs.yaml | 91 ++ .../boot/dts/exynos/exynos7-espresso.dts |4 + arch/arm64/boot/dts/exynos/exynos7.dtsi | 43 +- drivers/phy/samsung/Kconfig |9 + drivers/phy/samsung/Makefile |1 + drivers/phy/samsung/phy-exynos7-ufs.h | 86 ++ drivers/phy/samsung/phy-samsung-ufs.c | 380 + drivers/phy/samsung/phy-samsung-ufs.h | 143 ++ drivers/scsi/ufs/Kconfig | 12 + drivers/scsi/ufs/Makefile |1 + drivers/scsi/ufs/ufs-exynos.c | 1292 + drivers/scsi/ufs/ufs-exynos.h | 287 drivers/scsi/ufs/ufshcd.c | 126 +- drivers/scsi/ufs/ufshcd.h | 29 + drivers/scsi/ufs/unipro.h | 33 + 16 files changed, 2598 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml create mode 100644 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h create mode 100644 drivers/scsi/ufs/ufs-exynos.c create mode 100644 drivers/scsi/ufs/ufs-exynos.h base-commit: 0e698dfa282211e414076f9dc7e83c1c288314fd -- 2.17.1
