[PATCH v2 4/6] arm64: dts: qcom: sm8250: add wsa and va codec macros
Add support for WSA and VA codec macros along with WSA soundwire
controller required for getting audio on RB5.
Signed-off-by: Srinivas Kandagatla
Tested-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 56
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index ce8ae776160d..d2ade3ab3389 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2691,6 +2691,62 @@
};
};
+ wsamacro: codec@324 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wsa_swr_active>;
+
+ compatible = "qcom,sm8250-lpass-wsa-macro";
+ reg = <0 0x324 0 0x1000>;
+ clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
+ <&audiocc LPASS_CDC_WSA_NPL>,
+ <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&aoncc LPASS_CDC_VA_MCLK>,
+ <&vamacro>;
+
+ clock-names = "mclk", "npl", "macro", "dcodec", "va",
"fsgen";
+
+ #clock-cells = <0>;
+ clock-frequency = <960>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr0: soundwire-controller@325 {
+ reg = <0 0x325 0 0x2000>;
+ compatible = "qcom,soundwire-v1.5.1";
+ interrupts = ;
+ clocks = <&wsamacro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <2>;
+ qcom,dout-ports = <6>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1F
0x3F 0x07 0x1F 0x3F 0x0F 0x0F>;
+ qcom,ports-offset1 =/bits/ 8 <0x01 0x02
0x0C 0x06 0x12 0x0D 0x07 0x0A >;
+ qcom,ports-offset2 =/bits/ 8 <0xFF 0x00
0x1F 0xFF 0x00 0x1F 0x00 0x00>;
+ qcom,ports-block-pack-mode =/bits/ 8 <0x0 0x0 0x1
0x0 0x0 0x1 0x0 0x0>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ vamacro: codec@337 {
+ compatible = "qcom,sm8250-lpass-va-macro";
+ reg = <0 0x337 0 0x1000>;
+ clocks = <&aoncc LPASS_CDC_VA_MCLK>,
+ <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+
+ clock-names = "mclk", "macro", "dcodec";
+
+ #clock-cells = <0>;
+ clock-frequency = <960>;
+ clock-output-names = "fsgen";
+ #sound-dai-cells = <1>;
+ };
+
adsp: remoteproc@1730 {
compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x1730 0 0x100>;
--
2.21.0
[PATCH v2 1/6] arm64: dts: qcom: sm8250: add apr and its services
Add apr node and its associated services required for audio on RB5.
Signed-off-by: Srinivas Kandagatla
Tested-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 56
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 65acd1f381eb..d44120a6eadb 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -11,7 +11,9 @@
#include
#include
#include
+#include
#include
+#include
#include
/ {
@@ -2620,6 +2622,60 @@
label = "lpass";
qcom,remote-pid = <2>;
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,apr-domain = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ apr-service@3 {
+ reg = ;
+ compatible = "qcom,q6core";
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ };
+
+ q6afe: apr-service@4 {
+ compatible = "qcom,q6afe";
+ reg = ;
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ q6afedai: dais {
+ compatible =
"qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ q6afecc: cc {
+ compatible =
"qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+ };
+
+ q6asm: apr-service@7 {
+ compatible = "qcom,q6asm";
+ reg = ;
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ q6asmdai: dais {
+ compatible =
"qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu
0x1801 0x0>;
+ };
+ };
+
+ q6adm: apr-service@8 {
+ compatible = "qcom,q6adm";
+ reg = ;
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ q6routing: routing {
+ compatible =
"qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels =
"fastrpcglink-apps-dsp";
--
2.21.0
[PATCH v2 3/6] arm64: dts: qcom: sm8250: add lpass lpi pin controller node
Add LPASS LPI pinctrl node required for Audio functionality on RB5.
Signed-off-by: Srinivas Kandagatla
Tested-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 84
1 file changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index cddbb53db193..ce8ae776160d 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2607,6 +2607,90 @@
clock-names = "core", "audio", "bus";
};
+ lpass_tlmm: pinctrl@33c{
+ compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+ reg = <0 0x33c 0x0 0x2>,
+<0 0x355 0x0 0x1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 14>;
+
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ wsa_swr_active: wsa-swr-active-pins {
+ clk {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+
+ };
+ };
+
+ wsa_swr_sleep: wsa-swr-sleep-pins {
+ clk {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+
+ data {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+
+ };
+ };
+
+ dmic01_active: dmic01-active-pins {
+ clk {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+ data {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic01_sleep: dmic01-sleep-pins {
+ clk {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ data {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+ };
+
adsp: remoteproc@1730 {
compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x1730 0 0x100>;
--
2.21.0
[PATCH v2 0/6] arm64: dts: qcom: qrb5165-rb5 audio support
This patchset adds support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. All the audio related driver patches are merged via respective maintainer trees along with bindings. Only LPI pinctrl driver is not merged yet, however the bindings are acked by Rob, so am guessing that the dt changes should be okay to go! Thanks, srini Changes since v1: - updated pinctrl nodes as suggested by Bjorn - reordered include files. - removed unnecessary spaces - used mbn instead of mdt for adsp firmware Srinivas Kandagatla (6): arm64: dts: qcom: sm8250: add apr and its services arm64: dts: qcom: sm8250: add audio clock controllers arm64: dts: qcom: sm8250: add lpass lpi pin controller node arm64: dts: qcom: sm8250: add wsa and va codec macros arm64: dts: qcom: sm8250: add mi2s pinconfs arm64: dts: qcom: qrb5165-rb5: Add Audio support arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 121 ++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 276 +++ 2 files changed, 397 insertions(+) -- 2.21.0
[RESEND PATCH v6 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SM8250
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
Reviewed-by: Bjorn Andersson
---
.../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 ++
1 file changed, 130 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index ..e47ebf934daf
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ clocks:
+items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+const: 2
+
+ gpio-ranges:
+maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+type: object
+description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+$ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+properties:
+ pins:
+description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+items:
+ oneOf:
+- pattern: "^gpio([0-9]|[1-9][0-9])$"
+minItems: 1
+maxItems: 14
+
+ function:
+enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+dmic3_data, i2s2_data ]
+description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+enum: [2, 4, 6, 8, 10, 12, 14, 16]
+default: 2
+description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+0: No adjustments
+1: Higher Slew rate (faster edges)
+2: Lower Slew rate (slower edges)
+3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+required:
+ - pins
+ - function
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lpi_tlmm: pinctrl@33c {
+compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+reg = <0x33c 0x2>,
+ <0x355 0x1>;
+clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+clock-names = "core", "audio";
+gpio-controller;
+#gpio-cells = <2>;
+gpio-ranges = <&lpi_tlmm 0 0 14>;
+};
--
2.21.0
[RESEND PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 +++
3 files changed, 704 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..369ee20a7ea9
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,695 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASKBIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .slew_offset = soff,\
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5,
[RESEND PATCH v6 0/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl support
Sorry for the Noise, Resending this as previous one did not include Linus W email id!! This patch adds support for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This patch has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Am guessing existing qcom folder should cover maintining this driver too! If not I can send additional patch to consolidate this along with other Audio related drivers in Maintainer file! Changes since v5: - moved to use FIELD_* or u32_replace/encode apis where possible - remove all the SHIFT constants - updated function groups as suggested by Bjorn - updated setting slew rate as suggested by Bjorn Srinivas Kandagatla (2): dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 ++ 4 files changed, 834 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -- 2.21.0
[PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 +++
3 files changed, 704 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..369ee20a7ea9
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,695 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASKBIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .slew_offset = soff,\
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5,
[PATCH v6 0/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl support
This patch adds support for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This patch has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Am guessing existing qcom folder should cover maintining this driver too! If not I can send additional patch to consolidate this along with other Audio related drivers in Maintainer file! Changes since v5: - moved to use FIELD_* or u32_replace/encode apis where possible - remove all the SHIFT constants - updated function groups as suggested by Bjorn - updated setting slew rate as suggested by Bjorn Srinivas Kandagatla (2): dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 ++ 4 files changed, 834 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -- 2.21.0
[PATCH v6 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SM8250
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
Reviewed-by: Bjorn Andersson
---
.../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 ++
1 file changed, 130 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index ..e47ebf934daf
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ clocks:
+items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+const: 2
+
+ gpio-ranges:
+maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+type: object
+description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+$ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+properties:
+ pins:
+description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+items:
+ oneOf:
+- pattern: "^gpio([0-9]|[1-9][0-9])$"
+minItems: 1
+maxItems: 14
+
+ function:
+enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+dmic3_data, i2s2_data ]
+description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+enum: [2, 4, 6, 8, 10, 12, 14, 16]
+default: 2
+description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+0: No adjustments
+1: Higher Slew rate (faster edges)
+2: Lower Slew rate (slower edges)
+3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+required:
+ - pins
+ - function
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lpi_tlmm: pinctrl@33c {
+compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+reg = <0x33c 0x2>,
+ <0x355 0x1>;
+clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+clock-names = "core", "audio";
+gpio-controller;
+#gpio-cells = <2>;
+gpio-ranges = <&lpi_tlmm 0 0 14>;
+};
--
2.21.0
Re: [PATCH 1/6] arm64: dts: qcom: sm8250: add apr and its services
Many thanks Bjorn for review,
On 01/12/2020 19:25, Bjorn Andersson wrote:
On Tue 01 Dec 09:37 CST 2020, Srinivas Kandagatla wrote:
Add apr node and its associated services required for audio on RB5.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 56
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 65acd1f381eb..3b4e98b13d36 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -11,6 +11,8 @@
#include
#include
#include
+#include
+#include
Please move this line one step down to maintain the alphabetical sort
order.
I agree with all the comments on this patch as well as other patches,
will send v2 with those fixed!
Thanks,
srini
Thanks,
Bjorn
#include
#include
@@ -2620,6 +2622,60 @@
label = "lpass";
qcom,remote-pid = <2>;
+apr {
+ compatible = "qcom,apr-v2";
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,apr-domain = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ apr-service@3 {
+ reg = ;
+ compatible = "qcom,q6core";
+ qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
+ };
+
+ q6afe: apr-service@4 {
+ compatible = "qcom,q6afe";
+ reg = ;
+ qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
+ q6afedai: dais {
+ compatible =
"qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ q6afecc: cc {
+ compatible =
"qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+ };
+
+ q6asm: apr-service@7 {
+ compatible = "qcom,q6asm";
+ reg = ;
+ qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
+ q6asmdai: dais {
+ compatible =
"qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu
0x1801 0x0>;
+ };
+ };
+
+ q6adm: apr-service@8 {
+ compatible = "qcom,q6adm";
+ reg = ;
+ qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
+ q6routing: routing {
+ compatible =
"qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels =
"fastrpcglink-apps-dsp";
--
2.21.0
Re: [PATCH v4 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
On 01/12/2020 17:28, Bjorn Andersson wrote:
On Tue 01 Dec 04:01 CST 2020, Srinivas Kandagatla wrote:
Many thanks for review Bjorn,
On 01/12/2020 00:47, Bjorn Andersson wrote:
On Mon 16 Nov 08:34 CST 2020, Srinivas Kandagatla wrote:
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
Iiuc the LPI TLMM block is just "another pinmux/pinconf block" found in
these SoCs, with the additional magic that the 14 pads are muxed with
some of the TLMM pins - to allow the system integrator to choose how
many pins the LPI should have access to.
I also believe this is what the "egpio" bit in the TLMM registers are
used for (i.e. egpio = route to LPI, egpio = 1 route to TLMM), so we
should need to add support for toggling this bit in the TLMM as well
(which I think we should do as a pinconf in the pinctrl-msm).
Yes, we should add egpio function to these pins in main TLMM pinctrl!
I was thinking about abusing the pinconf system, but reading you
sentence makes me feel that expressing it as a "function" and adding a
special case handling in msm_pinmux_set_mux() would actually make things
much cleaner to the outside.
i.e. we would then end up with something in DT like:
pin-is-normal-tlmm-pin {
pins = "gpio146";
function = "gpio";
};
and
pin-routed-to-lpi-pin {
pins = "gpio146";
function = "egpio";
};
That is what I was thinking of.
Only "drawback" I can see is that we're inverting the chip's meaning of
"egpio" (i.e. active means route-to-tlmm in the hardware).
At somepoint we need to start defining what egpio really means w.r.t
pinctrl setup!
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
[..]
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
[..]
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_swr_tx_data1,
As there's no single pin that can be both data1 and data2 I think you
should have a single group for swr_tx_data and use this function for
both swr_tx_data pins. Or perhaps even just have one for swr or swr_tx.
(This is nice when you're writing DT later on)
I did think about this, but we have a rx_data2 pin in different function
compared to other rx data pins.
The reason to keep it as it is :
1> as this will bring in an additional complexity to the code
For each pin lpi_gpio_set_mux() will be invoked and you'd be searching
for the index (i) among that pins .funcs. So it doesn't matter that
looking up a particular function results in different register values
for different pins, it's already dealt with.
2> we have these represented exactly as what hw data sheet mentions it!
That is true, but the result is that you have to write 2 states in the
DT to get your 2 pins to switch to the particular function. By grouping
them you could do:
data-pins {
pins = "gpio1", "gpio2";
function = "swr_tx_data";
};
We do this quite extensively for the TLMM (pinctrl-msm) because it
results in cleaner DT.
These are now changed as requested!
+ LPI_MUX_qua_mi2s_ws,
[..]
+static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
+ .tlmm_reg_offset = 0x1000,
Do we have any platform in sight where this is not 0x1000? Could we just
make a define out of it?
Am not 100% sure ATM, But I wanted to keep this flexible as these offsets in
downstream were part of device tree for some reason, so having offset here
for particular compatible made more sense for me!
Downtream does indeed favor "flexible" code. I tend to prefer a #define
until we actually need the flexibility...
Done!
--srini
Regards,
Bjorn
Re: [PATCH v5 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
On 02/12/2020 09:56, Srinivas Kandagatla wrote:
+ case PIN_CONFIG_SLEW_RATE:
+ if (arg > LPI_SLEW_RATE_MAX) {
+ dev_err(pctldev->dev, "invalid slew rate %u for pin:
%d\n",
+ arg, group);
+ return -EINVAL;
+ }
+
+ slew_offset = g->slew_offset;
+ if (slew_offset == NO_SLEW)
+ break;
+
+ mutex_lock(&pctrl->slew_access_lock);
+ sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
+
+ for (i = 0; i < LPI_SLEW_BITS_SIZE; i++) {
+ assign_bit(slew_offset, &sval, arg & 0x01);
+ slew_offset++;
+ arg = arg >> 1;
+ }
Isn't this loop just the same as
FIELD_SET(3 << slew_offset, arg & 3, sval)
None of FIELD_* or replace_bits apis will work here, as the mask passed
to those macros should be a constant #define. Passing variable to them
in mask will result in compile error!
mask in this case is retrieved at runtime.
I think we should live with the existing code unless there is a strong
reason for it to change! Or a better alternative.
--srini
This will not work FIELD_SET will not clear any bits wich are already
set! assing_bit will work, but we could do better by adding slew_mask
per pin rather than slew_offset which should allow us to use
replace_bits straight away.
Re: [PATCH v5 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Thanks Alex for the comments, On 01/12/2020 20:21, Alex Elder wrote: On 12/1/20 8:28 AM, Srinivas Kandagatla wrote: Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla Bjorn called my attention to a comment he made on this patch. I'm not giving it a full review right now, but I have a general suggestion below. --- drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 727 +++ 3 files changed, 736 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 5fe7b8aaf69d..d3e4e89c2810 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -236,4 +236,12 @@ config PINCTRL_SM8250 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8250 platform. +config PINCTRL_LPASS_LPI + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + depends on GPIOLIB + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SoCs. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 9e3d9c91a444..c8520155fb1b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o +obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c new file mode 100644 index ..96c63a33fc99 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../core.h" +#include "../pinctrl-utils.h" + +#define LPI_GPIO_CFG_REG 0x00 +#define LPI_GPIO_VALUE_REG 0x04 +#define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_SLEW_RATE_MAX 0x03 +#define LPI_SLEW_BITS_SIZE 0x02 +#define LPI_GPIO_PULL_SHIFT 0x0 +#define LPI_GPIO_PULL_MASK GENMASK(1, 0) . . . If you have a mask like this, you do not need the shift. The mask alone encodes both the position and the width of the field you are describing. It is better to use just the one (mask) value and avoid even the possibility of the mask and shift being inconsistent. You halve the number of symbols you need to describe fields too. I did realize that while I was doing replace bits ,but did not go further in possibility of removing the redundant macros! For the macros and functions in the mask values must be constant at compile time, but you have that here. For the LPI_GPIO_PULL, you use it below this way: pull = (ctl_reg & LPI_GPIO_PULL_MASK) >> LPI_GPIO_PULL_SHIFT; Instead, use: pull = u32_get_bits(ctl_reg, LPI_GPIO_PULL_MASK); I see you're using u32_replace_bits(), and what I see looks good. But you can use u32_encode_bits() as well. For example, instead of: lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, value << LPI_GPIO_DIR_SHIFT); Use: val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_DIR_MASK); lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); (This one-bit mask might not be a great example.) In addition to getting rid of extra symbols, using these functions typically results in simpler-looking code. Many thanks for the examples, Will convert to either using FIELD_* macros or u32_encode/get apis and remove redundant SHIFT macros! --srini -Alex
Re: [PATCH v5 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Thanks Bjorn for the review,
On 01/12/2020 19:48, Bjorn Andersson wrote:
On Tue 01 Dec 08:28 CST 2020, Srinivas Kandagatla wrote:
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 727 +++
3 files changed, 736 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..96c63a33fc99
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,727 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_GPIO_PULL_SHIFT0x0
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_SHIFT0x2
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_SHIFT0x6
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_SHIFT 0x9
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_DIR_SHIFT 0x1
+#define LPI_GPIO_DIR_MASK 0x2
The naming of these two constants no longer relates the their register.
And you no longer use the MASK, so please drop this.
Yes, most of these defines are redundant can be removed, I will clean
that up!
That said the use of "shift" still doesn't give away the obvious fact
that this is a single bit specifying if the output should be high or
low. You would capture this by doing something like:
#define LPI_GPIO_VALUE_HIGH BIT(1)
Sure will make this explicit!
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) ((v / 2 - 1) << LPI_GPIO_OUT_STRENGTH_SHIFT)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+
+static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
+ unsigned int group_num
[PATCH 6/6] arm64: dts: qcom: qrb5165-rb5: Add Audio support
This patch add support for two WSA881X smart speakers attached via Soundwire
and a DMIC0 on the main board.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 125 +++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index ce22d4fa383e..03229d5cb9d3 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -7,6 +7,8 @@
#include
#include
+#include
+#include
#include "sm8250.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@@ -120,6 +122,11 @@
};
};
+&adsp {
+ status = "okay";
+ firmware-name = "qcom/sm8250/adsp.mdt";
+};
+
&apps_rsc {
pm8009-rpmh-regulators {
compatible = "qcom,pm8009-rpmh-regulators";
@@ -483,6 +490,35 @@
status = "okay";
};
+&q6afedai {
+ qi2s@16 {
+ reg = <16>;
+ qcom,sd-lines = <0 1 2 3>;
+ };
+};
+
+/* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */
+&q6afedai {
+ qi2s@20 {
+ reg = <20>;
+ qcom,sd-lines = <0>;
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+};
+
&sdhc_2 {
status = "okay";
pinctrl-names = "default";
@@ -497,6 +533,88 @@
no-emmc;
};
+&swr0 {
+
+ left_spkr: wsa8810-left{
+ compatible = "sdw10217211000";
+ reg = <0 3>;
+ powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
+ #thermal-sensor-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ #sound-dai-cells = <0>;
+ };
+
+
+ right_spkr: wsa8810-right{
+ compatible = "sdw10217211000";
+ reg = <0 4>;
+ powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
+ #thermal-sensor-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ #sound-dai-cells = <0>;
+ };
+};
+
+&sound {
+ compatible = "qcom,qrb5165-rb5";
+ pinctrl-0 = <&tert_mi2s_sck_active
+&tert_mi2s_sd0_active
+&tert_mi2s_ws_active>;
+ pinctrl-names = "default";
+ model = "Qualcomm-RB5-WSA8815-Speakers-DMIC0";
+ audio-routing =
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA DMIC0", "vdd-micb",
+"VA DMIC1", "vdd-micb",
+ "MM_DL1", "MultiMedia1 Playback",
+ "MultiMedia3 Capture", "MM_UL3";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ dma-dai-link {
+ link-name = "WSA Playback";
+ cpu {
+ sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>,
<&wsamacro 0>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+ cpu {
+ sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&vamacro 0>;
+ };
+ };
+};
+
/* CAN */
&spi0 {
status = "okay";
@@ -792,3 +910,10 @@
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p92>;
};
+
+&vamacro {
+ pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
+ pinctrl-names = "default";
+ vdd-micb-supply = <&vreg_s4a_1p8>;
+ qcom,dmic-sample-rate = <60>;
+};
--
2.21.0
[PATCH 5/6] arm64: dts: qcom: sm8250: add mi2s pinconfs
Add primary and tertinary mi2s pinconfs required to get I2S audio.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 98
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 19dd7460e586..a87940e157be 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1561,6 +1561,9 @@
};
};
+ sound: sound {
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8250-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
@@ -1884,6 +1887,60 @@
gpio-ranges = <&tlmm 0 0 180>;
wakeup-parent = <&pdc>;
+ pri_mi2s_sck_active: pri-mi2s-sck-active {
+ mux {
+ pins = "gpio138";
+ function = "mi2s0_sck";
+ };
+
+ config {
+ pins = "gpio138";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ pri_mi2s_ws_active: pri-mi2s-ws-active {
+ mux {
+ pins = "gpio141";
+ function = "mi2s0_ws";
+ };
+
+ config {
+ pins = "gpio141";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ pri_mi2s_sd0_active: pri-mi2s-sd0-active {
+ mux {
+ pins = "gpio139";
+ function = "mi2s0_data0";
+ };
+
+ config {
+ pins = "gpio139";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ pri_mi2s_sd1_active: pri-mi2s-sd1-active {
+ mux {
+ pins = "gpio140";
+ function = "mi2s0_data1";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
qup_i2c0_default: qup-i2c0-default {
mux {
pins = "gpio28", "gpio29";
@@ -2480,6 +2537,47 @@
function = "qup18";
};
};
+
+ tert_mi2s_sck_active: tert-mi2s-sck-active {
+ mux {
+ pins = "gpio133";
+ function = "mi2s2_sck";
+ };
+
+ config {
+ pins = "gpio133";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ tert_mi2s_sd0_active: tert-mi2s-sd0-active {
+ mux {
+ pins = "gpio134";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio134";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ tert_mi2s_ws_active: tert-mi2s-ws-acti
[PATCH 4/6] arm64: dts: qcom: sm8250: add wsa and va codec macros
Add support for WSA and VA codec macros along with WSA soundwire
controller required for getting audio on RB5.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 56
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4e1309b6571e..19dd7460e586 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2702,6 +2702,62 @@
};
};
+ wsamacro: codec@324 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
+
+ compatible = "qcom,sm8250-lpass-wsa-macro";
+ reg = <0 0x324 0 0x1000>;
+ clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
+ <&audiocc LPASS_CDC_WSA_NPL>,
+ <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&aoncc LPASS_CDC_VA_MCLK>,
+ <&vamacro>;
+
+ clock-names = "mclk", "npl", "macro", "dcodec", "va",
"fsgen";
+
+ #clock-cells = <0>;
+ clock-frequency = <960>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr0: soundwire-controller@325 {
+ reg = <0 0x325 0 0x2000>;
+ compatible = "qcom,soundwire-v1.5.1";
+ interrupts = ;
+ clocks = <&wsamacro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <2>;
+ qcom,dout-ports = <6>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1F
0x3F 0x07 0x1F 0x3F 0x0F 0x0F>;
+ qcom,ports-offset1 =/bits/ 8 <0x01 0x02
0x0C 0x06 0x12 0x0D 0x07 0x0A >;
+ qcom,ports-offset2 =/bits/ 8 <0xFF 0x00
0x1F 0xFF 0x00 0x1F 0x00 0x00>;
+ qcom,ports-block-pack-mode =/bits/ 8 <0x0 0x0 0x1
0x0 0x0 0x1 0x0 0x0>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ vamacro: codec@337 {
+ compatible = "qcom,sm8250-lpass-va-macro";
+ reg = <0 0x337 0 0x1000>;
+ clocks = <&aoncc LPASS_CDC_VA_MCLK>,
+ <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+
+ clock-names = "mclk", "macro", "dcodec";
+
+ #clock-cells = <0>;
+ clock-frequency = <960>;
+ clock-output-names = "fsgen";
+ #sound-dai-cells = <1>;
+ };
+
adsp: remoteproc@1730 {
compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x1730 0 0x100>;
--
2.21.0
[PATCH 2/6] arm64: dts: qcom: sm8250: add audio clock controllers
Add audiocc and aoncc clock controller nodes required for audio on RB5.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 3b4e98b13d36..ec5b53b8f656 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -6,6 +6,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -2585,6 +2587,26 @@
;
};
+ audiocc: clock-controller@330 {
+ compatible = "qcom,sm8250-lpass-audiocc";
+ reg = <0 0x0330 0 0x3>;
+ #clock-cells = <1>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio", "bus";
+ };
+
+ aoncc: clock-controller@338 {
+ compatible = "qcom,sm8250-lpass-aoncc";
+ reg = <0 0x0338 0 0x4>;
+ #clock-cells = <1>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio", "bus";
+ };
+
adsp: remoteproc@1730 {
compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x1730 0 0x100>;
--
2.21.0
[PATCH 3/6] arm64: dts: qcom: sm8250: add lpass lpi pin controller node
Add LPASS LPI pinctrl node required for Audio functionality on RB5.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 95
1 file changed, 95 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index ec5b53b8f656..4e1309b6571e 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2607,6 +2607,101 @@
clock-names = "core", "audio", "bus";
};
+ lpass_tlmm: pinctrl@33c{
+ compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+ reg = <0 0x33c 0x0 0x2>,
+<0 0x355 0x0 0x1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 14>;
+
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE
LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ wsa_swr_clk_pin {
+ wsa_swr_clk_sleep: wsa_swr_clk_sleep {
+ mux {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_clk_active: wsa_swr_clk_active {
+ mux {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+ };
+
+ wsa_swr_data_pin {
+ wsa_swr_data_sleep: wsa_swr_data_sleep {
+ mux {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_data_active: wsa_swr_data_active {
+ mux {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ cdc_dmic01_data_active: dmic01_data_active {
+ mux {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_data_sleep: dmic01_data_sleep {
+ mux {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_clk_active: dmic01_clk_active {
+ mux {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
[PATCH 1/6] arm64: dts: qcom: sm8250: add apr and its services
Add apr node and its associated services required for audio on RB5.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 56
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 65acd1f381eb..3b4e98b13d36 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -11,6 +11,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -2620,6 +2622,60 @@
label = "lpass";
qcom,remote-pid = <2>;
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,apr-domain = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ apr-service@3 {
+ reg = ;
+ compatible = "qcom,q6core";
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ };
+
+ q6afe: apr-service@4 {
+ compatible = "qcom,q6afe";
+ reg = ;
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ q6afedai: dais {
+ compatible =
"qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ q6afecc: cc {
+ compatible =
"qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+ };
+
+ q6asm: apr-service@7 {
+ compatible = "qcom,q6asm";
+ reg = ;
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ q6asmdai: dais {
+ compatible =
"qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu
0x1801 0x0>;
+ };
+ };
+
+ q6adm: apr-service@8 {
+ compatible = "qcom,q6adm";
+ reg = ;
+ qcom,protection-domain =
"avs/audio", "msm/adsp/audio_pd";
+ q6routing: routing {
+ compatible =
"qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels =
"fastrpcglink-apps-dsp";
--
2.21.0
[PATCH 0/6] arm64: dts: qcom: qrb5165-rb5 audio support
This patchset adds support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. All the audio related driver patches are merged via respective maintainer trees along with bindings. Only LPI pinctrl driver is not merged yet, however the bindings are acked by Rob, so am guessing that the dt changes should be okay to go! Thanks, srini Srinivas Kandagatla (6): arm64: dts: qcom: sm8250: add apr and its services arm64: dts: qcom: sm8250: add audio clock controllers arm64: dts: qcom: sm8250: add lpass lpi pin controller node arm64: dts: qcom: sm8250: add wsa and va codec macros arm64: dts: qcom: sm8250: add mi2s pinconfs arm64: dts: qcom: qrb5165-rb5: Add Audio support arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 125 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 327 +++ 2 files changed, 452 insertions(+) -- 2.21.0
[PATCH v5 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 727 +++
3 files changed, 736 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..96c63a33fc99
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,727 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_GPIO_PULL_SHIFT0x0
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_SHIFT0x2
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_SHIFT0x6
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_SHIFT 0x9
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_DIR_SHIFT 0x1
+#define LPI_GPIO_DIR_MASK 0x2
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) ((v / 2 - 1) << LPI_GPIO_OUT_STRENGTH_SHIFT)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .slew_offset = soff,\
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f
[PATCH v5 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SM8250
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
---
.../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 132 ++
1 file changed, 132 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index ..3543324d9194
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ clocks:
+items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+const: 2
+
+ gpio-ranges:
+maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+type: object
+description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+$ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+properties:
+ pins:
+description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+items:
+ oneOf:
+- pattern: "^gpio([0-9]|[1-9][0-9])$"
+minItems: 1
+maxItems: 14
+
+ function:
+enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws,
+swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1,
+swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2,
+dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk,
+i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk,
+i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data,
+i2s2_data1 ]
+description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+enum: [2, 4, 6, 8, 10, 12, 14, 16]
+default: 2
+description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+0: No adjustments
+1: Higher Slew rate (faster edges)
+2: Lower Slew rate (slower edges)
+3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+required:
+ - pins
+ - function
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lpi_tlmm: pinctrl@33c {
+compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+reg = <0x33c 0x2>,
+ <0x355 0x1>;
+clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+clock-names = "core", "audio";
+gpio-controller;
+#gpio-cells = <2>;
+gpio-ranges = <&lpi_tlmm 0 0 14>;
+};
--
2.21.0
[PATCH v5 0/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl support
This patch adds support for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This patch has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Am guessing existing qcom folder should cover maintining this driver too! If not I can send additional patch to consolidate this along with other Audio related drivers in Maintainer file! Changes since v4: - added Rob's review - updated slew reg range - used u32p_replace_bits - sorted pin functions and its defines - address various trivial comments from Bjorn Srinivas Kandagatla (2): dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 132 drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 727 ++ 4 files changed, 868 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -- 2.21.0
Re: [PATCH v4 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
On 01/12/2020 00:55, Bjorn Andersson wrote: +reg = <0x33c 0x2>, + <0x355a000 0x1000>; We shouldn't reference parts of blocks, so this should be 16KB at yes, makes sense! Will change the example accordingly! 0x3550 and if we have multiple drivers that needs to poke in that region we'd need to abstract that somehow (e.g. though a syscon).Yes! Regards, Bjorn
Re: [PATCH v4 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Many thanks for review Bjorn, On 01/12/2020 00:47, Bjorn Andersson wrote: On Mon 16 Nov 08:34 CST 2020, Srinivas Kandagatla wrote: Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] Iiuc the LPI TLMM block is just "another pinmux/pinconf block" found in these SoCs, with the additional magic that the 14 pads are muxed with some of the TLMM pins - to allow the system integrator to choose how many pins the LPI should have access to. I also believe this is what the "egpio" bit in the TLMM registers are used for (i.e. egpio = route to LPI, egpio = 1 route to TLMM), so we should need to add support for toggling this bit in the TLMM as well (which I think we should do as a pinconf in the pinctrl-msm). Yes, we should add egpio function to these pins in main TLMM pinctrl! This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Seems like this is just a property of what functions they routed in this region of the TLMM - and when egpio = 1 it could have been anything else. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla --- drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile| 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 734 +++ 3 files changed, 743 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 5fe7b8aaf69d..d3e4e89c2810 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -236,4 +236,12 @@ config PINCTRL_SM8250 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8250 platform. +config PINCTRL_LPASS_LPI + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + depends on GPIOLIB + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SoCs. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 9e3d9c91a444..c8520155fb1b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o +obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c new file mode 100644 index ..63cfbb2d032a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../core.h" +#include "../pinctrl-utils.h" + +#define LPI_GPIO_REG_VAL_CTL 0x00 I think LPI_GPIO_CFG_REG would be a better name for this. +#define LPI_GPIO_REG_DIR_CTL 0x04 Afaict, BIT(9) of LPI_GPIO_CFG_REG controls of the if the pin should be output or not. This register provides the read value as BIT(0) and the output value in BIT(1). So this would rather be the LPI_GPIO_VALUE_REG. Yes, that is true, will change it accordingly! +#define LPI_SLEW_REG_VAL_CTL 0x00 +#define LPI_SLEW_RATE_MAX0x03 +#define LPI_SLEW_BITS_SIZE 0x02 +#define LPI_GPIO_REG_PULL_SHIFT0x0 +#define LPI_GPIO_REG_PULL_MASK GENMASK(1, 0) +#define LPI_GPIO_REG_FUNCTION_SHIFT0x2 +#define LPI_GPIO_REG_FUNCTION_MASK GENMASK(5, 2) +#define LPI_GPIO_REG_OUT_STRENGTH_SHIFT0x6 +#define LPI_GPIO_REG_OUT_STRENGTH_MASK GENMASK(8, 6) +#define LPI_GPIO_REG_OE_SHIFT 0x9 +#define LPI_GPIO_REG_OE_MASK BIT(9) +#define LPI_GPIO_REG_DIR_SHIFT 0x1 +#define LPI_GPIO_REG_DIR_MASK 0x2 +#define LPI_GPIO_BIAS_DISABLE 0x0 +#define LPI_GPIO_PULL_DOWN 0x1 +#define LPI_GPIO_KEEPER
[PATCH] slimbus: qcom-ngd-ctrl: fix SSR dependencies
NGD should depend on QCOM_RPROC_COMMON instead of selecting it, as this will be selected by respective remoteproc driver. Reported-by: kernel test robot Signed-off-by: Srinivas Kandagatla --- drivers/slimbus/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig index 7d59956b5dfb..1235b7dc8496 100644 --- a/drivers/slimbus/Kconfig +++ b/drivers/slimbus/Kconfig @@ -22,10 +22,9 @@ config SLIM_QCOM_CTRL config SLIM_QCOM_NGD_CTRL tristate "Qualcomm SLIMbus Satellite Non-Generic Device Component" - depends on HAS_IOMEM && DMA_ENGINE && NET && REMOTEPROC + depends on HAS_IOMEM && DMA_ENGINE && NET && QCOM_RPROC_COMMON depends on ARCH_QCOM || COMPILE_TEST select QCOM_QMI_HELPERS - select QCOM_RPROC_COMMON select QCOM_PDR_HELPERS help Select driver if Qualcomm's SLIMbus Satellite Non-Generic Device -- 2.21.0
Re: [PATCH v4 2/2] ASoC: qcom: Add support for playback recover after resume
On 28/11/2020 04:59, Srinivasa Rao Mandadapu wrote:
To support playback continuation after hard suspend(bypass powerd)
and resume add component driver ops and do regcache sync.
Signed-off-by: V Sujith Kumar Reddy
Signed-off-by: Srinivasa Rao Mandadapu
LGTM,
Reviewed-by: Srinivas Kandagatla
---
sound/soc/qcom/lpass-platform.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c
index 0e71899..12764a8 100644
--- a/sound/soc/qcom/lpass-platform.c
+++ b/sound/soc/qcom/lpass-platform.c
@@ -827,6 +827,39 @@ static void lpass_platform_pcm_free(struct
snd_soc_component *component,
}
}
+static int lpass_platform_pcmops_suspend(struct snd_soc_component *component)
+{
+ struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
+ struct regmap *map;
+ unsigned int dai_id = component->id;
+
+ if (dai_id == LPASS_DP_RX)
+ map = drvdata->hdmiif_map;
+ else
+ map = drvdata->lpaif_map;
+
+ regcache_cache_only(map, true);
+ regcache_mark_dirty(map);
+
+ return 0;
+}
+
+static int lpass_platform_pcmops_resume(struct snd_soc_component *component)
+{
+ struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
+ struct regmap *map;
+ unsigned int dai_id = component->id;
+
+ if (dai_id == LPASS_DP_RX)
+ map = drvdata->hdmiif_map;
+ else
+ map = drvdata->lpaif_map;
+
+ regcache_cache_only(map, false);
+ return regcache_sync(map);
+}
+
+
static const struct snd_soc_component_driver lpass_component_driver = {
.name = DRV_NAME,
.open = lpass_platform_pcmops_open,
@@ -839,6 +872,8 @@ static const struct snd_soc_component_driver
lpass_component_driver = {
.mmap = lpass_platform_pcmops_mmap,
.pcm_construct = lpass_platform_pcm_new,
.pcm_destruct = lpass_platform_pcm_free,
+ .suspend= lpass_platform_pcmops_suspend,
+ .resume = lpass_platform_pcmops_resume,
};
Re: [PATCH v4 1/2] Partially revert ASoC: qcom: Fix enabling BCLK and LRCLK in LPAIF invalid state
On 28/11/2020 04:59, Srinivasa Rao Mandadapu wrote:
This reverts part of commit b1824968221c
("ASoC: qcom: Fix enabling BCLK and LRCLK in LPAIF invalid state")
This should probably go to Fixes tag!
To identify LPAIF invalid state after device suspend and resume,
made I2S and DMA control registers not volatile, which is not necessary.
This comment is bit confusing!
Basically it should be something like
"DMA control registers are not volatile, so remove these from volatile
registers list"
--srini
Instead invalid reg state can be handled with regcache APIs.
The BCLK ref count is necessary to enable clock only it's in disable state.
Signed-off-by: V Sujith Kumar Reddy
Signed-off-by: Srinivasa Rao Mandadapu
---
sound/soc/qcom/lpass-cpu.c | 20 ++--
sound/soc/qcom/lpass-platform.c | 11 ---
2 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c
index af684fd..c5e99c2 100644
--- a/sound/soc/qcom/lpass-cpu.c
+++ b/sound/soc/qcom/lpass-cpu.c
@@ -270,18 +270,6 @@ static int lpass_cpu_daiops_trigger(struct
snd_pcm_substream *substream,
struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
unsigned int id = dai->driver->id;
int ret = -EINVAL;
- unsigned int val = 0;
-
- ret = regmap_read(drvdata->lpaif_map,
- LPAIF_I2SCTL_REG(drvdata->variant,
dai->driver->id), &val);
- if (ret) {
- dev_err(dai->dev, "error reading from i2sctl reg: %d\n", ret);
- return ret;
- }
- if (val == LPAIF_I2SCTL_RESET_STATE) {
- dev_err(dai->dev, "error in i2sctl register state\n");
- return -ENOTRECOVERABLE;
- }
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
@@ -454,20 +442,16 @@ static bool lpass_cpu_regmap_volatile(struct device *dev,
unsigned int reg)
struct lpass_variant *v = drvdata->variant;
int i;
- for (i = 0; i < v->i2s_ports; ++i)
- if (reg == LPAIF_I2SCTL_REG(v, i))
- return true;
for (i = 0; i < v->irq_ports; ++i)
if (reg == LPAIF_IRQSTAT_REG(v, i))
return true;
for (i = 0; i < v->rdma_channels; ++i)
- if (reg == LPAIF_RDMACURR_REG(v, i) || reg ==
LPAIF_RDMACTL_REG(v, i))
+ if (reg == LPAIF_RDMACURR_REG(v, i))
return true;
for (i = 0; i < v->wrdma_channels; ++i)
- if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start) ||
- reg == LPAIF_WRDMACTL_REG(v, i +
v->wrdma_channel_start))
+ if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
return true;
return false;
diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c
index 80b09de..0e71899 100644
--- a/sound/soc/qcom/lpass-platform.c
+++ b/sound/soc/qcom/lpass-platform.c
@@ -452,7 +452,6 @@ static int lpass_platform_pcmops_trigger(struct
snd_soc_component *component,
unsigned int reg_irqclr = 0, val_irqclr = 0;
unsigned int reg_irqen = 0, val_irqen = 0, val_mask = 0;
unsigned int dai_id = cpu_dai->driver->id;
- unsigned int dma_ctrl_reg = 0;
ch = pcm_data->dma_ch;
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
@@ -469,17 +468,7 @@ static int lpass_platform_pcmops_trigger(struct
snd_soc_component *component,
id = pcm_data->dma_ch - v->wrdma_channel_start;
map = drvdata->lpaif_map;
}
- ret = regmap_read(map, LPAIF_DMACTL_REG(v, ch, dir, dai_id),
&dma_ctrl_reg);
- if (ret) {
- dev_err(soc_runtime->dev, "error reading from rdmactl reg:
%d\n", ret);
- return ret;
- }
- if (dma_ctrl_reg == LPAIF_DMACTL_RESET_STATE ||
- dma_ctrl_reg == LPAIF_DMACTL_RESET_STATE + 1) {
- dev_err(soc_runtime->dev, "error in rdmactl register state\n");
- return -ENOTRECOVERABLE;
- }
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
Re: [PATCH v3 1/2] arm64: dts: qcom: sc7180: Update lpass cpu node for audio over dp
On 30/09/2020 07:42, Srinivasa Rao Mandadapu wrote:
From: V Sujith Kumar Reddy
Updaate lpass dts node with HDMI reg, interrupt and iommu
for supporting audio over dp.
Signed-off-by: Srinivasa Rao Mandadapu
Signed-off-by: V Sujith Kumar Reddy
Reviewed-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 427a4bf..802ea0a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
/ {
interrupt-parent = <&intc>;
@@ -3428,16 +3429,18 @@
#power-domain-cells = <1>;
};
- lpass_cpu: lpass@62f0 {
+ lpass_cpu: lpass@62d87000 {
compatible = "qcom,sc7180-lpass-cpu";
- reg = <0 0x62f0 0 0x29000>;
- reg-names = "lpass-lpaif";
+ reg = <0 0x62d87000 0 0x68000>, <0 0x62f0 0
0x29000>;
+ reg-names = "lpass-hdmiif", "lpass-lpaif";
- iommus = <&apps_smmu 0x1020 0>;
+ iommus = <&apps_smmu 0x1020 0>, <&apps_smmu 0x1032 0>;
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
+ status = "disabled";
+
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
<&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
<&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
@@ -3449,13 +3452,13 @@
"mclk0", "pcnoc-mport-clk",
"mi2s-bit-clk0", "mi2s-bit-clk1";
-
#sound-dai-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = ;
- interrupt-names = "lpass-irq-lpaif";
+ interrupts = ,
+ ;
+ interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
};
lpass_hm: clock-controller@6300 {
Re: [PATCH v3 2/2] arm64: dts: qcom: sc7180-trogdor: Add lpass dai link for HDMI
On 30/09/2020 07:42, Srinivasa Rao Mandadapu wrote:
From: V Sujith Kumar Reddy
Add dai link in sc7180-trogdor.dtsi for supporting audio over DP
Signed-off-by: V Sujith Kumar Reddy
Signed-off-by: Srinivasa Rao Mandadapu
Reviewed-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 5724982..850b43e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -231,6 +231,7 @@
audio-jack = <&alc5682>;
+ #sound-dai-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -257,6 +258,17 @@
sound-dai = <&max98357a>;
};
};
+ dai-link@2 {
+ link-name = "MultiMedia2";
+ reg = <2>;
+ cpu {
+ sound-dai = <&lpass_cpu 2>;
+ };
+
+ codec {
+ sound-dai = <&msm_dp>;
+ };
+ };
};
};
@@ -782,6 +794,9 @@ hp_i2c: &i2c9 {
reg = ;
qcom,playback-sd-lines = <0>;
};
+ hdmi-primary@0 {
+ reg = ;
+ };
};
&mdp {
Re: [PATCH v4] arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver
On 18/09/2020 18:33, Srinivasa Rao Mandadapu wrote:
From: Ajit Pandey
Add the I2S controller node to sc7180 dtsi.
Add pinmux for primary and secondary I2S.
Signed-off-by: Ajit Pandey
Signed-off-by: Cheng-Yi Chiang
Signed-off-by: V Sujith Kumar Reddy
Signed-off-by: Srinivasa Rao Mandadapu
---
Reviewed-by: Srinivas Kandagatla
Changes since v3:
-- The typo error fix
Changes since v2:
-- The plement of lpass_cpu node is changed
Changes since v1:
-- Updated I2S pin control nodes with grouping common pin controls
-- Updated lpass_cpu node with proper control names
arch/arm64/boot/dts/qcom/sc7180.dtsi | 69
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6678f1e..427a4bf 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1742,6 +1742,45 @@
};
};
+ sec_mi2s_active: sec-mi2s-active {
+ pinmux {
+ pins = "gpio49", "gpio50", "gpio51";
+ function = "mi2s_1";
+ };
+
+ pinconf {
+ pins = "gpio49", "gpio50", "gpio51";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ pri_mi2s_active: pri-mi2s-active {
+ pinmux {
+ pins = "gpio53", "gpio54", "gpio55",
"gpio56";
+ function = "mi2s_0";
+ };
+
+ pinconf {
+ pins = "gpio53", "gpio54", "gpio55",
"gpio56";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ pri_mi2s_mclk_active: pri-mi2s-mclk-active {
+ pinmux {
+ pins = "gpio57";
+ function = "lpass_ext";
+ };
+
+ pinconf {
+ pins = "gpio57";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
sdc1_on: sdc1-on {
pinconf-clk {
pins = "sdc1_clk";
@@ -3389,6 +3428,36 @@
#power-domain-cells = <1>;
};
+ lpass_cpu: lpass@62f0 {
+ compatible = "qcom,sc7180-lpass-cpu";
+
+ reg = <0 0x62f0 0 0x29000>;
+ reg-names = "lpass-lpaif";
+
+ iommus = <&apps_smmu 0x1020 0>;
+
+ power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
+
+ clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
+<&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
+<&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
+<&lpasscc
LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
+<&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
+<&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
+
+ clock-names = "pcnoc-sway-clk", "audio-core",
+ "mclk0", "pcnoc-mport-clk",
+ "mi2s-bit-clk0", "mi2s-bit-clk1";
+
+
+ #sound-dai-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupts = ;
+ interrupt-names = "lpass-irq-lpaif";
+ };
+
lpass_hm: clock-controller@6300 {
compatible = "qcom,sc7180-lpasshm";
reg = <0 0x6300 0 0x28>;
Re: [PATCH v3] ASoC: qcom: Fix playback recover problem in suspend resume
On 27/11/2020 09:56, Srinivasa Rao Mandadapu wrote:
To support playback continuation after hard suspend(bypass powerd)
and resume:
Prepare device in platform trigger callback.
Make I2s and DMA control registers as non volatile.
Looks like there are two changes here, One is fixing the volatile registers!
Other is preparing device after suspend!
Consider splitting them!
Fixes tag is missing here?
Signed-off-by: V Sujith Kumar Reddy
Signed-off-by: Srinivasa Rao Mandadapu
---
Changes Since v1 and v2:
-- Subject lines changed
sound/soc/qcom/lpass-cpu.c | 8 ++--
sound/soc/qcom/lpass-platform.c | 5 +++--
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c
index af684fd..c99be03 100644
--- a/sound/soc/qcom/lpass-cpu.c
+++ b/sound/soc/qcom/lpass-cpu.c
@@ -454,20 +454,16 @@ static bool lpass_cpu_regmap_volatile(struct device *dev,
unsigned int reg)
struct lpass_variant *v = drvdata->variant;
int i;
- for (i = 0; i < v->i2s_ports; ++i)
- if (reg == LPAIF_I2SCTL_REG(v, i))
- return true;
for (i = 0; i < v->irq_ports; ++i)
if (reg == LPAIF_IRQSTAT_REG(v, i))
return true;
for (i = 0; i < v->rdma_channels; ++i)
- if (reg == LPAIF_RDMACURR_REG(v, i) || reg ==
LPAIF_RDMACTL_REG(v, i))
+ if (reg == LPAIF_RDMACURR_REG(v, i))
return true;
for (i = 0; i < v->wrdma_channels; ++i)
- if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start) ||
- reg == LPAIF_WRDMACTL_REG(v, i +
v->wrdma_channel_start))
+ if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
return true;
return false;
diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c
index 80b09de..2b0a7c1 100644
--- a/sound/soc/qcom/lpass-platform.c
+++ b/sound/soc/qcom/lpass-platform.c
@@ -481,8 +481,9 @@ static int lpass_platform_pcmops_trigger(struct
snd_soc_component *component,
return -ENOTRECOVERABLE;
}
switch (cmd) {
- case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
+ lpass_platform_pcmops_prepare(component, substream);
Can you elaborate the actual issue here?
Are any other registers needs to re-programmed??
Does it make sense to use
regcache_mark_dirty()
regcache_sync() in pm suspend resume path,
instead of calling prepare explicitly?
--srini
+ case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = regmap_fields_write(dmactl->enable, id,
LPAIF_DMACTL_ENABLE_ON);
@@ -592,7 +593,7 @@ static int lpass_platform_pcmops_trigger(struct
snd_soc_component *component,
break;
}
- return 0;
+ return ret;
}
static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
[PATCH 3/5] dt-bindings: nvmem: Add soc qfprom compatible strings
From: Evan Green
Add SoC-specific compatible strings so that data can be attached
to it in the driver.
Signed-off-by: Evan Green
Reviewed-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
---
.../devicetree/bindings/nvmem/qcom,qfprom.yaml | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 1a18b6bab35e..992777c90a0b 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -14,7 +14,18 @@ allOf:
properties:
compatible:
-const: qcom,qfprom
+items:
+ - enum:
+ - qcom,apq8064-qfprom
+ - qcom,apq8084-qfprom
+ - qcom,msm8974-qfprom
+ - qcom,msm8916-qfprom
+ - qcom,msm8996-qfprom
+ - qcom,msm8998-qfprom
+ - qcom,qcs404-qfprom
+ - qcom,sc7180-qfprom
+ - qcom,sdm845-qfprom
+ - const: qcom,qfprom
reg:
# If the QFPROM is read-only OS image then only the corrected region
@@ -60,7 +71,7 @@ examples:
#size-cells = <2>;
efuse@784000 {
-compatible = "qcom,qfprom";
+compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>,
<0 0x0078 0 0x7a0>,
<0 0x00782000 0 0x100>,
@@ -85,7 +96,7 @@ examples:
#size-cells = <2>;
efuse@784000 {
-compatible = "qcom,qfprom";
+compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
--
2.21.0
[PATCH 5/5] nvmem: imx-ocotp: add support for the unaliged word count
From: Peng Fan
When offset is not 4 bytes aligned, directly shift righty by 2 bits
will cause reading out wrong data. Since imx ocotp only supports
4 bytes reading once, we need handle offset is not 4 bytes aligned
and enlarge the bytes to 4 bytes aligned. After reading finished,
copy the needed data from buffer to caller and free buffer.
Signed-off-by: Peng Fan
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/imx-ocotp.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 7a1ebd6fd08b..08f41328cc71 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -4,6 +4,8 @@
*
* Copyright (c) 2015 Pengutronix, Philipp Zabel
*
+ * Copyright 2019 NXP
+ *
* Based on the barebox ocotp driver,
* Copyright (c) 2010 Baruch Siach ,
* Orex Computed Radiography
@@ -158,22 +160,30 @@ static int imx_ocotp_read(void *context, unsigned int
offset,
{
struct ocotp_priv *priv = context;
unsigned int count;
- u32 *buf = val;
+ u8 *buf, *p;
int i, ret;
- u32 index;
+ u32 index, num_bytes;
index = offset >> 2;
- count = bytes >> 2;
+ num_bytes = round_up((offset % 4) + bytes, 4);
+ count = num_bytes >> 2;
if (count > (priv->params->nregs - index))
count = priv->params->nregs - index;
+ p = kzalloc(num_bytes, GFP_KERNEL);
+ if (!p)
+ return -ENOMEM;
+
mutex_lock(&ocotp_mutex);
+ buf = p;
+
ret = clk_prepare_enable(priv->clk);
if (ret < 0) {
mutex_unlock(&ocotp_mutex);
dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
+ kfree(p);
return ret;
}
@@ -184,7 +194,7 @@ static int imx_ocotp_read(void *context, unsigned int
offset,
}
for (i = index; i < (index + count); i++) {
- *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
+ *(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
i * IMX_OCOTP_OFFSET_PER_WORD);
/* 47.3.1.2
@@ -193,13 +203,21 @@ static int imx_ocotp_read(void *context, unsigned int
offset,
* software before any new write, read or reload access can be
* issued
*/
- if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
+ if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL)
imx_ocotp_clr_err_if_set(priv);
+
+ buf += 4;
}
+ index = offset % 4;
+ memcpy(val, &p[index], bytes);
+
read_end:
clk_disable_unprepare(priv->clk);
mutex_unlock(&ocotp_mutex);
+
+ kfree(p);
+
return ret;
}
@@ -447,7 +465,7 @@ static struct nvmem_config imx_ocotp_nvmem_config = {
.name = "imx-ocotp",
.read_only = false,
.word_size = 4,
- .stride = 4,
+ .stride = 1,
.reg_read = imx_ocotp_read,
.reg_write = imx_ocotp_write,
};
--
2.21.0
[PATCH 0/5] nvmem: patches (set 1) for 5.11
Hi Greg, Here are some nvmem patches for 5.11 which includes - adding support to keepout regions in nvmem core - support for unaligned word count in imx provider - imx and qfprom new compatible strings. Can you please queue them up for 5.11. thanks for you help, srini Evan Green (3): nvmem: core: Add support for keepout regions dt-bindings: nvmem: Add soc qfprom compatible strings nvmem: qfprom: Don't touch certain fuses Fabien Parent (1): dt-bindings: nvmem: mtk-efuse: add documentation for MT8516 SoC Peng Fan (1): nvmem: imx-ocotp: add support for the unaliged word count .../devicetree/bindings/nvmem/mtk-efuse.txt | 1 + .../bindings/nvmem/qcom,qfprom.yaml | 17 +- drivers/nvmem/core.c | 153 +- drivers/nvmem/imx-ocotp.c | 30 +++- drivers/nvmem/qfprom.c| 30 include/linux/nvmem-provider.h| 17 ++ 6 files changed, 235 insertions(+), 13 deletions(-) -- 2.21.0
[PATCH 4/5] nvmem: qfprom: Don't touch certain fuses
From: Evan Green
Some fuse ranges are protected by the XPU such that the AP cannot
access them. Attempting to do so causes an SError. Use the newly
introduced per-soc compatible string, and the newly introduced
nvmem keepout support to attach the set of regions
we should not access.
Signed-off-by: Evan Green
Reviewed-by: Douglas Anderson
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/qfprom.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 5e9e60e2e591..6cace24dfbf7 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
/* Blow timer clock frequency in Mhz */
@@ -88,6 +89,28 @@ struct qfprom_touched_values {
u32 timer_val;
};
+/**
+ * struct qfprom_soc_compatible_data - Data matched against the SoC
+ * compatible string.
+ *
+ * @keepout: Array of keepout regions for this SoC.
+ * @nkeepout: Number of elements in the keepout array.
+ */
+struct qfprom_soc_compatible_data {
+ const struct nvmem_keepout *keepout;
+ unsigned int nkeepout;
+};
+
+static const struct nvmem_keepout sc7180_qfprom_keepout[] = {
+ {.start = 0x128, .end = 0x148},
+ {.start = 0x220, .end = 0x228}
+};
+
+static const struct qfprom_soc_compatible_data sc7180_qfprom = {
+ .keepout = sc7180_qfprom_keepout,
+ .nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
+};
+
/**
* qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
* @priv: Our driver data.
@@ -281,6 +304,7 @@ static int qfprom_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct resource *res;
struct nvmem_device *nvmem;
+ const struct qfprom_soc_compatible_data *soc_data;
struct qfprom_priv *priv;
int ret;
@@ -299,6 +323,11 @@ static int qfprom_probe(struct platform_device *pdev)
econfig.priv = priv;
priv->dev = dev;
+ soc_data = device_get_match_data(dev);
+ if (soc_data) {
+ econfig.keepout = soc_data->keepout;
+ econfig.nkeepout = soc_data->nkeepout;
+ }
/*
* If more than one region is provided then the OS has the ability
@@ -354,6 +383,7 @@ static int qfprom_probe(struct platform_device *pdev)
static const struct of_device_id qfprom_of_match[] = {
{ .compatible = "qcom,qfprom",},
+ { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom},
{/* sentinel */},
};
MODULE_DEVICE_TABLE(of, qfprom_of_match);
--
2.21.0
[PATCH 1/5] dt-bindings: nvmem: mtk-efuse: add documentation for MT8516 SoC
From: Fabien Parent Add binding documentation for MT8516 SoCs. Signed-off-by: Fabien Parent Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt index 0668c45a156d..ef93c3b95424 100644 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt @@ -7,6 +7,7 @@ Required properties: "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 + "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 - reg: Should contain registers location and length = Data cells = -- 2.21.0
[PATCH 2/5] nvmem: core: Add support for keepout regions
From: Evan Green
Introduce support into the nvmem core for arrays of register ranges
that should not result in actual device access. For these regions a
constant byte (repeated) is returned instead on read, and writes are
quietly ignored and returned as successful.
This is useful for instance if certain efuse regions are protected
from access by Linux because they contain secret info to another part
of the system (like an integrated modem).
Signed-off-by: Evan Green
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/core.c | 153 -
include/linux/nvmem-provider.h | 17
2 files changed, 166 insertions(+), 4 deletions(-)
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index a09ff8409f60..177f5bf27c6d 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -34,6 +34,8 @@ struct nvmem_device {
struct bin_attributeeeprom;
struct device *base_dev;
struct list_headcells;
+ const struct nvmem_keepout *keepout;
+ unsigned intnkeepout;
nvmem_reg_read_treg_read;
nvmem_reg_write_t reg_write;
struct gpio_desc*wp_gpio;
@@ -66,8 +68,8 @@ static LIST_HEAD(nvmem_lookup_list);
static BLOCKING_NOTIFIER_HEAD(nvmem_notifier);
-static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset,
- void *val, size_t bytes)
+static int __nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset,
+ void *val, size_t bytes)
{
if (nvmem->reg_read)
return nvmem->reg_read(nvmem->priv, offset, val, bytes);
@@ -75,8 +77,8 @@ static int nvmem_reg_read(struct nvmem_device *nvmem,
unsigned int offset,
return -EINVAL;
}
-static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset,
- void *val, size_t bytes)
+static int __nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset,
+void *val, size_t bytes)
{
int ret;
@@ -90,6 +92,88 @@ static int nvmem_reg_write(struct nvmem_device *nvmem,
unsigned int offset,
return -EINVAL;
}
+static int nvmem_access_with_keepouts(struct nvmem_device *nvmem,
+ unsigned int offset, void *val,
+ size_t bytes, int write)
+{
+
+ unsigned int end = offset + bytes;
+ unsigned int kend, ksize;
+ const struct nvmem_keepout *keepout = nvmem->keepout;
+ const struct nvmem_keepout *keepoutend = keepout + nvmem->nkeepout;
+ int rc;
+
+ /*
+* Skip all keepouts before the range being accessed.
+* Keepouts are sorted.
+*/
+ while ((keepout < keepoutend) && (keepout->end <= offset))
+ keepout++;
+
+ while ((offset < end) && (keepout < keepoutend)) {
+ /* Access the valid portion before the keepout. */
+ if (offset < keepout->start) {
+ kend = min(end, keepout->start);
+ ksize = kend - offset;
+ if (write)
+ rc = __nvmem_reg_write(nvmem, offset, val,
ksize);
+ else
+ rc = __nvmem_reg_read(nvmem, offset, val,
ksize);
+
+ if (rc)
+ return rc;
+
+ offset += ksize;
+ val += ksize;
+ }
+
+ /*
+* Now we're aligned to the start of this keepout zone. Go
+* through it.
+*/
+ kend = min(end, keepout->end);
+ ksize = kend - offset;
+ if (!write)
+ memset(val, keepout->value, ksize);
+
+ val += ksize;
+ offset += ksize;
+ keepout++;
+ }
+
+ /*
+* If we ran out of keepouts but there's still stuff to do, send it
+* down directly
+*/
+ if (offset < end) {
+ ksize = end - offset;
+ if (write)
+ return __nvmem_reg_write(nvmem, offset, val, ksize);
+ else
+ return __nvmem_reg_read(nvmem, offset, val, ksize);
+ }
+
+ return 0;
+}
+
+static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset,
+ void *val, size_t bytes)
+{
+ if (!nvmem->nkeepout)
+ return __nvmem_reg_read(nvmem, offset, val, bytes);
+
+ return nvmem_access_with_keepouts(nvmem, offset, val, bytes, false);
+}
+
+static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset,
+ void *val, size_t bytes)
+{
+ if (!nvmem->nkeepout)
+ return __nvmem_reg_wri
[PATCH 7/7] slimbus: qcom-ngd-ctrl: remove redundant out of memory messages
Failure of dma_alloc_coherent will already throw a error message,
so addition message is really redundant here. Remove it!
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/qcom-ngd-ctrl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c
index 82dad7490588..c054e83ab636 100644
--- a/drivers/slimbus/qcom-ngd-ctrl.c
+++ b/drivers/slimbus/qcom-ngd-ctrl.c
@@ -689,7 +689,6 @@ static int qcom_slim_ngd_init_rx_msgq(struct
qcom_slim_ngd_ctrl *ctrl)
ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base,
GFP_KERNEL);
if (!ctrl->rx_base) {
- dev_err(dev, "dma_alloc_coherent failed\n");
ret = -ENOMEM;
goto rel_rx;
}
@@ -728,7 +727,6 @@ static int qcom_slim_ngd_init_tx_msgq(struct
qcom_slim_ngd_ctrl *ctrl)
ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base,
GFP_KERNEL);
if (!ctrl->tx_base) {
- dev_err(dev, "dma_alloc_coherent failed\n");
ret = -EINVAL;
goto rel_tx;
}
--
2.21.0
[PATCH 2/7] slimbus: qcom-ngd-ctrl: add Sub System Restart support
This patch adds SSR(SubSystem Restart) support which includes, synchronisation
between SSR and QMI server notifications. Also with this patch now NGD is taken
down by SSR instead of QMI server down notification.
NGD up path now relies on both SSR and QMI notifications and particularly
sequence of SSR up followed by QMI server up notification.
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/Kconfig | 3 +-
drivers/slimbus/qcom-ngd-ctrl.c | 97 +++--
2 files changed, 95 insertions(+), 5 deletions(-)
diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig
index 8cd595148d17..02534ce86e46 100644
--- a/drivers/slimbus/Kconfig
+++ b/drivers/slimbus/Kconfig
@@ -22,9 +22,10 @@ config SLIM_QCOM_CTRL
config SLIM_QCOM_NGD_CTRL
tristate "Qualcomm SLIMbus Satellite Non-Generic Device Component"
- depends on HAS_IOMEM && DMA_ENGINE && NET
+ depends on HAS_IOMEM && DMA_ENGINE && NET && REMOTEPROC
depends on ARCH_QCOM || COMPILE_TEST
select QCOM_QMI_HELPERS
+ select QCOM_RPROC_COMMON
help
Select driver if Qualcomm's SLIMbus Satellite Non-Generic Device
Component is programmed using Linux kernel.
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c
index 218aefc3531c..d32e6b37514d 100644
--- a/drivers/slimbus/qcom-ngd-ctrl.c
+++ b/drivers/slimbus/qcom-ngd-ctrl.c
@@ -13,6 +13,9 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
@@ -155,8 +158,14 @@ struct qcom_slim_ngd_ctrl {
struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
struct completion reconf;
struct work_struct m_work;
+ struct work_struct ngd_up_work;
struct workqueue_struct *mwq;
+ struct completion qmi_up;
spinlock_t tx_buf_lock;
+ struct mutex tx_lock;
+ struct mutex ssr_lock;
+ struct notifier_block nb;
+ void *notifier;
enum qcom_slim_ngd_state state;
dma_addr_t rx_phys_base;
dma_addr_t tx_phys_base;
@@ -868,14 +877,18 @@ static int qcom_slim_ngd_xfer_msg(struct slim_controller
*sctrl,
if (txn->msg && txn->msg->wbuf)
memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
+ mutex_lock(&ctrl->tx_lock);
ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
- if (ret)
+ if (ret) {
+ mutex_unlock(&ctrl->tx_lock);
return ret;
+ }
timeout = wait_for_completion_timeout(&tx_sent, HZ);
if (!timeout) {
dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
txn->mt);
+ mutex_unlock(&ctrl->tx_lock);
return -ETIMEDOUT;
}
@@ -884,10 +897,12 @@ static int qcom_slim_ngd_xfer_msg(struct slim_controller
*sctrl,
if (!timeout) {
dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x",
txn->mc, txn->mt);
+ mutex_unlock(&ctrl->tx_lock);
return -ETIMEDOUT;
}
}
+ mutex_unlock(&ctrl->tx_lock);
return 0;
}
@@ -1200,6 +1215,13 @@ static void qcom_slim_ngd_master_worker(struct
work_struct *work)
}
}
+static int qcom_slim_ngd_update_device_status(struct device *dev, void *null)
+{
+ slim_report_absent(to_slim_device(dev));
+
+ return 0;
+}
+
static int qcom_slim_ngd_runtime_resume(struct device *dev)
{
struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
@@ -1267,7 +1289,7 @@ static int qcom_slim_ngd_qmi_new_server(struct qmi_handle
*hdl,
qmi->svc_info.sq_node = service->node;
qmi->svc_info.sq_port = service->port;
- qcom_slim_ngd_enable(ctrl, true);
+ complete(&ctrl->qmi_up);
return 0;
}
@@ -1280,10 +1302,9 @@ static void qcom_slim_ngd_qmi_del_server(struct
qmi_handle *hdl,
struct qcom_slim_ngd_ctrl *ctrl =
container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
+ reinit_completion(&ctrl->qmi_up);
qmi->svc_info.sq_node = 0;
qmi->svc_info.sq_port = 0;
-
- qcom_slim_ngd_enable(ctrl, false);
}
static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
@@ -1333,6 +1354,64 @@ static const struct of_device_id
qcom_slim_ngd_dt_match[] = {
MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
+static void qcom_slim_ngd_down(struct qcom_slim_ngd_ctrl *ctrl)
+{
+ mutex_lock(&ctrl->ssr_lock);
+ device_for_each_child(ctrl->ctrl.dev, NULL,
+ qcom_slim_ngd_update_device_status);
+ qcom_slim_ngd_enable(ctrl, false);
+ mutex_unlock(&ctrl->ssr_
[PATCH 5/7] slimbus: qcom-ngd-ctrl: Constify static structs
From: Rikard Falkeborn
qcom_slim_qmi_msg_handlers[] and qcom_slim_ngd_qmi_svc_event_ops are
only used as input arguments to qmi_handle_init() which accepts const
pointers to both qmi_ops and qmi_msg_handler. Make them const to allow
the compiler to put them in read-only memory.
Signed-off-by: Rikard Falkeborn
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/qcom-ngd-ctrl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c
index 943d55a0bc59..172ddcc2a241 100644
--- a/drivers/slimbus/qcom-ngd-ctrl.c
+++ b/drivers/slimbus/qcom-ngd-ctrl.c
@@ -434,7 +434,7 @@ static int qcom_slim_qmi_send_power_request(struct
qcom_slim_ngd_ctrl *ctrl,
return 0;
}
-static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
+static const struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
{
.type = QMI_RESPONSE,
.msg_id = SLIMBUS_QMI_POWER_RESP_V01,
@@ -1309,7 +1309,7 @@ static void qcom_slim_ngd_qmi_del_server(struct
qmi_handle *hdl,
qmi->svc_info.sq_port = 0;
}
-static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
+static const struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
.new_server = qcom_slim_ngd_qmi_new_server,
.del_server = qcom_slim_ngd_qmi_del_server,
};
--
2.21.0
[PATCH 0/7] slimbus: patches for 5.11
Hi Greg, Here are some slimbus patches for 5.11 which includes - ngd controller has added PDR and SSR support along with a trival fixes. - few doc and clang warning fixes in slimbus Can you please queue them up for 5.11. thanks for you help, srini Bjorn Andersson (1): slimbus: qcom-ngd-ctrl: Avoid sending power requests without QMI Gustavo A. R. Silva (1): slimbus: messaging: Fix fall-through warnings for Clang Mauro Carvalho Chehab (1): slimbus: fix a kernel-doc markup Rikard Falkeborn (1): slimbus: qcom-ngd-ctrl: Constify static structs Srinivas Kandagatla (3): slimbus: qcom-ngd-ctrl: add Sub System Restart support slimbus: qcom-ngd-ctrl: add Protection Domain Restart Support slimbus: qcom-ngd-ctrl: remove redundant out of memory messages drivers/slimbus/Kconfig | 4 +- drivers/slimbus/messaging.c | 1 + drivers/slimbus/qcom-ngd-ctrl.c | 133 ++-- drivers/slimbus/slimbus.h | 2 +- 4 files changed, 130 insertions(+), 10 deletions(-) -- 2.21.0
[PATCH 6/7] slimbus: qcom-ngd-ctrl: Avoid sending power requests without QMI
From: Bjorn Andersson
Attempting to send a power request during PM operations, when the QMI
handle isn't initialized results in a NULL pointer dereference. So check
if the QMI handle has been initialized before attempting to post the
power requests.
Fixes: 917809e2280b ("slimbus: ngd: Add qcom SLIMBus NGD driver")
Signed-off-by: Bjorn Andersson
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/qcom-ngd-ctrl.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c
index 172ddcc2a241..82dad7490588 100644
--- a/drivers/slimbus/qcom-ngd-ctrl.c
+++ b/drivers/slimbus/qcom-ngd-ctrl.c
@@ -1229,6 +1229,9 @@ static int qcom_slim_ngd_runtime_resume(struct device
*dev)
struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
int ret = 0;
+ if (!ctrl->qmi.handle)
+ return 0;
+
if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
ret = qcom_slim_ngd_power_up(ctrl);
if (ret) {
@@ -1616,6 +1619,9 @@ static int __maybe_unused
qcom_slim_ngd_runtime_suspend(struct device *dev)
struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
int ret = 0;
+ if (!ctrl->qmi.handle)
+ return 0;
+
ret = qcom_slim_qmi_power_request(ctrl, false);
if (ret && ret != -EBUSY)
dev_info(ctrl->dev, "slim resource not idle:%d\n", ret);
--
2.21.0
[PATCH 3/7] slimbus: qcom-ngd-ctrl: add Protection Domain Restart Support
Add support to protection domain restart. Protection domain restart
would also restart the service just like SSR.
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/Kconfig | 1 +
drivers/slimbus/qcom-ngd-ctrl.c | 24
2 files changed, 25 insertions(+)
diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig
index 02534ce86e46..7d59956b5dfb 100644
--- a/drivers/slimbus/Kconfig
+++ b/drivers/slimbus/Kconfig
@@ -26,6 +26,7 @@ config SLIM_QCOM_NGD_CTRL
depends on ARCH_QCOM || COMPILE_TEST
select QCOM_QMI_HELPERS
select QCOM_RPROC_COMMON
+ select QCOM_PDR_HELPERS
help
Select driver if Qualcomm's SLIMbus Satellite Non-Generic Device
Component is programmed using Linux kernel.
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c
index d32e6b37514d..943d55a0bc59 100644
--- a/drivers/slimbus/qcom-ngd-ctrl.c
+++ b/drivers/slimbus/qcom-ngd-ctrl.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include "slimbus.h"
@@ -166,6 +167,7 @@ struct qcom_slim_ngd_ctrl {
struct mutex ssr_lock;
struct notifier_block nb;
void *notifier;
+ struct pdr_handle *pdr;
enum qcom_slim_ngd_state state;
dma_addr_t rx_phys_base;
dma_addr_t tx_phys_base;
@@ -1382,6 +1384,7 @@ static int qcom_slim_ngd_ssr_pdr_notify(struct
qcom_slim_ngd_ctrl *ctrl,
{
switch (action) {
case QCOM_SSR_BEFORE_SHUTDOWN:
+ case SERVREG_SERVICE_STATE_DOWN:
/* Make sure the last dma xfer is finished */
mutex_lock(&ctrl->tx_lock);
if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) {
@@ -1393,6 +1396,7 @@ static int qcom_slim_ngd_ssr_pdr_notify(struct
qcom_slim_ngd_ctrl *ctrl,
mutex_unlock(&ctrl->tx_lock);
break;
case QCOM_SSR_AFTER_POWERUP:
+ case SERVREG_SERVICE_STATE_UP:
schedule_work(&ctrl->ngd_up_work);
break;
default:
@@ -1412,6 +1416,12 @@ static int qcom_slim_ngd_ssr_notify(struct
notifier_block *nb,
return qcom_slim_ngd_ssr_pdr_notify(ctrl, action);
}
+static void slim_pd_status(int state, char *svc_path, void *priv)
+{
+ struct qcom_slim_ngd_ctrl *ctrl = (struct qcom_slim_ngd_ctrl *)priv;
+
+ qcom_slim_ngd_ssr_pdr_notify(ctrl, state);
+}
static int of_qcom_slim_ngd_register(struct device *parent,
struct qcom_slim_ngd_ctrl *ctrl)
{
@@ -1499,6 +1509,7 @@ static int qcom_slim_ngd_ctrl_probe(struct
platform_device *pdev)
struct qcom_slim_ngd_ctrl *ctrl;
struct resource *res;
int ret;
+ struct pdr_service *pds;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
@@ -1549,6 +1560,18 @@ static int qcom_slim_ngd_ctrl_probe(struct
platform_device *pdev)
init_completion(&ctrl->qmi.qmi_comp);
init_completion(&ctrl->qmi_up);
+ ctrl->pdr = pdr_handle_alloc(slim_pd_status, ctrl);
+ if (IS_ERR(ctrl->pdr)) {
+ dev_err(dev, "Failed to init PDR handle\n");
+ return PTR_ERR(ctrl->pdr);
+ }
+
+ pds = pdr_add_lookup(ctrl->pdr, "avs/audio", "msm/adsp/audio_pd");
+ if (IS_ERR(pds) && PTR_ERR(pds) != -EALREADY) {
+ dev_err(dev, "pdr add lookup failed: %d\n", ret);
+ return PTR_ERR(pds);
+ }
+
platform_driver_register(&qcom_slim_ngd_driver);
return of_qcom_slim_ngd_register(dev, ctrl);
}
@@ -1565,6 +1588,7 @@ static int qcom_slim_ngd_remove(struct platform_device
*pdev)
struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
+ pdr_handle_release(ctrl->pdr);
qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb);
qcom_slim_ngd_enable(ctrl, false);
qcom_slim_ngd_exit_dma(ctrl);
--
2.21.0
[PATCH 4/7] slimbus: messaging: Fix fall-through warnings for Clang
From: "Gustavo A. R. Silva" In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva Signed-off-by: Srinivas Kandagatla --- drivers/slimbus/messaging.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/slimbus/messaging.c b/drivers/slimbus/messaging.c index d5879142dbef..f2b5d347d227 100644 --- a/drivers/slimbus/messaging.c +++ b/drivers/slimbus/messaging.c @@ -258,6 +258,7 @@ int slim_xfer_msg(struct slim_device *sbdev, struct slim_val_inf *msg, case SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION: case SLIM_MSG_MC_CLEAR_INFORMATION: txn->rl += msg->num_bytes; + break; default: break; } -- 2.21.0
[PATCH 1/7] slimbus: fix a kernel-doc markup
From: Mauro Carvalho Chehab
Fix the name of the enum on its kernel-doc markup:
enum slim_ch_aux_fmt -> enum slim_ch_aux_bit_fmt
Signed-off-by: Mauro Carvalho Chehab
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/slimbus.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/slimbus/slimbus.h b/drivers/slimbus/slimbus.h
index c73035915f1d..00a7f112574b 100644
--- a/drivers/slimbus/slimbus.h
+++ b/drivers/slimbus/slimbus.h
@@ -244,7 +244,7 @@ enum slim_ch_data_fmt {
};
/**
- * enum slim_ch_aux_fmt: SLIMbus channel Aux Field format IDs according to
+ * enum slim_ch_aux_bit_fmt: SLIMbus channel Aux Field format IDs according to
* Table 63 of SLIMbus Spec 2.0
* @SLIM_CH_AUX_FMT_NOT_APPLICABLE: Undefined
* @SLIM_CH_AUX_FMT_ZCUV_TUNNEL_IEC60958: ZCUV for tunneling IEC60958
--
2.21.0
Re: drivers/soundwire/qcom.c:767: undefined reference to `slimbus_bus'
On 25/11/2020 05:51, Vinod Koul wrote:
Hi Randy,
On 04-11-20, 19:32, Randy Dunlap wrote:
On 11/2/20 11:47 AM, kernel test robot wrote:
All errors (new ones prefixed by >>):
or1k-linux-ld: drivers/soundwire/qcom.o: in function `qcom_swrm_probe':
drivers/soundwire/qcom.c:767: undefined reference to `slimbus_bus'
or1k-linux-ld: drivers/soundwire/qcom.c:771: undefined reference to
`slimbus_bus'
09309093d5e8f87 Jonathan Marek 2020-09-08 770 #if
IS_ENABLED(CONFIG_SLIMBUS)
02efb49aa805cee Srinivas Kandagatla 2020-01-13 @771if (dev->parent->bus ==
&slimbus_bus) {
5bd773242f75da3 Jonathan Marek 2020-09-05 772 #else
5bd773242f75da3 Jonathan Marek 2020-09-05 773if (false) {
5bd773242f75da3 Jonathan Marek 2020-09-05 774 #endif
config SOUNDWIRE_QCOM
tristate "Qualcomm SoundWire Master driver"
imply SLIMBUS
depends on SND_SOC
The kernel config that was attached has:
CONFIG_SOUNDWIRE_QCOM=y
CONFIG_SLIMBUS=m
I expected that "imply" would make SLIMBUS=y since SOUNDWIRE_QCOM=y,
but I guess that's not the case. :(
Any ideas about what to do here?
Sorry to have missed this earlier. I did some digging and found the
Kconfig code to be correct, but not the driver code. Per the
Documentation if we are using imply we should use IS_REACHABLE() rather
than IS_ENABLED.
This seems to take care of build failure for me on arm64 and x64 builds.
Can you confirm with below patch:
---><8---
From: Vinod Koul
Date: Wed, 25 Nov 2020 11:15:22 +0530
Subject: [PATCH] soundwire: qcom: Fix build failure when slimbus is module
Commit 5bd773242f75 ("soundwire: qcom: avoid dependency on
CONFIG_SLIMBUS") removed hard dependency on Slimbus for qcom driver but
it results in build failure when:
CONFIG_SOUNDWIRE_QCOM=y
CONFIG_SLIMBUS=m
drivers/soundwire/qcom.o: In function `qcom_swrm_probe':
qcom.c:(.text+0xf44): undefined reference to `slimbus_bus'
Fix this by using IS_REACHABLE() in driver which is recommended to be
sued with imply.
Fixes: 5bd773242f75 ("soundwire: qcom: avoid dependency on CONFIG_SLIMBUS")
Reported-by: kernel test robot
Signed-off-by: Vinod Koul
---
Thanks Vinod,
Tested-by: Srinivas Kandagatla
Reviewed-by: Srinivas Kandagatla
--srini
drivers/soundwire/qcom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index fbca4ebf63e9..6d22df01f354 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -799,7 +799,7 @@ static int qcom_swrm_probe(struct platform_device *pdev)
data = of_device_get_match_data(dev);
ctrl->rows_index = sdw_find_row_index(data->default_rows);
ctrl->cols_index = sdw_find_col_index(data->default_cols);
-#if IS_ENABLED(CONFIG_SLIMBUS)
+#if IS_REACHABLE(CONFIG_SLIMBUS)
if (dev->parent->bus == &slimbus_bus) {
#else
if (false) {
Re: [PATCH] slimbus: qcom-ngd-ctrl: Avoid sending power requests without QMI
On 25/11/2020 05:42, Bjorn Andersson wrote:
Attempting to send a power request during PM operations, when the QMI
handle isn't initialized results in a NULL pointer dereference. So check
if the QMI handle has been initialized before attempting to post the
power requests.
Fixes: 917809e2280b ("slimbus: ngd: Add qcom SLIMBus NGD driver")
Signed-off-by: Bjorn Andersson
Applied thanks,
--srini
Re: [PATCH 1/2] dt-bindings: nvmem: mtk-efuse: add documentation for MT8516 SoC
On 16/10/2020 18:18, Fabien Parent wrote: Add binding documentation for MT8516 SoCs. Signed-off-by: Fabien Parent I have picked up the dt-bindings patch, but dts changes have to go via arm-soc tree! --srini
Re: [PATCH] nvmem: imx-ocotp: add support for the unaliged word count
On 22/10/2020 08:44, peng@nxp.com wrote: From: Peng Fan When offset is not 4 bytes aligned, directly shift righty by 2 bits will cause reading out wrong data. Since imx ocotp only supports 4 bytes reading once, we need handle offset is not 4 bytes aligned and enlarge the bytes to 4 bytes aligned. After reading finished, copy the needed data from buffer to caller and free buffer. Signed-off-by: Peng Fan Applied thanks, srini
Re: [PATCH 126/141] slimbus: messaging: Fix fall-through warnings for Clang
On 20/11/2020 18:39, Gustavo A. R. Silva wrote: In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva --- Applied thanks, srini drivers/slimbus/messaging.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/slimbus/messaging.c b/drivers/slimbus/messaging.c index d5879142dbef..f2b5d347d227 100644 --- a/drivers/slimbus/messaging.c +++ b/drivers/slimbus/messaging.c @@ -258,6 +258,7 @@ int slim_xfer_msg(struct slim_device *sbdev, struct slim_val_inf *msg, case SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION: case SLIM_MSG_MC_CLEAR_INFORMATION: txn->rl += msg->num_bytes; + break; default: break; }
Re: [PATCH] slimbus: qcom-ngd-ctrl: Constify static structs
On 22/11/2020 23:42, Rikard Falkeborn wrote: qcom_slim_qmi_msg_handlers[] and qcom_slim_ngd_qmi_svc_event_ops are only used as input arguments to qmi_handle_init() which accepts const pointers to both qmi_ops and qmi_msg_handler. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn --- Applied thanks, --srini
[PATCH] ASoC: codecs: lpass-va-macro: add missing MODULE_DEVICE_TABLE
Fix module loading due by adding missing MODULE_DEVICE_TABLE.
Fixes: 908e6b1df26e ("ASoC: codecs: lpass-va-macro: Add support to VA Macro")
Signed-off-by: Srinivas Kandagatla
---
sound/soc/codecs/lpass-va-macro.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/codecs/lpass-va-macro.c
b/sound/soc/codecs/lpass-va-macro.c
index b604de07e650..3e6bbef26dcb 100644
--- a/sound/soc/codecs/lpass-va-macro.c
+++ b/sound/soc/codecs/lpass-va-macro.c
@@ -1487,6 +1487,7 @@ static const struct of_device_id va_macro_dt_match[] = {
{ .compatible = "qcom,sm8250-lpass-va-macro" },
{}
};
+MODULE_DEVICE_TABLE(of, va_macro_dt_match);
static struct platform_driver va_macro_driver = {
.driver = {
--
2.21.0
[PATCH 2/2] slimbus: qcom-ngd-ctrl: add Protection Domain Restart Support
Add support to protection domain restart. Protection domain restart
would also restart the service just like SSR.
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/Kconfig | 1 +
drivers/slimbus/qcom-ngd-ctrl.c | 24
2 files changed, 25 insertions(+)
diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig
index 7c950948a9ec..060a2c65978a 100644
--- a/drivers/slimbus/Kconfig
+++ b/drivers/slimbus/Kconfig
@@ -26,6 +26,7 @@ config SLIM_QCOM_NGD_CTRL
depends on ARCH_QCOM || COMPILE_TEST
select QCOM_QMI_HELPERS
select QCOM_RPROC_COMMON
+ select QCOM_PDR_HELPERS
help
Select driver if Qualcomm's SLIMbus Satellite Non-Generic Device
Component is programmed using Linux kernel.
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c
index f62693653d2b..d8decb345e9d 100644
--- a/drivers/slimbus/qcom-ngd-ctrl.c
+++ b/drivers/slimbus/qcom-ngd-ctrl.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include "slimbus.h"
@@ -166,6 +167,7 @@ struct qcom_slim_ngd_ctrl {
struct mutex ssr_lock;
struct notifier_block nb;
void *notifier;
+ struct pdr_handle *pdr;
enum qcom_slim_ngd_state state;
dma_addr_t rx_phys_base;
dma_addr_t tx_phys_base;
@@ -1382,6 +1384,7 @@ static int qcom_slim_ngd_ssr_pdr_notify(struct
qcom_slim_ngd_ctrl *ctrl,
{
switch (action) {
case QCOM_SSR_BEFORE_SHUTDOWN:
+ case SERVREG_SERVICE_STATE_DOWN:
/* Make sure the last dma xfer is finished */
mutex_lock(&ctrl->tx_lock);
if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) {
@@ -1393,6 +1396,7 @@ static int qcom_slim_ngd_ssr_pdr_notify(struct
qcom_slim_ngd_ctrl *ctrl,
mutex_unlock(&ctrl->tx_lock);
break;
case QCOM_SSR_AFTER_POWERUP:
+ case SERVREG_SERVICE_STATE_UP:
schedule_work(&ctrl->ngd_up_work);
break;
default:
@@ -1412,6 +1416,12 @@ static int qcom_slim_ngd_ssr_notify(struct
notifier_block *nb,
return qcom_slim_ngd_ssr_pdr_notify(ctrl, action);
}
+static void slim_pd_status(int state, char *svc_path, void *priv)
+{
+ struct qcom_slim_ngd_ctrl *ctrl = (struct qcom_slim_ngd_ctrl *)priv;
+
+ qcom_slim_ngd_ssr_pdr_notify(ctrl, state);
+}
static int of_qcom_slim_ngd_register(struct device *parent,
struct qcom_slim_ngd_ctrl *ctrl)
{
@@ -1499,6 +1509,7 @@ static int qcom_slim_ngd_ctrl_probe(struct
platform_device *pdev)
struct qcom_slim_ngd_ctrl *ctrl;
struct resource *res;
int ret;
+ struct pdr_service *pds;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
@@ -1549,6 +1560,18 @@ static int qcom_slim_ngd_ctrl_probe(struct
platform_device *pdev)
init_completion(&ctrl->qmi.qmi_comp);
init_completion(&ctrl->qmi_up);
+ ctrl->pdr = pdr_handle_alloc(slim_pd_status, ctrl);
+ if (IS_ERR(ctrl->pdr)) {
+ dev_err(dev, "Failed to init PDR handle\n");
+ return PTR_ERR(ctrl->pdr);
+ }
+
+ pds = pdr_add_lookup(ctrl->pdr, "avs/audio", "msm/adsp/audio_pd");
+ if (IS_ERR(pds) && PTR_ERR(pds) != -EALREADY) {
+ dev_err(dev, "pdr add lookup failed: %d\n", ret);
+ return PTR_ERR(pds);
+ }
+
platform_driver_register(&qcom_slim_ngd_driver);
return of_qcom_slim_ngd_register(dev, ctrl);
}
@@ -1565,6 +1588,7 @@ static int qcom_slim_ngd_remove(struct platform_device
*pdev)
struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
+ pdr_handle_release(ctrl->pdr);
qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb);
qcom_slim_ngd_enable(ctrl, false);
qcom_slim_ngd_exit_dma(ctrl);
--
2.21.0
[PATCH 0/2] slimbus: qcom-ngd: Add SSR and PDR support
Qualcomm DSPs support SSR(Subsystem Restart) and PDR(Protection Domain Restart) which usually restart the associated services! Current code does only relies on QMI channel notifications, but there could be race conditions between QMI notifcations and actual PDR/SSR events. This patchset adds support to these two events to address those race conditions. Tested it on Dragon Board DB845c. Srinivas Kandagatla (2): slimbus: qcom-ngd-ctrl: add Sub System Restart support slimbus: qcom-ngd-ctrl: add Protection Domain Restart Support drivers/slimbus/Kconfig | 2 + drivers/slimbus/qcom-ngd-ctrl.c | 121 ++-- 2 files changed, 119 insertions(+), 4 deletions(-) -- 2.21.0
[PATCH 1/2] slimbus: qcom-ngd-ctrl: add Sub System Restart support
This patch adds SSR(SubSystem Restart) support which includes, synchronisation
between SSR and QMI server notifications. Also with this patch now NGD is taken
down by SSR instead of QMI server down notification.
NGD up path now relies on both SSR and QMI notifications and particularly
sequence of SSR up followed by QMI server up notification.
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/Kconfig | 1 +
drivers/slimbus/qcom-ngd-ctrl.c | 97 +++--
2 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig
index 8cd595148d17..7c950948a9ec 100644
--- a/drivers/slimbus/Kconfig
+++ b/drivers/slimbus/Kconfig
@@ -25,6 +25,7 @@ config SLIM_QCOM_NGD_CTRL
depends on HAS_IOMEM && DMA_ENGINE && NET
depends on ARCH_QCOM || COMPILE_TEST
select QCOM_QMI_HELPERS
+ select QCOM_RPROC_COMMON
help
Select driver if Qualcomm's SLIMbus Satellite Non-Generic Device
Component is programmed using Linux kernel.
diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c
index 218aefc3531c..f62693653d2b 100644
--- a/drivers/slimbus/qcom-ngd-ctrl.c
+++ b/drivers/slimbus/qcom-ngd-ctrl.c
@@ -13,6 +13,9 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
@@ -155,8 +158,14 @@ struct qcom_slim_ngd_ctrl {
struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
struct completion reconf;
struct work_struct m_work;
+ struct work_struct ngd_up_work;
struct workqueue_struct *mwq;
+ struct completion qmi_up;
spinlock_t tx_buf_lock;
+ struct mutex tx_lock;
+ struct mutex ssr_lock;
+ struct notifier_block nb;
+ void *notifier;
enum qcom_slim_ngd_state state;
dma_addr_t rx_phys_base;
dma_addr_t tx_phys_base;
@@ -868,14 +877,18 @@ static int qcom_slim_ngd_xfer_msg(struct slim_controller
*sctrl,
if (txn->msg && txn->msg->wbuf)
memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
+ mutex_lock(&ctrl->tx_lock);
ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
- if (ret)
+ if (ret) {
+ mutex_unlock(&ctrl->tx_lock);
return ret;
+ }
timeout = wait_for_completion_timeout(&tx_sent, HZ);
if (!timeout) {
dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
txn->mt);
+ mutex_unlock(&ctrl->tx_lock);
return -ETIMEDOUT;
}
@@ -884,10 +897,12 @@ static int qcom_slim_ngd_xfer_msg(struct slim_controller
*sctrl,
if (!timeout) {
dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x",
txn->mc, txn->mt);
+ mutex_unlock(&ctrl->tx_lock);
return -ETIMEDOUT;
}
}
+ mutex_unlock(&ctrl->tx_lock);
return 0;
}
@@ -1200,6 +1215,13 @@ static void qcom_slim_ngd_master_worker(struct
work_struct *work)
}
}
+static int qcom_slim_ngd_update_device_status(struct device *dev, void *null)
+{
+ slim_report_absent(to_slim_device(dev));
+
+ return 0;
+}
+
static int qcom_slim_ngd_runtime_resume(struct device *dev)
{
struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
@@ -1267,7 +1289,7 @@ static int qcom_slim_ngd_qmi_new_server(struct qmi_handle
*hdl,
qmi->svc_info.sq_node = service->node;
qmi->svc_info.sq_port = service->port;
- qcom_slim_ngd_enable(ctrl, true);
+ complete(&ctrl->qmi_up);
return 0;
}
@@ -1280,10 +1302,9 @@ static void qcom_slim_ngd_qmi_del_server(struct
qmi_handle *hdl,
struct qcom_slim_ngd_ctrl *ctrl =
container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
+ reinit_completion(&ctrl->qmi_up);
qmi->svc_info.sq_node = 0;
qmi->svc_info.sq_port = 0;
-
- qcom_slim_ngd_enable(ctrl, false);
}
static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
@@ -1333,6 +1354,64 @@ static const struct of_device_id
qcom_slim_ngd_dt_match[] = {
MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
+static void qcom_slim_ngd_down(struct qcom_slim_ngd_ctrl *ctrl)
+{
+ mutex_lock(&ctrl->ssr_lock);
+ device_for_each_child(ctrl->ctrl.dev, NULL,
+ qcom_slim_ngd_update_device_status);
+ qcom_slim_ngd_enable(ctrl, false);
+ mutex_unlock(&ctrl->ssr_lock);
+}
+
+static void qcom_slim_ngd_up_worker(struct work_struct *work)
+{
+ struct qcom_slim_ngd_ctrl *ctrl;
+
+ ctrl = container_of(work, struct qcom_slim_ngd_ctrl, ngd_up_work);
+
+
[PATCH] mfd: core: update mfd_of_node_list list on mfd_remove_devices
Call to mfd_add_devices() after mfd_remove_devices() will always
fail in device tree use-case, because new device will find a matching node
in the global mfd_of_node_list resulting in mfd_match_of_node_to_dev()
to return -EAGAIN.
This is one of the use-case with WCD934x where mfd devices can disappear and
reappear when ADSP either restarts or its services restarts.
Fix this issue by removing the state entry in global mfd_of_node_list
during mfd_remove_devices.
Fixes: 466a62d7642f ("mfd: core: Make a best effort attempt to match devices
with the correct of_nodes")
Signed-off-by: Srinivas Kandagatla
---
drivers/mfd/mfd-core.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index fc00aaccb5f7..3e845be895ac 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -359,6 +359,7 @@ static int mfd_remove_devices_fn(struct device *dev, void
*data)
struct platform_device *pdev;
const struct mfd_cell *cell;
int *level = data;
+ struct mfd_of_node_entry *of_entry, *tmp;
if (dev->type != &mfd_dev_type)
return 0;
@@ -372,6 +373,12 @@ static int mfd_remove_devices_fn(struct device *dev, void
*data)
regulator_bulk_unregister_supply_alias(dev, cell->parent_supplies,
cell->num_parent_supplies);
+ list_for_each_entry_safe(of_entry, tmp, &mfd_of_node_list, list)
+ if (of_entry->dev == &pdev->dev) {
+ list_del(&of_entry->list);
+ kfree(of_entry);
+ }
+
platform_device_unregister(pdev);
return 0;
}
--
2.21.0
Re: [PATCH v3 0/2] nvmem: skip nodes with compatibles other than "nvmem-cell"
On 16/11/2020 17:04, Ahmad Fatoum wrote: To allow for co-existence of NVMEM cells and other subnodes, would following patch be acceptable to you and Srini? Gentle ping. Would the patch below be acceptable? Did you have time to look at this? I did reply back to this thread way back in June saying that "Thanks for the patch, this looks good to me, lets wait for Rob to ack the bindings! " --srini
[PATCH v4 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SM8250
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla
---
.../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 132 ++
1 file changed, 132 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index ..704e761146ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ clocks:
+items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+const: 2
+
+ gpio-ranges:
+maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+type: object
+description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+$ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+properties:
+ pins:
+description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+items:
+ oneOf:
+- pattern: "^gpio([0-9]|[1-9][0-9])$"
+minItems: 1
+maxItems: 14
+
+ function:
+enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws,
+swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1,
+swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2,
+dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk,
+i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk,
+i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data,
+i2s2_data1 ]
+description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+enum: [2, 4, 6, 8, 10, 12, 14, 16]
+default: 2
+description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+0: No adjustments
+1: Higher Slew rate (faster edges)
+2: Lower Slew rate (slower edges)
+3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+required:
+ - pins
+ - function
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lpi_tlmm: pinctrl@33c {
+compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+reg = <0x33c 0x2>,
+ <0x355a000 0x1000>;
+clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+clock-names = "core", "audio";
+gpio-controller;
+#gpio-cells = <2>;
+gpio-ranges = <&lpi_tlmm 0 0 14>;
+};
--
2.21.0
[PATCH v4 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 734 +++
3 files changed, 743 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..63cfbb2d032a
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_GPIO_REG_VAL_CTL 0x00
+#define LPI_GPIO_REG_DIR_CTL 0x04
+#define LPI_SLEW_REG_VAL_CTL 0x00
+#define LPI_SLEW_RATE_MAX0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_GPIO_REG_PULL_SHIFT0x0
+#define LPI_GPIO_REG_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_REG_FUNCTION_SHIFT0x2
+#define LPI_GPIO_REG_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_REG_OUT_STRENGTH_SHIFT0x6
+#define LPI_GPIO_REG_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_REG_OE_SHIFT 0x9
+#define LPI_GPIO_REG_OE_MASK BIT(9)
+#define LPI_GPIO_REG_DIR_SHIFT 0x1
+#define LPI_GPIO_REG_DIR_MASK 0x2
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) ((v / 2 - 1) << LPI_GPIO_REG_OUT_STRENGTH_SHIFT)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .slew_offset = soff,\
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f
[PATCH v4 0/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl support
This patch adds support for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This patch has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Am guessing existing qcom folder should cover maintining this driver too! If not I can send additional patch to consolidate this along with other Audio related drivers in Maintainer file! Changes since v3: - updated bindings as per Rob's review! Srinivas Kandagatla (2): dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 132 drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 734 ++ 4 files changed, 875 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -- 2.21.0
[PATCH v3 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SM8250
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla
---
.../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 ++
1 file changed, 129 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index ..562520f41a33
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ clocks:
+items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+const: 2
+
+ gpio-ranges:
+maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+if:
+ type: object
+then:
+ properties:
+pins:
+ description:
+List of gpio pins affected by the properties specified in this
+subnode.
+ items:
+oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 14
+
+function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws,
+ swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1,
+ swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2,
+ dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk,
+ i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk,
+ i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data,
+ i2s2_data1 ]
+ description:
+Specify the alternative function to be configured for the specified
+pins.
+
+drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+Selects the drive strength for the specified pins, in mA.
+
+slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+bias-pull-down: true
+
+bias-pull-up: true
+
+bias-disable: true
+
+output-high: true
+
+output-low: true
+
+ required:
+- pins
+- function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lpi_tlmm: pinctrl@33c {
+compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+reg = <0x33c 0x2>,
+ <0x355a000 0x1000>;
+clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+clock-names = "core", "audio";
+gpio-controller;
+#gpio-cells = <2>;
+gpio-ranges = <&lpi_tlmm 0 0 14>;
+};
--
2.21.0
[PATCH v3 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 734 +++
3 files changed, 743 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..1b1e03f120b3
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_GPIO_REG_VAL_CTL 0x00
+#define LPI_GPIO_REG_DIR_CTL 0x04
+#define LPI_SLEW_REG_VAL_CTL 0x00
+#define LPI_SLEW_RATE_MAX0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_GPIO_REG_PULL_SHIFT0x0
+#define LPI_GPIO_REG_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_REG_FUNCTION_SHIFT0x2
+#define LPI_GPIO_REG_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_REG_OUT_STRENGTH_SHIFT0x6
+#define LPI_GPIO_REG_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_REG_OE_SHIFT 0x9
+#define LPI_GPIO_REG_OE_MASK BIT(9)
+#define LPI_GPIO_REG_DIR_SHIFT 0x1
+#define LPI_GPIO_REG_DIR_MASK 0x2
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) ((v / 2 - 1) << LPI_GPIO_REG_OUT_STRENGTH_SHIFT)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .slew_offset = soff,\
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f
[PATCH v3 0/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl support
This patch adds support for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This patch has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Am guessing existing qcom folder should cover maintining this driver too! If not I can send additional patch to consolidate this along with other Audio related drivers in Maintainer file! Changes since v2: - addressed various coding style related comments by Andy Shevchenko - moved to devm and bluk apis as suggested by Andy Shevchenko - moved slew offset to group struct for more clarity - updated comment log to reflect few similarities between other msm TLMM blocks. Srinivas Kandagatla (2): dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 +++ drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 734 ++ 4 files changed, 872 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -- 2.21.0
Re: [PATCH v2 1/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Thanks Andy for the review,
On 05/11/2020 12:32, Andy Shevchenko wrote:
On Thu, Nov 5, 2020 at 2:06 PM Srinivas Kandagatla
wrote:
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB && OF
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+#include
+#include
I agree with most of the style related comments! will fix them in next
version!
...
+#ifdef CONFIG_DEBUG_FS
+#include
+#else
+#define lpi_gpio_dbg_show NULL
+#endif
Hmm... Doesn't pin control provide a wrapper for this?
I does, but the custom code can provide additional information (such as
pullup/pulldown configuration) which default one does not provide.
Most of the pinctrl drivers have there own version of this!
...
+ int ret, npins;
+ struct clk *core_vote = NULL;
+ struct clk *audio_vote = NULL;
+
+ struct lpi_pinctrl *pctrl;
+ const struct lpi_pinctrl_variant_data *data;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
Redundant blank line. Can you keep them in reversed xmas tree order?
...
+ core_vote = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(core_vote)) {
+ dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
+ __func__, "core_vote", ret);
First of all you missed the deferred probe issue, second, __func__ is
redundant for *_dbg() calls (okay, when Dynamic Debug is enabled).
That said why not
return dev_err_probe();
?
It looks neat, I will use that!
Thanks for this hint, I never knew we had some function like that!
+ return PTR_ERR(core_vote);
+ }
...
+ audio_vote = devm_clk_get(&pdev->dev, "audio");
+ if (IS_ERR(audio_vote)) {
+ dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
+ __func__, "audio_vote", ret);
+ return PTR_ERR(audio_vote);
Ditto/
+ }
Why is it not a bulk?
I can try that!
+ clk_prepare_enable(pctrl->core_vote);
+ clk_prepare_enable(pctrl->audio_vote);
Either from them may return an error. Also, when you go devm_*() the
rule of thumb is either all or none. Because here you will have
ordering issue on ->remove().
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pctrl->tlmm_base = devm_ioremap_resource(&pdev->dev, res);
devm_platform_ioremap_resource()
make sense, I remember doing this! somehow I missed it in this version!
rest of the comments looks sensible to me, will make sure that those are
fixed in next version.
thanks,
srini
Re: [PATCH v2 1/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Thanks Linus for review!
On 06/11/2020 09:50, Linus Walleij wrote:
Hi Srinivas,
thanks for your patch!
On Thu, Nov 5, 2020 at 1:04 PM Srinivas Kandagatla
wrote:
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
Signed-off-by: Srinivas Kandagatla
So this is in essence a completely new pin controller that shares
nothing with the previous Qcom SoC pin control hardware?
I'd still like Bjorn to review it of course, but if you are going to
maintain this driver an entry to the MAINTAINERS file would
be nice.
I'd like some more talk in the commit message about how this
driver is engineered so I point those things out below.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB && OF
These days you can actually just
select GPIOLIB
but no big deal.
Will take care of this!
+#include
+#include
+#include
Do not use this legacy header for new GPIO drivers.
#include
should work.
Sure!
+#define LPI_GPIO_REG_VAL_CTL 0x00
+#define LPI_GPIO_REG_DIR_CTL 0x04
+#define LPI_SLEW_REG_VAL_CTL 0x00
+#define LPI_SLEW_RATE_MAX0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_GPIO_REG_PULL_SHIFT0x0
+#define LPI_GPIO_REG_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_REG_FUNCTION_SHIFT0x2
+#define LPI_GPIO_REG_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_REG_OUT_STRENGTH_SHIFT0x6
+#define LPI_GPIO_REG_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_REG_OE_SHIFT 0x9
+#define LPI_GPIO_REG_OE_MASK BIT(9)
+#define LPI_GPIO_REG_DIR_SHIFT 0x1
+#define LPI_GPIO_REG_DIR_MASK 0x2
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
So the way I understand it, the GPIO lines have one register each and then the
functionality of each line is handled by different bits in that register, like
output is driven in bit 9.
Yes exactly!
This would be nice to have mentioned in the commit message.
I will add more detailed commit message in next version.
+static const unsigned int gpio0_pins[] = { 0 };
+static const unsigned int gpio1_pins[] = { 1 };
+static const unsigned int gpio2_pins[] = { 2 };
+static const unsigned int gpio3_pins[] = { 3 };
+static const unsigned int gpio4_pins[] = { 4 };
+static const unsigned int gpio5_pins[] = { 5 };
+static const unsigned int gpio6_pins[] = { 6 };
+static const unsigned int gpio7_pins[] = { 7 };
+static const unsigned int gpio8_pins[] = { 8 };
+static const unsigned int gpio9_pins[] = { 9 };
+static const unsigned int gpio10_pins[] = { 10 };
+static const unsigned int gpio11_pins[] = { 11 };
+static const unsigned int gpio12_pins[] = { 12 };
+static const unsigned int gpio13_pins[] = { 13 };
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data1_groups[] = { "gpio1" };
+static const char * const swr_tx_data2_groups[] = { "gpio2" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data1_groups[] = { "gpio4" };
+static const char * const swr_tx_data3_groups[] = { "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data0_groups[] = { "gpio2" };
+static const char * const qua_mi2s_data1_groups[] = { "gpio3" };
+static const char * const qua_mi2s_data2_groups[] = { "gpio4" };
+static const char * const swr_rx_data2_groups[] = { "gpio5" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data0_groups[] = { "gpio8" };
+static const char * const i2s1_data1_groups[] = { "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data0_groups[] = { "gpio12&
[PATCH v2 2/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SM8250
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla
---
.../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 ++
1 file changed, 129 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index ..562520f41a33
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ clocks:
+items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+const: 2
+
+ gpio-ranges:
+maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+if:
+ type: object
+then:
+ properties:
+pins:
+ description:
+List of gpio pins affected by the properties specified in this
+subnode.
+ items:
+oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 14
+
+function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws,
+ swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1,
+ swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2,
+ dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk,
+ i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk,
+ i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data,
+ i2s2_data1 ]
+ description:
+Specify the alternative function to be configured for the specified
+pins.
+
+drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+Selects the drive strength for the specified pins, in mA.
+
+slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+bias-pull-down: true
+
+bias-pull-up: true
+
+bias-disable: true
+
+output-high: true
+
+output-low: true
+
+ required:
+- pins
+- function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lpi_tlmm: pinctrl@33c {
+compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+reg = <0x33c 0x2>,
+ <0x355a000 0x1000>;
+clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+clock-names = "core", "audio";
+gpio-controller;
+#gpio-cells = <2>;
+gpio-ranges = <&lpi_tlmm 0 0 14>;
+};
--
2.21.0
[PATCH v2 1/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 781 +++
3 files changed, 790 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..af26f4c51f77 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB && OF
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..3b30c4397773
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_GPIO_REG_VAL_CTL 0x00
+#define LPI_GPIO_REG_DIR_CTL 0x04
+#define LPI_SLEW_REG_VAL_CTL 0x00
+#define LPI_SLEW_RATE_MAX0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_GPIO_REG_PULL_SHIFT0x0
+#define LPI_GPIO_REG_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_REG_FUNCTION_SHIFT0x2
+#define LPI_GPIO_REG_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_REG_OUT_STRENGTH_SHIFT0x6
+#define LPI_GPIO_REG_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_REG_OE_SHIFT 0x9
+#define LPI_GPIO_REG_OE_MASK BIT(9)
+#define LPI_GPIO_REG_DIR_SHIFT 0x1
+#define LPI_GPIO_REG_DIR_MASK 0x2
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5,\
+ }
+struct lpi_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int npins;
+ unsigned int pin;
+ unsigned int *funcs;
+ unsigned int nfuncs;
+};
+
+struct lpi_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct lpi_pinctrl_variant_data {
+ int tlmm_reg_offset;
+ const struct pinctrl_pin_desc *pins;
+ int npins;
+ const struct lpi_pingroup *groups;
+ int ngroups;
+ const struct lpi_function *functions;
+ int nfunctions;
+ int *slew_reg_pin_offsets;
+};
+
+struct lpi_pinctrl {
+ struct device *dev;
[PATCH v2 0/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl support
This patch adds support for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This patch has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Changes since v1: - updated bindings to use '-pins$' instead of wild card matching as suggested by Rob. Srinivas Kandagatla (2): pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 +++ drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 781 ++ 4 files changed, 919 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -- 2.21.0
[PATCH] ASoC: q6afe-clocks: fix warning on symbol scope
This patch fixes below warning when module is compiled with W=1 C=1
sound/soc/qcom/qdsp6/q6afe-clocks.c:122:18: warning: symbol 'q6afe_clks'
was not declared. Should it be static?
Fixes: 520a1c396d196 ("ASoC: q6afe-clocks: add q6afe clock controller")
Signed-off-by: Srinivas Kandagatla
---
sound/soc/qcom/qdsp6/q6afe-clocks.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/qcom/qdsp6/q6afe-clocks.c
b/sound/soc/qcom/qdsp6/q6afe-clocks.c
index 2efc2eaa0424..87e4633afe2c 100644
--- a/sound/soc/qcom/qdsp6/q6afe-clocks.c
+++ b/sound/soc/qcom/qdsp6/q6afe-clocks.c
@@ -119,7 +119,7 @@ static const struct clk_ops clk_vote_q6afe_ops = {
.unprepare = clk_unvote_q6afe_block,
};
-struct q6afe_clk *q6afe_clks[Q6AFE_MAX_CLK_ID] = {
+static struct q6afe_clk *q6afe_clks[Q6AFE_MAX_CLK_ID] = {
[LPASS_CLK_ID_PRI_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
[LPASS_CLK_ID_PRI_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
[LPASS_CLK_ID_SEC_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
--
2.21.0
[PATCH] ASoc: qcom: lpass-cpu: fix warning on symbol scope
This patch fixes below warning when module is compiled with W=1 C=1
lpass-cpu.c:677:22: warning: symbol 'lpass_hdmi_regmap_config'
was not declared. Should it be static?
Fixes: 7cb37b7bd0d3 ("ASoC: qcom: Add support for lpass hdmi driver")
Signed-off-by: Srinivas Kandagatla
---
sound/soc/qcom/lpass-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c
index 9d17c87445a9..1fd862e3fd8a 100644
--- a/sound/soc/qcom/lpass-cpu.c
+++ b/sound/soc/qcom/lpass-cpu.c
@@ -674,7 +674,7 @@ static bool lpass_hdmi_regmap_volatile(struct device *dev,
unsigned int reg)
return false;
}
-struct regmap_config lpass_hdmi_regmap_config = {
+static struct regmap_config lpass_hdmi_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
--
2.21.0
[PATCH v3 0/6] ASoC: codecs: add support for LPASS Codec macros
This patchset adds support for two Codec Macro blocks( WSA and VA) available in Qualcomm LPASS (Low Power Audio SubSystem). There are WSA, VA, TX and RX Macros on LPASS IP, each of the Macro block has specific connectivity like WSA Macros are intended to connect to WSA Smart speaker codecs via SoundWire. VA Macro is intended for DMICs, and TX/RX for Analog codecs via SoundWire like other WCD Codecs to provide headphone/ear/lineout etc .. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. This patchset has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Thanks, srini -Changes since v2: - various unnecessary variable intializations removed, suggested by Pierre - fixed a static checker error - collected reviews for dt-bindings. - fixed licence headers as suggested by Pierre. Srinivas Kandagatla (6): ASoC: qcom: dt-bindings: add bindings for lpass wsa macro codec ASoC: codecs: lpass-wsa-macro: Add support to WSA Macro ASoC: codecs: lpass-wsa-macro: add dapm widgets and route ASoC: qcom: dt-bindings: add bindings for lpass va macro codec ASoC: codecs: lpass-va-macro: Add support to VA Macro ASoC: codecs: lpass-va-macro: add dapm widgets and routes .../bindings/sound/qcom,lpass-va-macro.yaml | 67 + .../bindings/sound/qcom,lpass-wsa-macro.yaml | 69 + sound/soc/codecs/Kconfig |8 + sound/soc/codecs/Makefile |4 + sound/soc/codecs/lpass-va-macro.c | 1503 ++ sound/soc/codecs/lpass-wsa-macro.c| 2464 + sound/soc/codecs/lpass-wsa-macro.h| 17 + 7 files changed, 4132 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml create mode 100644 sound/soc/codecs/lpass-va-macro.c create mode 100644 sound/soc/codecs/lpass-wsa-macro.c create mode 100644 sound/soc/codecs/lpass-wsa-macro.h -- 2.21.0
[PATCH v3 1/6] ASoC: qcom: dt-bindings: add bindings for lpass wsa macro codec
This binding is for LPASS has internal codec WSA macro which is
for connecting with WSA Smart speakers.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
---
.../bindings/sound/qcom,lpass-wsa-macro.yaml | 69 +++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
new file mode 100644
index ..435b019a1e3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,lpass-wsa-macro.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPASS(Low Power Audio Subsystem) VA Macro audio codec DT bindings
+
+maintainers:
+ - Srinivas Kandagatla
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-wsa-macro
+
+ reg:
+maxItems: 1
+
+ "#sound-dai-cells":
+const: 1
+
+ '#clock-cells':
+const: 0
+
+ clocks:
+maxItems: 5
+
+ clock-names:
+items:
+ - const: mclk
+ - const: npl
+ - const: macro
+ - const: dcodec
+ - const: fsgen
+
+ clock-output-names:
+items:
+ - const: mclk
+
+ qcom,dmic-sample-rate:
+description: dmic sample rate
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ vdd-micb-supply:
+description: phandle to voltage regulator of MIC Bias
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+codec@324 {
+ compatible = "qcom,sm8250-lpass-wsa-macro";
+ reg = <0x324 0x1000>;
+ #sound-dai-cells = <1>;
+ #clock-cells = <0>;
+ clocks = <&audiocc 1>,
+ <&audiocc 0>,
+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&vamacro>;
+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+ clock-output-names = "mclk";
+};
--
2.21.0
[PATCH v3 6/6] ASoC: codecs: lpass-va-macro: add dapm widgets and routes
Add dapm widgets and routes for this codec.
Signed-off-by: Srinivas Kandagatla
---
sound/soc/codecs/lpass-va-macro.c | 620 ++
1 file changed, 620 insertions(+)
diff --git a/sound/soc/codecs/lpass-va-macro.c
b/sound/soc/codecs/lpass-va-macro.c
index e7590e70f2c0..b604de07e650 100644
--- a/sound/soc/codecs/lpass-va-macro.c
+++ b/sound/soc/codecs/lpass-va-macro.c
@@ -27,6 +27,8 @@
#define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088)
#define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C)
#define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090)
+#define CDC_VA_DMIC_EN_MASKBIT(0)
+#define CDC_VA_DMIC_ENABLE BIT(0)
#define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1)
#define CDC_VA_DMIC_CLK_SEL_SHFT 1
#define CDC_VA_DMIC_CLK_SEL_DIV0 0x0
@@ -452,6 +454,327 @@ static int va_macro_mclk_enable(struct va_macro *va, bool
mclk_enable)
return 0;
}
+static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+ struct va_macro *va = snd_soc_component_get_drvdata(comp);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ return va_macro_mclk_enable(va, true);
+ case SND_SOC_DAPM_POST_PMD:
+ return va_macro_mclk_enable(va, false);
+ }
+
+ return 0;
+}
+
+static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
+struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget =
+ snd_soc_dapm_kcontrol_widget(kcontrol);
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(widget->dapm);
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val;
+ u16 mic_sel_reg;
+
+ val = ucontrol->value.enumerated.item[0];
+
+ switch (e->reg) {
+ case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
+ mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
+ break;
+ case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
+ mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
+ break;
+ case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
+ mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
+ break;
+ case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
+ mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
+ break;
+ default:
+ dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
+ __func__, e->reg);
+ return -EINVAL;
+ }
+
+ if (val != 0)
+ snd_soc_component_update_bits(component, mic_sel_reg,
+ CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
+ CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
+
+ return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
+}
+
+static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
+struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget =
+ snd_soc_dapm_kcontrol_widget(kcontrol);
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(widget->dapm);
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ u32 dai_id = widget->shift;
+ u32 dec_id = mc->shift;
+ struct va_macro *va = snd_soc_component_get_drvdata(component);
+
+ if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
+ ucontrol->value.integer.value[0] = 1;
+ else
+ ucontrol->value.integer.value[0] = 0;
+
+ return 0;
+}
+
+static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
+struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget =
+ snd_soc_dapm_kcontrol_widget(kcontrol);
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(widget->dapm);
+ struct snd_soc_dapm_update *update = NULL;
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ u32 dai_id = widget->shift;
+ u32 dec_id = mc->shift;
+ u32 enable = ucontrol->value.integer.value[0];
+ struct va_macro *va = snd_soc_component_get_drvdata(component);
+
+ if (enable) {
+ set_bit(dec_id, &va->active_ch_mask[dai_id]);
+ va->active_ch_cnt[dai_id]++;
+ va->active_decimator[dai_id] = dec_id;
+ } else {
+ clear_bit(dec_id, &va->active_ch_mask[dai_id]);
[PATCH v3 5/6] ASoC: codecs: lpass-va-macro: Add support to VA Macro
Qualcomm LPASS (Low Power Audio SubSystem) has internal codec VA macro block which is used for connecting with DMICs. This patch adds support to the codec part of the VA Macro block Signed-off-by: Srinivas Kandagatla --- sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/lpass-va-macro.c | 883 ++ 3 files changed, 889 insertions(+) create mode 100644 sound/soc/codecs/lpass-va-macro.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index d91b51470a73..98d8624fec26 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1788,4 +1788,8 @@ config SND_SOC_LPASS_WSA_MACRO depends on COMMON_CLK tristate "Qualcomm WSA Macro in LPASS(Low Power Audio SubSystem)" +config SND_SOC_LPASS_VA_MACRO + depends on COMMON_CLK + tristate "Qualcomm VA Macro in LPASS(Low Power Audio SubSystem)" + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9f24b3daf5df..5d68da2b1182 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -104,6 +104,7 @@ snd-soc-lm4857-objs := lm4857.o snd-soc-lm49453-objs := lm49453.o snd-soc-lochnagar-sc-objs := lochnagar-sc.o snd-soc-lpass-wsa-macro-objs := lpass-wsa-macro.o +snd-soc-lpass-va-macro-objs := lpass-va-macro.o snd-soc-madera-objs := madera.o snd-soc-max9759-objs := max9759.o snd-soc-max9768-objs := max9768.o @@ -615,3 +616,4 @@ obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o obj-$(CONFIG_SND_SOC_SIMPLE_AMPLIFIER) += snd-soc-simple-amplifier.o obj-$(CONFIG_SND_SOC_TPA6130A2)+= snd-soc-tpa6130a2.o obj-$(CONFIG_SND_SOC_LPASS_WSA_MACRO) += snd-soc-lpass-wsa-macro.o +obj-$(CONFIG_SND_SOC_LPASS_VA_MACRO) += snd-soc-lpass-va-macro.o diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c new file mode 100644 index ..e7590e70f2c0 --- /dev/null +++ b/sound/soc/codecs/lpass-va-macro.c @@ -0,0 +1,883 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* VA macro registers */ +#define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x) +#define CDC_VA_MCLK_CONTROL_EN BIT(0) +#define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) +#define CDC_VA_FS_CONTROL_EN BIT(0) +#define CDC_VA_CLK_RST_CTRL_SWR_CONTROL(0x0008) +#define CDC_VA_TOP_CSR_TOP_CFG0(0x0080) +#define CDC_VA_FS_BROADCAST_EN BIT(1) +#define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084) +#define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088) +#define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C) +#define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090) +#define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1) +#define CDC_VA_DMIC_CLK_SEL_SHFT 1 +#define CDC_VA_DMIC_CLK_SEL_DIV0 0x0 +#define CDC_VA_DMIC_CLK_SEL_DIV1 0x2 +#define CDC_VA_DMIC_CLK_SEL_DIV2 0x4 +#define CDC_VA_DMIC_CLK_SEL_DIV3 0x6 +#define CDC_VA_DMIC_CLK_SEL_DIV4 0x8 +#define CDC_VA_DMIC_CLK_SEL_DIV5 0xa +#define CDC_VA_TOP_CSR_DMIC_CFG(0x0094) +#define CDC_VA_RESET_ALL_DMICS_MASKBIT(7) +#define CDC_VA_RESET_ALL_DMICS_RESET BIT(7) +#define CDC_VA_RESET_ALL_DMICS_DISABLE 0 +#define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3) +#define CDC_VA_DMIC3_FREQ_CHANGE_ENBIT(3) +#define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2) +#define CDC_VA_DMIC2_FREQ_CHANGE_ENBIT(2) +#define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1) +#define CDC_VA_DMIC1_FREQ_CHANGE_ENBIT(1) +#define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0) +#define CDC_VA_DMIC0_FREQ_CHANGE_ENBIT(0) +#define CDC_VA_DMIC_FREQ_CHANGE_DISABLE0 +#define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C) +#define CDC_VA_TOP_CSR_DEBUG_EN(0x00A0) +#define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4) +#define CDC_VA_TOP_CSR_I2S_CLK (0x00A8) +#define CDC_VA_TOP_CSR_I2S_RESET (0x00AC) +#define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0) +#define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4) +#define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8) +#define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC) +#define CDC_VA_TOP_CSR_SWR_MIC_CTL0(0x00D0) +#define CDC_VA_TOP_CSR_SWR_MIC_CTL1(0x00D4) +#define CDC_VA_TOP_CSR_SWR_MIC_CTL2(0x00D8) +#define CDC_VA_TOP_CSR_SWR_CTRL(0x00DC) +#define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100) +#define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104) +#define CDC_VA_I
[PATCH v3 4/6] ASoC: qcom: dt-bindings: add bindings for lpass va macro codec
This binding is for LPASS has internal codec VA macro which is
for connecting with DMICs.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
---
.../bindings/sound/qcom,lpass-va-macro.yaml | 67 +++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
new file mode 100644
index ..679b49cbe30f
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,lpass-va-macro.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPASS(Low Power Audio Subsystem) VA Macro audio codec DT bindings
+
+maintainers:
+ - Srinivas Kandagatla
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-va-macro
+
+ reg:
+maxItems: 1
+
+ "#sound-dai-cells":
+const: 1
+
+ '#clock-cells':
+const: 0
+
+ clocks:
+maxItems: 3
+
+ clock-names:
+items:
+ - const: mclk
+ - const: core
+ - const: dcodec
+
+ clock-output-names:
+items:
+ - const: fsgen
+
+ qcom,dmic-sample-rate:
+description: dmic sample rate
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ vdd-micb-supply:
+description: phandle to voltage regulator of MIC Bias
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+codec@337 {
+ compatible = "qcom,sm8250-lpass-va-macro";
+ reg = <0x337 0x1000>;
+ #sound-dai-cells = <1>;
+ #clock-cells = <0>;
+ clocks = <&aoncc 0>,
+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk", "core", "dcodec";
+ clock-output-names = "fsgen";
+ qcom,dmic-sample-rate = <60>;
+ vdd-micb-supply = <&vreg_s4a_1p8>;
+};
--
2.21.0
[PATCH v3 2/6] ASoC: codecs: lpass-wsa-macro: Add support to WSA Macro
Qualcomm LPASS (Low Power Audio SubSystem) has internal codec WSA macro block which is used for connecting with WSA Smart speakers over soundwire. This patch adds support to the codec part of the WSA Macro block. Signed-off-by: Srinivas Kandagatla --- sound/soc/codecs/Kconfig |4 + sound/soc/codecs/Makefile |2 + sound/soc/codecs/lpass-wsa-macro.c | 1383 sound/soc/codecs/lpass-wsa-macro.h | 17 + 4 files changed, 1406 insertions(+) create mode 100644 sound/soc/codecs/lpass-wsa-macro.c create mode 100644 sound/soc/codecs/lpass-wsa-macro.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 5791b7056af6..d91b51470a73 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1784,4 +1784,8 @@ config SND_SOC_TPA6130A2 tristate "Texas Instruments TPA6130A2 headphone amplifier" depends on I2C +config SND_SOC_LPASS_WSA_MACRO + depends on COMMON_CLK + tristate "Qualcomm WSA Macro in LPASS(Low Power Audio SubSystem)" + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 11ce98c25d6c..9f24b3daf5df 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -103,6 +103,7 @@ snd-soc-l3-objs := l3.o snd-soc-lm4857-objs := lm4857.o snd-soc-lm49453-objs := lm49453.o snd-soc-lochnagar-sc-objs := lochnagar-sc.o +snd-soc-lpass-wsa-macro-objs := lpass-wsa-macro.o snd-soc-madera-objs := madera.o snd-soc-max9759-objs := max9759.o snd-soc-max9768-objs := max9768.o @@ -613,3 +614,4 @@ obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o obj-$(CONFIG_SND_SOC_SIMPLE_AMPLIFIER) += snd-soc-simple-amplifier.o obj-$(CONFIG_SND_SOC_TPA6130A2)+= snd-soc-tpa6130a2.o +obj-$(CONFIG_SND_SOC_LPASS_WSA_MACRO) += snd-soc-lpass-wsa-macro.o diff --git a/sound/soc/codecs/lpass-wsa-macro.c b/sound/soc/codecs/lpass-wsa-macro.c new file mode 100644 index ..76873d582eff --- /dev/null +++ b/sound/soc/codecs/lpass-wsa-macro.c @@ -0,0 +1,1383 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lpass-wsa-macro.h" + +#define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x) +#define CDC_WSA_MCLK_EN_MASK BIT(0) +#define CDC_WSA_MCLK_ENABLEBIT(0) +#define CDC_WSA_MCLK_DISABLE 0 +#define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL(0x0004) +#define CDC_WSA_FS_CNT_EN_MASK BIT(0) +#define CDC_WSA_FS_CNT_ENABLE BIT(0) +#define CDC_WSA_FS_CNT_DISABLE 0 +#define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008) +#define CDC_WSA_SWR_CLK_EN_MASKBIT(0) +#define CDC_WSA_SWR_CLK_ENABLE BIT(0) +#define CDC_WSA_SWR_RST_EN_MASKBIT(1) +#define CDC_WSA_SWR_RST_ENABLE BIT(1) +#define CDC_WSA_SWR_RST_DISABLE0 +#define CDC_WSA_TOP_TOP_CFG0 (0x0080) +#define CDC_WSA_TOP_TOP_CFG1 (0x0084) +#define CDC_WSA_TOP_FREQ_MCLK (0x0088) +#define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C) +#define CDC_WSA_TOP_DEBUG_EN0 (0x0090) +#define CDC_WSA_TOP_DEBUG_EN1 (0x0094) +#define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098) +#define CDC_WSA_TOP_RX_I2S_CTL (0x009C) +#define CDC_WSA_TOP_TX_I2S_CTL (0x00A0) +#define CDC_WSA_TOP_I2S_CLK(0x00A4) +#define CDC_WSA_TOP_I2S_RESET (0x00A8) +#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0(0x0100) +#define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASKGENMASK(5, 3) +#define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0) +#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1(0x0104) +#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0(0x0108) +#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1(0x010C) +#define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110) +#define CDC_WSA_RX_MIX_TX1_SEL_MASKGENMASK(5, 3) +#define CDC_WSA_RX_MIX_TX1_SEL_SHFT3 +#define CDC_WSA_RX_MIX_TX0_SEL_MASKGENMASK(2, 0) +#define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) +#define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) +#define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) +#define CDC_WSA_TX_SPKR_PROT_RESET_MASKBIT(5) +#define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) +#define CDC_WSA_TX_SPKR_PROT_NO_RESET 0 +#define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4) +#define CDC_WSA_TX_SPKR_PROT_CLK_ENABLEBIT(4) +#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0 +#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0) +#define CD
[PATCH v3 3/6] ASoC: codecs: lpass-wsa-macro: add dapm widgets and route
This patch adds dapm widgets and routes on this codec
Signed-off-by: Srinivas Kandagatla
---
sound/soc/codecs/lpass-wsa-macro.c | 1081
1 file changed, 1081 insertions(+)
diff --git a/sound/soc/codecs/lpass-wsa-macro.c
b/sound/soc/codecs/lpass-wsa-macro.c
index 76873d582eff..25f1df214ca5 100644
--- a/sound/soc/codecs/lpass-wsa-macro.c
+++ b/sound/soc/codecs/lpass-wsa-macro.c
@@ -354,6 +354,26 @@ struct wsa_macro {
static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
+static const char *const rx_text[] = {
+ "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1"
+};
+
+static const char *const rx_mix_text[] = {
+ "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1"
+};
+
+static const char *const rx_mix_ec_text[] = {
+ "ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
+};
+
+static const char *const rx_mux_text[] = {
+ "ZERO", "AIF1_PB", "AIF_MIX1_PB"
+};
+
+static const char *const rx_sidetone_mix_text[] = {
+ "ZERO", "SRC0"
+};
+
static const char * const wsa_macro_ear_spkr_pa_gain_text[] = {
"G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB",
"G_4_DB", "G_5_DB", "G_6_DB"
@@ -362,6 +382,84 @@ static const char * const
wsa_macro_ear_spkr_pa_gain_text[] = {
static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum,
wsa_macro_ear_spkr_pa_gain_text);
+/* RX INT0 */
+static const struct soc_enum rx0_prim_inp0_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
+ 0, 7, rx_text);
+
+static const struct soc_enum rx0_prim_inp1_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
+ 3, 7, rx_text);
+
+static const struct soc_enum rx0_prim_inp2_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
+ 3, 7, rx_text);
+
+static const struct soc_enum rx0_mix_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
+ 0, 5, rx_mix_text);
+
+static const struct soc_enum rx0_sidetone_mix_enum =
+ SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
+
+static const struct snd_kcontrol_new rx0_prim_inp0_mux =
+ SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum);
+
+static const struct snd_kcontrol_new rx0_prim_inp1_mux =
+ SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx0_prim_inp2_mux =
+ SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx0_mix_mux =
+ SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum);
+
+static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
+ SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
+
+/* RX INT1 */
+static const struct soc_enum rx1_prim_inp0_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
+ 0, 7, rx_text);
+
+static const struct soc_enum rx1_prim_inp1_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
+ 3, 7, rx_text);
+
+static const struct soc_enum rx1_prim_inp2_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
+ 3, 7, rx_text);
+
+static const struct soc_enum rx1_mix_chain_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
+ 0, 5, rx_mix_text);
+
+static const struct snd_kcontrol_new rx1_prim_inp0_mux =
+ SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum);
+
+static const struct snd_kcontrol_new rx1_prim_inp1_mux =
+ SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx1_prim_inp2_mux =
+ SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix_mux =
+ SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum);
+
+static const struct soc_enum rx_mix_ec0_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
+ 0, 3, rx_mix_ec_text);
+
+static const struct soc_enum rx_mix_ec1_enum =
+ SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
+ 3, 3, rx_mix_ec_text);
+
+static const struct snd_kcontrol_new rx_mix_ec0_mux =
+ SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
+
+static const struct snd_kcontrol_new rx_mix_ec1_mux =
+ SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
+
static const struct reg_default wsa_defaults[] = {
/* WSA Macro */
{ CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
@@ -1038,6 +1136,613 @@ static void wsa_macro_mclk_enable(struct
[PATCH] soundwire: Fix DEBUG_LOCKS_WARN_ON for uninitialized attribute
running kernel with CONFIG_DEBUG_LOCKS_ALLOC enabled will below warning:
BUG: key 502e09807098 has not been registered!
DEBUG_LOCKS_WARN_ON(1)
WARNING: CPU: 5 PID: 129 at kernel/locking/lockdep.c:4623
lockdep_init_map_waits+0xe8/0x250
Modules linked in:
CPU: 5 PID: 129 Comm: kworker/5:1 Tainted: G
W 5.10.0-rc1-00277-ged49f224ca3f-dirty #1210
Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT)
Workqueue: events deferred_probe_work_func
pstate: 80c5 (Nzcv daif +PAN +UAO -TCO BTYPE=--)
pc : lockdep_init_map_waits+0xe8/0x250
lr : lockdep_init_map_waits+0xe8/0x250
[ Trimmed ]
Call trace:
lockdep_init_map_waits+0xe8/0x250
__kernfs_create_file+0x78/0x180
sysfs_add_file_mode_ns+0x94/0x1c8
internal_create_group+0x110/0x3e0
sysfs_create_group+0x18/0x28
devm_device_add_group+0x4c/0xb0
add_all_attributes+0x438/0x490
sdw_slave_sysfs_dpn_init+0x128/0x138
sdw_slave_sysfs_init+0x80/0xa0
sdw_drv_probe+0x94/0x170
really_probe+0x118/0x3e0
driver_probe_device+0x5c/0xc0
[ Trimmed ]
CPU: 5 PID: 129 Comm: kworker/5:1 Tainted: G
W 5.10.0-rc1-00277-ged49f224ca3f-dirty #1210
Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT)
Workqueue: events deferred_probe_work_func
Call trace:
dump_backtrace+0x0/0x1c0
show_stack+0x18/0x68
dump_stack+0xd8/0x134
__warn+0xa0/0x158
report_bug+0xc8/0x178
bug_handler+0x20/0x78
brk_handler+0x70/0xc8
[ Trimmed ]
Fix this by initializing dynamically allocated sysfs attribute to keep lockdep
happy!
Fixes: bcac59029955 ("soundwire: add Slave sysfs support")
Signed-off-by: Srinivas Kandagatla
---
drivers/soundwire/sysfs_slave_dpn.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soundwire/sysfs_slave_dpn.c
b/drivers/soundwire/sysfs_slave_dpn.c
index 05a721ea9830..c4b6543c09fd 100644
--- a/drivers/soundwire/sysfs_slave_dpn.c
+++ b/drivers/soundwire/sysfs_slave_dpn.c
@@ -37,6 +37,7 @@ static int field##_attribute_alloc(struct device *dev,
\
return -ENOMEM; \
dpn_attr->N = N;\
dpn_attr->dir = dir;\
+ sysfs_attr_init(&dpn_attr->dev_attr.attr); \
dpn_attr->format_string = format_string;\
dpn_attr->dev_attr.attr.name = __stringify(field); \
dpn_attr->dev_attr.attr.mode = 0444;\
--
2.21.0
Re: [PATCH v2 2/6] ASoC: codecs: lpass-wsa-macro: Add support to WSA Macro
On 29/10/2020 15:47, Pierre-Louis Bossart wrote:
+static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool
mclk_enable)
+{
+ struct regmap *regmap = wsa->regmap;
+
+ if (mclk_enable) {
+ if (wsa->wsa_mclk_users == 0) {
+ regcache_mark_dirty(regmap);
+ regcache_sync_region(regmap, 0x0, WSA_MAX_OFFSET);
I am not a regcache/regmap expert but the sequence seems odd. I could be
wrong, but one would typically sync *after* doing changes, no?
In this code path the MCLK is going from OFF to ON state, so the
registers would be put in reset state, so we need to sync them with
current cache state!
--srini
Re: [PATCH v2 3/6] ASoC: codecs: lpass-wsa-macro: add dapm widgets and route
On 29/10/2020 15:52, Pierre-Louis Bossart wrote:
+static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
+ u16 gain_reg;
+ int offset_val = 0;
+ int val = 0;
+
+ switch (w->reg) {
+ case CDC_WSA_RX0_RX_PATH_MIX_CTL:
+ gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
+ break;
+ case CDC_WSA_RX1_RX_PATH_MIX_CTL:
+ gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
+ break;
+ default:
+ return 0;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ val = snd_soc_component_read(component, gain_reg);
+ val += offset_val;
+ snd_soc_component_write(component, gain_reg, val);
missed from v1: offset_val is zero so the sequence is reading and
writing the same thing. Is this intentional or useful?
Its useless, I should get rid of offset_val!
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_component_update_bits(component, w->reg,
+ CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
+ CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
+ break;
+ }
+
+ return 0;
+}
+
[...]
+static bool wsa_macro_adie_lb(struct snd_soc_component *component,
+ int interp_idx)
+{
+ u16 int_mux_cfg0 = 0, int_mux_cfg1 = 0;
these inits are ignored
+ u8 int_mux_cfg0_val = 0, int_mux_cfg1_val = 0;
these as well
+ u8 int_n_inp0 = 0, int_n_inp1 = 0, int_n_inp2 = 0;
and these are also ignored.
Yes, these are ignored, I should have removed the unnecessary
initialization!
It would have been nice if sparse could catch such errors!
are you using tool to catch these?
--srini
+ int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
+ int_mux_cfg1 = int_mux_cfg0 + 4;
+ int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
+ int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
+
+ int_n_inp0 = int_mux_cfg0_val & 0x0F;
+ if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
+ int_n_inp0 == INTn_1_INP_SEL_DEC1)
+ return true;
+
+ int_n_inp1 = int_mux_cfg0_val >> 4;
+ if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
+ int_n_inp1 == INTn_1_INP_SEL_DEC1)
+ return true;
+
+ int_n_inp2 = int_mux_cfg1_val >> 4;
+ if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
+ int_n_inp2 == INTn_1_INP_SEL_DEC1)
+ return true;
+
+ return false;
+}
Re: [PATCH] ASoC: wcd9335: remove unneeded semicolon
Thanks for the patch, On 01/11/2020 17:21, t...@redhat.com wrote: From: Tom Rix A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix Reviewed-by: Srinivas Kandagatla --- sound/soc/codecs/wcd-clsh-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/wcd-clsh-v2.c b/sound/soc/codecs/wcd-clsh-v2.c index 817d8259758c..73258e292e7e 100644 --- a/sound/soc/codecs/wcd-clsh-v2.c +++ b/sound/soc/codecs/wcd-clsh-v2.c @@ -507,7 +507,7 @@ static bool wcd_clsh_is_state_valid(int state) return true; default: return false; - }; + } } /*
Re: [PATCH v2 5/6] ASoC: codecs: lpass-va-macro: Add support to VA Macro
Thanks Pierre for review,
On 29/10/2020 15:56, Pierre-Louis Bossart wrote:
diff --git a/sound/soc/codecs/lpass-va-macro.c
b/sound/soc/codecs/lpass-va-macro.c
new file mode 100644
index ..8cb23c32631d
--- /dev/null
+++ b/sound/soc/codecs/lpass-va-macro.c
@@ -0,0 +1,882 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
Missing copyright information?
I will recheck this on all files and fix it before sending next version!
--srini
[...]
+module_platform_driver(va_macro_driver);
+MODULE_DESCRIPTION("VA macro driver");
+MODULE_LICENSE("GPL v2");
"GPL" ? The v2 adds no information.
https://www.kernel.org/doc/html/latest/process/license-rules.html
“GPL” Module is licensed under GPL version 2. This does not express
any distinction between GPL-2.0-only or GPL-2.0-or-later. The exact
license information can only be determined via the license information
in the corresponding source files.
“GPL v2” Same as “GPL”. It exists for historic reasons.
Re: [PATCH v3 0/4] nvmem: qfprom: Avoid untouchable regions
On 29/10/2020 00:28, Evan Green wrote: Certain fuses are protected by the XPU such that the AP cannot access them. Attempting to do so causes an SError. Introduce an SoC-specific compatible string, and introduce support into the nvmem core to avoid accessing specified regions. Then use those new elements in the qfprom driver to avoid SErrors when usermode accesses certain registers. Changes in v3: - Fixed example (Doug and rob-bot) - Use min()/max() macros instead of defining my own (Doug) - Comment changes to indicate sorting (Doug) - Add function to validate keepouts are proper (Doug) Changes in v2: - Add other soc compatible strings (Doug) - Fix compatible string definition (Doug) - Introduced keepout regions into the core (Srini) - Use new core support in qfprom (Srini) Evan Green (4): dt-bindings: nvmem: Add soc qfprom compatible strings arm64: dts: qcom: sc7180: Add soc-specific qfprom compat string nvmem: core: Add support for keepout regions nvmem: qfprom: Don't touch certain fuses Except dts patch, I have applied all the patches, dts patch should go via arm-soc tree! --srini .../bindings/nvmem/qcom,qfprom.yaml | 17 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- drivers/nvmem/core.c | 153 +- drivers/nvmem/qfprom.c| 30 include/linux/nvmem-provider.h| 17 ++ 5 files changed, 211 insertions(+), 8 deletions(-)
[PATCH 0/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl support
This patch adds support for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. This patch has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Srinivas Kandagatla (2): dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 +++ drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 781 ++ 4 files changed, 919 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c -- 2.21.0
[PATCH 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SM8250
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla
---
.../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 ++
1 file changed, 129 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
diff --git
a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index ..8a0732574aee
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ clocks:
+items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+const: 2
+
+ gpio-ranges:
+maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '^.*$':
+if:
+ type: object
+then:
+ properties:
+pins:
+ description:
+List of gpio pins affected by the properties specified in this
+subnode.
+ items:
+oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 14
+
+function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws,
+ swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1,
+ swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2,
+ dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk,
+ i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk,
+ i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data,
+ i2s2_data1 ]
+ description:
+Specify the alternative function to be configured for the specified
+pins.
+
+drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+Selects the drive strength for the specified pins, in mA.
+
+slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+bias-pull-down: true
+
+bias-pull-up: true
+
+bias-disable: true
+
+output-high: true
+
+output-low: true
+
+ required:
+- pins
+- function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lpi_tlmm: pinctrl@33c {
+compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+reg = <0x33c 0x2>,
+ <0x355a000 0x1000>;
+clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+clock-names = "core", "audio";
+gpio-controller;
+#gpio-cells = <2>;
+gpio-ranges = <&lpi_tlmm 0 0 14>;
+};
--
2.21.0
[PATCH 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 781 +++
3 files changed, 790 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..af26f4c51f77 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB && OF
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..88937485e3bb
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_GPIO_REG_VAL_CTL 0x00
+#define LPI_GPIO_REG_DIR_CTL 0x04
+#define LPI_SLEW_REG_VAL_CTL 0x00
+#define LPI_SLEW_RATE_MAX0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_GPIO_REG_PULL_SHIFT0x0
+#define LPI_GPIO_REG_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_REG_FUNCTION_SHIFT0x2
+#define LPI_GPIO_REG_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_REG_OUT_STRENGTH_SHIFT0x6
+#define LPI_GPIO_REG_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_REG_OE_SHIFT 0x9
+#define LPI_GPIO_REG_OE_MASK BIT(9)
+#define LPI_GPIO_REG_DIR_SHIFT 0x1
+#define LPI_GPIO_REG_DIR_MASK 0x2
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5,\
+ }
+struct lpi_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int npins;
+ unsigned int pin;
+ unsigned int *funcs;
+ unsigned int nfuncs;
+};
+
+struct lpi_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct lpi_pinctrl_variant_data {
+ int tlmm_reg_offset;
+ const struct pinctrl_pin_desc *pins;
+ int npins;
+ const struct lpi_pingroup *groups;
+ int ngroups;
+ const struct lpi_function *functions;
+ int nfunctions;
+ int *slew_reg_pin_offsets;
+};
+
+struct lpi_pinctrl {
+ struct device *dev;
Re: [PATCH v2 19/39] docs: ABI: stable: make files ReST compatible
On 30/10/2020 07:40, Mauro Carvalho Chehab wrote: Several entries at the stable ABI files won't parse if we pass them directly to the ReST output. Adjust them, in order to allow adding their contents as-is at the stable ABI book. Signed-off-by: Mauro Carvalho Chehab --- Documentation/ABI/stable/firewire-cdev| 4 + Documentation/ABI/stable/sysfs-acpi-pmprofile | 22 +++-- Documentation/ABI/stable/sysfs-bus-firewire | 3 + Documentation/ABI/stable/sysfs-bus-nvmem | 19 ++-- for nvmem parts: Acked-by: Srinivas Kandagatla --srini Documentation/ABI/stable/sysfs-bus-usb| 6 +- .../ABI/stable/sysfs-class-backlight | 1 + .../ABI/stable/sysfs-class-infiniband | 93 +-- Documentation/ABI/stable/sysfs-class-rfkill | 13 ++- Documentation/ABI/stable/sysfs-class-tpm | 90 +- Documentation/ABI/stable/sysfs-devices| 5 +- Documentation/ABI/stable/sysfs-driver-ib_srp | 1 + .../ABI/stable/sysfs-firmware-efi-vars| 4 + .../ABI/stable/sysfs-firmware-opal-dump | 5 + .../ABI/stable/sysfs-firmware-opal-elog | 2 + Documentation/ABI/stable/sysfs-hypervisor-xen | 3 + Documentation/ABI/stable/vdso | 5 +- 16 files changed, 176 insertions(+), 100 deletions(-)
Re: [PATCH v3 3/4] nvmem: core: Add support for keepout regions
Thanks Evan for doing this,
On 29/10/2020 00:28, Evan Green wrote:
Introduce support into the nvmem core for arrays of register ranges
that should not result in actual device access. For these regions a
constant byte (repeated) is returned instead on read, and writes are
quietly ignored and returned as successful.
This is useful for instance if certain efuse regions are protected
from access by Linux because they contain secret info to another part
of the system (like an integrated modem).
Signed-off-by: Evan Green
Overall the patch looks good for me.
I have applied just this patch for more testing in next!
I can pick up 1/4 and 4/4 once Rob's Ack/Reviews the patch!
thanks,
srini
---
Changes in v3:
- Use min()/max() macros instead of defining my own (Doug)
- Comment changes to indicate sorting (Doug)
- Add function to validate keepouts are proper (Doug)
Changes in v2:
- Introduced keepout regions into the core (Srini)
drivers/nvmem/core.c | 153 -
include/linux/nvmem-provider.h | 17
2 files changed, 166 insertions(+), 4 deletions(-)
diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c
index a09ff8409f600..177f5bf27c6d5 100644
--- a/drivers/nvmem/core.c
+++ b/drivers/nvmem/core.c
@@ -34,6 +34,8 @@ struct nvmem_device {
struct bin_attributeeeprom;
struct device *base_dev;
struct list_headcells;
+ const struct nvmem_keepout *keepout;
+ unsigned intnkeepout;
nvmem_reg_read_treg_read;
nvmem_reg_write_t reg_write;
struct gpio_desc*wp_gpio;
@@ -66,8 +68,8 @@ static LIST_HEAD(nvmem_lookup_list);
static BLOCKING_NOTIFIER_HEAD(nvmem_notifier);
-static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset,
- void *val, size_t bytes)
+static int __nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset,
+ void *val, size_t bytes)
{
if (nvmem->reg_read)
return nvmem->reg_read(nvmem->priv, offset, val, bytes);
@@ -75,8 +77,8 @@ static int nvmem_reg_read(struct nvmem_device *nvmem,
unsigned int offset,
return -EINVAL;
}
-static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset,
- void *val, size_t bytes)
+static int __nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset,
+void *val, size_t bytes)
{
int ret;
@@ -90,6 +92,88 @@ static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset,
return -EINVAL;
}
+static int nvmem_access_with_keepouts(struct nvmem_device *nvmem,
+ unsigned int offset, void *val,
+ size_t bytes, int write)
+{
+
+ unsigned int end = offset + bytes;
+ unsigned int kend, ksize;
+ const struct nvmem_keepout *keepout = nvmem->keepout;
+ const struct nvmem_keepout *keepoutend = keepout + nvmem->nkeepout;
+ int rc;
+
+ /*
+* Skip all keepouts before the range being accessed.
+* Keepouts are sorted.
+*/
+ while ((keepout < keepoutend) && (keepout->end <= offset))
+ keepout++;
+
+ while ((offset < end) && (keepout < keepoutend)) {
+ /* Access the valid portion before the keepout. */
+ if (offset < keepout->start) {
+ kend = min(end, keepout->start);
+ ksize = kend - offset;
+ if (write)
+ rc = __nvmem_reg_write(nvmem, offset, val,
ksize);
+ else
+ rc = __nvmem_reg_read(nvmem, offset, val,
ksize);
+
+ if (rc)
+ return rc;
+
+ offset += ksize;
+ val += ksize;
+ }
+
+ /*
+* Now we're aligned to the start of this keepout zone. Go
+* through it.
+*/
+ kend = min(end, keepout->end);
+ ksize = kend - offset;
+ if (!write)
+ memset(val, keepout->value, ksize);
+
+ val += ksize;
+ offset += ksize;
+ keepout++;
+ }
+
+ /*
+* If we ran out of keepouts but there's still stuff to do, send it
+* down directly
+*/
+ if (offset < end) {
+ ksize = end - offset;
+ if (write)
+ return __nvmem_reg_write(nvmem, offset, val, ksize);
+ else
+ return __nvmem_reg_read(nvmem, offset, val, ksize);
+ }
+
+ return 0;
+}
+
+static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset,
+ void *val, size_t bytes)
+{
+ if (!n
[PATCH v2 6/6] ASoC: codecs: lpass-va-macro: add dapm widgets and routes
Add dapm widgets and routes for this codec.
Signed-off-by: Srinivas Kandagatla
---
sound/soc/codecs/lpass-va-macro.c | 618 ++
1 file changed, 618 insertions(+)
diff --git a/sound/soc/codecs/lpass-va-macro.c
b/sound/soc/codecs/lpass-va-macro.c
index 8cb23c32631d..ff86f20c6180 100644
--- a/sound/soc/codecs/lpass-va-macro.c
+++ b/sound/soc/codecs/lpass-va-macro.c
@@ -451,6 +451,327 @@ static int va_macro_mclk_enable(struct va_macro *va, bool
mclk_enable)
return 0;
}
+static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+ struct va_macro *va = snd_soc_component_get_drvdata(comp);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ return va_macro_mclk_enable(va, true);
+ case SND_SOC_DAPM_POST_PMD:
+ return va_macro_mclk_enable(va, false);
+ }
+
+ return 0;
+}
+
+static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
+struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget =
+ snd_soc_dapm_kcontrol_widget(kcontrol);
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(widget->dapm);
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val;
+ u16 mic_sel_reg;
+
+ val = ucontrol->value.enumerated.item[0];
+
+ switch (e->reg) {
+ case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
+ mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
+ break;
+ case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
+ mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
+ break;
+ case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
+ mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
+ break;
+ case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
+ mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
+ break;
+ default:
+ dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
+ __func__, e->reg);
+ return -EINVAL;
+ }
+
+ if (val != 0)
+ snd_soc_component_update_bits(component, mic_sel_reg,
+ CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
+ CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
+
+ return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
+}
+
+static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
+struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget =
+ snd_soc_dapm_kcontrol_widget(kcontrol);
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(widget->dapm);
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ u32 dai_id = widget->shift;
+ u32 dec_id = mc->shift;
+ struct va_macro *va = snd_soc_component_get_drvdata(component);
+
+ if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
+ ucontrol->value.integer.value[0] = 1;
+ else
+ ucontrol->value.integer.value[0] = 0;
+
+ return 0;
+}
+
+static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
+struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget *widget =
+ snd_soc_dapm_kcontrol_widget(kcontrol);
+ struct snd_soc_component *component =
+ snd_soc_dapm_to_component(widget->dapm);
+ struct snd_soc_dapm_update *update = NULL;
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ u32 dai_id = widget->shift;
+ u32 dec_id = mc->shift;
+ u32 enable = ucontrol->value.integer.value[0];
+ struct va_macro *va = snd_soc_component_get_drvdata(component);
+
+ if (enable) {
+ set_bit(dec_id, &va->active_ch_mask[dai_id]);
+ va->active_ch_cnt[dai_id]++;
+ va->active_decimator[dai_id] = dec_id;
+ } else {
+ clear_bit(dec_id, &va->active_ch_mask[dai_id]);
+ va->active_ch_cnt[dai_id]--;
+ va->active_decimator[dai_id] = -1;
+ }
+
+ snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
+
+ return 0;
+}
+
+static int va_dmic_clk_enable(struct snd_soc_component *component,
+ u32 dmic, bool enable)
+{
+ struct va_macro *va = snd_soc_component_get_drvdata(component);
+ u8 dmic_clk_en = 0x01;
+ u16 dmic_clk_reg;
+ s32 *dmic_clk_cnt
[PATCH v2 4/6] ASoC: qcom: dt-bindings: add bindings for lpass va macro codec
This binding is for LPASS has internal codec VA macro which is
for connecting with DMICs.
Signed-off-by: Srinivas Kandagatla
---
.../bindings/sound/qcom,lpass-va-macro.yaml | 67 +++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
new file mode 100644
index ..679b49cbe30f
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,lpass-va-macro.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPASS(Low Power Audio Subsystem) VA Macro audio codec DT bindings
+
+maintainers:
+ - Srinivas Kandagatla
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-va-macro
+
+ reg:
+maxItems: 1
+
+ "#sound-dai-cells":
+const: 1
+
+ '#clock-cells':
+const: 0
+
+ clocks:
+maxItems: 3
+
+ clock-names:
+items:
+ - const: mclk
+ - const: core
+ - const: dcodec
+
+ clock-output-names:
+items:
+ - const: fsgen
+
+ qcom,dmic-sample-rate:
+description: dmic sample rate
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ vdd-micb-supply:
+description: phandle to voltage regulator of MIC Bias
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+codec@337 {
+ compatible = "qcom,sm8250-lpass-va-macro";
+ reg = <0x337 0x1000>;
+ #sound-dai-cells = <1>;
+ #clock-cells = <0>;
+ clocks = <&aoncc 0>,
+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk", "core", "dcodec";
+ clock-output-names = "fsgen";
+ qcom,dmic-sample-rate = <60>;
+ vdd-micb-supply = <&vreg_s4a_1p8>;
+};
--
2.21.0
[PATCH v2 3/6] ASoC: codecs: lpass-wsa-macro: add dapm widgets and route
This patch adds dapm widgets and routes on this codec
Signed-off-by: Srinivas Kandagatla
---
sound/soc/codecs/lpass-wsa-macro.c | 1006
1 file changed, 1006 insertions(+)
diff --git a/sound/soc/codecs/lpass-wsa-macro.c
b/sound/soc/codecs/lpass-wsa-macro.c
index 75381d80a791..d3de35e80cf0 100644
--- a/sound/soc/codecs/lpass-wsa-macro.c
+++ b/sound/soc/codecs/lpass-wsa-macro.c
@@ -398,6 +398,21 @@ static const struct soc_enum rx0_mix_chain_enum =
static const struct soc_enum rx0_sidetone_mix_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
+static const struct snd_kcontrol_new rx0_prim_inp0_mux =
+ SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum);
+
+static const struct snd_kcontrol_new rx0_prim_inp1_mux =
+ SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx0_prim_inp2_mux =
+ SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx0_mix_mux =
+ SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum);
+
+static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
+ SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
+
/* RX INT1 */
static const struct soc_enum rx1_prim_inp0_chain_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
@@ -435,6 +450,12 @@ static const struct soc_enum rx_mix_ec1_enum =
SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
3, 3, rx_mix_ec_text);
+static const struct snd_kcontrol_new rx_mix_ec0_mux =
+ SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
+
+static const struct snd_kcontrol_new rx_mix_ec1_mux =
+ SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
+
static const struct reg_default wsa_defaults[] = {
/* WSA Macro */
{ CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
@@ -1121,6 +1142,615 @@ static void wsa_macro_mclk_enable(struct wsa_macro
*wsa, bool mclk_enable)
}
}
+static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
+ struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
+
+ wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
+ return 0;
+}
+
+static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
+ struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
+ u32 tx_reg0, tx_reg1;
+
+ if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
+ tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
+ tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL;
+ } else if (test_bit(WSA_MACRO_TX1,
&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
+ tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL;
+ tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ /* Enable V&I sensing */
+ snd_soc_component_update_bits(component, tx_reg0,
+ CDC_WSA_TX_SPKR_PROT_RESET_MASK,
+ CDC_WSA_TX_SPKR_PROT_RESET);
+ snd_soc_component_update_bits(component, tx_reg1,
+ CDC_WSA_TX_SPKR_PROT_RESET_MASK,
+ CDC_WSA_TX_SPKR_PROT_RESET);
+ snd_soc_component_update_bits(component, tx_reg0,
+
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
+ CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
+ snd_soc_component_update_bits(component, tx_reg1,
+
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
+ CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
+ snd_soc_component_update_bits(component, tx_reg0,
+ CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
+ CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
+ snd_soc_component_update_bits(component, tx_reg1,
+ CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
+ CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
+ snd_soc_component_update_bits(component, tx_reg0,
+ CDC_WSA_TX_SPKR_PROT_RESET_MASK,
+ CD
[PATCH v2 5/6] ASoC: codecs: lpass-va-macro: Add support to VA Macro
Qualcomm LPASS (Low Power Audio SubSystem) has internal codec VA macro block which is used for connecting with DMICs. This patch adds support to the codec part of the VA Macro block Signed-off-by: Srinivas Kandagatla --- sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/lpass-va-macro.c | 882 ++ 3 files changed, 888 insertions(+) create mode 100644 sound/soc/codecs/lpass-va-macro.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index d91b51470a73..98d8624fec26 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1788,4 +1788,8 @@ config SND_SOC_LPASS_WSA_MACRO depends on COMMON_CLK tristate "Qualcomm WSA Macro in LPASS(Low Power Audio SubSystem)" +config SND_SOC_LPASS_VA_MACRO + depends on COMMON_CLK + tristate "Qualcomm VA Macro in LPASS(Low Power Audio SubSystem)" + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9f24b3daf5df..5d68da2b1182 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -104,6 +104,7 @@ snd-soc-lm4857-objs := lm4857.o snd-soc-lm49453-objs := lm49453.o snd-soc-lochnagar-sc-objs := lochnagar-sc.o snd-soc-lpass-wsa-macro-objs := lpass-wsa-macro.o +snd-soc-lpass-va-macro-objs := lpass-va-macro.o snd-soc-madera-objs := madera.o snd-soc-max9759-objs := max9759.o snd-soc-max9768-objs := max9768.o @@ -615,3 +616,4 @@ obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o obj-$(CONFIG_SND_SOC_SIMPLE_AMPLIFIER) += snd-soc-simple-amplifier.o obj-$(CONFIG_SND_SOC_TPA6130A2)+= snd-soc-tpa6130a2.o obj-$(CONFIG_SND_SOC_LPASS_WSA_MACRO) += snd-soc-lpass-wsa-macro.o +obj-$(CONFIG_SND_SOC_LPASS_VA_MACRO) += snd-soc-lpass-va-macro.o diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c new file mode 100644 index ..8cb23c32631d --- /dev/null +++ b/sound/soc/codecs/lpass-va-macro.c @@ -0,0 +1,882 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* VA macro registers */ +#define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x) +#define CDC_VA_MCLK_CONTROL_EN BIT(0) +#define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) +#define CDC_VA_FS_CONTROL_EN BIT(0) +#define CDC_VA_CLK_RST_CTRL_SWR_CONTROL(0x0008) +#define CDC_VA_TOP_CSR_TOP_CFG0(0x0080) +#define CDC_VA_FS_BROADCAST_EN BIT(1) +#define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084) +#define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088) +#define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C) +#define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090) +#define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1) +#define CDC_VA_DMIC_CLK_SEL_SHFT 1 +#define CDC_VA_DMIC_CLK_SEL_DIV0 0x0 +#define CDC_VA_DMIC_CLK_SEL_DIV1 0x2 +#define CDC_VA_DMIC_CLK_SEL_DIV2 0x4 +#define CDC_VA_DMIC_CLK_SEL_DIV3 0x6 +#define CDC_VA_DMIC_CLK_SEL_DIV4 0x8 +#define CDC_VA_DMIC_CLK_SEL_DIV5 0xa +#define CDC_VA_TOP_CSR_DMIC_CFG(0x0094) +#define CDC_VA_RESET_ALL_DMICS_MASKBIT(7) +#define CDC_VA_RESET_ALL_DMICS_RESET BIT(7) +#define CDC_VA_RESET_ALL_DMICS_DISABLE 0 +#define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3) +#define CDC_VA_DMIC3_FREQ_CHANGE_ENBIT(3) +#define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2) +#define CDC_VA_DMIC2_FREQ_CHANGE_ENBIT(2) +#define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1) +#define CDC_VA_DMIC1_FREQ_CHANGE_ENBIT(1) +#define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0) +#define CDC_VA_DMIC0_FREQ_CHANGE_ENBIT(0) +#define CDC_VA_DMIC_FREQ_CHANGE_DISABLE0 +#define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C) +#define CDC_VA_TOP_CSR_DEBUG_EN(0x00A0) +#define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4) +#define CDC_VA_TOP_CSR_I2S_CLK (0x00A8) +#define CDC_VA_TOP_CSR_I2S_RESET (0x00AC) +#define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0) +#define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4) +#define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8) +#define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC) +#define CDC_VA_TOP_CSR_SWR_MIC_CTL0(0x00D0) +#define CDC_VA_TOP_CSR_SWR_MIC_CTL1(0x00D4) +#define CDC_VA_TOP_CSR_SWR_MIC_CTL2(0x00D8) +#define CDC_VA_TOP_CSR_SWR_CTRL(0x00DC) +#define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100) +#define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104) +#define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108) +#define CDC_VA_INP_MUX_ADC_MUX1_CF
[PATCH v2 2/6] ASoC: codecs: lpass-wsa-macro: Add support to WSA Macro
Qualcomm LPASS (Low Power Audio SubSystem) has internal codec WSA macro block which is used for connecting with WSA Smart speakers over soundwire. This patch adds support to the codec part of the WSA Macro block. Signed-off-by: Srinivas Kandagatla --- sound/soc/codecs/Kconfig |4 + sound/soc/codecs/Makefile |2 + sound/soc/codecs/lpass-wsa-macro.c | 1466 sound/soc/codecs/lpass-wsa-macro.h | 15 + 4 files changed, 1487 insertions(+) create mode 100644 sound/soc/codecs/lpass-wsa-macro.c create mode 100644 sound/soc/codecs/lpass-wsa-macro.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 5791b7056af6..d91b51470a73 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1784,4 +1784,8 @@ config SND_SOC_TPA6130A2 tristate "Texas Instruments TPA6130A2 headphone amplifier" depends on I2C +config SND_SOC_LPASS_WSA_MACRO + depends on COMMON_CLK + tristate "Qualcomm WSA Macro in LPASS(Low Power Audio SubSystem)" + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 11ce98c25d6c..9f24b3daf5df 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -103,6 +103,7 @@ snd-soc-l3-objs := l3.o snd-soc-lm4857-objs := lm4857.o snd-soc-lm49453-objs := lm49453.o snd-soc-lochnagar-sc-objs := lochnagar-sc.o +snd-soc-lpass-wsa-macro-objs := lpass-wsa-macro.o snd-soc-madera-objs := madera.o snd-soc-max9759-objs := max9759.o snd-soc-max9768-objs := max9768.o @@ -613,3 +614,4 @@ obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o obj-$(CONFIG_SND_SOC_SIMPLE_AMPLIFIER) += snd-soc-simple-amplifier.o obj-$(CONFIG_SND_SOC_TPA6130A2)+= snd-soc-tpa6130a2.o +obj-$(CONFIG_SND_SOC_LPASS_WSA_MACRO) += snd-soc-lpass-wsa-macro.o diff --git a/sound/soc/codecs/lpass-wsa-macro.c b/sound/soc/codecs/lpass-wsa-macro.c new file mode 100644 index ..75381d80a791 --- /dev/null +++ b/sound/soc/codecs/lpass-wsa-macro.c @@ -0,0 +1,1466 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lpass-wsa-macro.h" + +#define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x) +#define CDC_WSA_MCLK_EN_MASK BIT(0) +#define CDC_WSA_MCLK_ENABLEBIT(0) +#define CDC_WSA_MCLK_DISABLE 0 +#define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL(0x0004) +#define CDC_WSA_FS_CNT_EN_MASK BIT(0) +#define CDC_WSA_FS_CNT_ENABLE BIT(0) +#define CDC_WSA_FS_CNT_DISABLE 0 +#define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008) +#define CDC_WSA_TOP_TOP_CFG0 (0x0080) +#define CDC_WSA_TOP_TOP_CFG1 (0x0084) +#define CDC_WSA_TOP_FREQ_MCLK (0x0088) +#define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C) +#define CDC_WSA_TOP_DEBUG_EN0 (0x0090) +#define CDC_WSA_TOP_DEBUG_EN1 (0x0094) +#define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098) +#define CDC_WSA_TOP_RX_I2S_CTL (0x009C) +#define CDC_WSA_TOP_TX_I2S_CTL (0x00A0) +#define CDC_WSA_TOP_I2S_CLK(0x00A4) +#define CDC_WSA_TOP_I2S_RESET (0x00A8) +#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0(0x0100) +#define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASKGENMASK(5, 3) +#define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0) +#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1(0x0104) +#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0(0x0108) +#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1(0x010C) +#define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110) +#define CDC_WSA_RX_MIX_TX1_SEL_MASKGENMASK(5, 3) +#define CDC_WSA_RX_MIX_TX1_SEL_SHFT3 +#define CDC_WSA_RX_MIX_TX0_SEL_MASKGENMASK(2, 0) +#define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) +#define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) +#define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) +#define CDC_WSA_TX_SPKR_PROT_RESET_MASKBIT(5) +#define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) +#define CDC_WSA_TX_SPKR_PROT_NO_RESET 0 +#define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4) +#define CDC_WSA_TX_SPKR_PROT_CLK_ENABLEBIT(4) +#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0 +#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0) +#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0 +#define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0(0x0248) +#define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264) +#define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0(0x0268) +#define CDC_WSA_TX2_SPKR_PROT_PATH
[PATCH v2 1/6] ASoC: qcom: dt-bindings: add bindings for lpass wsa macro codec
This binding is for LPASS has internal codec WSA macro which is
for connecting with WSA Smart speakers.
Signed-off-by: Srinivas Kandagatla
---
.../bindings/sound/qcom,lpass-wsa-macro.yaml | 69 +++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
new file mode 100644
index ..435b019a1e3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,lpass-wsa-macro.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPASS(Low Power Audio Subsystem) VA Macro audio codec DT bindings
+
+maintainers:
+ - Srinivas Kandagatla
+
+properties:
+ compatible:
+const: qcom,sm8250-lpass-wsa-macro
+
+ reg:
+maxItems: 1
+
+ "#sound-dai-cells":
+const: 1
+
+ '#clock-cells':
+const: 0
+
+ clocks:
+maxItems: 5
+
+ clock-names:
+items:
+ - const: mclk
+ - const: npl
+ - const: macro
+ - const: dcodec
+ - const: fsgen
+
+ clock-output-names:
+items:
+ - const: mclk
+
+ qcom,dmic-sample-rate:
+description: dmic sample rate
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ vdd-micb-supply:
+description: phandle to voltage regulator of MIC Bias
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+codec@324 {
+ compatible = "qcom,sm8250-lpass-wsa-macro";
+ reg = <0x324 0x1000>;
+ #sound-dai-cells = <1>;
+ #clock-cells = <0>;
+ clocks = <&audiocc 1>,
+ <&audiocc 0>,
+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&vamacro>;
+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+ clock-output-names = "mclk";
+};
--
2.21.0
[PATCH v2 0/6] ASoC: codecs: add support for LPASS Codec macros
This patchset adds support for two Codec Macro blocks( WSA and VA) available in Qualcomm LPASS (Low Power Audio SubSystem). There are WSA, VA, TX and RX Macros on LPASS IP, each of the Macro block has specific connectivity like WSA Macros are intended to connect to WSA Smart speaker codecs via SoundWire. VA Macro is intended for DMICs, and TX/RX for Analog codecs via SoundWire like other WCD Codecs to provide headphone/ear/lineout etc .. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. This patchset has been tested on support to Qualcomm Robotics RB5 Development Kit based on QRB5165 Robotics SoC. This board has 2 WSA881X smart speakers with onboard DMIC connected to internal LPASS codec via WSA and VA macros respectively. Thanks, srini -Changes since v1: - updated code to fix cppcheck errors suggested by Pierre - fixed various coding style and variable initialization suggested by Pierre. - yaml bindings clock names replaced with constants. Srinivas Kandagatla (6): ASoC: qcom: dt-bindings: add bindings for lpass wsa macro codec ASoC: codecs: lpass-wsa-macro: Add support to WSA Macro ASoC: codecs: lpass-wsa-macro: add dapm widgets and route ASoC: qcom: dt-bindings: add bindings for lpass va macro codec ASoC: codecs: lpass-va-macro: Add support to VA Macro ASoC: codecs: lpass-va-macro: add dapm widgets and routes .../bindings/sound/qcom,lpass-va-macro.yaml | 67 + .../bindings/sound/qcom,lpass-wsa-macro.yaml | 69 + sound/soc/codecs/Kconfig |8 + sound/soc/codecs/Makefile |4 + sound/soc/codecs/lpass-va-macro.c | 1500 ++ sound/soc/codecs/lpass-wsa-macro.c| 2472 + sound/soc/codecs/lpass-wsa-macro.h| 15 + 7 files changed, 4135 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml create mode 100644 sound/soc/codecs/lpass-va-macro.c create mode 100644 sound/soc/codecs/lpass-wsa-macro.c create mode 100644 sound/soc/codecs/lpass-wsa-macro.h -- 2.21.0
[PATCH 1/2] ASoC: qcom: dt-bindings: sm8250: update compatibles
Update compatible string as board compatible and device compatible
should not be same!. New compatible is now suffixed with -sndcard
to be inline with other Qualcomm Sound cards.
This also fixes the warnings/error reported by dt_binding_check.
Fixes: 765c37598494 ("ASoC: qcom: dt-bindings: Add SM8250 sound card bindings")
Reported-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree/bindings/sound/qcom,sm8250.yaml | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
index b8f97fe6e92c..72ad9ab91832 100644
--- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
@@ -16,10 +16,8 @@ description:
properties:
compatible:
oneOf:
- - const: qcom,qrb5165-rb5
- - items:
-- const: qcom,sm8250
-- const: qcom,qrb5165-rb5
+ - const: qcom,sm8250-sndcard
+ - const: qcom,qrb5165-rb5-sndcard
audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
@@ -83,7 +81,7 @@ examples:
#include
#include
sound {
-compatible = "qcom,qrb5165-rb5";
+compatible = "qcom,qrb5165-rb5-sndcard";
model = "Qualcomm-qrb5165-RB5-WSA8815-Speakers-DMIC0";
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
--
2.21.0
[PATCH 2/2] ASoC: qcom: sm8250: update compatible with new bindings
Update compatible string as board compatible and device compatible
should not be same!. Make the driver inline with the new bindings.
Fixes: aa2e2785545a ("ASoC: qcom: sm8250: add sound card qrb5165-rb5 support")
Reported-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
---
sound/soc/qcom/sm8250.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/qcom/sm8250.c b/sound/soc/qcom/sm8250.c
index 52c40512102f..315ed6ccb7c4 100644
--- a/sound/soc/qcom/sm8250.c
+++ b/sound/soc/qcom/sm8250.c
@@ -207,8 +207,8 @@ static int sm8250_platform_probe(struct platform_device
*pdev)
}
static const struct of_device_id snd_sm8250_dt_match[] = {
- {.compatible = "qcom,sdm8250"},
- {.compatible = "qcom,qrb5165-rb5"},
+ {.compatible = "qcom,sm8250-sndcard"},
+ {.compatible = "qcom,qrb5165-rb5-sndcard"},
{}
};
--
2.21.0
