[linux-sunxi] Re: [PATCH v4 5/9] sunxi: add support for Cubietruck booting in FEL mode
On Thursday, May 01, 2014 at 08:40:48 PM, Ian Campbell wrote: Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Jens Kuske jensku...@gmail.com Signed-off-by: Ian Campbell i...@hellion.org.uk Reviewed-by: Tom Rini tr...@ti.com Reviewed-by: Marek Vasut ma...@denx.de --- v4: Based on d9fe0a1e061e sunxi: mksunxiboot: remove unnecessary casts. v3: Based on c89867dca2e9 sunxi: clocks: clock_get_pll5 prototype and coding style. v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c sunxi: mmc: checkpatch whitespace fixes with v2014.04-rc2 merged in. v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 arm: Handle .gnu.hash section in ldscripts vs v2014.01. Reviewed-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 8/9] sunxi: non-FEL SPL boot support for sun7i
On Thursday, May 01, 2014 at 08:40:51 PM, Ian Campbell wrote: Add support for booting from an MMC card. Signed-off-by: Stefan Roese s...@denx.de Signed-off-by: Henrik Nordström hen...@henriknordstrom.net Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Tom Cubie mr.hip...@gmail.com Reviewed-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 4/9] sunxi: add sun7i cpu, board and start of day support
On Thursday, May 01, 2014 at 08:40:47 PM, Ian Campbell wrote: This patch adds generic board, start of day and basic build system support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Adam Sampson a...@offog.org Signed-off-by: Aleksei Mamlin mamli...@gmail.com Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com Signed-off-by: Chen-Yu Tsai w...@csie.org Signed-off-by: Emilio López emi...@elopez.com.ar Signed-off-by: Hans de Goede hdego...@redhat.com Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net Signed-off-by: Jens Kuske jensku...@gmail.com Signed-off-by: Luc Verhaegen l...@skynet.be Signed-off-by: Luke Leighton l...@lkcl.net Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Patrick Wood patrickhw...@gmail.com Signed-off-by: Stefan Roese s...@denx.de Signed-off-by: Wills Wang wills.wang.o...@gmail.com Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Tom Cubie mr.hip...@gmail.com Reviewed-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 7/9] sunxi: mmc support
On Thursday, May 01, 2014 at 08:40:50 PM, Ian Campbell wrote: This adds support for the MMC controller on the Allwinner A20 (sun7i) processor. Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net Signed-off-by: Luke Leighton l...@lkcl.net Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Wills Wang wills.wang.o...@gmail.com Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Stefan Roese s...@denx.de Cc: Tom Cubie mr.hip...@gmail.com Cc: Aaron Maoye leafy.m...@allwinnertech.com Cc: Pantelis Antoniou pa...@antoniou-consulting.com Reviewed-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 6/9] sunxi: add gmac Ethernet support
On Thursday, May 01, 2014 at 08:40:49 PM, Ian Campbell wrote: Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i) processors. Enable for the Cubietruck. Signed-off-by: Chen-Yu Tsai w...@csie.org Signed-off-by: Jens Kuske jensku...@gmail.com Signed-off-by: Ian Campbell i...@hellion.org.uk Reviewed-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v5 2/8] dt-bindings: add vendor-prefix for X-Powers
On Fri, May 2, 2014 at 7:24 AM, Michal Simek mon...@monstr.eu wrote: On 05/01/2014 02:29 PM, Carlo Caione wrote: Signed-off-by: Carlo Caione ca...@caione.org --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index abc3080..792cf56 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -135,3 +135,4 @@ wmWondermedia Technologies, Inc. xes Extreme Engineering Solutions (X-ES) xlnx Xilinx zyxelZyXEL Communications Corp. +x-powers X-Powers Keep list sorted. Fooled by rebasing on master :( I'll sort it, thanks. -- Carlo Caione -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v5 1/8] mfd: AXP20x: Add mfd driver for AXP20x PMIC
This patch introduces the preliminary support for PMICs X-Powers AXP202 and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit) used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company of Allwinner. The core enables support for two subsystems: - PEK (Power Enable Key) - Regulators Signed-off-by: Carlo Caione ca...@caione.org Acked-by: Lee Jones lee.jo...@linaro.org --- I guess I can just apply this and expect not to see any adverse symptoms? -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH v5 1/8] mfd: AXP20x: Add mfd driver for AXP20x PMIC
On Fri, May 2, 2014 at 10:15 AM, Lee Jones lee.jo...@linaro.org wrote: This patch introduces the preliminary support for PMICs X-Powers AXP202 and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit) used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company of Allwinner. The core enables support for two subsystems: - PEK (Power Enable Key) - Regulators Signed-off-by: Carlo Caione ca...@caione.org Acked-by: Lee Jones lee.jo...@linaro.org --- I guess I can just apply this and expect not to see any adverse symptoms? It has been tested with a sun7i/cubieboard2 with to adverse symptoms. It's not core stuff so I guess you could apply it. Thank you, -- Carlo Caione -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [U-Boot] [PATCH v4 4/9] sunxi: add sun7i cpu, board and start of day support
Hi Ian, On 2014-05-01 19:40, Ian Campbell wrote: This patch adds generic board, start of day and basic build system support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Adam Sampson a...@offog.org Signed-off-by: Aleksei Mamlin mamli...@gmail.com Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com Signed-off-by: Chen-Yu Tsai w...@csie.org Signed-off-by: Emilio López emi...@elopez.com.ar Signed-off-by: Hans de Goede hdego...@redhat.com Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net Signed-off-by: Jens Kuske jensku...@gmail.com Signed-off-by: Luc Verhaegen l...@skynet.be Signed-off-by: Luke Leighton l...@lkcl.net Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Patrick Wood patrickhw...@gmail.com Signed-off-by: Stefan Roese s...@denx.de Signed-off-by: Wills Wang wills.wang.o...@gmail.com Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Tom Cubie mr.hip...@gmail.com --- v4: Based on d9fe0a1e061e sunxi: mksunxiboot: remove unnecessary casts. v3: Based on c89867dca2e9 sunxi: clocks: clock_get_pll5 prototype and coding style. v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c sunxi: mmc: checkpatch whitespace fixes with v2014.04-rc2 merged in: - just init dram once - remove clock ramping until power control is implemented - add CONFIG_SUN7I to simplify future SUN?I support. - fix a typo v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 arm: Handle .gnu.hash section in ldscripts vs v2014.01. --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/sunxi/Makefile | 11 +++ arch/arm/cpu/armv7/sunxi/board.c| 88 + arch/arm/cpu/armv7/sunxi/cpu_info.c | 19 arch/arm/cpu/armv7/sunxi/start.c| 1 + arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 77 +++ arch/arm/include/asm/arch-sunxi/cpu.h | 122 arch/arm/include/asm/arch-sunxi/spl.h | 20 board/sunxi/Makefile| 11 +++ board/sunxi/board.c | 57 +++ include/configs/sun7i.h | 24 + include/configs/sunxi-common.h | 141 12 files changed, 572 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/sunxi/board.c create mode 100644 arch/arm/cpu/armv7/sunxi/cpu_info.c create mode 100644 arch/arm/cpu/armv7/sunxi/start.c create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h create mode 100644 arch/arm/include/asm/arch-sunxi/spl.h create mode 100644 board/sunxi/Makefile create mode 100644 board/sunxi/board.c create mode 100644 include/configs/sun7i.h create mode 100644 include/configs/sunxi-common.h [...] diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h new file mode 100644 index 000..7400559 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. www.allwinnertech.com + * Tom Cubie tangli...@allwinnertech.com + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_H +#define _SUNXI_CPU_H + +#define SUNXI_SRAM_A1_BASE 0x +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define SUNXI_SRAM_A2_BASE 0x4000 /* 16 kiB */ +#define SUNXI_SRAM_A3_BASE 0x8000 /* 13 kiB */ +#define SUNXI_SRAM_A4_BASE 0xb400 /* 3 kiB */ +#define SUNXI_SRAM_D_BASE 0x01c0 +#define SUNXI_SRAM_B_BASE 0x01c0 /* 64 kiB (secure) */ Can we please fix these last two values which are obviously wrong (at least on sun7i, they point to the SRAM controller address, as shown in the documentation on page 18). I've been carrying a patch for this in my tree: http://git.kernel.org/cgit/linux/kernel/git/maz/u-boot.git/commit/?h=wip/psci-v4-a20id=e8cea4226fdbf7718f0b888b32f24d2803b168c6 Can you squash it into your next version? Thanks, M. -- Who you jivin' with that Cosmik Debris? -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 3/3] ARM: sun7i: dt: Add ahci/sata support to pcDuino3 DTS
This patch adds sunxi SATA support to the pcDuino V3 board.
Signed-off-by: Zoltan HERPAI wigy...@uid0.hu
---
arch/arm/boot/dts/sun7i-a20-pcduino3.dts |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 100717f..a92e49c 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -20,6 +20,11 @@
compatible = linksprite,a20-pcduino3, allwinner,sun7i-a20;
soc@01c0 {
+ ahci: sata@01c18000 {
+ target-supply = reg_ahci_5v;
+ status = okay;
+ };
+
pinctrl@01c20800 {
led_pins_pcduino3: led_pins@0 {
allwinner,pins = PH2;
@@ -96,4 +101,8 @@
reg_usb2_vbus: usb2-vbus {
status = okay;
};
+
+ reg_ahci_5v: ahci-5v {
+ status = okay;
+ };
};
--
1.7.10.4
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[linux-sunxi] [PATCH 0/3] Add board support for LinkSprite pcDuino V3
The LinkSprite pcDuino V3 is an A20-based revision of the earlier pcDuinos. This series will add support for the board, along with some of its devices where the driver is accepted or soon-to-be-accepted into mainline. Signed-off-by: Zoltan HERPAI wigy...@uid0.hu Zoltan HERPAI (3): ARM: sun7i: dt: Add basic board support for LinkSprite pcDuino V3 ARM: sun7i: dt: Add USB host nodes to pcDuino3 DTS ARM: sun7i: dt: Add ahci/sata support to pcDuino3 DTS arch/arm/boot/dts/Makefile |3 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 108 ++ 2 files changed, 110 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun7i-a20-pcduino3.dts -- 1.7.10.4 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 1/3] ARM: sun7i: dt: Add basic board support for LinkSprite pcDuino V3
This patch will add a basic board support DT for the
LinkSprite pcDuino V3, which is based on A20.
Signed-off-by: Zoltan HERPAI wigy...@uid0.hu
---
arch/arm/boot/dts/Makefile |3 +-
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 70 ++
2 files changed, 72 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun7i-a20-pcduino3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1cd137d..821fa99 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -354,7 +354,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
sun6i-a31-m9.dtb \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
- sun7i-a20-olinuxino-micro.dtb
+ sun7i-a20-olinuxino-micro.dtb \
+ sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
tegra20-medcom-wide.dtb \
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
new file mode 100644
index 000..bf9d527
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI wigy...@uid0.hu
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ sun7i-a20.dtsi
+/include/ sunxi-common-regulators.dtsi
+#include dt-bindings/input/input.h
+
+/ {
+ model = LinkSprite pcDuino V3;
+ compatible = linksprite,a20-pcduino3, allwinner,sun7i-a20;
+
+ soc@01c0 {
+ pinctrl@01c20800 {
+ led_pins_pcduino3: led_pins@0 {
+ allwinner,pins = PH2;
+ allwinner,function = gpio_out;
+ allwinner,drive = 1;
+ allwinner,pull = 0;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+ };
+
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins_a;
+ status = okay;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ gmac: ethernet@01c5 {
+ pinctrl-names = default;
+ pinctrl-0 = gmac_pins_mii_a;
+ phy = phy1;
+ phy-mode = mii;
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
+ };
+
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_pins_pcduino3;
+
+ green {
+ label = a20-pcduino3:green:usr;
+ gpios = pio 7 2 0;
+ default-state = on;
+ };
+ };
+
+};
--
1.7.10.4
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Re: [linux-sunxi] [PATCH 0/3] Add board support for LinkSprite pcDuino V3
On Fri, May 02, 2014 at 01:45:03PM +0200, Zoltan HERPAI wrote: The LinkSprite pcDuino V3 is an A20-based revision of the earlier pcDuinos. This series will add support for the board, along with some of its devices where the driver is accepted or soon-to-be-accepted into mainline. Signed-off-by: Zoltan HERPAI wigy...@uid0.hu Zoltan HERPAI (3): ARM: sun7i: dt: Add basic board support for LinkSprite pcDuino V3 ARM: sun7i: dt: Add USB host nodes to pcDuino3 DTS ARM: sun7i: dt: Add ahci/sata support to pcDuino3 DTS Where is the sunxi wiki page on this hw? Seems like you never worked through our New_Device_howto, and never added sunxi-3.4 support to begin with. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [U-Boot] [PATCH v4 4/9] sunxi: add sun7i cpu, board and start of day support
On Fri, 2014-05-02 at 10:45 +0100, Marc Zyngier wrote: #define SUNXI_SRAM_D_BASE 0x01c0 +#define SUNXI_SRAM_B_BASE 0x01c0 /* 64 kiB (secure) */ Can we please fix these last two values which are obviously wrong (at least on sun7i, they point to the SRAM controller address, as shown in the documentation on page 18). I've been carrying a patch for this in my tree: http://git.kernel.org/cgit/linux/kernel/git/maz/u-boot.git/commit/?h=wip/psci-v4-a20id=e8cea4226fdbf7718f0b888b32f24d2803b168c6 Can you squash it into your next version? Yes. Well, actually what I will do is repost it for application to u-boot-sunxi.git and then resync, but the affect is the same. Ian. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 3/3] ARM: sun7i: dt: Add ahci/sata support to pcDuino3 DTS
Hi,
On 05/02/2014 01:45 PM, Zoltan HERPAI wrote:
This patch adds sunxi SATA support to the pcDuino V3 board.
Signed-off-by: Zoltan HERPAI wigy...@uid0.hu
While git am-ing this for the sunxi-devel branch I got the following:
/home/hans/projects/sunxi/linux/.git/rebase-apply/patch:15: space before tab in
indent.
status = okay;
/home/hans/projects/sunxi/linux/.git/rebase-apply/patch:27: space before tab in
indent.
status = okay;
warning: 2 lines add whitespace errors.
Regards,
Hans
---
arch/arm/boot/dts/sun7i-a20-pcduino3.dts |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 100717f..a92e49c 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -20,6 +20,11 @@
compatible = linksprite,a20-pcduino3, allwinner,sun7i-a20;
soc@01c0 {
+ ahci: sata@01c18000 {
+ target-supply = reg_ahci_5v;
+ status = okay;
+ };
+
pinctrl@01c20800 {
led_pins_pcduino3: led_pins@0 {
allwinner,pins = PH2;
@@ -96,4 +101,8 @@
reg_usb2_vbus: usb2-vbus {
status = okay;
};
+
+ reg_ahci_5v: ahci-5v {
+ status = okay;
+ };
};
--
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Re: [linux-sunxi] [PATCH 0/3] Add board support for LinkSprite pcDuino V3
On Fri, 2 May 2014, Luc Verhaegen wrote: On Fri, May 02, 2014 at 01:45:03PM +0200, Zoltan HERPAI wrote: The LinkSprite pcDuino V3 is an A20-based revision of the earlier pcDuinos. This series will add support for the board, along with some of its devices where the driver is accepted or soon-to-be-accepted into mainline. Where is the sunxi wiki page on this hw? Seems like you never worked through our New_Device_howto, and never added sunxi-3.4 support to begin with. I've created the wiki page for the v3, and have updated the earlier v1/v2 page as well. For the u-boot support, the patch is yet to be created and sent. Regards, -w- -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH 3/3] ARM: sun7i: dt: Add ahci/sata support to pcDuino3 DTS
Hi,
On Fri, 2 May 2014, Hans de Goede wrote:
While git am-ing this for the sunxi-devel branch I got the following:
/home/hans/projects/sunxi/linux/.git/rebase-apply/patch:15: space before tab in
indent.
status = okay;
/home/hans/projects/sunxi/linux/.git/rebase-apply/patch:27: space before tab in
indent.
status = okay;
warning: 2 lines add whitespace errors.
Hmm, this wasn't caught with the checkpatch I've used from 3.13.8. Let me
do a re-send.
Regards,
-w-
---
arch/arm/boot/dts/sun7i-a20-pcduino3.dts |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 100717f..a92e49c 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -20,6 +20,11 @@
compatible = linksprite,a20-pcduino3, allwinner,sun7i-a20;
soc@01c0 {
+ ahci: sata@01c18000 {
+ target-supply = reg_ahci_5v;
+ status = okay;
+ };
+
pinctrl@01c20800 {
led_pins_pcduino3: led_pins@0 {
allwinner,pins = PH2;
@@ -96,4 +101,8 @@
reg_usb2_vbus: usb2-vbus {
status = okay;
};
+
+ reg_ahci_5v: ahci-5v {
+ status = okay;
+ };
};
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Re: [linux-sunxi] Re: [U-Boot] [PATCH v4 4/9] sunxi: add sun7i cpu, board and start of day support
On 2014-05-02 13:31, Ian Campbell wrote: On Fri, 2014-05-02 at 10:45 +0100, Marc Zyngier wrote: #define SUNXI_SRAM_D_BASE 0x01c0 +#define SUNXI_SRAM_B_BASE 0x01c0 /* 64 kiB (secure) */ Can we please fix these last two values which are obviously wrong (at least on sun7i, they point to the SRAM controller address, as shown in the documentation on page 18). I've been carrying a patch for this in my tree: http://git.kernel.org/cgit/linux/kernel/git/maz/u-boot.git/commit/?h=wip/psci-v4-a20id=e8cea4226fdbf7718f0b888b32f24d2803b168c6 Can you squash it into your next version? Yes. Well, actually what I will do is repost it for application to u-boot-sunxi.git and then resync, but the affect is the same. Sure. Whatever is the most convenient for everyone. Thanks, M. -- Who you jivin' with that Cosmik Debris? -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v10 04/15] ARM: dts: sun4i: Add mmc controller nodes
From: David Lanzendörfer david.lanzendoer...@o2s.ch
Add nodes for the 4 mmc controllers found on A10 SoCs to
arch/arm/boot/dts/sun4i-a10.dtsi.
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index fe845eb..a0240b7 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -377,6 +377,42 @@
#size-cells = 0;
};
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun4i-a10-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb_gates 8, mmc0_clk;
+ clock-names = ahb, mmc;
+ interrupts = 32;
+ status = disabled;
+ };
+
+ mmc1: mmc@01c1 {
+ compatible = allwinner,sun4i-a10-mmc;
+ reg = 0x01c1 0x1000;
+ clocks = ahb_gates 9, mmc1_clk;
+ clock-names = ahb, mmc;
+ interrupts = 33;
+ status = disabled;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = allwinner,sun4i-a10-mmc;
+ reg = 0x01c11000 0x1000;
+ clocks = ahb_gates 10, mmc2_clk;
+ clock-names = ahb, mmc;
+ interrupts = 34;
+ status = disabled;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = allwinner,sun4i-a10-mmc;
+ reg = 0x01c12000 0x1000;
+ clocks = ahb_gates 11, mmc3_clk;
+ clock-names = ahb, mmc;
+ interrupts = 35;
+ status = disabled;
+ };
+
usbphy: phy@01c13400 {
#phy-cells = 1;
compatible = allwinner,sun4i-a10-usb-phy;
--
1.9.0
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[linux-sunxi] [PATCH v10 08/15] ARM: dts: sun5i: Enable mmc controller on various A10s and A13 boards
The cd pin settings have been taken from the original firmware fex files,
and have been confirmed to work on the actual boards.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 32
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 16
arch/arm/boot/dts/sun5i-a13-olinuxino.dts| 16
3 files changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 23611b7..de91308 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -35,6 +35,24 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_olinuxino_micro;
+ bus-width = 4;
+ cd-gpios = pio 6 1 0; /* PG1 */
+ cd-inverted;
+ status = okay;
+ };
+
+ mmc1: mmc@01c1 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc1_pins_a,
mmc1_cd_pin_olinuxino_micro;
+ bus-width = 4;
+ cd-gpios = pio 6 13 0; /* PG13 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
status = okay;
@@ -49,6 +67,20 @@
};
pinctrl@01c20800 {
+ mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
+ allwinner,pins = PG1;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
+ allwinner,pins = PG13;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
led_pins_olinuxino: led_pins@0 {
allwinner,pins = PE3;
allwinner,function = gpio_out;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 11169d5..8515f19 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -21,6 +21,15 @@
compatible = olimex,a13-olinuxino-micro, allwinner,sun5i-a13;
soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a, mmc0_cd_pin_olinuxinom;
+ bus-width = 4;
+ cd-gpios = pio 6 0 0; /* PG0 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
status = okay;
@@ -35,6 +44,13 @@
};
pinctrl@01c20800 {
+ mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
+ allwinner,pins = PG0;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
led_pins_olinuxinom: led_pins@0 {
allwinner,pins = PG9;
allwinner,function = gpio_out;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 7a9187b..51a9438 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -20,6 +20,15 @@
compatible = olimex,a13-olinuxino, allwinner,sun5i-a13;
soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a, mmc0_cd_pin_olinuxino;
+ bus-width = 4;
+ cd-gpios = pio 6 0 0; /* PG0 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
status = okay;
@@ -34,6 +43,13 @@
};
pinctrl@01c20800 {
+ mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
+ allwinner,pins = PG0;
+ allwinner,function = gpio_in;
+
[linux-sunxi] [PATCH v10 11/15] ARM: dts: sun6i: Add new sun6i-a31-m9 dts file for Mele M9
Add a new sun6i-a31-m9 dts file for the Mele M9 / Mele A1000G Quad. These
HTPCs use the same board in a different case, for more details see:
http://linux-sunxi.org/Mele_M9
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun6i-a31-m9.dts | 48 ++
2 files changed, 49 insertions(+)
create mode 100644 arch/arm/boot/dts/sun6i-a31-m9.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 377b7c3..ffa3f5e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -344,6 +344,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun6i-a31-colombus.dtb \
+ sun6i-a31-m9.dtb \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-olinuxino-micro.dtb
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts
b/arch/arm/boot/dts/sun6i-a31-m9.dts
new file mode 100644
index 000..22eacf8
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ sun6i-a31.dtsi
+
+/ {
+ model = Mele M9 / A1000G Quad top set box;
+ compatible = mele,m9, allwinner,sun6i-a31;
+
+ chosen {
+ bootargs = earlyprintk console=ttyS0,115200;
+ };
+
+ soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a, mmc0_cd_pin_m9;
+ bus-width = 4;
+ cd-gpios = pio 7 22 0; /* PH22 */
+ cd-inverted;
+ status = okay;
+ };
+
+ pio: pinctrl@01c20800 {
+ mmc0_cd_pin_m9: mmc0_cd_pin@0 {
+ allwinner,pins = PH22;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+ };
+ };
+};
--
1.9.0
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[linux-sunxi] [PATCH v10 10/15] ARM: dts: sun6i: Add mmc controller nodes
Add nodes for the 4 mmc controllers found on A31 SoCs to
arch/arm/boot/dts/sun6i-a31.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index f2bb07c..d97721d 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -277,6 +277,50 @@
#size-cells = 1;
ranges;
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb1_gates 8, mmc0_clk;
+ clock-names = ahb, mmc;
+ resets = ahb1_rst 8;
+ reset-names = ahb;
+ interrupts = 0 60 4;
+ status = disabled;
+ };
+
+ mmc1: mmc@01c1 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c1 0x1000;
+ clocks = ahb1_gates 9, mmc1_clk;
+ clock-names = ahb, mmc;
+ resets = ahb1_rst 9;
+ reset-names = ahb;
+ interrupts = 0 61 4;
+ status = disabled;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c11000 0x1000;
+ clocks = ahb1_gates 10, mmc2_clk;
+ clock-names = ahb, mmc;
+ resets = ahb1_rst 10;
+ reset-names = ahb;
+ interrupts = 0 62 4;
+ status = disabled;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c12000 0x1000;
+ clocks = ahb1_gates 11, mmc3_clk;
+ clock-names = ahb, mmc;
+ resets = ahb1_rst 11;
+ reset-names = ahb;
+ interrupts = 0 63 4;
+ status = disabled;
+ };
+
nmi_intc: interrupt-controller@01f00c0c {
compatible = allwinner,sun6i-a31-sc-nmi;
interrupt-controller;
--
1.9.0
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[linux-sunxi] [PATCH v10 02/15] clk: sunxi: Implement MMC phase control
From: Emilio López emi...@elopez.com.ar
HdG: add header exporting clk_sunxi_mmc_phase_control
Signed-off-by: Emilio López emi...@elopez.com.ar
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/clk/sunxi/clk-sunxi.c | 36
include/linux/clk/sunxi.h | 22 ++
2 files changed, 58 insertions(+)
create mode 100644 include/linux/clk/sunxi.h
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index bd7dc73..59f9040 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -507,6 +507,42 @@ CLK_OF_DECLARE(sun7i_a20_gmac,
allwinner,sun7i-a20-gmac-clk,
/**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
+{
+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite,
hw)
+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+ struct clk_composite *composite = to_clk_composite(hw);
+ struct clk_hw *rate_hw = composite-rate_hw;
+ struct clk_factors *factors = to_clk_factors(rate_hw);
+ unsigned long flags = 0;
+ u32 reg;
+
+ if (factors-lock)
+ spin_lock_irqsave(factors-lock, flags);
+
+ reg = readl(factors-reg);
+
+ /* set sample clock phase control */
+ reg = ~(0x7 20);
+ reg |= ((sample 0x7) 20);
+
+ /* set output clock phase control */
+ reg = ~(0x7 8);
+ reg |= ((output 0x7) 8);
+
+ writel(reg, factors-reg);
+
+ if (factors-lock)
+ spin_unlock_irqrestore(factors-lock, flags);
+}
+EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
+
+
+/**
* sunxi_factors_clk_setup() - Setup function for factor clocks
*/
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 000..1ef5c89
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 - Hans de Goede hdego...@redhat.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+#include linux/clk.h
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
+
+#endif
--
1.9.0
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[linux-sunxi] [PATCH v10 05/15] ARM: dts: sun4i: Add pin-muxing info for the mmc0 controller
mmc0 is the only controller actually being used on boards, so limit the
pin-muxing options to that.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index a0240b7..34651e9 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -565,6 +565,20 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins =
PF0,PF1,PF2,PF3,PF4,PF5;
+ allwinner,function = mmc0;
+ allwinner,drive = 2;
+ allwinner,pull = 0;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = PH1;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
};
timer@01c20c00 {
--
1.9.0
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[linux-sunxi] [PATCH v10 15/15] ARM: dts: sun7i: Add basic support for the Cubietruck WiFi module
From: Chen-Yu Tsai w...@csie.org
The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The WiFi
part is a BCM43362 IC connected to MMC3 in the A20 SoC via SDIO.
The IC also takes a power enable signal via GPIO.
The WiFi module supports out-of-band interrupt signaling via GPIO,
but this is not supported in this patch.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 31 ++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index b2e2efd..97b6f02 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -29,6 +29,14 @@
status = okay;
};
+ mmc3: mmc@01c12000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc3_pins_a;
+ vmmc-supply = reg_vmmc3;
+ non-removable;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
@@ -57,6 +65,18 @@
};
pinctrl@01c20800 {
+ mmc3_pins_a: mmc3@0 {
+ /* AP6210 requires pull-up */
+ allwinner,pull = 1;
+ };
+
+ vmmc3_pin_cubietruck: vmmc3_pin@0 {
+ allwinner,pins = PH9;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
allwinner,pins = PH12;
allwinner,function = gpio_out;
@@ -148,4 +168,15 @@
reg_usb2_vbus: usb2-vbus {
status = okay;
};
+
+ reg_vmmc3: vmmc3 {
+ compatible = regulator-fixed;
+ pinctrl-names = default;
+ pinctrl-0 = vmmc3_pin_cubietruck;
+ regulator-name = vmmc3;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ enable-active-high;
+ gpio = pio 7 9 0;
+ };
};
--
1.9.0
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[linux-sunxi] [PATCH v10 14/15] ARM: dts: sun7i: Enable mmc controller on various A20 boards
The cd pin settings have been taken from the original firmware fex files,
and have been confirmed to work on the actual boards.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 9 +
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 9 +
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 25 +
3 files changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 68de89f..3918e2f 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -20,6 +20,15 @@
compatible = cubietech,cubieboard2, allwinner,sun7i-a20;
soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index cb25d3c..b2e2efd 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -20,6 +20,15 @@
compatible = cubietech,cubietruck, allwinner,sun7i-a20;
soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index eeadf76..1bfef12 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -31,6 +31,24 @@
status = okay;
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
+ mmc3: mmc@01c12000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc3_pins_a, mmc3_cd_pin_olinuxinom;
+ bus-width = 4;
+ cd-gpios = pio 7 11 0; /* PH11 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
@@ -65,6 +83,13 @@
};
pinctrl@01c20800 {
+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
+ allwinner,pins = PH11;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
led_pins_olinuxino: led_pins@0 {
allwinner,pins = PH2;
allwinner,function = gpio_out;
--
1.9.0
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[linux-sunxi] [PATCH v10 09/15] ARM: dts: sun6i: Add mmc clocks
Add clk-nodes for the mmc clocks.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1cfaf52..f2bb07c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -206,6 +206,38 @@
apb2_uart4, apb2_uart5;
};
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-a10-mod0-clk;
+ reg = 0x01c20088 0x4;
+ clocks = osc24M, pll6;
+ clock-output-names = mmc0;
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-a10-mod0-clk;
+ reg = 0x01c2008c 0x4;
+ clocks = osc24M, pll6;
+ clock-output-names = mmc1;
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-a10-mod0-clk;
+ reg = 0x01c20090 0x4;
+ clocks = osc24M, pll6;
+ clock-output-names = mmc2;
+ };
+
+ mmc3_clk: clk@01c20094 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-a10-mod0-clk;
+ reg = 0x01c20094 0x4;
+ clocks = osc24M, pll6;
+ clock-output-names = mmc3;
+ };
+
spi0_clk: clk@01c200a0 {
#clock-cells = 0;
compatible = allwinner,sun4i-a10-mod0-clk;
--
1.9.0
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[linux-sunxi] [PATCH v10 01/15] clk: sunxi: factors: automatic reparenting support
From: Emilio López emi...@elopez.com.ar
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López emi...@elopez.com.ar
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-factors.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 9e23264..3806d97 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw,
unsigned long rate,
return rate;
}
+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ struct clk **best_parent_p)
+{
+ struct clk *clk = hw-clk, *parent, *best_parent = NULL;
+ int i, num_parents;
+ unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
+
+ /* find the parent that can help provide the fastest rate = rate */
+ num_parents = __clk_get_num_parents(clk);
+ for (i = 0; i num_parents; i++) {
+ parent = clk_get_parent_by_index(clk, i);
+ if (!parent)
+ continue;
+ if (__clk_get_flags(clk) CLK_SET_RATE_PARENT)
+ parent_rate = __clk_round_rate(parent, rate);
+ else
+ parent_rate = __clk_get_rate(parent);
+
+ child_rate = clk_factors_round_rate(hw, rate, parent_rate);
+
+ if (child_rate = rate child_rate best_child_rate) {
+ best_parent = parent;
+ best = parent_rate;
+ best_child_rate = child_rate;
+ }
+ }
+
+ if (best_parent)
+ *best_parent_p = best_parent;
+ *best_parent_rate = best;
+
+ return best_child_rate;
+}
+
static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned
long rate,
}
const struct clk_ops clk_factors_ops = {
+ .determine_rate = clk_factors_determine_rate,
.recalc_rate = clk_factors_recalc_rate,
.round_rate = clk_factors_round_rate,
.set_rate = clk_factors_set_rate,
--
1.9.0
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[linux-sunxi] [PATCH v10 06/15] ARM: dts: sun4i: Enable mmc controller on various A10 boards
Tested on a subset of these boards, for the others boards the settings match
the ones of the tested boards according to the original firmware fex files.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 9 +
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 9 +
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 9 +
arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 9 +
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 9 +
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 9 +
arch/arm/boot/dts/sun4i-a10-pcduino.dts| 9 +
7 files changed, 63 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index fa746aea..93af306 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -36,6 +36,15 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 4684cbe..8581385 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -34,6 +34,15 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index d7c17e4..9dc7b1c 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -36,6 +36,15 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index fe9272e..297b8f6 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -24,6 +24,15 @@
};
soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
uart0: serial@01c28000 {
pinctrl-names = default;
pinctrl-0 = uart0_pins_a;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index dd84a9e..b7a4218 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -20,6 +20,15 @@
compatible = pineriver,mini-xplus, allwinner,sun4i-a10;
soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default;
+ pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
+
usbphy: phy@01c13400 {
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index 66cf0c7..4b7fd04 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -33,6 +33,15 @@
[linux-sunxi] [PATCH v10 07/15] ARM: dts: sun5i: Add mmc controller nodes
From: David Lanzendörfer david.lanzendoer...@o2s.ch
Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc
controllers found on A13 SoCs.
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 27 +++
arch/arm/boot/dts/sun5i-a13.dtsi | 18 ++
2 files changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi
b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 9493b21..aa1dd59 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -338,6 +338,33 @@
#size-cells = 0;
};
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb_gates 8, mmc0_clk;
+ clock-names = ahb, mmc;
+ interrupts = 32;
+ status = disabled;
+ };
+
+ mmc1: mmc@01c1 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c1 0x1000;
+ clocks = ahb_gates 9, mmc1_clk;
+ clock-names = ahb, mmc;
+ interrupts = 33;
+ status = disabled;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c11000 0x1000;
+ clocks = ahb_gates 10, mmc2_clk;
+ clock-names = ahb, mmc;
+ interrupts = 34;
+ status = disabled;
+ };
+
usbphy: phy@01c13400 {
#phy-cells = 1;
compatible = allwinner,sun5i-a13-usb-phy;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index dda9df6..c9fdb7b 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -320,6 +320,24 @@
#size-cells = 0;
};
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb_gates 8, mmc0_clk;
+ clock-names = ahb, mmc;
+ interrupts = 32;
+ status = disabled;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c11000 0x1000;
+ clocks = ahb_gates 10, mmc2_clk;
+ clock-names = ahb, mmc;
+ interrupts = 34;
+ status = disabled;
+ };
+
usbphy: phy@01c13400 {
#phy-cells = 1;
compatible = allwinner,sun5i-a13-usb-phy;
--
1.9.0
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[linux-sunxi] [PATCH v10 03/15] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
From: David Lanzendörfer david.lanzendoer...@o2s.ch
The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in
designware idmac controller, which is identical to the one found in the mmc-dw
hosts. However the rest of the host is not identical to mmc-dw, it deals with
sending stop commands in hardware which makes it significantly different
from the mmc-dw devices.
HdG: Various cleanups and fixes.
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/mmc/sunxi-mmc.txt | 43 +
drivers/mmc/host/Kconfig |7 +
drivers/mmc/host/Makefile |2 +
drivers/mmc/host/sunxi-mmc.c | 1125
4 files changed, 1177 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
create mode 100644 drivers/mmc/host/sunxi-mmc.c
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
new file mode 100644
index 000..91b3a34
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -0,0 +1,43 @@
+* Allwinner sunxi MMC controller
+
+The highspeed MMC host controller on Allwinner SoCs provides an interface
+for MMC, SD and SDIO types of memory cards.
+
+Supported maximum speeds are the ones of the eMMC standard 4.5 as well
+as the speed of SD standard 3.0.
+Absolute maximum transfer rate is 200MB/s
+
+Required properties:
+ - compatible : allwinner,sun4i-a10-mmc or allwinner,sun5i-a13-mmc
+ - reg : mmc controller base registers
+ - clocks : a list with 2 phandle + clock specifier pairs
+ - clock-names : must contain ahb and mmc
+ - interrupts : mmc controller interrupt
+
+Optional properties:
+ - resets : phandle + reset specifier pair
+ - reset-names : must contain ahb
+ - for cd, bus-width and additional generic mmc parameters
+ please refer to mmc.txt within this directory
+
+Examples:
+ - Within .dtsi:
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb_gates 8, mmc0_clk;
+ clock-names = ahb, mod;
+ interrupts = 0 32 4;
+ status = disabled;
+ };
+
+ - Within dts:
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default, default;
+ pinctrl-0 = mmc0_pins_a;
+ pinctrl-1 = mmc0_cd_pin_reference_design;
+ bus-width = 4;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ cd-inverted;
+ status = okay;
+ };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 8aaf8c1..d50ac1c 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -694,3 +694,10 @@ config MMC_REALTEK_PCI
help
Say Y here to include driver code to support SD/MMC card interface
of Realtek PCI-E card reader
+
+config MMC_SUNXI
+ tristate Allwinner sunxi SD/MMC Host Controller support
+ depends on ARCH_SUNXI
+ help
+ This selects support for the SD/MMC Host Controller on
+ Allwinner sunxi SoCs.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 0c8aa5e..c706c0f 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -53,6 +53,8 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
+obj-$(CONFIG_MMC_SUNXI)+= sunxi-mmc.o
+
obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
obj-$(CONFIG_MMC_SDHCI_CNS3XXX)+= sdhci-cns3xxx.o
obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
new file mode 100644
index 000..2706b64
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -0,0 +1,1125 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2007-2011 Aaron Maoye leafy.m...@reuuimllatech.com
+ * (C) Copyright 2013-2014 O2S GmbH www.o2s.ch
+ * (C) Copyright 2013-2014 David Lanzendörfer david.lanzendoer...@o2s.ch
+ * (C) Copyright 2013-2014 Hans de Goede hdego...@redhat.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/io.h
+#include linux/device.h
+#include linux/interrupt.h
+#include linux/delay.h
+#include linux/err.h
+
+#include linux/clk.h
+#include linux/clk-private.h
+#include linux/clk/sunxi.h
+
+#include linux/gpio.h
+#include linux/platform_device.h
+#include linux/spinlock.h
+#include linux/scatterlist.h
+#include linux/dma-mapping.h
+#include linux/slab.h
[linux-sunxi] [PATCH v10 00/15] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
Hi All,
Here is v10 of the sunxi-mmc patch-set David Lanzendörfer and I have been
working on, this has some minor changes since v9, the plan for upstreaming is
still the same:
The first 2 patches are depenencies which should go in through the clk tree,
Mike can you pick these 2 up please ? :
clk: sunxi: factors: automatic reparenting support
Is uncontroversial and has been favorably reviewed by various people.
clk: sunxi: Implement MMC phase control
Is somewhat more controversial as there has been lots of discussion about
adding a generic phase control method to the clk framework. The problem is
that there has been a lot of talk about such a generic phase control method
but not a single patch. Therefor I would like to move forwards with using
a platform specific method for now. I hereby promise that once we've a generic
method I'll write patches to convert the sunxi code to that method.
The third patch is the patch adding the actual mmc driver and should go in
through the mmc tree.
All the other patches are devicetree patches hooking things up, and should
go upstream through Maxime's sunxi-dt tree.
Changes since v1:
-Using mmc_of_parse instead of diy dt parsing
-Adding nodes for all mmc controller to the dtsi files,
including sofar unused controllers
-Using generic GPIO slot library for WP/CD
-Adding additional MMC device nodes into DTSI files
Changes since v2:
-Add missing Signed-off-by tags
-Stop using __raw_readl / __raw_writel so that barriers are properly used
-Adding missing new lines
-Adding missing patch for automatic reparenting of clocks
Changes since v3:
-Move clk_enable / disable into host_init / exit (Hans)
-Fix hang on boot caused by irq storm (Hans)
Changes since v4:
-moving sunxi-mci.{c/h} to sunxi-mmc.{c/h}
-removing camel cases from the defines in sunxi-mmc.h
-moving defines out of the struct definition
since this is bad coding style
-adding documentation for the device tree binding
Changes since v5:
-adding host initialization for when the sdio irq is enabled
(just to make sure having a defined state at all time)
-add mmc support fixup: set pullup on cd pins
-fixup: Don't set MMC_CAP_NEEDS_POLL / MMC_CAP_4_BIT_DATA
Changes since v6:
-fixing copyright info in sunxi-mmc.*
-s/__SUNXI_MCI_H__/__SUNXI_MMC_H__/g
-s/SDXC_RESPONSE_/SDXC_RESP_/g
-s/define/definitions - Comment from Priit Laes
Changes since v7:
-Merge sunxi-mmc.h into sunxi-mmc.c
-Various style fixes / cleanups based on Maxime's review
-sun6i support
-Fix a race condition in interrupt / tasklet interaction
-Split the dts patches into 3 per platform:
1) Add mmc nodes to the dtsi
2) Add mmc pinmux to the dtsi
3) Add mmc nodes to the various board files
-Moved setting of bus-width and cd gpio polarity from .dtsi to the board-files
-Added sun6i dts patches
Changes since v8:
-Don't claim MMC_CAP_SDIO_IRQ by default, sdio-irq support appears to not
always be reliable. Can be re-added to the caps on a per board basis
through dts
-Added EXPORT_SYMBOL(clk_sunxi_mmc_phase_control)
-Moved bus-width and cd-inverted dts attributes for sun6i from dtsi to dts
-Squashed patches adding sun6i-a31-m9.dts and mmc support for m9 together
-Added a patch enabling the sdio wifi on the cubietruck in dts
Changes since v9:
-Drop the sun5i and sun6i dts pinmux patches as those have already been
accepted
-Rename the mmc clock for the controller from mod to mmc so as
to not confuse it with a regular mod0 clock
-Rename pinmux for the reference design card-detect pin from cd_pin_a to
cd_pin_reference_design
Regards,
Hans
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[linux-sunxi] [PATCH v10 12/15] ARM: dts: sun7i: Add mmc controller nodes
Add nodes for the 4 mmc controllers found on A20 SoCs to
arch/arm/boot/dts/sun7i-a20.dtsi.
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f9f5e0c..9c0ee6f 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -461,6 +461,42 @@
#size-cells = 0;
};
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb_gates 8, mmc0_clk;
+ clock-names = ahb, mmc;
+ interrupts = 0 32 4;
+ status = disabled;
+ };
+
+ mmc1: mmc@01c1 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c1 0x1000;
+ clocks = ahb_gates 9, mmc1_clk;
+ clock-names = ahb, mmc;
+ interrupts = 0 33 4;
+ status = disabled;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c11000 0x1000;
+ clocks = ahb_gates 10, mmc2_clk;
+ clock-names = ahb, mmc;
+ interrupts = 0 34 4;
+ status = disabled;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c12000 0x1000;
+ clocks = ahb_gates 11, mmc3_clk;
+ clock-names = ahb, mmc;
+ interrupts = 0 35 4;
+ status = disabled;
+ };
+
usbphy: phy@01c13400 {
#phy-cells = 1;
compatible = allwinner,sun7i-a20-usb-phy;
--
1.9.0
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[linux-sunxi] [PATCH v10 13/15] ARM: dts: sun7i: Add pin-muxing info for the mmc controllers
This adds pin-muxing info for the mmc controller / port combinations which
are known to be used on actual boards.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9c0ee6f..9edd7fe 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -703,6 +703,27 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins =
PF0,PF1,PF2,PF3,PF4,PF5;
+ allwinner,function = mmc0;
+ allwinner,drive = 2;
+ allwinner,pull = 0;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = PH1;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ mmc3_pins_a: mmc3@0 {
+ allwinner,pins =
PI4,PI5,PI6,PI7,PI8,PI9;
+ allwinner,function = mmc3;
+ allwinner,drive = 2;
+ allwinner,pull = 0;
+ };
};
timer@01c20c00 {
--
1.9.0
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[linux-sunxi] Re: [PATCH v7] DMA: sun6i: Add driver for the Allwinner A31 DMA controller
On Wed, Apr 30, 2014 at 02:53:22PM -0700, Maxime Ripard wrote:
Hi Vinod,
On Wed, Apr 30, 2014 at 12:34:08PM +0530, Vinod Koul wrote:
On Thu, Apr 24, 2014 at 04:22:44PM +0200, Maxime Ripard wrote:
+static inline void sun6i_dma_free(struct sun6i_dma_dev *sdc)
+{
+ int i;
+
+ for (i = 0; i NR_MAX_VCHANS; i++) {
+ struct sun6i_vchan *vchan = sdc-vchans[i];
+
+ list_del(vchan-vc.chan.device_node);
+ tasklet_kill(vchan-vc.task);
+ }
+
+ tasklet_kill(sdc-task);
This is again not good. see http://lwn.net/Articles/588457/
At this point HW can still generate interrupts or you can have irq running!
I'm not sure to fully understand the issue here, but what is not good?
the first or the second tasklet_kill calls, or both?
From what I understood, the issue is only there whenever you are
calling tasklet_disable without making sure that no one will schedule
your tasklet before disabling it.
But the point is I don't actually use either _enable/_disable. I might
be wrong in not using those functions, but I don't really see how I
can be impacted.
Well that was one part of it. How do you ensure the tasklet is not scheduled
while and after you are killing it. You need to ensure irq is disabled and
pending irqs
have finished processing. I dont see that bit.
--
~Vinod
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[linux-sunxi] [PATCH] sunxi: fix SRAM_B/SRAM_D memory map
From: Marc Zyngier marc.zyng...@arm.com Move the B and D SRAM bank to their actual location (or at least where the documentation pretends they are). Signed-off-by: Marc Zyngier marc.zyng...@arm.com Signed-off-by: Ian Campbell i...@hellion.org.uk --- Reposting since this patch from Marc since it is wanted for the upstream version. I've confirmed the addresses in both A10 and A20 manuals --- arch/arm/include/asm/arch-sunxi/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 9285181..359ff67 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -15,8 +15,8 @@ #define SUNXI_SRAM_A2_BASE 0x4000 /* 16 kiB */ #define SUNXI_SRAM_A3_BASE 0x8000 /* 13 kiB */ #define SUNXI_SRAM_A4_BASE 0xb400 /* 3 kiB */ -#define SUNXI_SRAM_D_BASE 0x01c0 -#define SUNXI_SRAM_B_BASE 0x01c0 /* 64 kiB (secure) */ +#define SUNXI_SRAM_D_BASE 0x0001 /* 4 kiB */ +#define SUNXI_SRAM_B_BASE 0x0002 /* 64 kiB (secure) */ #define SUNXI_SRAMC_BASE 0x01c0 #define SUNXI_DRAMC_BASE 0x01c01000 -- 1.9.0 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH u-boot-sunxi 2/2] sunxi: add comments to pll1_para array.
The entries must be ordered by frequency and the final entry is a catchall
which configures the maximum supported frequency.
Make pll1_para static at the same time.
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index c0680bb..5a7da3c 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -92,10 +92,11 @@ int clock_twi_onoff(int port, int state)
0 CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
(M) CCM_PLL1_CFG_FACTOR_M_SHIFT)
-struct {
+static struct {
u32 pll1_cfg;
unsigned int freq;
} pll1_para[] = {
+ /* This array must be ordered by frequency. */
{ PLL1_CFG(16, 0, 0, 0), 38400 },
{ PLL1_CFG(16, 1, 0, 0), 76800 },
{ PLL1_CFG(20, 1, 0, 0), 96000 },
@@ -110,6 +111,7 @@ struct {
{ PLL1_CFG(29, 1, 0, 0), 139200},
{ PLL1_CFG(30, 1, 0, 0), 144000},
{ PLL1_CFG(31, 1, 0, 0), 148800},
+ /* Final catchall entry */
{ PLL1_CFG(31, 1, 0, 0), ~0},
};
--
1.9.0
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[linux-sunxi] [PATCH u-boot-sunxi 1/2] sunxi: hz parameter to clock_set_pll1 should be an unsigned int.
Requested by Marek during upstream review.
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 4 ++--
arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 5720201..c0680bb 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -113,7 +113,7 @@ struct {
{ PLL1_CFG(31, 1, 0, 0), ~0},
};
-void clock_set_pll1(int hz)
+void clock_set_pll1(unsigned int hz)
{
int i = 0;
int axi, ahb, apb0;
@@ -131,7 +131,7 @@ void clock_set_pll1(int hz)
ahb = DIV_ROUND_UP(hz/axi, 20400); /* Max 250MHz */
apb0 = 2; /* Max 150MHz */
- printf(CPU: %dHz, AXI/AHB/APB: %d/%d/%d\n, hz, axi, ahb, apb0);
+ printf(CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n, hz, axi, ahb, apb0);
/* Map divisors to register values */
axi = axi - 1;
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index a12d096..012c2af 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -24,7 +24,7 @@
#ifndef __ASSEMBLY__
int clock_init(void);
int clock_twi_onoff(int port, int state);
-void clock_set_pll1(int hz);
+void clock_set_pll1(unsigned int hz);
unsigned int clock_get_pll6(void);
void clock_init_safe(void);
void clock_init_uart(void);
--
1.9.0
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[linux-sunxi] Re: [PATCH v5 3/8] mfd: AXP20x: Add bindings documentation
Hi, On Thu, May 01, 2014 at 02:29:29PM +0200, Carlo Caione wrote: Bindings documentation for the AXP20x driver. In this file also sub-nodes are documented. Signed-off-by: Carlo Caione ca...@caione.org Acked-by: Maxime Ripard maxime.rip...@free-electrons.com Thanks for your efforts, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH v5 1/8] mfd: AXP20x: Add mfd driver for AXP20x PMIC
On Thu, May 01, 2014 at 02:29:27PM +0200, Carlo Caione wrote: This patch introduces the preliminary support for PMICs X-Powers AXP202 and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit) used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company of Allwinner. The core enables support for two subsystems: - PEK (Power Enable Key) - Regulators Signed-off-by: Carlo Caione ca...@caione.org Acked-by: Lee Jones lee.jo...@linaro.org Acked-by: Maxime Ripard maxime.rip...@free-electrons.com Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH 1/3] ARM: sun7i: dt: Add basic board support for LinkSprite pcDuino V3
Hi,
On Fri, May 02, 2014 at 01:45:04PM +0200, Zoltan HERPAI wrote:
This patch will add a basic board support DT for the
LinkSprite pcDuino V3, which is based on A20.
Signed-off-by: Zoltan HERPAI wigy...@uid0.hu
---
arch/arm/boot/dts/Makefile |3 +-
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 70
++
2 files changed, 72 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun7i-a20-pcduino3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1cd137d..821fa99 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -354,7 +354,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
sun6i-a31-m9.dtb \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
- sun7i-a20-olinuxino-micro.dtb
+ sun7i-a20-olinuxino-micro.dtb \
+ sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
tegra20-medcom-wide.dtb \
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
new file mode 100644
index 000..bf9d527
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI wigy...@uid0.hu
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ sun7i-a20.dtsi
+/include/ sunxi-common-regulators.dtsi
+#include dt-bindings/input/input.h
I don't think you're using it anywhere.
+
+/ {
+ model = LinkSprite pcDuino V3;
+ compatible = linksprite,a20-pcduino3, allwinner,sun7i-a20;
+
+ soc@01c0 {
+ pinctrl@01c20800 {
+ led_pins_pcduino3: led_pins@0 {
+ allwinner,pins = PH2;
+ allwinner,function = gpio_out;
+ allwinner,drive = 1;
+ allwinner,pull = 0;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+ };
+
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins_a;
+ status = okay;
+ #address-cells = 1;
+ #size-cells = 0;
You're missing a closing bracket here. Make sure to compile your DT
whenever you're submitting it.
Apart from that it looks good. The next two patches can be merged with
this one however.
Thanks!
Maxime
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[linux-sunxi] Re: [PATCH v5 4/8] input: misc: Add driver for AXP20x Power Enable Key
On Thu, May 01, 2014 at 02:29:30PM +0200, Carlo Caione wrote: This patch add support for the Power Enable Key found on MFD AXP202 and AXP209. Besides the basic support for the button, the driver adds two entries in sysfs to configure the time delay for power on/off. Signed-off-by: Carlo Caione ca...@caione.org Acked-by: Maxime Ripard maxime.rip...@free-electrons.com -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH v5 8/8] ARM: sun7i/sun4i: dt: Add AXP209 support to various boards
Hi,
On Thu, May 01, 2014 at 02:29:34PM +0200, Carlo Caione wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 58 ++
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 58 ++
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 64
arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 58 ++
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 65
+
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 64
arch/arm/boot/dts/sun4i-a10-pcduino.dts | 58 ++
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 59 ++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 59 ++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 59 ++
10 files changed, 602 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index fa746aea..57d3fb4 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -88,6 +88,56 @@
pinctrl-names = default;
pinctrl-0 = i2c0_pins_a;
status = okay;
+
+ axp209: pmic@34 {
+ compatible = x-powers,axp209;
+ reg = 0x34;
+ interrupts = 0;
+
+ interrupt-controller;
+ #interrupt-cells = 1;
+
+ acin-supply = reg_axp_ipsout;
+ vin2-supply = reg_axp_ipsout;
+ vin3-supply = reg_axp_ipsout;
+ ldo24in-supply = reg_axp_ipsout;
+ ldo3in-supply = reg_axp_ipsout;
+ ldo5in-supply = reg_axp_ipsout;
+
+ regulators {
+ x-powers,dcdc-freq = 1500;
+
+ axp_vcore_reg: dcdc2 {
+ regulator-min-microvolt =
70;
+ regulator-max-microvolt =
2275000;
+ regulator-always-on;
+ };
+
+ axp_ddr_reg: dcdc3 {
+ regulator-always-on;
+ };
+
+ axp_rtc_reg: ldo1 {
+ regulator-always-on;
+ };
+
+ axp_analog_reg: ldo2 {
+ regulator-always-on;
+ };
+
+ axp_pll_reg: ldo3 {
+ regulator-always-on;
+ };
+
+ axp_hdmi_reg: ldo4 {
+ regulator-always-on;
+ };
+
+ axp_mic_reg: ldo5 {
+ regulator-always-on;
Do all these regulators need to be always on? It makes sense for the
pll and vcore, but I don't get why the mic and hdmi regulators need
this.
Maxime
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